A single photon detector with anti background light noise event detection function

Abstract

The application discloses an anti-background light noise event detection type single photon detector with address coding function, comprising four SPAD devices, quenching circuits, photon event detection circuits and address coding circuits. The event detection type single photon detector with address coding function can adjust a photon detection window time and a photon detection threshold value. The TIMING signal of the application becomes a high level only after the window signal WIN ends, so the time between the TIMING signal and the first arrived photon signal is fixed as the time of a detection window. The application locks the SPAD state of the trigger detection window WIN through the address coding circuit, and outputs the corresponding address coding response, so as to provide a basis for the trigger position judgment in the macro-pixel unit, and improve the spatial resolution of the detector. The single photon detector can ensure the resolution and the accuracy of the obtained echo photons in the photon event detection circuit with the address coding function.

Description

Technical Field

[0001] This invention relates to a single-photon detector with address encoding function that is resistant to background light noise event detection, belonging to the field of single-photon detector technology. Background Technology

[0002] A single-photon detector is a precision optical sensor capable of detecting single-photon signals, possessing extremely high sensitivity and time resolution. It achieves photon-level detection by converting weak light signals into measurable electrical signals, even in extremely low light intensity environments. As a crucial component of modern optical detection technology, single-photon detectors play a key role in fields such as quantum communication, lidar, and biomedical imaging.

[0003] Single-photon detectors mainly consist of a single-photon avalanche photodiode (SPAD) and a quenching circuit. The process is as follows: the SPAD converts the captured single photon into an electrical pulse through the avalanche multiplication effect, while the quenching circuit terminates the avalanche process and restores the SPAD to its original state for detecting the next photon. However, in practical applications, background light noise interference becomes a key factor affecting the performance of single-photon detectors. Light noise can cause the quenching circuit to mistrigger, especially when noise signals appear independently, where a single echo signal is highly likely to be misinterpreted as a valid signal. To solve this problem, a photon event detection circuit has been developed. This circuit can effectively collect continuous echo photons and significantly improve the detector's anti-interference capability by eliminating isolated echo signals caused by noise.

[0004] Currently, mainstream photon event detection circuits employ the following mechanism: when the first photon echo signal is detected, the circuit synchronously generates a time window signal. If the number of echo signals within the window reaches a preset threshold, the window signal closes, and a high-level signal is output as the valid photon echo signal within that pixel. Although this design has achieved some success in suppressing optical noise interference, it still faces two key challenges: First, since the first photon signal is used as the starting point of the window, there is a time error between the valid echo signal and the starting point. This error will directly translate into ranging error in ranging applications such as lidar, affecting measurement accuracy. Second, the circuit is typically applied to macro-pixel units and cannot subdivide the units within a pixel, limiting the spatial resolution of the detector. Therefore, developing a detection circuit that can accurately measure echo photon signals without being limited by resolution is of great significance for improving the ranging and imaging performance of lidar. Summary of the Invention

[0005] The purpose of this invention is to address the problem that existing photon event detection circuits cannot accurately measure echo photon signals and limit the spatial resolution of the detector. It proposes a single-photon detector with address encoding function that is resistant to background light noise event detection. This single-photon detector can ensure both resolution and accuracy in acquiring echo photons in a photon event detection circuit with address encoding function.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: an event detection type single-photon detector with address encoding function, comprising four SPAD devices, a quenching circuit, a photon event detection circuit, and an address encoding circuit. The input terminals of the quenching circuit are V1~V4 and Vc. V1~V4 are connected to the anode of the SPAD devices; Vc is connected to a 0~1.8V voltage signal. The output terminals of the quenching circuit are S1~S4, respectively connected to the input terminals I1~I4 of the photon event detection circuit and the input terminals T1~T4 of the address encoding circuit. The input terminals of the photon event detection circuit are I1~I4, P1, P2, R, and VP. I1~I4 are connected to the four photon quenching signals output by the quenching circuit; P1 and P2 are connected to high / low level signals to control the photon threshold of the photon event detection circuit; R is connected to a reset signal; and VP is connected to a 0~1.8V voltage signal to control the window width of the photon event detection circuit. The output terminals of the photon event detection circuit are TIMING and WIN, which are connected to the INT and INWIN terminals of the address encoding circuit, respectively. The input terminals of the address encoding circuit are T1~T4, INT, and INWIN. The T1~T4 terminals are connected to the photon quenching signal output by the quenching circuit; the INT terminal is connected to the TIMING terminal of the photon event detection circuit; and the INWIN terminal is connected to the WIN terminal of the photon event detection circuit.

[0007] As a preferred embodiment of the event detection single-photon detector with address encoding function described in this invention, the quenching circuit includes four NMOS transistors, two PMOS transistors, one OR gate, and one inverter. The four NMOS transistors are denoted as NM1, NM2, NM3, and NM4; the two PMOS transistors are denoted as PM1 and PM2; the OR gate is denoted as OR; and the inverter is denoted as INV. The drain, source, and gate of NM1 are connected to the anode of a single SPAD device / the source of NM2, ground, and the external voltage Vc / the gate of NM2, respectively; the drain, source, and gate of NM2 are connected to the gate of PM1 / the gate of NM3, the drain of NM1, and the external voltage Vc / the gate of NM2, respectively; the drain, source, and gate of NM3 are connected to the drain of PM1 / the gate of NM4, ground, and the drain of NM2 / the gate of PM1, respectively; the drain, source, and gate of NM4 are connected to the drain of PM2 / OR gate input stage A1, ground, the drain of PM1 / NM3 / OR gate input stage A2, respectively; the drain, source, and gate of PM1 are connected to NM3 / NM2 / NM2 / NM2 / NM3 ... Drain / NM4 gate / OR gate input stage A2, power supply, NM2 drain / NM3 gate; PM2 drain, source, and gate are respectively connected to NM4 drain / OR gate input stage A1, power supply, OR gate output stage O / inverter input stage I; OR gate input terminals A1 and A2 are respectively connected to NM4 drain / PM2 drain, NM3 drain / NM4 gate / PM1 drain; OR gate output terminal O is respectively connected to PM2 gate / inverter INV input stage I; inverter INV input terminal is respectively connected to PM2 gate / OR gate output stage O; inverter INV output terminal is connected to photon event detection circuit input stage.

[0008] As a preferred embodiment of the event-detecting single-photon detector with address encoding function described in this invention, the photon event detection circuit includes three D flip-flops, two delay units, four inverters, five AND gates, and five OR gates. The three D flip-flops are denoted as DFF1, DFF2, and DFF3; the two delay units are denoted as Delay1 and Delay2; the four inverters are denoted as INV1, INV2, INV3, and INV4; the five AND gates are denoted as AND1, AND2, AND3, AND4, and AND5; and the five OR gates are denoted as OR1, OR2, OR3, OR4, and OR5. DFF1 inputs D, Clk, and R are connected to power supply VDD, OR5 output CK, and AND5 output OUTR, respectively; DFF1 output Q is connected to INV1 and AND1 inputs; DFF2 inputs D, Clk, and R are connected to DFF2 output Qb, OR5 output CK, and AND5 outputs, respectively; DFF2 output Q is connected to OR1 input, Qb is connected to DFF2 input D, and DFF3 input Clk; DFF3 input Clk is connected to DFF2 input D and DFF2 output Qb; D The input terminal D of FF3 is connected to the output terminal Qb of DFF3; the output terminals Q and Qb of DFF3 are connected to the input terminals of OR2 and D of DFF3, respectively; the input terminal of the delay unit Delay1 is connected to the output terminal of INV1 and the delay control voltage VP, respectively; the output terminal of the delay unit Delay1 is connected to the input terminal of INV2; the input terminal of the delay unit Delay2 is connected to the output terminal of AND2 and the delay control voltage VP, respectively; the output terminal of the delay unit Delay2 is connected to the input terminal of INV4; the input terminal of INV1 is connected to the output terminals Q and AN of DFF1. The input terminal of D1 is connected to the output terminal of INV1, which is then connected to the input terminal of Delay1. The input terminal of INV2 is connected to the output terminal of Delay1, which is then connected to the input terminal of AND1. The input terminal of INV3 is connected to the output terminal WIN of AND1, which is then connected to the input terminal of AND3. The input terminal of INV4 is connected to the output terminal of Delay2, which is then connected to the input terminal of AND3. The two input terminals of AND1 are respectively connected to the output terminal Q of DFF1, the input terminal of INV1, and the output terminal of INV2. The AND1 output is connected to the INV3 input; the AND2 input is connected to the OR1 and OR2 outputs respectively; the AND2 output is connected to the Delay2 delay unit input; the AND3 input is connected to the INV3 and INV4 outputs respectively; the AND3 output outputs the photon detection coincidence signal TIMING; the AND4 input is connected to the INV4 output and the external reset signal R respectively; the AND4 output is connected to the AND5 input; the AND5 input is connected to the AND4 output and the external reset signal R respectively.The output of AND5 is connected to the reset terminal R of DFF1, DFF2, and DFF3; the input of OR1 is connected to the threshold control signal P1 and the output terminal Q of DFF2, respectively; the output of OR1 is connected to the input of AND2; the input of OR2 is connected to the threshold control signal P2 and the output terminal Q of DFF3, respectively; the output of OR2 is connected to the input of AND2; the input of OR3 is connected to the input terminals I1 and I2 of the photon event detection circuit, respectively; the output of OR3 is connected to the input of OR5; the input of OR4 is connected to the input terminals I3 and I4 of the photon event detection circuit, respectively; the output of OR4 is connected to the input of OR5; the input of OR5 is connected to the output terminals of OR3 and OR4, respectively; the output of OR5 is connected to the Clk terminal of DFF1 and DFF2.

[0009] As a preferred embodiment of the event-detection single-photon detector with address encoding function described in this invention, the address encoding circuit includes four D flip-flops, two AND gates, one three-input OR gate, two PMOS transistors, and four NMOS transistors. The four D flip-flops are denoted as DFF4, DFF5, DFF6, and DFF7; the two AND gates are denoted as AND6 and AND7; the three-input OR gate is denoted as OR6; the two PMOS transistors are denoted as PM1 and PM2; and the four NMOS transistors are denoted as NM1, NM2, NM3, and NM4. The inputs D, Clk, and R of DFF4 are connected to the input T1 of the address encoding circuit, the window signal INWIN, and the output ROUT of AND7, respectively; the output of DFF4 is connected to the gate of NM1. The inputs D, Clk, and R of DFF5 are connected to the input T2 of the address encoding circuit, the window signal INWIN, and the output ROUT of AND7, respectively; the output of DFF5 is connected to the gate of NM2. The inputs D, Clk, and R of DFF6 are connected to the input T3 of the address encoding circuit, the window signal INWIN, and the output ROUT of AND7, respectively; the output of DFF6 is connected to the gate of NM3. The inputs D, Clk, and R of DFF7 are connected to the input T4 of the address encoding circuit, the window signal INWIN, and the output ROUT of AND7, respectively; the output of DFF7 is connected to the gate of NM4. The inputs of AND6 are connected to the drains of PM1 and PM2, respectively. OR6 is a three-input OR gate, with its three inputs connected to the output of AND6, the input INT of the address encoding circuit, and the output of the address encoding circuit, respectively. The input terminal is INWIN; the output terminal of OR6 is connected to one input terminal of AND7, and the other input terminal of AND7 is connected to an external active-low reset signal R; the output terminal ROUT of AND7 is connected to the reset terminals R of DFF4, DFF5, DFF6, and DFF7; the gate and source of PM1 are grounded to VSS and the power supply VDD, respectively; the drain of PM1 is connected to the drains of NM2 and NM3 and the input terminal ADDR1 of AND6; the gate and source of PM2 are grounded to VSS and the power supply VDD, respectively; the drain of PM2 is connected to... The drains of NM1 and NM4 and the input terminal ADDR0 of AND6 are connected; the gate, source, and drain of NM1 are connected to the output terminal Q of DFF4, ground VSS, and the drain of PM2, respectively; the gate, source, and drain of NM2 are connected to the output terminal Q of DFF5, ground VSS, and the drain of PM1, respectively; the gate, source, and drain of NM3 are connected to the output terminal Q of DFF6, ground VSS, and the drain of PM1, respectively; the gate, source, and drain of NM4 are connected to the output terminal Q of DFF7, ground VSS, and the drain of PM1, respectively.

[0010] To further address the issues of sacrificed spatial resolution and random errors in current photon event detection, this invention proposes an event-detection type single-photon detector with address encoding function. The detector includes: generating a detection window WIN and latching the SPAD trigger state after detecting a photon signal output from a quenching circuit; determining whether the photon count meets a threshold; and resetting all circuits. As a preferred embodiment of the event-detection single-photon detector with address encoding function described in this invention, the generation of a detection window WIN and latching of the SPAD trigger state after detecting the photon signal output by the quenching circuit includes: all D flip-flops in this invention use low-level reset. Each time the circuit is powered on, a low-level pulse needs to be input to the input terminal R to reset all D flip-flops. After reset, the output terminals Q and Qb of the D flip-flops output low and high levels respectively. After the reset is completed, the level state of each node in the circuit will not change until the photon signal arrives. The four photon quenching signals S1~S4 are input to the I1~I4 terminals of the photon event detection circuit, and simultaneously input to the T1~T4 terminals of the address encoding circuit. When any one of I1~I4 generates a photon signal, the output of OR5 will generate a high-level signal CK with the same pulse width as the photon signal. Signal CK will trigger DFF1. Since the D input of DFF1 is connected to the power supply VDD, the Q output of DFF1 will be high, causing AND1 to output a high-level signal. This causes the output WIN of the photon event detection circuit to change from low to high. The output WIN of the photon event detection circuit is connected to the input INWIN of the address encoding circuit. When WIN becomes high, INWIN also becomes high, causing DFF4~7 to latch the states of T1~T4. The states of T1~T4 are saved as SPAD1~4. SPAD1~4 are connected to the gates of NM1~4. When the gate of NM1 or NM4 becomes high, the corresponding NMOS transistor is turned on, causing the lower address bit ADDR0 to change from high to low. When the gate of NM2 or NM3 becomes high, the corresponding NMOS transistor is turned on, causing the higher address bit ADDR1 to change from high to low. The initial state of ADDR1 and ADDR0 is "11". After the detection window is generated, their level state is determined by the latched SPAD trigger state, which is used to characterize the address encoding response corresponding to the trigger SPAD.

[0011] As a preferred embodiment of the event detection type single-photon detector with address encoding function described in this invention, the determination of whether the number of photons meets the threshold includes: DFF2 and DFF3 forming a two-bit counter, with the output terminals Q of DFF2 and DFF3 being the low-order and high-order bits of the two-bit counter, respectively. As the number of photons increases, the output state of the counter is successively "00", "01", "10", and "11". The low-order and high-order bits of the counter are connected to the input terminals of OR1 and OR2, respectively, and the other input terminal of OR1 and OR2 is connected to P1 and P2. P1 and P2 are externally set photon thresholds. When the number of photons received by the photon event detection circuit reaches the set photon threshold, TIMING will become high; otherwise, it will remain low. P1 and P2 can be set to "00", "01", "10", and "11".

[0012] If we denote the output Q of DFF2 as the low-order bit Q0 of the counter, and the output Q of DFF3 as the high-order bit Q1 of the counter, then the output of OR1 is the logical OR of P1 and Q0, the output of OR2 is the logical OR of P2 and Q1, and the output of AND2 satisfies the following logical relationship: AND2 = (P1 or Q0) AND (P2 or Q1). Therefore, when P1P2 is set to "00", AND2 outputs a high level only when the counter state is "11"; when P1P2 is set to "01", AND2 outputs a high level as long as the low-order bit Q0 of the counter is high; when P1P2 is set to "10", AND2 outputs a high level as long as the high-order bit Q1 of the counter is high; when P1P2 is set to "11", AND2 remains high. When AND2 outputs a high level, and the detection window WIN ends, TIMING outputs a high level, indicating that the photon event within the window meets the preset detection conditions.

[0013] As a preferred embodiment of the event-detection single-photon detector with address encoding function described in this invention, the reset of all circuits includes: upon receiving a photon, the output terminal Q of DFF1 in the photon event detection circuit outputs a high level, causing the input terminal of the delay unit Delay1 to become low. After a delay period, the delay unit Delay1 outputs a high level, causing the output voltage of INV2 to become low. For ease of explanation, the output node of INV2 is denoted as INR, where the delay time is determined by the delay control voltage VP. When INR becomes low, the output WIN of AND1 becomes low, and OUTR becomes low through AND5. The low-level OUTR resets DFF1, DFF2, and DFF3, causing the output terminals Q of all D flip-flops to become low again. This low level, after passing through the delay unit Delay1, causes INR to become high again.

[0014] In the address latch circuit, the initial state of ADDR0 and ADDR1 is "11". When a photon is received, if a state of "0" appears in ADDR0 and ADDR1, AND6 will output a low level. OR6 will wait for INT and INWIN to go low before outputting a low level. This low level causes ROUT to go low, thereby resetting DFF4~7.

[0015] Beneficial effects: 1. This invention improves the spatial resolution and reduces measurement errors of array lidar detectors employing macropixel units. Traditional photon event detection circuits suffer from two problems. First, when the photon count reaches a threshold, a coincidence detection signal (TIMING) is immediately output. Therefore, the time between the TIMING signal and the first arriving photon signal is random, becoming a random error in laser ranging. Second, traditional photon event detection circuits applied to macropixel units sacrifice spatial resolution to detect photon events, thus failing to output the address of a single pixel within the macropixel unit.

[0016] 2. This invention effectively solves two problems existing in the traditional photon event detection circuit. Firstly, the TIMING signal only goes high after the window signal WIN ends, thus fixing the time between the TIMING signal and the first arriving photon signal to the duration of a detection window. Secondly, this invention latches the SPAD state of the trigger detection window WIN through an address encoding circuit and outputs a corresponding address encoding response, enabling further differentiation of the trigger positions within the macropixel unit, thereby improving the spatial resolution of the laser rangefinder.

[0017] 3. The single-photon detector of the present invention can ensure both resolution and accuracy in acquiring echo photons in a photon event detection circuit with address encoding function. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a block diagram of an event-detection type single-photon detector with address encoding function.

[0019] Figure 2 This is a block diagram of the quenching circuit.

[0020] Figure 3 This is a block diagram of a photon event detection circuit.

[0021] Figure 4 This is a block diagram of an address encoding circuit.

[0022] Figure 5 This is the timing diagram for the photon event detection circuit.

[0023] Figure 6 This is a simulation diagram of a photon event detection circuit. Detailed Implementation

[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0026] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0027] Reference Figures 1-4 This is a circuit structure diagram of the main modules in this invention. This invention provides an event detection type single-photon detector with address encoding function; the overall circuit structure is as follows. Figure 1 As shown, it includes the following: The system comprises a quenching circuit, a photon event detection circuit, and an address encoding circuit. The input terminals of the quenching circuit are V1~V4 and Vc, respectively; V1~V4 are connected to the anode of the SPAD device, and Vc is connected to an external voltage control signal. The output terminals of the quenching circuit are S1~S4, connected to the input terminals I1~I4 of the photon event detection circuit and the input terminals T1~T4 of the address encoding circuit, respectively. The input terminals of the photon event detection circuit are I1~I4, P1, P2, R, and VP, respectively; I1~I4 are connected to the four photon quenching signals output from the quenching circuit; P1 and P2 are connected to binary encoding signals, serving as the photon threshold of the photon event detection circuit; R is connected to a reset signal; and VP is connected to a 0~1.8V voltage signal, serving as the window width signal for controlling the photon event detection circuit. The output terminals of the photon event detection circuit are TIMING and WIN, respectively connected to the INT and INWIN terminals of the address encoding circuit. The input terminals of the address encoding circuit are T1~T4, INT and INWIN, respectively; wherein T1~T4 are connected to the four photon quenching signals output by the quenching circuit, INT is connected to the TIMING terminal of the photon event detection circuit, and INWIN is connected to the WIN terminal of the photon event detection circuit.

[0028] The structure of the quenching circuit is as follows: Figure 2 As shown, the circuit includes four NMOS transistors, two PMOS transistors, one OR gate, and one inverter. The four NMOS transistors are denoted as NM1, NM2, NM3, and NM4; the two PMOS transistors are denoted as PM1 and PM2; the OR gate is denoted as OR; and the inverter is denoted as INV. The drain, source, and gate of NM1 are connected to the SPAD anode / NM2 source, ground, and the external voltage control terminal Vc / NM2 gate, respectively. The drain, source, and gate of NM2 are connected to the PM1 gate / NM3 gate, the NM1 drain, and the external voltage control terminal Vc / NM2 gate, respectively. The drain, source, and gate of NM3 are connected to the PM1 drain / NM4 gate, ground, and the NM2 drain / PM1 gate, respectively. The drain, source, and gate of NM4 are connected to the PM2 drain / OR gate OR input stage A1, ground, and the PM1 drain / NM3 drain / OR gate OR input stage A2, respectively. The drain, source, and gate of PM1 are connected to the N... M3 drain / NM4 gate / OR gate input stage A2, power supply, NM2 drain / NM3 gate; PM2 drain, source, and gate are respectively connected to NM4 drain / OR gate input stage A1, power supply, OR gate output stage O / inverter input I; OR gate inputs A1 and A2 are respectively connected to NM4 drain / PM2 drain, NM3 drain / NM4 gate / PM1 drain; OR gate output O is respectively connected to PM2 gate / inverter INV input stage I; inverter INV input is respectively connected to PM2 gate / OR gate output stage O; inverter INV output is connected to photon event detection circuit input stage.

[0029] The structure of the photon event detection circuit is as follows: Figure 3As shown, it includes three D flip-flops, two delay units, four inverters, five AND gates, and five OR gates. The three D flip-flops are denoted as DFF1, DFF2, and DFF3; the two delay units are denoted as Delay1 and Delay2; the four inverters are denoted as INV1, INV2, INV3, and INV4; the five AND gates are denoted as AND1, AND2, AND3, AND4, and AND5; and the five OR gates are denoted as OR1, OR2, OR3, OR4, and OR5. DFF1 inputs D, Clk, and R are connected to power supply VDD, OR5 output CK, and AND5 output OUTR, respectively; DFF1 output Q is connected to INV1 and AND1 inputs; DFF2 inputs D, Clk, and R are connected to DFF2 output Qb, OR5 output CK, and AND5 outputs, respectively; DFF2 output Q is connected to OR1 input, Qb is connected to DFF2 input D and DFF3 input Clk; DFF3 input Clk is connected to DFF2 input D and DFF2 output Qb; DFF3 input D is connected to DFF3... Output terminal Qb; Output terminals Q and Qb of DFF3 are connected to the input terminals of OR2 and D of DFF3, respectively; Input terminals of delay unit Delay1 are connected to the output terminal of INV1 and the delay control voltage VP, respectively; Output terminal of delay unit Delay1 is connected to the input terminal of INV2; Input terminals of delay unit Delay2 are connected to the output terminal of AND2 and the delay control voltage VP, respectively; Output terminal of delay unit Delay2 is connected to the input terminal of INV4; Input terminal of INV1 is connected to the output terminal Q of DFF1 and the input terminal of AND1; Output terminal of INV1 is connected to the input terminal of delay unit Delay1. The input terminal of INV2 is connected to the output terminal of delay unit Delay1; the output terminal of INV2 is connected to the input terminal of AND1; the input terminal of INV3 is connected to the output terminal WIN of AND1; the output terminal of INV3 is connected to the input terminal of AND3; the input terminal of INV4 is connected to the output terminal of delay unit Delay2; the output terminal of INV4 is connected to the input terminal of AND3; the two input terminals of AND1 are connected to the output terminal Q of DFF1, the input terminal of INV1, and the output terminal of INV2 respectively; the output terminal of AND1 is connected to the input terminal of INV3; the input terminals of AND2 are connected to the output terminals of OR1 and OR2 respectively. The output of AND2 is connected to the input of the delay unit Delay2; the input of AND3 is connected to the outputs of INV3 and INV4 respectively; the output of AND3 outputs the photon detection coincidence signal TIMING; the input of AND4 is connected to the output of INV4 and the external reset signal R respectively; the output of AND4 is connected to the input of AND5; the input of AND5 is connected to the output of AND4 and the external reset signal R respectively; the output of AND5 is connected to the reset terminals R of DFF1, DFF2 and DFF3; the input of OR1 is connected to the threshold control signal P1 and the output Q of DFF2 respectively.The output of OR1 is connected to the input of AND2; the input of OR2 is connected to the threshold control signal P2 and the output Q of DFF3, respectively; the output of OR2 is connected to the input of AND2; the input of OR3 is connected to the inputs I1 and I2 of the photon event detection circuit, respectively; the output of OR3 is connected to the input of OR5; the input of OR4 is connected to the inputs I3 and I4 of the photon event detection circuit, respectively; the output of OR4 is connected to the input of OR5; the input of OR5 is connected to the outputs of OR3 and OR4, respectively; the output of OR5 is connected to the Clk terminal of DFF1 and DFF2.

[0030] The structure of the address encoding circuit is as follows: Figure 4As shown, it includes four D flip-flops, two AND gates, one three-input OR gate, two PMOS transistors, and four NMOS transistors. The four D flip-flops are denoted as DFF4, DFF5, DFF6, and DFF7; the two AND gates are denoted as AND6 and AND7; the three-input OR gate is denoted as OR6; the two PMOS transistors are denoted as PM1 and PM2; and the four NMOS transistors are denoted as NM1, NM2, NM3, and NM4. The inputs D, Clk, and R of DFF4 are connected to the input T1 of the address encoding circuit, the window signal INWIN, and the output ROUT of AND7, respectively; the output of DFF4 is connected to the gate of NM1. The inputs D, Clk, and R of DFF5 are connected to the input T2 of the address encoding circuit, the window signal INWIN, and the output ROUT of AND7, respectively; the output of DFF5 is connected to the gate of NM2. The inputs D, Clk, and R of DFF6 are connected to the input T3 of the address encoding circuit, the window signal INWIN, and the output ROUT of AND7, respectively; the output of DFF6 is connected to the gate of NM3. The inputs D, Clk, and R of DFF7 are connected to the input T4 of the address encoding circuit, the window signal INWIN, and the output ROUT of AND7, respectively; the output of DFF7 is connected to the gate of NM4. The inputs of AND6 are connected to the drains of PM1 and PM2, respectively. OR6 is a three-input OR gate, with its three inputs connected to the output of AND6, the input INT of the address encoding circuit, and the output of the address encoding circuit, respectively. The input terminal is INWIN; the output terminal of OR6 is connected to one input terminal of AND7, and the other input terminal of AND7 is connected to an external active-low reset signal R; the output terminal ROUT of AND7 is connected to the reset terminals R of DFF4, DFF5, DFF6, and DFF7; the gate and source of PM1 are grounded to VSS and the power supply VDD, respectively; the drain of PM1 is connected to the drains of NM2 and NM3 and the input terminal ADDR1 of AND6; the gate and source of PM2 are grounded to VSS and the power supply VDD, respectively; the drain of PM2 is connected to... The drains of NM1 and NM4 and the input terminal ADDR0 of AND6 are connected; the gate, source, and drain of NM1 are connected to the output terminal Q of DFF4, ground VSS, and the drain of PM2, respectively; the gate, source, and drain of NM2 are connected to the output terminal Q of DFF5, ground VSS, and the drain of PM1, respectively; the gate, source, and drain of NM3 are connected to the output terminal Q of DFF6, ground VSS, and the drain of PM1, respectively; the gate, source, and drain of NM4 are connected to the output terminal Q of DFF7, ground VSS, and the drain of PM1, respectively.

[0031] Reference Figure 5 A complete duty cycle of the event-detecting single-photon detector with address encoding function proposed in this invention includes the following: S1: After detecting a photon signal, a detection window WIN is generated and the SPAD trigger state is latched.

[0032] Specifically, all D flip-flops in this invention employ a low-level reset. Each time the circuit is powered on, a low-level pulse needs to be input to the input terminal R to reset all D flip-flops. After reset, the output terminals Q and Qb of the D flip-flops output low and high levels, respectively. After the reset, the level states of each node in the circuit will not change until the photon signal arrives. The four photon quenching signals S1~S4 are input to the I1~I4 terminals of the photon event detection circuit, and simultaneously to the T1~T4 terminals of the address encoding circuit. When any one of I1~I4 generates a photon signal, the output of OR5 will generate a high-level signal CK with the same pulse width as the photon signal. Signal CK will trigger DFF1. Since the D input of DFF1 is connected to the power supply VDD, the Q output of DFF1 will be high, causing AND1 to output a high-level signal. This causes the output WIN of the photon event detection circuit to change from low to high. The output WIN of the photon event detection circuit is connected to the input INWIN of the address encoding circuit. When WIN becomes high, INWIN also becomes high, causing DFF4~7 to latch the states of T1~T4. The states of T1~T4 are saved as SPAD1~4. SPAD1~4 are connected to the gates of NM1~4. When the gate of NM1 or NM4 becomes high, the corresponding NMOS transistor is turned on, causing the lower address bit ADDR0 to change from high to low. When the gate of NM2 or NM3 becomes high, the corresponding NMOS transistor is turned on, causing the higher address bit ADDR1 to change from high to low. The initial state of ADDR1 and ADDR0 is "11". After the detection window is generated, their level state is determined by the latched SPAD trigger state, which is used to characterize the address encoding response corresponding to the trigger SPAD.

[0033] S2: Determine whether the number of photons meets the threshold.

[0034] DFF2 and DFF3 form a two-bit counter. The outputs Q of DFF2 and DFF3 are the low-order and high-order bits of the two-bit counter, respectively. As the number of photons increases, the output states of the counter are "00", "01", "10", and "11" sequentially. The low-order and high-order bits of the counter are connected to the inputs of OR1 and OR2, respectively. The other inputs of OR1 and OR2 are connected to P1 and P2. P1 and P2 are externally set photon thresholds. When the number of photons received by the photon event detection circuit reaches the set photon threshold, TIMING will go high; otherwise, it will remain low. P1 and P2 can be set to "00", "01", "10", and "11".

[0035] If we denote the output Q of DFF2 as the low-order bit Q0 of the counter, and the output Q of DFF3 as the high-order bit Q1 of the counter, then the output of OR1 is the logical OR of P1 and Q0, the output of OR2 is the logical OR of P2 and Q1, and the output of AND2 satisfies the following logical relationship: AND2 = (P1 or Q0) AND (P2 or Q1). Therefore, when P1P2 is set to "00", AND2 outputs a high level only when the counter state is "11"; when P1P2 is set to "01", AND2 outputs a high level as long as the low-order bit Q0 of the counter is high; when P1P2 is set to "10", AND2 outputs a high level as long as the high-order bit Q1 of the counter is high; when P1P2 is set to "11", AND2 remains high. When AND2 outputs a high level, and the detection window WIN ends, TIMING outputs a high level, indicating that the photon event within the window meets the preset detection conditions.

[0036] S3: Reset all circuits.

[0037] Specifically, upon receiving a photon, the output Q of DFF1 in the photon event detection circuit goes high, causing the input of the delay unit Delay1 to go low. After a delay period, Delay1 outputs a high level, causing the output voltage of INV2 to go low. For ease of explanation, the output node of INV2 is denoted as INR, where the delay time is determined by the delay control voltage VP. When INR goes low, it causes the output WIN of AND1 to go low, and through AND5, it causes OUTR to go low. The low-level OUTR resets DFF1, DFF2, and DFF3, causing all D flip-flop outputs Q to go low again. This low level, after passing through the delay unit Delay1, causes INR to go high again.

[0038] In the address latch circuit, the initial state of ADDR0 and ADDR1 is "11". When a photon is received, if a state of "0" appears in ADDR0 and ADDR1, AND6 will output a low level. OR6 will wait for INT and INWIN to go low before outputting a low level. This low level causes ROUT to go low, thereby resetting DFF4~7.

[0039] like Figure 6 As shown, based on the circuit structure and working method, the present invention provides waveform diagrams of key modules to further describe its effects. Figure 6This is a simulation diagram of the overall circuit function when P1 and P2 are set to state "10" and the time window WIN is 2 ns. If ≥2 photons are detected within the time window, a coincidence detection TIMING signal is generated. The TIMING signal differs from the first photon signal Photon1 by 2.4 ns. This is because the TIMING signal is always generated at the falling edge of the time window WIN. Therefore, the fixed error between the TOF value measured by the detector and the actual TOF value is the time window time (2 ns) plus the circuit delay time (0.4 ns). It should be further noted that under the same simulation conditions, when scanning the temperature (scanning range -20℃ ~ 85℃), the time jitter of the TIMING signal is only 10 ps. Furthermore, to improve the circuit's adaptability to the environment, not only is the photon threshold adjustable, but the time window can also be adjusted by controlling the voltage, ranging from 1 ns to 10 ns. The function of the pixel-level address encoding circuit is to latch the state of the SPAD device triggering the detection window within a pixel and output the corresponding address encoding response through the address encoding circuit, thereby expanding the spatial resolution of the detector. Circuit simulation results are as follows Figure 6 As shown, after the time window WIN is generated, the address encoding circuit latches the SPAD device state of the trigger detection window within the time window and outputs the corresponding address encoding response (ADDR1 is the high bit, ADDR0 is the low bit). For example, in the simulation, the address encoding response for Photon1 is "01", and the address encoding response for Photon2 is "10". It is worth noting that the address encoding circuit always starts after the time window WIN is generated, even if the number of photons within that time window has not reached the set threshold.

[0040] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A single-photon detector with address encoding function, characterized in that, The system includes four SPAD devices, a quenching circuit, a photon event detection circuit, and an address encoding circuit. The anodes of the four SPAD devices are respectively connected to the input terminals V1~V4 of the quenching circuit. The quenching circuit is used to quench the avalanche signals generated by the SPAD devices and output four photon quenching signals S1~S4. The input terminals I1~I4 of the photon event detection circuit receive the four photon quenching signals S1~S4 respectively, and generate a window signal WIN and a coincidence detection signal TIMING according to the threshold control signals P1, P2 and the window width control voltage VP. The input terminals T1~T4 of the address encoding circuit receive the four photon quenching signals S1~S4 respectively, and latch the state of the SPAD device that triggers the detection window when the window signal WIN is valid, and output the corresponding address encoding response.

2. A single-photon detector with address encoding function for detecting background light noise events, as described in claim 1, is characterized in that, The photon detector includes a Vc terminal connected to a 0~1.8V voltage signal; the input terminals of the photon event detection circuit are I1~I4, P1, P2, R, and VP, wherein I1~I4 are connected to four photon quenching signals output by the quenching circuit; P1 and P2 are connected to high / low level signals to control the photon threshold of the photon event detection circuit; R is connected to a reset signal; VP is connected to a 0~1.8V voltage signal to control the window width of the photon event detection circuit; the output terminals of the photon event detection circuit are TIMING and WIN, which are respectively connected to the INT and INWIN terminals of the address encoding circuit; the input terminals of the address encoding circuit are T1~T4, INT, and INWIN, wherein T1~T4 are connected to the photon quenching signals output by the quenching circuit; the INT terminal is connected to the TIMING terminal of the photon event detection circuit; and the INWIN terminal is connected to the WIN terminal of the photon event detection circuit.

3. A single-photon detector with address encoding function for detecting background light noise events, as described in claim 1, is characterized in that... The photon event detection circuit includes DFF1, DFF2, DFF3, Delay1, Delay2, INV1~INV4, AND1~AND5, and OR1~OR5.

4. A single-photon detector with address encoding function for detecting background light noise events, as described in claim 1, is characterized in that, The quenching circuit includes four NMOS transistors, two PMOS transistors, one OR gate, and one inverter. The four NMOS transistors are denoted as NM1, NM2, NM3, and NM4; the two PMOS transistors are denoted as PM1 and PM2; the OR gate is denoted as OR; and the inverter is denoted as INV. The drain, source, and gate of NM1 are connected to the anode of a single SPAD device / the source of NM2, ground, and the external voltage Vc / the gate of NM2, respectively. The drain, source, and gate of NM2 are connected to the gate of PM1 / the gate of NM3, the drain of NM1, and the external voltage Vc / the gate of NM2, respectively. The drain, source, and gate of NM3 are connected to the drain of PM1 / the gate of NM4, ground, and the drain of NM2 / the gate of PM1, respectively. The drain, source, and gate of NM4 are connected to the drain of PM2 / OR gate. OR gate input stage A1, ground, PM1 drain / NM3 drain / OR gate input stage A2; PM1 drain, source, and gate are connected to NM3 drain / NM4 gate / OR gate input stage A2, power supply, NM2 drain / NM3 gate respectively; PM2 drain, source, and gate are connected to NM4 drain / OR gate input stage A1, power supply, OR gate output stage O / inverter input stage I respectively; OR gate input terminals A1 and A2 are connected to NM4 drain / PM2 drain, NM3 drain / NM4 gate / PM1 drain respectively; OR gate output terminal O is connected to PM2 gate / inverter INV input stage I respectively; inverter INV input terminal is connected to PM2 gate / OR gate output stage O respectively; inverter INV output terminal is connected to photon event detection circuit input stage.

5. A single-photon detector with address encoding function for detecting background light noise events, as described in claim 1, is characterized in that, DFF2 and DFF3 form a two-bit counter used to count the number of photons received within the detection window WIN.

6. A single-photon detector with address encoding function for detecting background light noise events, as described in claim 1, is characterized in that, The threshold control signals P1 and P2 are used to adjust the detection conditions of the photon event detection circuit.

7. A single-photon detector with address encoding function for detecting background light noise events, as described in claim 1, is characterized in that, The window width control voltage VP is used to adjust the duration of the detection window WIN.

8. A single-photon detector with address encoding function for detecting background light noise events, as described in claim 1, is characterized in that, The coincidence detection signal TIMING is generated after the detection window WIN ends.

9. A single-photon detector with address encoding function for detecting background light noise events, as described in claim 1, is characterized in that, The address encoding circuit is used to latch the SPAD device state of the trigger detection window WIN and output the corresponding address encoding response to provide auxiliary judgment information on the trigger position inside the macro pixel unit.

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