Electronic clinical thermometer

Abstract

The embodiment of the present application provides an electronic thermometer, which comprises an RC oscillation module, a frequency division module, a resistance open circuit detection module and a capacitance open circuit detection module. The RC oscillation module comprises a thermistor, a reference resistor and an oscillation capacitor. The thermistor and the reference resistor are alternated with the oscillation capacitor to form an oscillator, which generates a first oscillation signal. The frequency division module is connected with the RC oscillation module and is used for frequency dividing the first oscillation signal to output a second oscillation signal. The resistance open circuit detection module is connected with the frequency division module and is used for outputting a first abnormal signal when at least one of the thermistor and the reference resistor is open-circuited according to the second oscillation signal. The capacitance open circuit detection module is connected with the RC oscillation module and is used for outputting a second abnormal signal when the oscillation capacitor is open-circuited according to the first oscillation signal. The electronic thermometer provided by the embodiment of the present application can automatically detect the open circuit conditions of the resistance and the capacitance of the electronic thermometer and give a reminder, so that the detection efficiency is high and the labor is saved.

Description

Technical Field

[0001] This application relates to the field of temperature measurement technology, and in particular to an electronic thermometer. Background Technology

[0002] In related technologies, electronic thermometers are mostly implemented using SOC chips, which require external connections of thermistors, reference resistors, and oscillation capacitors. Due to the small size of electronic thermometers, these components are often surface-mount devices. During assembly, it's easy for these components to be missing or have poor soldering. These issues are only discovered after assembly and temperature calibration in a constant-temperature water bath, causing significant inconvenience in production and increasing manual calibration and rework costs. Summary of the Invention

[0003] This application provides an electronic thermometer to solve at least some of the problems in the related art.

[0004] This application provides an electronic thermometer, comprising:

[0005] An RC oscillation module includes a thermistor, a reference resistor, and an oscillation capacitor, wherein the thermistor, the reference resistor, and the oscillation capacitor alternately form an oscillator to generate a first oscillation signal;

[0006] The frequency divider module is connected to the RC oscillation module and is used to divide the first oscillation signal to output a second oscillation signal.

[0007] A resistor open-circuit detection module, connected to the frequency divider module, is used to output a first abnormal signal based on the second oscillation signal when at least one of the thermistor and the reference resistor is open-circuited; and

[0008] A capacitor open-circuit detection module, connected to the RC oscillation module, is used to output a second abnormal signal when the oscillation capacitor is open, based on the first oscillation signal.

[0009] Optionally, the RC oscillation module further includes a pulse generation control circuit for controlling the duration of the oscillator formed by the thermistor and the oscillation capacitor to be equal to the duration of the oscillator formed by the reference resistor and the oscillation capacitor.

[0010] Optionally, when both the thermistor and the reference resistor are not open-circuited, the second oscillation signal is a pulse signal, and the resistor open-circuit detection module is used to output a first normal signal based on the pulse signal;

[0011] When at least one of the thermistor and the reference resistor is open-circuited, the second oscillation signal includes at least half of a constant signal. The open-circuit detection module is used to output the first abnormal signal based on the constant signal, and the first abnormal signal is different from the first normal signal.

[0012] Optionally, the open-circuit resistance detection module includes an RS flip-flop, a first D flip-flop, and a first latch. The set terminal of the RS flip-flop is connected to a first clock signal, and the reset terminal of the RS flip-flop is connected to the frequency divider module. The main output terminal of the RS flip-flop is connected to the data input terminal of the first D flip-flop, the clock input terminal of the first D flip-flop is connected to a second clock signal, the main output terminal of the first D flip-flop is connected to the input terminal of the first latch, and the output terminal of the first latch serves as the output terminal of the open-circuit resistance detection module.

[0013] Optionally, the period of the first clock signal is the same as the period of the second clock signal, and both are half the period of the second oscillation signal; the second oscillation signal and the first clock signal are at a low level at the beginning of each period, and the first clock signal includes a high-level pulse in each period, the high-level pulse being within the low-level period of the second oscillation signal; the first D flip-flop is rising-edge triggered, and the second clock signal includes a rising edge in each period, located at the beginning of each period.

[0014] Optionally, the first latch includes a second D flip-flop, which is rising-edge triggered. The clock input of the second D flip-flop is connected to the main output of the first D flip-flop, and the data input of the second D flip-flop is connected to a high level.

[0015] Optionally, when the oscillation capacitor is not open-circuited, the pulse period of the first oscillation signal is a first period; when the oscillation capacitor is open-circuited, the pulse period of the first oscillation signal is a second period; the first period is greater than the second period.

[0016] The capacitor open-circuit detection module is used to output a second normal signal according to the first cycle of the first oscillation signal;

[0017] The capacitor open-circuit detection module is used to output a second abnormal signal according to the second period of the first oscillation signal. The second abnormal signal is different from the second normal signal.

[0018] Optionally, the capacitor open-circuit detection module includes a plurality of T flip-flops and a second latch connected in sequence. The plurality of T flip-flops includes a first T flip-flop connected to the RC oscillation module, a second T flip-flop connected to the second latch, and an intermediate T flip-flop connected between the first T flip-flop and the second T flip-flop.

[0019] The reset terminals of the plurality of T flip-flops are connected to a third clock signal; the clock input terminal of the first T flip-flop is connected to the RC oscillation module; the inverted output terminals of the first T flip-flop and the intermediate T flip-flop are connected to the clock input terminals of adjacent T flip-flops; the main output terminal of the second T flip-flop is connected to the input terminal of the second latch; and the output terminal of the second latch serves as the output terminal of the capacitor open-circuit detection module.

[0020] Optionally, the difference between the period of the third clock signal and the first period of the first oscillation signal is a first difference, and the difference between the period of the third clock signal and the second period of the first oscillation signal is a second difference, wherein the second difference is greater than the first difference.

[0021] Optionally, the second latch includes a third D flip-flop, which is rising-edge triggered. The main output of the second T flip-flop is connected to the clock input of the third D flip-flop, and the data input of the third D flip-flop is connected to a high level.

[0022] Optionally, the electronic thermometer further includes a display module, which is connected to the resistance open circuit detection module and the capacitance open circuit detection module respectively, and is used to output the first abnormal signal and the second abnormal signal.

[0023] The electronic thermometer provided in this application incorporates a resistance open-circuit detection module and a capacitance open-circuit module, and connects the resistance open-circuit detection module to a frequency divider module. Based on a second oscillation signal, it outputs a first abnormal signal when at least one of the thermistor or the reference resistor is open-circuited. The capacitance open-circuit detection module is connected to an RC oscillation module, which outputs a second abnormal signal when the oscillating capacitor is open-circuited, based on the first oscillation signal. This allows for automatic detection of open-circuit conditions in the electronic thermometer's resistance and capacitance, providing a timely alert with high detection efficiency and reduced labor costs. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0025] Figure 1 This is a circuit diagram of an electronic thermometer in related technologies;

[0026] Figure 2A circuit diagram of an electronic thermometer is provided for one embodiment of this application;

[0027] Figure 3 for Figure 2 The circuit diagram shown is one embodiment of the pulse generation control circuit.

[0028] Figure 4 for Figure 2 The circuit diagram shown is of one embodiment of the resistance open-circuit detection module.

[0029] Figure 5 for Figure 2 The timing diagram shown is for the resistor open-circuit detection module when neither the thermistor nor the reference resistor is open-circuited.

[0030] Figure 6 for Figure 2 The timing diagram shown is for the resistor open-circuit detection module when both the thermistor and the reference resistor are open-circuited.

[0031] Figure 7 for Figure 2 The timing diagram shown is for the resistor open-circuit detection module when at least one of the thermistor and the reference resistor is open.

[0032] Figure 8 for Figure 2 The circuit diagram shown is of one embodiment of the capacitor open-circuit detection module.

[0033] Figure 9 for Figure 2 The timing diagram shown is for the capacitor open-circuit detection module when the oscillating capacitor is not open-circuited.

[0034] Figure 10 for Figure 2 The timing diagram shown is for the capacitor open-circuit detection module when the oscillating capacitor is open.

[0035] Figure label:

[0036] Electronic thermometer 1, RC oscillation module 10, thermistor 11, reference resistor 12, oscillation capacitor 13, pulse generation control circuit 14, first switch 141, second switch 142, third switch 143, power supply 144, ground terminal 145, frequency divider module 20, frequency divider coefficient lookup table module 21, counter 22, resistor open circuit detection module 30, RS flip-flop 31, first D flip-flop 32, first latch 33, first clock signal 34, second clock signal 35, capacitor open circuit detection module 40, first T flip-flop 41, second T flip-flop 42, intermediate T flip-flop 43, second latch 44, third clock signal 45, display module 50. Detailed Implementation

[0037] This application provides an electronic thermometer. The electronic thermometer of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0038] Please refer to Figure 1 , Figure 1 This is a circuit diagram of an electronic thermometer in related technologies. For example... Figure 1 As shown, the electronic thermometer includes a thermistor, a reference resistor, an oscillation capacitor, a pulse generation control circuit, a frequency divider module, a counter, a frequency divider coefficient lookup table module, and an LCD driver module. The pulse generation control circuit controls the reference resistor and the oscillation capacitor to alternately form an oscillator. The output of the pulse generation control circuit is connected to the input of the frequency divider module, the output of the frequency divider module is connected to the input of the counter, the input of the frequency divider coefficient lookup table module is connected to the counter, the output of the frequency divider coefficient lookup table module is connected to the frequency divider module, and the input of the LCD driver module is connected to the counter. Figure 1 Among the related technologies shown, pulse signal counting is generated using RC oscillation, which is independent of power supply voltage and does not require an A / D module or a reference module, resulting in stable circuit operation. The counting and frequency division method requires only 11 groups of 8-bit division coefficients, resulting in small storage space and low chip implementation cost.

[0039] exist Figure 1 In the related technologies shown, pulse signal counting is generated by RC oscillation. Since the electronic thermometer is small in size, the reference resistor, thermistor and oscillation capacitor are surface-mount structures. During the assembly process, thermistor, reference resistor and oscillation capacitor are prone to being missing or having open circuits due to poor soldering, which makes it impossible to measure temperature. Moreover, the detection of open circuits in thermistor, reference resistor and oscillation capacitor is time-consuming and labor-intensive, with low detection efficiency and wasted labor costs.

[0040] To address the issues of time-consuming, labor-intensive, inefficient, and costly detection of open circuits in thermistors, reference resistors, and oscillation capacitors in related technologies, this application provides an electronic thermometer that can automatically detect open circuits in the resistance and capacitance of the electronic thermometer and provide alerts, resulting in high detection efficiency and labor savings.

[0041] Please refer to Figure 2 , Figure 2 A circuit diagram of an electronic thermometer 1 is provided for one embodiment of this application. For example... Figure 2As shown, the electronic thermometer 1 includes an RC oscillation module 10, a frequency divider module 20, a resistance open-circuit detection module 30, and a capacitor open-circuit detection module 40. The RC oscillation module includes a thermistor 11, a reference resistor 12, and an oscillation capacitor 13. The thermistor 11, reference resistor 12, and oscillation capacitor 13 alternately form an oscillator to generate a first oscillation signal. The frequency divider module 20 is connected to the RC oscillation module 10 and is used to divide the first oscillation signal to output a second oscillation signal. The resistance open-circuit detection module 30 is connected to the frequency divider module 20 and is used to output a first abnormal signal when at least one of the thermistor 11 and reference resistor 12 is open, based on the second oscillation signal. The capacitor open-circuit detection module 40 is connected to the RC oscillation module 10 and is used to output a second abnormal signal when the oscillation capacitor 13 is open, based on the first oscillation signal.

[0042] The electronic thermometer 1 provided in this application incorporates a resistance open-circuit detection module 30 and a capacitor open-circuit module 40, with the resistance open-circuit detection module 30 connected to a frequency divider module 20. This allows the thermometer to output a first abnormal signal when at least one of the thermistor 11 or the reference resistor 12 is open, based on a second oscillation signal. The capacitor open-circuit detection module 40 is connected to an RC oscillation module 10, allowing it to output a second abnormal signal when the oscillating capacitor 13 is open, based on the first oscillation signal. This allows for automatic detection of the resistance and capacitor open-circuit conditions of the electronic thermometer 1, providing a timely alert with high detection efficiency and reduced labor costs.

[0043] exist Figure 2 In the illustrated embodiment, the RC oscillation module 10 further includes a pulse generation control circuit 14, used to control the duration of the oscillator formed by the thermistor 11 and the oscillating capacitor 13 to be equal to the duration of the oscillator formed by the reference resistor 12 and the oscillating capacitor 13. This ensures that in the first oscillation signal and the frequency-divided second oscillation signal generated by the RC oscillation module 10, the oscillation signal formed by the thermistor 11 and the oscillating capacitor 13 and the oscillator formed by the reference resistor 12 and the oscillating capacitor 13 each account for half of the oscillation signal duration. This facilitates the determination of the frequency division coefficient of the frequency division module 20 through the frequency division coefficient lookup table module 21 based on the difference between the number of oscillations of the oscillator formed by the thermistor 11 and the oscillating capacitor 13, and the calculation of the number of pulses of the second oscillation signal by the counter 22 to obtain temperature information.

[0044] Please refer to Figure 3 , Figure 3 for Figure 2 The circuit diagram shown represents one embodiment of the pulse generation control circuit; in Figure 3In the illustrated embodiment, the pulse generation control circuit 14 may include a first switch 141, a second switch 142, a third switch 143, a power supply 144, and a ground terminal 145. The first switch 141 is connected between the thermistor 11 and the power supply 144, the second switch 142 is connected between the reference resistor 12 and the power supply 144, and the third switch 143 is connected between the oscillating capacitor 13 and the ground terminal 145. By controlling the conduction time of the first switch 141 and the second switch 142 to be equal, the duration for which the thermistor 11 and the oscillating capacitor 13 form an oscillator can be made equal to the duration for which the reference resistor 12 and the oscillating capacitor 13 form an oscillator.

[0045] Thermistor 11, reference resistor 12, and oscillating capacitor 13 alternately form an oscillator to generate a first oscillation signal. The duration of the oscillator formed by thermistor 11 and oscillating capacitor 13 is equal to the duration of the oscillator formed by reference resistor 12 and oscillating capacitor 13. Therefore, in the second oscillation signal, half is the oscillation signal generated by the oscillator composed of thermistor 11 and oscillating capacitor 13 after frequency division processing, and the other half is the oscillation signal generated by the oscillator composed of reference resistor 12 and oscillating capacitor 13 after frequency division processing. Furthermore, in the second oscillation signal, the oscillation signal generated by the oscillator composed of thermistor 11 and oscillating capacitor 13 after frequency division processing and the oscillation signal generated by the oscillator composed of reference resistor 12 and oscillating capacitor 13 after frequency division processing appear alternately.

[0046] When both thermistor 11 and reference resistor 12 are not open-circuited, the oscillation signal generated by the oscillator composed of thermistor 11 and oscillating capacitor 13, after frequency division processing, becomes a pulse signal. The oscillation signal generated by the oscillator composed of reference resistor 12 and oscillating capacitor 13, after frequency division processing, also becomes a pulse signal. The second oscillation signal is a pulse signal. The resistor open-circuit detection module 30 is used to output a first normal signal based on the pulse signal.

[0047] When at least one of the thermistor 11 and the reference resistor 12 is open-circuited, the second oscillation signal comprises at least half of the constant signal. The open-circuit detection module 30 is used to output a first abnormal signal based on the constant signal, the first abnormal signal being different from the first normal signal.

[0048] Specifically, when both thermistor 11 and reference resistor 12 are open-circuited, the oscillation signal generated by the oscillator composed of thermistor 11 and oscillating capacitor 13, after frequency division processing, is a constant signal. Similarly, the oscillation signal generated by the oscillator composed of reference resistor 12 and oscillating capacitor 13, after frequency division processing, is also a constant signal. Therefore, when both thermistor 11 and reference resistor 12 are open-circuited, the second oscillation signal is a constant signal.

[0049] When the thermistor 11 is open-circuited and the reference resistor 12 is not open-circuited, the oscillation signal generated by the oscillator composed of the thermistor 11 and the oscillating capacitor 13, after frequency division processing, is a constant signal; the oscillation signal generated by the oscillator composed of the reference resistor 12 and the oscillating capacitor 13, after frequency division processing, is a pulse signal. When the thermistor 11 is not open-circuited and the reference resistor 12 is open-circuited, the oscillation signal generated by the oscillator composed of the thermistor 11 and the oscillating capacitor 13, after frequency division processing, is a pulse signal; the oscillation signal generated by the oscillator composed of the reference resistor 12 and the oscillating capacitor 13, after frequency division processing, is a constant signal.

[0050] When both thermistor 11 and reference resistor 12 are open, the second oscillation signal is a constant signal. When one of thermistor 11 and reference resistor 12 is open, the second oscillation signal includes half of a constant signal and half of a pulse signal, and the constant signal and the pulse signal appear alternately.

[0051] Understandably, the open-circuit detection module 30 outputs different signals depending on whether the second oscillation signal is different when at least one of the thermistor 11 and the reference resistor 12 is open or when neither the thermistor 11 nor the reference resistor 12 is open. These different signals reflect whether an open circuit exists in the thermistor 11 and the reference resistor 12.

[0052] Please refer to Figure 4 , Figure 4 for Figure 2 The circuit diagram shown illustrates one embodiment of the resistance open-circuit detection module 30. Figure 4 In the illustrated embodiment, the open-circuit resistance detection module 30 includes an RS flip-flop 31, a first D flip-flop 32, and a first latch 33. The set terminal of the RS flip-flop 31 is connected to a first clock signal 34, and the reset terminal of the RS flip-flop 31 is connected to a frequency divider module 20. The main output terminal of the RS flip-flop 31 is connected to the data input terminal of the first D flip-flop 32, the clock input terminal of the first D flip-flop 32 is connected to a second clock signal 35, and the main output terminal of the first D flip-flop 32 is connected to the input terminal of the first latch 33. The output terminal of the first latch 33 serves as the output terminal of the open-circuit resistance detection module 30.

[0053] Please refer to Figure 5 , Figure 6 and Figure 7 , Figure 5 for Figure 2 The timing diagram of the resistor open-circuit detection module 30 is shown when both the thermistor 11 and the reference resistor 12 are not open-circuited. Figure 6 for Figure 2 The timing diagram of the resistor open-circuit detection module 30 is shown when both the thermistor 11 and the reference resistor 12 are open-circuited. Figure 7 for Figure 2The timing diagram shown is for the open-circuit detection module 30 when at least one of the thermistor 11 and the reference resistor 12 is open.

[0054] like Figure 5 , Figure 6 and Figure 7 As shown, the periods of the first clock signal 34 and the second clock signal 35 are the same, and both are half the period of the second oscillation signal. The first clock signal 34 and the second clock signal 35 are the clock signals provided by the system clock of the electronic thermometer 1. After processing by the frequency divider module 20, the period of the second oscillation signal is twice the period of the first clock signal 34 and also twice the period of the second clock signal 35. This facilitates the separate processing of the partial oscillation signals generated by the thermistor 11 and the oscillation capacitor 13, and the partial oscillation signals generated by the reference resistor 12 and the oscillation capacitor 13, within adjacent periods of the first clock signal 34 and the second clock signal 35, respectively.

[0055] The first clock signal 34 is a clock signal with a period of 0.5 seconds, and the second clock signal 35 is a square wave signal with a period of 0.5 seconds. The second oscillation signal is an oscillation signal generated by an RC oscillator after frequency division processing, with a period of 1 second. Since the electronic thermometer detects the temperature once every 1 second, the pulse generation control circuit 14 alternately turns on the reference resistor 12 and the thermistor 11, and controls the reference resistor 12 and the thermistor 11 to be turned on for the same duration. Therefore, the time that the reference resistor 12 is connected is equal to the time that the thermistor 11 is connected, both being 0.5 seconds. Thus, the open circuit detection module 30 also detects once every 0.5 seconds.

[0056] exist Figure 5 , Figure 6 and Figure 7 In the diagram, signal A is the signal at the inverted output terminal of RS flip-flop 31, signal D is the signal at the main output terminal of RS flip-flop 31, signal Q is the signal at the main output terminal of the first D flip-flop 32, and signal Q_Err1 is the signal at the main output terminal of the first latch 33.

[0057] The second oscillation signal and the first clock signal 34 are both low at the beginning of each cycle, causing the main output terminal D of the RS flip-flop 31 to output a low level. Within each cycle, the first clock signal 34 includes a high-level pulse, the duration of which falls within the low-level period of the second oscillation signal. This causes the main output terminal D of the RS flip-flop 31 to output a high level. If the second oscillation signal is a pulse signal within the period of the first clock signal 34, the main output terminal D of the RS flip-flop 31 will output a low level until the second oscillation signal reaches a high level.

[0058] exist Figure 5In the first clock signal 34, the second oscillation signal is a pulse signal in each cycle of the first clock signal 34. When the high-level pulse arrives in each cycle of the first clock signal 34, the main output terminal D of the RS flip-flop 31 outputs a high level. When the second oscillation signal is high, the main output terminal D of the RS flip-flop 31 outputs a low level.

[0059] exist Figure 6 In this circuit, the second oscillation signal is a constant signal and a low-level signal in each cycle of the first clock signal 34. When a high-level pulse arrives in each cycle of the first clock signal 34, the main output terminal D of the RS flip-flop 31 outputs a high level and maintains a high level.

[0060] exist Figure 7 In the first clock signal 34, the second oscillation signal is a pulse signal during the first cycle and a constant signal during the second cycle. At the end of the first cycle of the first clock signal 34, the main output terminal D of the RS flip-flop 31 outputs a low level, and at the end of the second cycle of the first clock signal 34, the main output terminal D of the RS flip-flop 31 outputs a high level.

[0061] like Figure 5 , Figure 6 and Figure 7 As shown, the first D flip-flop 32 is rising-edge triggered. Within each cycle, the second clock signal 35 includes a rising edge at the beginning of each cycle. The first D flip-flop 32 outputs a low level at the end of each cycle of the first clock signal 34, when the main output terminal D of the RS flip-flop 31 is low. Conversely, the first D flip-flop 32 outputs a high level at the end of each cycle of the first clock signal 34, when the main output terminal D of the RS flip-flop 31 is high.

[0062] exist Figure 5 In the process, the second oscillation signal is a pulse signal in each cycle of the first clock signal 34 and the second clock signal 35. At the rising edge of the second clock signal 35, the main output terminal D of the RS flip-flop 31 is at a low level. Therefore, the main output terminal Q of the first D flip-flop 32 is always at a low level, and the first latch 33 outputs a low-level first normal signal.

[0063] exist Figure 6 In this circuit, the second oscillation signal is a constant signal within each cycle of the first clock signal 34, and the main output terminal D of the RS flip-flop 31 is high at the end of each cycle of the first clock signal 34. At the rising edge of the second clock signal 35, the main output terminal D of the RS flip-flop 31 is high, so the main output terminal Q of the first D flip-flop 32 outputs a rising edge signal, and the first latch 33 outputs a high-level second abnormal signal and latches it.

[0064] exist Figure 7 In the first clock signal 34, the second oscillation signal is a pulse signal during the first cycle and a constant signal during the second cycle. The main output terminal D of RS flip-flop 31 is high at the end of the cycle of the first clock signal 34 corresponding to the constant signal. At the rising edge of the second clock signal 35, the main output terminal D of RS flip-flop 31 is high, so the main output terminal Q of the first D flip-flop 32 outputs a rising edge signal, and the first latch 33 outputs a high-level second abnormal signal and latches it.

[0065] exist Figure 4 In the illustrated embodiment, the first latch 33 includes a second D flip-flop, which is rising-edge triggered. The clock input of the second D flip-flop is connected to the main output of the first D flip-flop 32, and the data input of the second D flip-flop is connected to a high level. When the main output Q of the first D flip-flop 32 is always low, the main output of the second D flip-flop is always low. When the main output of the first D flip-flop 32 outputs a rising edge, the main output of the second D flip-flop outputs a high level and latches the data.

[0066] By including a second D flip-flop in the first latch 33, the rising edge signal output from the main output of the first D flip-flop 32 can be latched. As long as the main output of the first D flip-flop 32 is not always low and a rising edge exists, the second D flip-flop will be triggered. Because the data input of the second D flip-flop is connected to a high level, its main output outputs a high level and is latched. The second D flip-flop will reset and re-detect after the electronic thermometer 1 is powered off and then powered on again. This avoids missing abnormal signals output from the main output of the first D flip-flop 32, improving detection accuracy.

[0067] The detection principle of the capacitor open-circuit detection module 40 provided in this application embodiment is as follows: when the oscillating capacitor 13 is not open-circuited, the pulse period of the first oscillation signal is the first period. When the oscillating capacitor 13 is in normal working condition, the oscillation frequency of the circuit is stable, and the period of the generated pulse signal is the first period. This period is the normal period expected in the circuit design.

[0068] When the oscillation capacitor 13 is open, the pulse period of the first oscillation signal is the second period. The first period is longer than the second period. Normally, when the oscillation capacitor 13 is open, no pulse signal is generated. However, due to the parasitic capacitance in the electronic thermometer 1, when the oscillation capacitor 13 is open, a second oscillation signal with a very small period is generated.

[0069] The capacitor open-circuit detection module 40 is used to output a second normal signal based on the first cycle of the first oscillation signal; the capacitor open-circuit detection module 40 is also used to output a second abnormal signal based on the second cycle of the first oscillation signal, and the second abnormal signal is different from the second normal signal. The capacitor open-circuit detection module 40 can determine whether the oscillating capacitor 13 is open-circuited by observing the change in the pulse period of the first oscillation signal. Under normal circumstances, the pulse period is relatively long, while the period will become shorter when open-circuited, indicating that the capacitor has failed or disconnected.

[0070] Please refer to Figure 8 , Figure 8 for Figure 2 The circuit diagram shown illustrates one embodiment of the capacitor open-circuit detection module 40. Figure 8 In the embodiment shown, the capacitor open circuit detection module 40 includes a plurality of T flip-flops and a second latch 44 connected in sequence. The plurality of T flip-flops include a first T flip-flop 41 connected to the RC oscillation module 10, a second T flip-flop 42 connected to the second latch 44, and an intermediate T flip-flop 43 connected between the first T flip-flop 41 and the second T flip-flop 42.

[0071] The reset terminals of multiple T flip-flops are connected to a third clock signal 45. The third clock signal 45 is the system clock signal provided by the electronic thermometer 1. The clock input terminal of the first T flip-flop 41 is connected to the RC oscillation module 10. The inverted output terminals of the first T flip-flop 41 and the intermediate T flip-flop 43 are connected to the clock input terminals of adjacent T flip-flops. The main output terminal of the second T flip-flop 42 is connected to the input terminal of the second latch 44. The output terminal of the second latch 44 serves as the output terminal of the capacitor open-circuit detection module 40.

[0072] Please refer to Figure 9 and Figure 10 , Figure 9 for Figure 2 The timing diagram of the capacitor open-circuit detection module 40 shown is when the oscillating capacitor 13 is not open-circuited. Figure 10 for Figure 2 The timing diagram shown is for the capacitor open-circuit detection module 40 when the oscillating capacitor 13 is open. Figure 9 and Figure 10 In the above, T1 is the signal at the inverted output terminal of the first T flip-flop 41, T2 is the signal at the inverted output terminal of the first intermediate T flip-flop 43, T3 is the signal at the inverted output terminal of the second intermediate T flip-flop 43, T4 is the signal at the main output terminal of the second T flip-flop 42, and Q_Err2 is the signal at the main output terminal of the second latch 44.

[0073] exist Figure 9 and Figure 10In the first clock signal 45, the difference between the period of the third clock signal 45 and the first period of the first oscillation signal is the first difference, and the difference between the period of the third clock signal 45 and the second period of the first oscillation signal is the second difference. The second difference is greater than the first difference.

[0074] In some embodiments, the frequency of the third clock signal 45 is approximately 32.768 kHz, and the period is approximately 30 μs. When the oscillation capacitor 13 is not open, the frequency of the first oscillation signal in the RC oscillation system is approximately 20 kHz, and the period is approximately 50 μs. Figure 9 In the process, the period of the third clock signal 45 is close to the period of the first oscillation signal of the RC oscillation system when the oscillation capacitor 13 is not open. During the high-level period of the third clock signal 45, the first oscillation signal can be transmitted to the second stage T flip-flop at most. The main output of the last T flip-flop is always low, and the second latch 44 outputs a low level.

[0075] When the oscillation capacitor 13 is open-circuited in the RC oscillation system, due to the very small parasitic capacitance of PAD, the frequency of the oscillation signal generated by the parasitic capacitance is very high, reaching hundreds of times the normal frequency. Therefore, the period of the first oscillation signal in the RC oscillation system is very small when the oscillation capacitor 13 is open-circuited. Figure 10 In the circuit, the period of the third clock signal 45 differs significantly from the period of the first oscillation signal of the RC oscillation system when the oscillation capacitor 13 is open. The first oscillation signal can cause the output of the four-stage T flip-flop to flip, thereby causing the main output of the last T flip-flop to go high, which in turn causes the second latch 44 to go high.

[0076] exist Figure 8 In the embodiment shown, the multiple T flip-flops are low-level reset T flip-flops. When the third clock signal 45 is low, regardless of whether the first oscillation signal is high or low, the main output of the T flip-flops outputs a low level, and the inverted output outputs a high level.

[0077] Understandably, the number of intermediate T flip-flops 43 can be determined based on the relationship between the period of the first oscillation signal when the oscillation capacitor 13 is not open, the period of the first oscillation signal when the oscillation capacitor 13 is open, and the third period. This ensures that when the oscillation capacitor 13 is not open, the pulse of the first oscillation signal cannot be transmitted to the last T flip-flop, so that the main output of the second T flip-flop 42 is always low. When the oscillation capacitor 13 is open, the pulse of the first oscillation signal can be transmitted to the last T flip-flop, so that the main output of the second T flip-flop 42 can output a rising edge signal.

[0078] The second latch 44 includes a third D flip-flop, which is rising-edge triggered. The main output of the second T flip-flop 42 is connected to the clock input of the third D flip-flop, and the data input of the third D flip-flop is connected to a high level. The second latch 44 can remain untriggered and output a low level when the main output of the second T flip-flop 42 is always low. It is triggered when the main output of the second T flip-flop 42 outputs a rising-edge signal. Because the data input of the third D flip-flop is connected to a high level, the main output of the third D flip-flop outputs a high level and latches the signal until the electronic thermometer 1 is powered off and then powered on again. At this time, the third D flip-flop is reset and re-detects. This avoids missing abnormal signals output by the main output of the second T flip-flop 42, improving the accuracy of the detection.

[0079] Please review Figure 2 ,exist Figure 2 In the illustrated embodiment, the electronic thermometer 1 further includes a display module 50, which is connected to the resistance open-circuit detection module 30 and the capacitance open-circuit detection module 40, respectively, and is used to output a first abnormal signal and a second abnormal signal. Thus, the display module 50 of the electronic thermometer 1 can display whether the electronic thermometer 1 has an open circuit in either resistance or capacitance.

[0080] In some embodiments, the display module 50 includes a first sub-display module and a second sub-display module, the resistance open-circuit detection module 30 is connected to the first sub-display module, and the capacitance open-circuit detection module 40 is connected to the second sub-display module. Thus, the first and second sub-display modules can be used to determine whether the circuit is open due to a resistance or a capacitance, improving the specificity of the open-circuit detection results.

[0081] The electronic thermometer 1 provided in this application includes a resistance open-circuit detection module 30 and a capacitance open-circuit detection module 40. The resistance open-circuit detection module 30 is connected to a frequency divider module 20. Based on a second oscillation signal, it outputs a first abnormal signal when at least one of the thermistor 11 and the reference resistor 12 is open. The capacitance open-circuit detection module 40 is connected to an RC oscillation module 10. Based on the first oscillation signal, it outputs a second abnormal signal when the oscillating capacitor 13 is open. This allows for automatic detection of the resistance and capacitance open-circuit conditions of the electronic thermometer 1, providing a timely alert. This method is highly efficient and saves labor.

[0082] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0083] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An electronic thermometer, characterized in that, include: An RC oscillation module includes a thermistor, a reference resistor, and an oscillation capacitor, wherein the thermistor, the reference resistor, and the oscillation capacitor alternately form an oscillator to generate a first oscillation signal; The frequency divider module is connected to the RC oscillation module and is used to divide the first oscillation signal to output a second oscillation signal. A resistor open-circuit detection module, connected to the frequency divider module, is used to output a first abnormal signal based on the second oscillation signal when at least one of the thermistor and the reference resistor is open-circuited; and A capacitor open-circuit detection module, connected to the RC oscillation module, is used to output a second abnormal signal when the oscillation capacitor is open, based on the first oscillation signal.

2. The electronic thermometer according to claim 1, characterized in that, The RC oscillation module further includes a pulse generation control circuit, used to control the duration of the oscillator formed by the thermistor and the oscillation capacitor to be equal to the duration of the oscillator formed by the reference resistor and the oscillation capacitor.

3. The electronic thermometer according to claim 2, characterized in that, When neither the thermistor nor the reference resistor is open-circuited, the second oscillation signal is a pulse signal, and the resistor open-circuit detection module is used to output a first normal signal according to the pulse signal. When at least one of the thermistor and the reference resistor is open-circuited, the second oscillation signal includes at least half of a constant signal. The open-circuit detection module is used to output the first abnormal signal based on the constant signal, and the first abnormal signal is different from the first normal signal.

4. The electronic thermometer according to claim 3, characterized in that, The resistor open-circuit detection module includes an RS flip-flop, a first D flip-flop, and a first latch. The set terminal of the RS flip-flop is connected to a first clock signal, and the reset terminal of the RS flip-flop is connected to the frequency divider module. The main output of the RS flip-flop is connected to the data input of the first D flip-flop, the clock input of the first D flip-flop is connected to the second clock signal, the main output of the first D flip-flop is connected to the input of the first latch, and the output of the first latch serves as the output of the resistor open-circuit detection module.

5. The electronic thermometer according to claim 4, characterized in that, The period of the first clock signal is the same as the period of the second clock signal, and both are half the period of the second oscillation signal; the second oscillation signal and the first clock signal are at a low level at the beginning of each period, and the first clock signal includes a high-level pulse in each period, the high-level pulse being within the low-level period of the second oscillation signal; the first D flip-flop is rising-edge triggered, and the second clock signal includes a rising edge in each period, located at the beginning of each period.

6. The electronic thermometer according to claim 4, characterized in that, The first latch includes a second D flip-flop, which is rising-edge triggered. The clock input of the second D flip-flop is connected to the main output of the first D flip-flop, and the data input of the second D flip-flop is connected to a high level.

7. The electronic thermometer according to claim 1, characterized in that, When the oscillation capacitor is not open-circuited, the pulse period of the first oscillation signal is the first period; when the oscillation capacitor is open-circuited, the pulse period of the first oscillation signal is the second period; the first period is greater than the second period. The capacitor open-circuit detection module is used to output a second normal signal according to the first cycle of the first oscillation signal; The capacitor open-circuit detection module is used to output a second abnormal signal according to the second period of the first oscillation signal. The second abnormal signal is different from the second normal signal.

8. The electronic thermometer according to claim 7, characterized in that, The capacitor open circuit detection module includes multiple T flip-flops and a second latch connected in sequence. The multiple T flip-flops include a first T flip-flop connected to the RC oscillation module, a second T flip-flop connected to the second latch, and an intermediate T flip-flop connected between the first T flip-flop and the second T flip-flop. The reset terminals of the plurality of T flip-flops are connected to a third clock signal; the clock input terminal of the first T flip-flop is connected to the RC oscillation module; the inverted output terminals of the first T flip-flop and the intermediate T flip-flop are connected to the clock input terminals of adjacent T flip-flops; the main output terminal of the second T flip-flop is connected to the input terminal of the second latch; and the output terminal of the second latch serves as the output terminal of the capacitor open-circuit detection module.

9. The electronic thermometer according to claim 8, characterized in that, The difference between the period of the third clock signal and the first period of the first oscillation signal is a first difference, and the difference between the period of the third clock signal and the second period of the first oscillation signal is a second difference, wherein the second difference is greater than the first difference.

10. The electronic thermometer according to claim 9, characterized in that, The second latch includes a third D flip-flop, which is rising-edge triggered. The main output of the second T flip-flop is connected to the clock input of the third D flip-flop, and the data input of the third D flip-flop is connected to a high level.

11. The electronic thermometer according to claim 10, characterized in that, The electronic thermometer also includes a display module, which is connected to the resistance open circuit detection module and the capacitance open circuit detection module respectively, and is used to output the first abnormal signal and the second abnormal signal.

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