A tri-state ion gate driving circuit and a driving method

Abstract

The present application relates to a kind of tri-state ion gate driving circuit and its driving method, its characteristics are, the driving circuit uses suspended capacitor three-level bridge arm circuit, makes driving circuit whole floating in the reference potential of ion gate grid plane.The output node potential of the bridge arm circuit can be switched between the positive bus potential, hard midpoint potential and the negative bus potential by control circuit, corresponding two off states and one on state of tri-state ion gate.The driving circuit is realized by a pair of matched discharge resistance connected to output node and each other, suspended capacitor both ends voltage is maintained at half bus voltage.The driving method of the present application is by adjusting the residence time of three levels to turn off, turn on, turn off ion gate again, by changing the polarity of off level to realize the exchange of positive and negative ion mode.The present application replaces two-way independent isolated high-voltage pulse source with single power stage, can be compatible with positive and negative ion mode, the requirement of device voltage resistance is low, small in size, low in cost.

Description

Technical Field

[0001] This invention belongs to the field of sample introduction and ion gating technology for analytical instruments such as ion mobility spectrometry and mass spectrometry, specifically a driving circuit and driving method for a three-state ion gate. Background Technology

[0002] Instruments such as Ion Mobility Spectroscopy (IMS) commonly employ ion gates to time-select and cut off continuous ion currents. To obtain narrower ion fragments, higher resolution, and suppress residue and tailing caused by traditional ion gate control, thereby improving the recognition performance of IMS, in addition to traditional BN-type and TP-type ion gates, three-grid three-state ion gates are an effective method. A three-state ion gate consists of three parallel grids. To allow ions to pass through and turn off, it needs to operate in three states: positive deflection to turn off, conduction to allow passage, and reverse deflection to accelerate, i.e., controlling the intermediate grid in three different voltage states. To apply positive and negative deflection voltages separately outside the conduction state, current technologies typically use two independent isolated high-voltage pulse sources, such as... Figure 1 As shown: the first isolation high voltage pulse source (110) generates a positive pulse and the second isolation high voltage pulse source (120) generates a reverse pulse. The two work together to form three states on the ion gate (130).

[0003] The existing technology described above has the following shortcomings. First, it requires two independent isolated high-voltage power supplies, two power half-bridges, and two sets of isolation, resulting in complex circuitry, high size and cost, which is not conducive to portability and handheld operation. Second, the two pulse sources must be precisely synchronized; any timing deviation will introduce an unwanted intermediate potential or shoot-through at the moment of switching. Third, the switching devices of each pulse source typically need to withstand voltages close to the full swing (i.e., about twice the deflection voltage), placing higher demands on the voltage withstand capability of the devices. Fourth, the above solution is difficult to adapt to positive and negative ion operating modes and can only operate in a single mode. If rapid switching of polarity modes by migration spectrum is required, two more isolated high-voltage pulse circuits are needed, resulting in a larger size and more complex control.

[0004] Ion gate driving has two significant characteristics: First, the dwell time of each state is extremely asymmetrical—the off state often lasts for tens of milliseconds, while the on state lasts only for hundreds of microseconds; second, the ion gate is electrically approximated as a capacitive load, and once the gate capacitance is fully charged, almost no continuous current flows through it, with a capacitance value between several pF and tens of pF. Therefore, a reliable, simple, low-power, and fast three-state ion gate driving scheme is needed that can replace the dual-isolated high-voltage source with a single circuit, stably maintain the voltage under the unique operating conditions of the ion gate, and rapidly switch between positive and negative states. Summary of the Invention

[0005] The purpose of this invention is to address the above-mentioned problems by providing a three-state ion gate driving circuit and driving method based on a three-level topology of a floating capacitor. This simplifies the driving of the three-state ion gate, reduces the withstand voltage requirement, and stably maintains the floating capacitor voltage under conditions of asymmetric dwell time and near-capacitive load. It is also compatible with both positive and negative ion operating modes and enables rapid polarity switching.

[0006] To achieve the aforementioned objectives, the technical solution of this invention is a three-state ion gate driving circuit, characterized in that: the driving circuit includes a DC-isolated high-voltage power supply (20), a floating capacitor three-level bridge arm (30), a voltage balancing circuit (40), an ion gate controller (60), and an isolation gate driving circuit (61). The positive terminal of the DC-isolated high-voltage power supply (20) is connected to the positive bus (21), and the negative terminal of the DC-isolated high-voltage power supply (20) is connected to the negative bus (22). The upper bus capacitor (24) and the lower... After the bus capacitor (25) is connected in series, its two ends are connected in parallel between the positive bus (21) and the negative bus (22). The connection point between the upper bus capacitor (24) and the lower bus capacitor (25) is a hard midpoint M (23). This hard midpoint (23) is connected to the reference potential tap of the drift tube of the ion mobility spectrometer. The floating capacitor three-level bridge arm (30) consists of four series switches and a floating capacitor. The two ends of the four series switches are connected in parallel between the positive bus (21) and the negative bus (22). Switch one (31) and switch two (32) The connection point is the first inner node A (36), the connection point between switch three (33) and switch four (34) is the second inner node B (37), the floating capacitor (35) is connected between the first inner node A (36) and the second inner node B (37), the connection point between switch two (32) and switch three (33) is the output node (38) of the three-level bridge arm (30) of the floating capacitor, and this output node is electrically connected to the ion gate (50). The voltage balance circuit is composed of two discharge resistors, the first discharge resistor... The resistor (41) is set between the first inner node A (36) and the hard midpoint (23), the second discharge resistor (42) is set between the second inner node B (37) and the hard midpoint (23), the ion gate controller (60) is electrically connected to switch one (31), switch two (32), switch three (33) and switch four (34) respectively via the isolation gate drive circuit (61), and the ion gate controller (60) is electrically connected to the first inner node A (36) and the second inner node B (37) respectively.

[0007] In the above technical solution, the DC isolated high-voltage power supply (20) is used to establish a positive bus (21) and a negative bus (22) relative to the reference potential of the gate plane where the ion gate is located. The potential of the positive bus (21) is positive relative to the reference potential, and the potential of the negative bus (22) is negative relative to the reference potential. The hard midpoint M (23) has a potential equal to the reference potential and is located between the potential of the positive bus (21) and the potential of the negative bus (22). The floating capacitor three-level bridge arm (30) includes a first switch (31), a second switch (32), a third switch (33), and a fourth switch (34) connected in series between the positive bus (21) and the negative bus (22). The first internal node A (36) connected between the first switch (31) and the second switch (32) and the third switch (33) and the fourth switch (34) are connected in series. The floating capacitor (35) between the second inner node B (37) between 34) and the output node (38) led out from the second switch (32) and the third switch (33), the output node (38) being electrically connected to the ion gate (50); wherein, the voltage across the floating capacitor (35) is maintained at half the voltage between the positive bus (21) and the negative bus (22); the ion gate controller (60) controls the on / off state of the first switch (31) to the fourth switch (34) via the isolation gate drive circuit (61), so that the output node (38) switches between a first level equal to the potential of the positive bus, a second level equal to the potential of the hard midpoint and a third level equal to the potential of the negative bus, the first level, the second level and the third level respectively corresponding to the first off state, the on state and the second off state of the ion gate (50).

[0008] In the above technical solution, the resistance values ​​of the first bleeder (41) and the second bleeder (42) are equal and matched; when one of the positive bus (21) and the negative bus (22) is continuously clamped by the conducting switch, and one of the first inner node A (36) and the second inner node B (37) is in the floating state, the bleeder connected to the floating inner node pulls the floating inner node toward the potential of the hard midpoint M (23), thereby maintaining the voltage across the floating capacitor (35) at half the voltage between the positive bus (21) and the negative bus (22).

[0009] In the above technical solution, the floating capacitor three-level bridge arm (30) includes a first off level, a second on level, and a second off level. The second level is implemented by two redundant switch combinations: in the first switch combination, the first switch (31) is on with the third switch (33), and the second switch (32) is off with the fourth switch (34); in the second switch combination, the second switch (32) is on with the fourth switch (34), and the first switch (31) is off with the third switch (33).

[0010] In the above technical solution, the hard midpoint M (23) serves as both the reference potential of the ion gate (50) and the potential corresponding to the second level. When the output node (38) is at the second level, the potentials at both ends of the first discharge resistor (41) and the second discharge resistor (42) connected to the inner node on the output node side are equal, so that no current flows and no current is fed into the ion gate (50).

[0011] In the above technical solution, an overvoltage protection device (43) is connected across the two ends of the floating capacitor (35). The clamping threshold of the overvoltage protection device (43) is higher than the normal operating voltage range corresponding to half of the voltage between the positive bus (21) and the negative bus (22).

[0012] In the above technical solution, the ion gate controller (60) drives the first switch (31) to the fourth switch (34) via the isolation gate drive circuit (61), and the isolation withstand voltage of the isolation gate drive circuit (61) and the DC isolation high voltage power supply (20) relative to the reference potential is not lower than the absolute value of the reference potential.

[0013] In the above technical solution, the ion gate controller (60) selects between the first switch combination and the second switch combination based on the deviation of the voltage at both ends of the suspended capacitor (35) relative to half the voltage.

[0014] To achieve the purpose of this invention, this invention also provides a circuit driving method for a three-state ion gate. This driving method is based on the three-state ion gate driving circuit technology provided by this invention. The driving method involves controlling the driving ion gate (50) within one working cycle, causing the output node (38) to sequentially reside at a first off level, an on level, and a second off level. The first off level is resided for a first duration to turn off the ion gate (50); the on level is resided for a second duration to allow the ion packet to pass; and the second off level is resided for a third duration. The first duration is on the order of tens of milliseconds, and the second and third durations are both on the order of hundreds of microseconds. In this context, the conduction level is equal to the potential of the hard midpoint M (23); when the ion gate (50) is operating in positive ion mode, the first shutdown level is the potential of the negative bus (22) and the second shutdown level is the potential of the positive bus (21); when the ion gate (50) is operating in negative ion mode, the first shutdown level is the potential of the positive bus (21) and the second shutdown level is the potential of the negative bus (22); and the discharge resistor that sustains the voltage of the floating capacitor (35) interchanges between the first discharge resistor (41) and the second discharge resistor (42) as the positive ion mode and the negative ion mode switch.

[0015] In the above driving method, during the second duration of the conduction level, the rise time and fall time of the output node (38) are both no more than one-tenth of the second duration, so as to limit the time width of the released ion pack.

[0016] The advantages and beneficial effects of this invention include: (1) The two independent isolated high voltage pulse sources are replaced by a single floating capacitor three-level bridge arm (30). The isolation power supply is reduced from two to one, the power stage is reduced from two to one, and the isolation is reduced from two sets to one set, which significantly simplifies the circuit, reduces the size and reduces the cost, which is beneficial for portable and handheld instruments.

[0017] (2) Under the condition that the voltage of the floating capacitor is maintained at half the bus voltage, each switching device only bears about half the bus voltage stress (compared to nearly twice the deflection voltage of the dual-level half-bridge scheme, the stress is halved), reducing the voltage withstand requirements of the device.

[0018] (3) The “zero level” corresponding to the conduction state is the native output level of this topology, which can be obtained without relying on the precise synchronization of the two pulse sources, thus eliminating the intermediate potential and shoot-through risk caused by the timing deviation of the two sources.

[0019] (4) By using the hard midpoint “three-in-one” setting, the discharge resistor precisely clamps the voltage of the floating capacitor in the off state, while in the on state the potentials at both ends are equal, there is zero current, and no ion gate is loaded, thus achieving voltage balance and sample injection without interference.

[0020] (5) The balancing method is passive, and there is no need to set up a floating auxiliary power supply or a complex active voltage equalization circuit for the floating capacitor. Under typical parameters, the power consumption of the balancing branch is very low, and the voltage of the floating capacitor can be stably maintained within a small error band near half of the bus voltage.

[0021] (6) Through a pair of symmetrically matched bleed resistors, the circuit can be symmetrically compatible with both positive and negative ion modes, and the balance performance is consistent in both modes.

[0022] (7) Under the conditions of long-term suspension in the off state, short-term conduction state, and approximately capacitive load, the voltage of the floating capacitor is stably maintained at half the bus voltage.

[0023] (8) The three-state ion gate driving circuit of the present invention is not limited to the ion gate controlling the three grid gate of the ion mobility spectrometer, but can also be used for driving and controlling other high-voltage gates that require three states (e.g., forward deflection, conduction, acceleration or reverse deflection). Attached Figure Description

[0024] Figure 1 This is a block diagram illustrating the principle of using two independently isolated high-voltage pulse sources to drive a three-state ion gate in existing technologies.

[0025] Figure 2 This is a schematic diagram of one embodiment of the three-state ion gate driving circuit of the present invention.

[0026] Figure 3 This is a schematic diagram illustrating the principle of the two redundant intermediate states (conduction states) of the three-level bridge arm of the floating capacitor in this invention.

[0027] Figure 4 This is a driving timing diagram of the present invention, where (a) is the positive ion mode and (b) is the negative ion mode. The long turn-off segments in the diagram are schematic and are not drawn to scale.

[0028] In the attached diagrams, 20 is a DC isolated high-voltage power supply, 21 is the positive bus, 22 is the negative bus, 23 is the hard neutral point M, 24 is the upper bus capacitor, 25 is the lower bus capacitor, 30 is the floating capacitor three-level bridge arm, 31 is the first switch S1, 32 is the second switch S2, 33 is the third switch S3, 34 is the fourth switch S4, 35 is the floating capacitor Cf, 36 is the first internal node A, 37 is the second internal node B, 38 is the output node Vo, 40 is the voltage balancing circuit, 41 is the first bleeder resistor R_A, 42 is the second bleeder resistor R_B, 43 is the overvoltage protection device, 50 is the ion gate, 60 is the ion gate controller, 61 is the isolation barrier drive circuit, 110 is the first isolated high-voltage pulse source, 120 is the second isolated high-voltage pulse source, and 130 is the ion gate. Detailed Implementation

[0029] The present invention will be further described below with reference to the accompanying drawings and a specific embodiment. It should be understood that the embodiments described herein are for illustrative purposes only and not for limiting the present invention; the specific numerical values ​​given in the embodiments are exemplary parameters. Example 1:

[0030] This embodiment presents a three-state ion gate driving circuit applied to an ion mobility spectrometer. (See Appendix) Figure 2The entire structure is floated on the reference potential of the gate plane where the ion gate is located. This reference potential is determined by the corresponding potential tap of the drift tube. In this embodiment, it is approximately 2500V. The DC isolated high-voltage power supply (20) establishes a positive bus (21) and a negative bus (22) relative to this reference potential. The positive bus (21) has a reference potential of +250V (absolute potential to ground of approximately 2750V) and the negative bus (22) has a reference potential of −250V (absolute potential to ground of approximately 2250V). The hard midpoint M (23) is connected to the positive bus (21) via the upper bus capacitor (24), and to the negative bus (22) via the lower bus capacitor (25), and is connected to the reference potential tap of the drift tube, thereby forming a hard midpoint M (23) with a potential equal to the reference potential (relative reference potential of 0V) between +250V and −250V. In this embodiment, the three-level bridge arm (30) of the floating capacitor is composed of a first switch S1 (31), a second switch S2 (32), a third switch S3 (33) and a fourth switch S4 (34) connected in series between the positive bus (21) and the negative bus (22). The first internal node A (36) is between the first switch S1 (31) and the second switch S2 (32), and the second internal node B (37) is between the third switch S3 (33) and the fourth switch S4 (34). The floating capacitor Cf (35) is connected between the first internal node A (36) and the second internal node B (37). The output node Vo (38) is led out between the second switch S2 (32) and the third switch S3 (33), and the output node Vo (38) is electrically connected to the ion gate (50). An overvoltage protection device (43), such as a transient voltage suppressor or a Zener diode, is connected across the floating capacitor (35). Its clamping threshold is higher than the normal operating range corresponding to half the bus voltage. It only performs overvoltage protection in abnormal situations and does not participate in normal voltage regulation. The ion gate controller (60) controls the on / off of four switches via the isolation gate drive circuit (61), so that the output node M (38) switches between three levels equal to the positive bus potential, the hard neutral point potential, and the negative bus potential, which correspond to the first off state, the on state, and the second off state of the ion gate, respectively. The voltage across the floating capacitor (35) is maintained at half the voltage between the positive and negative buses.

[0031] In this embodiment, each switch is a silicon carbide or gallium nitride MOSFET device with a withstand voltage of 600V to 650V; the floating capacitor Cf (35) is a thin film capacitor or a C0G ceramic capacitor of about 0.47µF; since the voltage of the floating capacitor is maintained at half the bus voltage (about 250V), each switch only withstands about 250V when blocked.

[0032] In this embodiment, the ion gate controller (60) drives the first to fourth switches respectively via the isolation gate drive circuit (61). The first switch S1 (31) and the fourth switch S4 (34) are complementary, and the second switch S2 (32) and the third switch S3 (33) are complementary. Since the ion gate drive circuit in this embodiment is floated at a reference potential of approximately 2500V, the isolation withstand voltage between the isolation gate drive circuit (61) and the DC isolation high-voltage power supply (20) relative to ground should not be lower than this reference potential. In this embodiment, the isolation withstand voltage is an enhanced insulation of not less than 4kV.

[0033] In this embodiment, the correspondence between the three voltage levels of the output node M (38) and the switch state is shown in the table below ("1" indicates on, "0" indicates off):

[0034]

[0035] The +250V level is obtained by connecting the first switch S1 (31) and the second switch S2 (32) (at this time, the output node M is connected to the positive bus via S1 and S2); the −250V level is obtained by connecting the third switch S3 (33) and the fourth switch S4 (34); and the 0V (half bus voltage) level has two redundant implementation methods.

[0036] In this embodiment, the 0V level has two redundant states, see Appendix Figure 3 The voltage Vcf across the floating capacitor (35) is maintained at half the bus voltage (i.e., Vdc / 2, approximately 250V in this embodiment, where Vdc is the total voltage of 500V between the positive and negative buses) under steady-state conditions. Figure 3 In the first redundant state shown in (a), the first switch S1 (31) and the third switch S3 (33) are turned on: S1 clamps the first inner node A (36) to the positive bus potential Vdc, and S3 connects the second inner node B (37) to the output node Vo (38); since the floating capacitor Cf is connected between A and B, Vo = V(A) − Vcf = Vdc − Vdc / 2 = Vdc / 2, that is, the output is half of the bus voltage (relative to the reference potential of 0V). Figure 3In the second redundant state shown in (b), the second switch S2 (32) and the fourth switch S4 (34) are turned on: S4 clamps the second inner node B (37) to the negative bus potential, and S2 connects the first inner node A (36) to the output node Vo (38); at this time, Vo = V(B) + Vcf, which is also equal to half of the bus voltage. It can be seen that as long as the voltage of the floating capacitor Cf is kept at Vdc / 2, both redundant states can accurately output a 0V level. In addition, the charging and discharging directions of the two redundant states for the floating capacitor Cf are opposite, so it can be used to fine-tune the voltage of the floating capacitor Cf when needed.

[0037] In this embodiment, the voltage balancing circuit (40) includes a first bleeder resistor RA (41) and a second bleeder resistor RB (42), see Appendix Figure 2 The first inner node A (36) and the hard midpoint M (23), and the second inner node B (37) and the hard midpoint M (23), are respectively connected. In this embodiment, the single discharge resistor (41) is composed of two resistors of about 110kΩ connected in series (to meet the withstand voltage requirements), with a single arm resistance of about 220kΩ, and the resistance values ​​of the first discharge resistor RA and the second discharge resistor RB are equal and matched with each other. Since the ion gate has two working modes, positive ion mode and negative ion mode, the busbars clamped for a long time are opposite in the two modes, and the inner nodes that are suspended for a long time are opposite. Therefore, the discharge resistors that undertake the task of maintaining the voltage of the floating capacitor are interchanged between the two resistors. For this reason, the first discharge resistor (41) and the second discharge resistor (42) are taken to have equal resistance values ​​and are matched with each other (including temperature coefficient matching and symmetrical thermal layout), so that the circuit has consistent balanced performance in the two modes. When one of the positive or negative busbars is continuously clamped and the corresponding inner node is suspended for a long time, the discharge resistor connected to the suspended inner node pulls it toward the hard midpoint potential, thereby forcing the voltage across the floating capacitor (35) to be equal to half the busbar voltage.

[0038] This embodiment provides a three-state ion gate driving method using the above-described driving circuit: within one working cycle, the output node sequentially resides at a first off level (first duration, on the order of tens of milliseconds), an on level (second duration, on the order of hundreds of microseconds), and a second off level (third duration, on the order of hundreds of microseconds); the on level is equal to the hard neutral point potential; in positive ion mode, the first and second off levels are the negative and positive bus potentials, respectively, and the opposite is true in negative ion mode; the bleeder resistor responsible for maintaining the voltage of the floating capacitor is interchanged with the mode switching. Furthermore, the rise and fall times of the on level are no greater than one-tenth of the second duration, to limit the time width of the ion packet.

[0039] In this embodiment, one working cycle in positive ion mode is shown in the attached figure. Figure 4As shown in (a): the ion gate is in the off state most of the time, and the output node (38) is clamped at the negative bus potential (relative to the reference potential of −250V). This state is achieved by the conduction of the third switch (33) and the fourth switch (34) for about 49.4ms. In this state, the second inner node B (37) is clamped through S3 and S4, while the first inner node A (36) is floating. At this time, the first discharge resistor RA (41) connected to the floating first inner node A (36) pulls the first inner node A (36) to the hard midpoint potential (0V); since the second inner node B (37) is about the negative bus potential at this time, the voltage Vcf = V(A) − V(B) across the floating capacitor (35) is forced to be maintained at 0 − (−250V) = 250V, that is, half of the bus voltage. Meanwhile, the second discharge resistor RB (42) is connected between the clamped second inner node B (37) and the hard midpoint M, and its static current does not play a dominant role in balancing the floating capacitor (35).

[0040] In this embodiment, when in the on-state (output node equals hard midpoint potential 0V, lasting approximately 0.1ms), the potentials at both ends of the discharge resistor connected to the inner node on the output node side are equal (both ends are approximately 0V), therefore no current flows and no current is fed into the ion gate, thus not affecting the sample introduction window. This is precisely the synergistic effect brought about by setting the hard midpoint M(23) as a three-in-one structure of "reference potential = on-state level = common point of discharge resistor". The voltage of the floating capacitor is precisely clamped in the long off-state, and zero loading is achieved in the on-state.

[0041] In this embodiment, the design and estimation of balancing accuracy and dynamics are as follows: Assuming the net imbalance current of the balancing branch is I_net (caused by device leakage current, typically in the microampere range), the steady-state deviation of the floating capacitor voltage relative to half the bus voltage is approximately δ ≈ I_net·R, which is approximately 1V under the parameters of this embodiment; the balancing time constant τ ≈ R·Cf ≈ 0.1s, meaning it stabilizes after several operating cycles; the static power consumption of the balancing branch is approximately 0.28W (mainly borne by the resistor on the clamped side at any given time); the output ripple introduced by the balancing branch in the conduction state is in the millivolt range and can be ignored. Therefore, the floating capacitor voltage can be stably maintained within the range of approximately 250V ± 1V.

[0042] In this embodiment, one working cycle in negative ion mode is shown in the attached figure. Figure 4As shown in (b), the polarity of the output level is opposite: the ion gate is clamped at the positive bus potential for most of the time (relative to the reference potential of +250V, achieved by the first switch S1 and the second switch S2 being turned on, for about 49.4ms), and then switches to the negative bus potential (−250V, about 0.5ms) through the on state (0V, about 0.1ms). At this time, the positive bus is clamped for a long time, and the second inner node B (37) is left floating for a long time. The second bleeder resistor RB (42) takes on the task of maintaining the voltage of the floating capacitor (35), while the first bleeder resistor RA (41) takes on the static current on the clamped side. It can be seen that the roles of the two bleeder resistors are exactly interchanged in the two modes. Therefore, the first bleeder resistor (41) and the second bleeder resistor (42) must have equal resistance values ​​and be matched with each other (and have a matched temperature coefficient and symmetrical thermal layout). One of them cannot be omitted or reduced to ensure that the circuit has consistent balanced performance and thermal behavior in both positive and negative modes.

[0043] The design and calculation of the switching timing and edges in this embodiment are as follows, see [link to documentation]. Figure 4 The working cycle is approximately 50ms (repetition frequency approximately 20Hz), resulting in a very low switching frequency and negligible switching losses. However, the conduction window is only about 0.1ms. To accurately define the time width of the ion pack, the rise and fall times of the output node when entering and exiting the conduction level should be sufficiently fast. In this embodiment, this is taken as no more than one-tenth of the conduction duration (i.e., within approximately 10µs, preferably on the order of 100ns). The specific values ​​of tens of milliseconds / hundreds of microseconds mentioned above are only examples and can be adjusted according to the instrument's repetition frequency, ion pack width, and other requirements. Generally, the first duration is on the order of tens of milliseconds, and the second and third durations are on the order of hundreds of microseconds.

[0044] In this embodiment, an overvoltage protection device (43), such as a transient voltage suppressor (TVS) or a Zener diode, is connected across the floating capacitor (35). Its clamping threshold is set to be higher than half the normal operating range corresponding to the bus voltage (e.g., 270V~300V). It only provides overvoltage protection during abnormal transients and does not conduct or participate in voltage regulation during normal operation. It should be noted that the overvoltage protection device (43) is not suitable to replace the bleeder resistors (41, 42) for normal regulation of the floating capacitor voltage because it is a unidirectional device with discrete thresholds and characteristics such as positive temperature coefficient and leakage current before breakdown. Using it for normal regulation will cause voltage drift.

[0045] In this embodiment, the fine-tuning of the redundant state is also considered and designed. Since there are two redundant states with opposite charging and discharging directions for the suspended capacitor at the 0V level, the ion gate controller (60) can select or weight between the two redundant states according to the detection result of the voltage of the suspended capacitor (35), thereby actively fine-tuning the voltage of the suspended capacitor (35) in conjunction with the above passive balance.

[0046] In summary, this embodiment uses a single floating capacitor three-level bridge arm circuit to replace two isolated high-voltage pulse sources to achieve three-state ion gate driving. The key is to set the hard midpoint (23) as a "three-in-one" node: it is simultaneously the common connection point of (a) the reference potential of the ion gate, (b) the output level (second level) corresponding to the conduction state, and (c) the bleeder resistor. This achieves two synergistic effects: First, in the off state (the output node is clamped to the positive or negative bus, and the corresponding inner node is floating), the bleeder resistor on the side of the floating inner node accurately pulls the node to the hard midpoint potential, thereby clamping the floating capacitor voltage to half the bus voltage; Second, in the conduction state (the output node is equal to the hard midpoint potential), the potentials at both ends of the bleeder resistor connected to the inner node on the output node side are equal, so no current flows, no current is fed into the ion gate, and the sample injection window is not affected. It is precisely by using the "three-in-one" hard midpoint setting and a pair of matched and symmetrical discharge resistors that the floating capacitor voltage can be stably maintained under the asymmetric residence and near-capacitive load conditions unique to ion gates. It can also adapt to both positive and negative ion operating modes, and significantly reduce the voltage withstand requirements of the device, simplify the circuit, and reduce the size and cost. Example 2:

[0047] This second embodiment is based on the first embodiment, and uses a floating-ground active voltage equalization circuit, such as a controlled current source or a small DC-DC converter, to replace or assist the bleed resistor in the first embodiment in order to maintain the floating capacitor voltage under a wider range of operating conditions. Example 3:

[0048] This third embodiment is based on the first embodiment. It uses two inverted floating capacitor three-level bridge arms to drive the two sets of gate wires of the ion gate in a differential / push-pull manner, thereby enhancing the suppression of common-mode feedthrough.

[0049] The above embodiments should not be regarded as limitations on the present invention. All equivalent substitutions and improvements made within the essential technical features of the present invention should be included within the protection scope of the present invention.

Claims

1. A three-state ion gate driving circuit, characterized in that: The driving circuit includes a DC-isolated high-voltage power supply (20), a floating capacitor three-level bridge arm (30), a voltage balancing circuit (40), an ion gate controller (60), and an isolation gate driving circuit (61). The positive terminal of the DC-isolated high-voltage power supply (20) is connected to the positive bus (21), and the negative terminal of the DC-isolated high-voltage power supply (20) is connected to the negative bus (22). The upper bus capacitor (24) and the lower bus capacitor (25) are connected in series, and their two ends are connected in parallel to the positive bus (21) and the negative bus (22). Between 22), the connection point between the upper bus capacitor (24) and the lower bus capacitor (25) is a hard midpoint M (23), which is connected to the reference potential tap of the drift tube of the ion mobility spectrometer. The floating capacitor three-level bridge arm (30) consists of four series switches and a floating capacitor. The two ends of the four series switches are connected in parallel between the positive bus (21) and the negative bus (22). The connection point between switch one (31) and switch two (32) is the first inner node A (36). Switch three ( 33) The connection point between the switch and the fourth switch (34) is the second inner node B (37). The floating capacitor (35) is connected between the first inner node A (36) and the second inner node B (37). The connection point between the second switch (32) and the third switch (33) is the output node (38) of the three-level bridge arm (30) of the floating capacitor. This output node is electrically connected to the ion gate (50). The voltage balance circuit is composed of two discharge resistors. The first discharge resistor (41) is set between the first inner node A (36) and the hard midpoint (23). The second discharge resistor (42) is set between the second inner node B (37) and the hard midpoint M (23). The ion gate controller (60) is electrically connected to the first switch (31), the second switch (32), the third switch (33), and the fourth switch (34) respectively via the isolation gate drive circuit (61). The ion gate controller (60) is electrically connected to the first inner node A (36) and the second inner node B (37) respectively.

2. The three-state ion gate driving circuit according to claim 1, characterized in that: The DC-isolated high-voltage power supply (20) is used to establish a positive busbar (21) and a negative busbar (22) relative to the reference potential of the gate plane where the ion gate is located. The potential of the positive busbar (21) is positive relative to the reference potential, and the potential of the negative busbar (22) is negative relative to the reference potential. The hard midpoint M (23) has a potential equal to the reference potential and is located between the potential of the positive busbar (21) and the potential of the negative busbar (22). The floating capacitor three-level bridge arm (30) includes a first switch (31), a second switch (32), a third switch (33), and a fourth switch (34) connected in series between the positive busbar (21) and the negative busbar (22). The first internal node A (36) connected between the first switch (31) and the second switch (32) and the third switch (33) and the fourth switch (34) are connected in series. The floating capacitor (35) between the second inner node B (37) and the output node (38) led out from the second switch (32) and the third switch (33) are electrically connected to the ion gate (50); wherein, the voltage across the floating capacitor (35) is maintained at half the voltage between the positive bus (21) and the negative bus (22); the ion gate controller (60) controls the on / off state of the first switch (31) to the fourth switch (34) via the isolation gate drive circuit (61), so that the output node (38) switches between a first level equal to the potential of the positive bus, a second level equal to the potential of the hard midpoint and a third level equal to the potential of the negative bus, the first level, the second level and the third level respectively correspond to the first off state, the on state and the second off state of the ion gate (50).

3. The three-state ion gate driving circuit according to claim 1, characterized in that: The first bleeder resistor (41) and the second bleeder resistor (42) have the same resistance value and are matched with each other; when one of the positive bus (21) and the negative bus (22) is continuously clamped by the conducting switch, and one of the first inner node A (36) and the second inner node B (37) is in the floating state, the bleeder resistor connected to the floating inner node pulls the floating inner node toward the potential of the hard midpoint M (23), thereby maintaining the voltage across the floating capacitor (35) at half the voltage between the positive bus (21) and the negative bus (22).

4. The three-state ion gate driving circuit according to claim 1, characterized in that, The floating capacitor three-level bridge arm (30) includes a first off level, a second on level, and a second off level. The second level is implemented by two redundant switch combinations: in the first switch combination, the first switch (31) is on with the third switch (33), and the second switch (32) is off with the fourth switch (34); in the second switch combination, the second switch (32) is on with the fourth switch (34), and the first switch (31) is off with the third switch (33).

5. The three-state ion gate driving circuit according to claim 1 or 4, characterized in that, The hard midpoint M (23) serves as both the reference potential of the ion gate (50) and the potential corresponding to the second level. When the output node (38) is at the second level, the potentials at both ends of the first discharge resistor (41) and the second discharge resistor (42) connected to the inner node on the output node side are equal, so that no current flows and no current is fed into the ion gate (50).

6. The three-state ion gate driving circuit according to claim 1, characterized in that, The floating capacitor (35) is connected across an overvoltage protection device (43), and the clamping threshold of the overvoltage protection device (43) is higher than the normal operating voltage range corresponding to half the voltage between the positive bus (21) and the negative bus (22).

7. The three-state ion gate driving circuit according to claim 1, characterized in that, The ion gate controller (60) drives the first switch (31) to the fourth switch (34) via the isolation gate drive circuit (61), and the isolation withstand voltage of the isolation gate drive circuit (61) and the DC isolation high voltage power supply (20) relative to the reference potential is not lower than the absolute value of the reference potential.

8. The three-state ion gate driving circuit according to claim 1, characterized in that: The ion gate controller (60) selects between the first switch combination and the second switch combination based on the deviation of the voltage across the floating capacitor (35) relative to half the voltage.

9. A three-state ion gate driving method, employing a three-state ion gate driving circuit as described in any one of claims 1 to 8, characterized in that: The driving method involves controlling the output node (38) to sequentially reside at a first off level, an on level, and a second off level during one working cycle of the driven ion gate (50). The output node resides at the first off level for a first duration to turn off the ion gate (50); it resides at the on level for a second duration to allow the ion packet to pass through; and it resides at the second off level for a third duration. The first duration is on the order of tens of milliseconds, and the second and third durations are both on the order of hundreds of microseconds; the conduction level is equal to the potential of the hard midpoint M (23); when the ion gate (50) is working in positive ion mode, the first shutdown level is the potential of the negative bus (22) and the second shutdown level is the potential of the positive bus (21); When the ion gate (50) is operating in negative ion mode, the first shutdown level is the potential of the positive bus (21) and the second shutdown level is the potential of the negative bus (22); and the discharge resistor that maintains the voltage of the floating capacitor (35) is interchanged between the first discharge resistor (41) and the second discharge resistor (42) as the positive ion mode and the negative ion mode are switched.

10. The three-state ion gate driving method according to claim 9, characterized in that, During the second duration of the conduction level, the rise time and fall time of the output node (38) are both no more than one-tenth of the second duration, so as to limit the time width of the released ion pack.

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