Signal detection circuit, method, battery management chip, battery system and device

Abstract

Embodiments of the present application provide a signal detection circuit, a method, a battery management chip, a battery system and equipment. The signal detection circuit comprises: a current detection module configured to perform current detection on an input signal and output a first detection signal and a second detection signal; a signal processing module connected with the current detection module, the signal processing module configured to perform power metering according to the first detection signal; and a digital detection module connected with the current detection module, the digital detection module configured to perform overcurrent detection according to the second detection signal. The effect of improving the processing function integration of the signal detection circuit is achieved.

Description

Technical Field

[0001] This application relates to the field of current processing technology, and in particular to a signal detection circuit, method, battery management chip, battery system and device. Background Technology

[0002] With the rapid development of new energy vehicles, current detection can monitor the current in the circuit in real time. Based on the current detection results, the remaining capacity of the lithium battery can be estimated, which can then be used to estimate the vehicle's driving range. Furthermore, by monitoring the overcurrent state in the circuit in real time and taking timely measures to protect the circuit and battery when overcurrent is detected, the safety, stability, and reliability of the vehicle can be improved. Therefore, integrating current detection and overcurrent detection functions can enhance system safety.

[0003] Currently, a shunt is used to convert DC current into a voltage signal; a current detection circuit detects the voltage signal to obtain the current detection result; and an overcurrent detection circuit detects the overcurrent in the voltage signal to obtain the overcurrent detection result. The current detection circuit and the overcurrent detection circuit are implemented using different chips, resulting in low functional integration of the signal detection circuit. Summary of the Invention

[0004] This application provides a signal detection circuit, method, battery management chip, battery system, and device to improve the integration of the processing functions of the signal detection circuit.

[0005] In a first aspect, embodiments of this application provide a signal detection circuit, including:

[0006] The current detection module (10) is used to detect the current of the input signal and output a first detection signal and a second detection signal;

[0007] A signal processing module (20) is connected to the current detection module (10), and the signal processing module (20) is used to perform power measurement based on the first detection signal;

[0008] A digital detection module (11) is connected to the current detection module (10), and the digital detection module (11) is used to perform overcurrent detection based on the second detection signal.

[0009] Optionally, the current detection module (10) includes:

[0010] An analog-to-digital converter (2) receives an input signal and converts the input signal into a digital signal to obtain a detection signal;

[0011] The first rate adjustment module (7) is connected to the analog-to-digital converter (2) and is used to output the detection signal at a first output rate to obtain the first detection signal.

[0012] The second rate adjustment module (70) is connected to the analog-to-digital converter (2) and is used to output the detection signal at a second output rate to obtain the second detection signal; the first output rate and the second output rate are different.

[0013] Optionally, the current detection module (10) further includes:

[0014] The first processing module (1) is connected to the analog-to-digital converter (2) and is used to increase the amplitude of the first amplitude input signal to the second amplitude and transmit the second amplitude input signal to the analog-to-digital converter (2).

[0015] The second processing module (3) is connected to the first rate adjustment module (7) and the second rate adjustment module (70), and is used to restore the amplitude of the output signal of the first rate adjustment module (7) to the first amplitude and then output it to the signal processing module (20), and restore the amplitude of the output signal of the second rate adjustment module (70) to the first amplitude and then output it to the digital detection module (11).

[0016] Optionally, the second processing module (3) includes a first processing submodule (30) and a second processing submodule (40);

[0017] The first processing submodule (30) is connected to the first rate adjustment module (7) and is used to restore the amplitude of the output signal of the first rate adjustment module (7) to the first amplitude;

[0018] The second processing submodule (40) is connected to the second rate adjustment module (70) and is used to restore the amplitude of the output signal of the second rate adjustment module (70) to the first amplitude.

[0019] Optionally, the current detection module (10) further includes: a calibration module (8);

[0020] The calibration module (8) is connected to the first rate adjustment module (7), the second rate adjustment module (70), and the second processing module (3);

[0021] The calibration module (8) is used to calibrate the signals output by the first rate adjustment module (7) and the second rate adjustment module (70) and then output them to the second processing module (3).

[0022] Optionally, the calibration module (8) includes: a first calibration submodule (80) and a second calibration submodule (83);

[0023] One end of the first calibration submodule (80) is connected to the first rate adjustment module (7); the other end of the first calibration submodule (80) is connected to the first processing submodule (30) for calibrating the received signal and then outputting it.

[0024] One end of the second calibration submodule (83) is connected to the second rate adjustment module (70); the other end of the second calibration submodule (83) is connected to the second processing submodule (40) for calibrating the received signal and then outputting it.

[0025] Optionally, the first rate adjustment module (70) includes: a decimator (71), a first filter (72), and a second filter (76);

[0026] One end of the first filter (72) is connected to the analog-to-digital converter (2), and the other end of the first filter (72) is connected to one end of the decimator (71); the other end of the decimator (71) is connected to the second filter (76).

[0027] The extractor (71) is used to extract the detection signal output by the analog-to-digital converter (2) according to a set extraction frequency to obtain the first detection signal.

[0028] Optionally, the first processing module (1) includes: an amplification module (21) and a gain control module (4);

[0029] The amplification module (21) is connected to the gain control module (4) and the analog-to-digital converter (2);

[0030] The amplification module (21) is used to amplify the input signal according to the gain parameter so that the amplitude of the amplified input signal is the second amplitude, and transmit the signal with the second amplitude to the analog-to-digital converter (2);

[0031] The gain control module (4) is used to adjust the gain parameter of the amplification module (21) according to the first amplitude.

[0032] Optionally, the second processing module (3) includes: a divider (32);

[0033] The divider (32) is connected to the first rate adjustment module (7) and the second rate adjustment module (70), and is used to divide the signals output by the first rate adjustment module (7) and the second rate adjustment module (70) by the gain parameter, so as to restore the signals output by the first rate adjustment module (7) and the second rate adjustment module (70) to the first amplitude.

[0034] Optionally, the first processing module (1) includes: an addition module (25);

[0035] The addition module (25) is connected to the analog-to-digital converter (2) and is used to sum the input signal with a preset amplitude to increase the amplitude of the input signal to the second amplitude, and transmit the signal of the second amplitude to the analog-to-digital converter (2).

[0036] Optionally, the second processing module (3) includes: a subtraction module (35);

[0037] The subtraction module (35) is connected to the first rate adjustment module (7) and the second rate adjustment module (70), and is used to calculate the difference between the signals output by the first rate adjustment module (7) and the second rate adjustment module (70) and the preset amplitude, so as to restore the amplitude of the signals output by the first rate adjustment module (7) and the second rate adjustment module (70) to the first amplitude.

[0038] Optionally, the digital detection module (11) includes: a digital comparator (13) and a counting module (14);

[0039] The digital comparator (13) is connected to the current detection module (10) and is used to output an overcurrent signal in a first state if an overcurrent is detected, and to output an overcurrent signal in a second state if no overcurrent is detected.

[0040] The counting module (14) is connected to the digital comparator (13) and is used to count the overcurrent signal of the first state continuously output by the digital comparator (13), and generate a state signal representing the overcurrent when the counting result reaches a preset number of overcurrents.

[0041] Optionally, the counting module (14) includes: a first counter (15) and a result module (16);

[0042] The first counter (15) is connected to the digital comparator (13) and is used to count the overcurrent signal of the first state continuously output by the digital comparator (13);

[0043] The result module (16) is connected to the first counter (15) and is used to generate a status signal representing the overcurrent when the counting result of the first counter (15) reaches a preset number of overcurrent cycles.

[0044] Optionally, the digital detection module (11) further includes: an overcurrent logic module (17);

[0045] The overcurrent logic module (17) is connected to the counting module (14) and is used to receive the status signal output by the counting module (14) and convert it into an overcurrent output signal.

[0046] Optionally, the digital detection module (11) further includes: an output enable module (18);

[0047] The output enable module (18) is connected to the overcurrent logic module (17) and is used to control whether to output the overcurrent output signal.

[0048] In a second aspect, embodiments of this application provide a signal detection method, based on the signal detection circuit as described in any of the first aspects, comprising:

[0049] Obtain the first detection signal and the second detection signal output by the current detection module (10) of the signal detection circuit;

[0050] The power metering result is obtained based on the first detection signal, and the overcurrent detection result is obtained based on the second detection signal.

[0051] Thirdly, embodiments of this application provide a battery management chip, including: a signal detection circuit as described in any of the first aspects.

[0052] Fourthly, embodiments of this application provide a battery system, including a battery management chip as described in the third aspect, and a battery pack.

[0053] Fifthly, embodiments of this application provide a transportation device including the battery system described in the fourth aspect.

[0054] The signal detection circuit, method, battery management chip, battery system, and device provided in this application embodiment detect the current of the input signal through the current detection module 10 and output a first detection signal and a second detection signal; the signal processing module 20 can perform power measurement based on the first detection signal; and the digital detection module 11 can perform overcurrent detection based on the second detection signal. This satisfies the integration requirements of different processing functions. Attached Figure Description

[0055] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0056] Figure 1 This is a schematic diagram of a scenario involved in an embodiment of this application;

[0057] Figure 2 This is a schematic diagram of a signal detection circuit.

[0058] Figure 3 This is a schematic diagram of a signal detection circuit provided in an embodiment of this application;

[0059] Figure 4 This is a schematic diagram of another signal detection circuit provided in an embodiment of this application;

[0060] Figure 5 This is a schematic diagram of the structure of the third signal detection circuit provided in the embodiments of this application;

[0061] Figure 6 This is a schematic diagram of the structure of the fourth signal detection circuit provided in the embodiments of this application;

[0062] Figure 7 This is a schematic diagram of the structure of the fifth signal detection circuit provided in the embodiments of this application;

[0063] Figure 8 This is a schematic diagram of the structure of a digital detection module provided in an embodiment of this application;

[0064] Figure 9 This is a schematic diagram of the sixth signal detection circuit provided in the embodiments of this application;

[0065] Figure 10 This is a schematic diagram of the structure of a rate adjustment module provided in an embodiment of this application;

[0066] Figure 11 This is a schematic diagram of the structure of a chopper module provided in an embodiment of this application;

[0067] Figure 12 This is a schematic diagram of the structure of a gain control module provided in an embodiment of this application;

[0068] Figure 13 A schematic flowchart illustrating the output gain parameters of a gain control module provided in an embodiment of this application;

[0069] Figure 14 A flowchart illustrating a processing method provided in an embodiment of this application;

[0070] Figure 15 This is a schematic diagram of another processing method provided in an embodiment of this application.

[0071] Explanation of reference numerals in the attached figures:

[0072] 1: First processing module; 10: Current detection module; 11: Digital detection module; 13: Digital comparator; 14: Counting module; 15: First counter; 16: Result module; 17: Overcurrent logic module; 18: Output enable module; 19: Status indication module; 2: Analog-to-digital converter; 20: Signal processing module; 21: Amplification module; 22: Reference module; 25: Adder module; 3: Second processing module; 30: First processing submodule; 32: Divider; 35: Subtraction module; 4: Gain control module; 40: Second processing submodule; 41: Detector; 42: Comparator; 5: Input chopper module; 51: First switch Module; 6: Output chopper module; 61: Second switch module; 7: First rate adjustment module; 70: Second rate adjustment module; 71: Extractor; 72: First filter; 73: Integrator; 74: Adder; 75: First delay unit; 76: Second filter; 77: Comb filter; 78: Subtractor; 79: Second delay unit; 8: Calibration module; 80: First calibration submodule; 83: Second calibration submodule; 9: Measurement module; S1: First switch; S2: Second switch; S3: Third switch; S4: Fourth switch; S5: Fifth switch; S6: Sixth switch; S7: Seventh switch; S8: Eighth switch.

[0073] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0074] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0075] Figure 1 This is a schematic diagram of a scenario involved in an embodiment of this application, such as... Figure 1 As shown, the specific application scenario of this application is to detect the battery current and detect whether there is an overcurrent.

[0076] With the rapid development of new energy vehicles, current detection allows for real-time monitoring of the current in the circuit. Based on the current detection results, the remaining capacity of the lithium battery can be estimated, allowing users to estimate the vehicle's driving range. Furthermore, real-time monitoring of overcurrent in the circuit and timely implementation of measures to protect the circuit and battery when overcurrent is detected improves vehicle safety, stability, and reliability. Therefore, integrating current detection and overcurrent detection functions enhances system safety.

[0077] Currently, a shunt is used to convert DC current into a voltage signal; a current detection circuit detects the voltage signal to obtain the current detection result; and an overcurrent detection circuit detects the overcurrent in the voltage signal to obtain the overcurrent detection result.

[0078] Because current detection requires high accuracy, current detection circuits typically use a high-resolution analog-to-digital converter (ADC) to convert the voltage signal into a digital voltage. The coulomb counter can then obtain the measurement result of the electrical quantity based on this digital voltage.

[0079] Because overcurrent detection requires a relatively fast detection speed, overcurrent detection circuits typically use a lower-resolution second analog-to-digital converter to convert the voltage signal into a digital voltage. A digital comparator then compares this digital voltage with an overcurrent threshold to perform overcurrent detection and obtain the overcurrent detection result.

[0080] Based on the above scenarios, it can be seen that in the existing technology, the current detection circuit and the overcurrent detection circuit are implemented by different chips, resulting in low integration of circuit functions.

[0081] Figure 2 This is a schematic diagram of a signal detection circuit. Figure 2 As shown, a shunt is used to convert DC current into a voltage signal; the current detection circuit uses a high-resolution analog-to-digital converter (ADC) to convert the voltage signal into a digital voltage, and the coulomb counter obtains the electricity measurement result based on this digital voltage; the current detection circuit transmits the digital voltage output from the ADC to the controller, which performs overcurrent detection on the digital voltage according to the set overcurrent protection threshold. Since high-resolution ADCs typically require longer conversion times to ensure the accuracy of each quantization level, this results in a relatively slow conversion rate. This method suffers from slow overcurrent detection. The vehicle cannot respond promptly to overcurrent situations and take measures to protect circuits and batteries, potentially leading to equipment damage and affecting vehicle driving safety.

[0082] In summary, how to integrate multiple processing functions into a single signal detection circuit, such as integrating current detection and overcurrent detection functions, has become an urgent problem to be solved.

[0083] In view of this, embodiments of this application provide a signal detection circuit that uses a current detection module to detect the current of an input signal and outputs a first detection signal and a second detection signal; a signal processing module uses the first detection signal to perform power metering according to detection requirements; and a digital detection module uses the second detection signal to perform overcurrent detection according to detection requirements. This satisfies the integration requirements of multiple processing functions.

[0084] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0085] Figure 3 This is a schematic diagram of a signal detection circuit provided in an embodiment of this application, as shown below. Figure 3 As shown, it includes: a current detection module 10, a signal processing module 20, and a digital detection module 11;

[0086] The current detection module 10 can be any module capable of detecting current; for example, the current detection module 10 may include a high-precision analog-to-digital converter to output a higher resolution detection signal and improve the accuracy of the detection signal.

[0087] The signal processing module 20 can be any module capable of measuring electrical energy, such as a coulomb counter, a processor, etc.

[0088] The digital detection module 11 can be any module capable of converting the received analog input signal into a digital signal, and then performing overcurrent detection on the digital signal. For example, it may include a digital comparator.

[0089] Signal processing module 20 is connected to current detection module 10; digital detection module 11 is connected to current detection module 10.

[0090] The current detection module 10 is used to detect the current of the input signal and output a first detection signal and a second detection signal. For example, the input signal can be an analog voltage signal. When the current detection module 10 detects the current of the input signal, it can convert the analog voltage signal into a digital detection signal. The digital detection signal can be used to obtain the current value corresponding to the input signal.

[0091] The signal processing module 20 is used to receive the first detection signal and perform power measurement based on the detection signal.

[0092] The digital detection module 11 is used to receive the second detection signal and perform overcurrent detection based on the detection signal.

[0093] For example, the digital detection module 11 can preset an overcurrent threshold. For instance, when the received signal is less than the overcurrent threshold, the input current can be considered to be within a safe operating range; when the received signal is greater than the overcurrent threshold, the input current can be considered to have exceeded the maximum allowable current.

[0094] The digital detection module 11 can output an overcurrent signal, which indicates whether the digital detection module 11 has detected an overcurrent. The overcurrent signal can be, for example, a high-level or low-level signal. For example, if the digital detection module 11 detects an overcurrent, it can output an overcurrent signal in a first state; if the digital detection module 11 does not detect an overcurrent, it can output an overcurrent signal in a second state. For example, the overcurrent signal in the first state can be represented by 1, and the overcurrent signal in the second state can be represented by 0.

[0095] The output rates of the first detection signal and the second detection signal can be the same or different.

[0096] For example, for the signal processing module 20, which requires accurate signal processing results but not fast processing, the signal processing module 20 can use a higher resolution first detection signal for signal processing. During signal reconstruction, it can better preserve the details of the original signal, reduce errors, and thus obtain a more accurate processing result. In this case, the current detection module 10 can output a first detection signal with a lower output rate to the signal processing module 20. Alternatively, for the digital detection module 11, which requires fast processing results, the digital detection module 11 does not need a high-precision specific current value, but only needs to quickly obtain the overcurrent detection result. In this case, the current detection module 10 can output a second detection signal with a higher output rate to the digital detection module 11. The generation time of this detection signal is short, and the overcurrent detection result can be obtained quickly.

[0097] In summary, the signal detection circuit provided in this application embodiment detects the current of the input signal through the current detection module 10 and outputs a first detection signal and a second detection signal; the signal processing module 20 can perform power measurement based on the first detection signal; and the digital detection module 11 can perform overcurrent detection based on the second detection signal. This satisfies the integration requirements of different processing functions.

[0098] Figure 4 This is a schematic diagram of another signal detection circuit provided in an embodiment of this application. Figure 3 Based on the embodiments, the structure of the signal detection circuit will be described in detail. For example... Figure 4 As shown, the current detection module 10 includes: an analog-to-digital converter 2, a first rate adjustment module 7, and a second rate adjustment module 70;

[0099] The analog-to-digital converter 2 can be any device that can convert analog signals into digital signals. For example, it can include any of the following: successive approximation register ADC, Δ-Σ (Delta-Sigma) ADC, flash ADC, dual-slope ADC, etc.

[0100] The first rate adjustment module 7 and the second rate adjustment module 70 can both be any module capable of adjusting the rate of a signal. For example, they can include any of the following: a cascaded integrator-comb filter (CIC) filter, a half-sideband filter, etc.

[0101] Analog-to-digital converter 2 receives the input signal and converts it into a digital signal to obtain a detection signal;

[0102] The first rate adjustment module 7 is connected to the analog-to-digital converter 2 and is used to output the detection signal at the first output rate to obtain the first detection signal.

[0103] The second rate adjustment module 70 is connected to the analog-to-digital converter 2 and is used to output the detection signal at the second output rate to obtain the second detection signal.

[0104] The first output rate and the second output rate are different. For example, the first rate adjustment module 7 can output one detection signal every 512 detection signals to output a first detection signal with a lower rate. The second rate adjustment module 70 can output one detection signal every 8 detection signals to output a second detection signal with a higher rate.

[0105] Different signal processing requirements may require processing detection signals with different characteristics. For example, for processing requirements that need to obtain accurate signal processing results, higher resolution detection signal samples may be needed to capture more details of the input signal and improve the accuracy of the signal processing results, but a faster response time is not required. In this case, the first rate adjustment module 7 can be set to a lower decimation frequency, and the first detection signal can be output at a lower output rate. On the other hand, for processing requirements that need to obtain signal processing results quickly, the detection signal needs to be generated quickly. In this case, the second rate adjustment module 70 can be set to a higher decimation frequency, and the time to generate the detection signal is shorter, resulting in the output of a second detection signal at a higher output rate.

[0106] The first rate adjustment module 7 and the second rate adjustment module 70 output the first detection signal and the second detection signal at different output rates.

[0107] For example, the first rate adjustment module 7 is a typical current sampling CIC filter, and the second rate adjustment module 70 is a fast CIC filter. The oversampling rate of the second rate adjustment module 70 can be set much lower than that of the first rate adjustment module 7. For instance, if the oversampling rate of the first rate adjustment module 7 is 512 times, and each sampling takes approximately 10 microseconds (µs), then the time required for the first rate adjustment module 7 to output the detection signal is 512 * 10 µs = 5.12 milliseconds (ms). Therefore, the first rate adjustment module 7 can output the first detection signal at the first rate every 5.12 ms. Since the second rate adjustment module 70 does not require a high-precision specific current value, but only a signal indicating whether there is an overcurrent, this embodiment can set the oversampling rate of the second rate adjustment module 70 to 8 times. Therefore, the time required for the second rate adjustment module 70 to output the detection signal is 8 * 10 µs = 80 µs. The speed at which the second rate adjustment module 70 outputs the detection signal is 64 times that of the first rate adjustment module 7, i.e., 5120 µs / 80 µs = 64 times. Therefore, the digital detection module 11 performs overcurrent detection on the received second detection signal at the second rate, enabling a fast overcurrent detection function.

[0108] Furthermore, since the second rate adjustment module 70 does not require a high-precision specific current value, but only a signal indicating whether there is an overcurrent, the second rate adjustment module 70 can also only receive the high-order data in the detection signal output by the analog-to-digital converter 2 and discard the low-order data, thereby reducing the resolution of the detection signal and improving the data processing rate.

[0109] For example, power metering only requires a high resolution detection signal, without specifying the signal rate. In this case, the signal processing module 20 can receive the first detection signal at a lower transmission rate output by the first rate adjustment module 7. For overcurrent detection, high-precision current measurement may not be necessary; only an overcurrent signal is required. In this case, the digital detection module 11 can receive the detection signal at a higher transmission rate output by the second rate adjustment module 70, thus improving the overcurrent detection rate. This integrates current detection, power metering, and overcurrent detection functions into the signal detection circuit.

[0110] Furthermore, the current detection module 10 may also include: a first processing module 1 and a second processing module 3;

[0111] The first processing module 1 can be any module that can increase the amplitude of the input signal, such as any of the following: a fixed gain amplifier, a programmable gain amplifier, a transformer, a superimposed input signal source, etc.

[0112] The second processing module 3 can be any module that can reduce the amplitude of the input signal, such as any of the following: divider, voltage divider, transformer, or input signal source that subtracts superimposed signals.

[0113] The first processing module 1 is connected to the analog-to-digital converter 2 and is used to increase the amplitude of the first amplitude input signal to the second amplitude and transmit the second amplitude input signal to the analog-to-digital converter 2.

[0114] The second processing module 3 is connected to the first rate adjustment module 7 and the second rate adjustment module 70. It is used to restore the amplitude of the output signal of the first rate adjustment module 7 to the first amplitude and then output it to the signal processing module 20, and to restore the amplitude of the output signal of the second rate adjustment module 70 to the first amplitude and then output it to the digital detection module 11.

[0115] By adding a first processing module 1 before the analog-to-digital converter 2 to increase the amplitude of the input signal, the analog-to-digital converter 2 converts the amplified input signal into a digital signal. When the analog-to-digital converter 2 converts the amplified input signal, each quantization level of the analog-to-digital converter 2 represents a smaller actual voltage change, thereby improving the detection accuracy of the input signal and reducing errors. The first rate adjustment module 7 adjusts the signal rate output by the analog-to-digital converter 2, which can output a lower-rate first detection signal with higher accuracy. The second rate adjustment module 70 adjusts the signal rate output by the analog-to-digital converter 2, which can output a higher-rate second detection signal with higher accuracy. Then, a second processing module 3 is added to restore the amplitude of the output signals of the first rate adjustment module 7 and the second rate adjustment module 70 to obtain a first detection signal and a second detection signal with the same amplitude as the input signal, further improving the accuracy of the first detection signal and the second detection signal.

[0116] Furthermore, the second processing module 3 may include a first processing submodule 30 and a second processing submodule 40;

[0117] The first processing submodule 30 is connected to the first rate adjustment module 7 and is used to restore the amplitude of the output signal of the first rate adjustment module 7 to the first amplitude.

[0118] The second processing submodule 40 is connected to the second rate adjustment module 70 and is used to restore the amplitude of the output signal of the second rate adjustment module 70 to the first amplitude.

[0119] Furthermore, the current detection module 10 also includes: a calibration module 8;

[0120] The calibration module 8 can be any module that can calibrate the received signal.

[0121] The calibration module 8 is connected to the first rate adjustment module 7, the second rate adjustment module 70, and the second processing module 3; the calibration module 8 is used to calibrate the signals output by the first rate adjustment module 7 and the second rate adjustment module 70 and then output them to the second processing module.

[0122] By calibrating the signals output by the first rate adjustment module 7 and the second rate adjustment module 70 through the calibration module 8, deviations introduced in the other processing modules of the signal detection circuit before the signal is transmitted to the calibration module 8 can be corrected, thereby improving the accuracy of the output signal and the accuracy of power measurement and overcurrent detection.

[0123] Calibration module 8 includes: a first calibration submodule 80 and a second calibration submodule 83;

[0124] One end of the first calibration submodule 80 is connected to the first rate adjustment module 7; the other end of the first calibration submodule 80 is connected to the first processing submodule 30, and is used to calibrate the signal output by the received first rate adjustment module 7 and then output it.

[0125] One end of the second calibration submodule 83 is connected to the second rate adjustment module 70; the other end of the second calibration submodule 83 is connected to the second processing submodule 40, and is used to calibrate the signal received from the second rate adjustment module 70 before outputting it.

[0126] Furthermore, the signal processing module 20 may also include a metering module 9; the metering module 9 may be any module capable of measuring electrical energy, such as any of the following: coulomb counter, processor, etc.

[0127] The metering module 9 is connected to the second processing module 3 and is used to measure the power of the second detection signal.

[0128] Furthermore, the metering module 9 may include a coulomb meter. After converting the detection signal into a current signal, the coulomb meter integrates the current signal over time to measure the amount of electricity.

[0129] Coulomb counters calculate power consumption by integrating the current flowing through a circuit. Typically, a coulomb counter receives a voltage value, converts it to a current value, and then integrates it over time. This voltage value must be the input voltage. To improve current detection accuracy, related current detection modules often increase the amplitude of the input signal and then perform analog-to-digital conversion (ADC) on this increased signal. This reduces the amount of change in the actual input voltage represented by each quantization result of the ADC. However, this method essentially alters the output voltage value, leading to a mismatch between current detection and coulomb counter measurement requirements. This solution's current detection module first increases the amplitude of the input signal, then converts the analog signal to a digital signal, improving current detection accuracy. Finally, it restores the digital signal to a voltage with the same amplitude as the input signal, making it well-suited for coulomb counters and easy to integrate.

[0130] Figure 4 The following is an illustrative example: the signal detection circuit includes a first processor module 1, an analog-to-digital converter 2, a first rate adjustment module 7, a second rate adjustment module 70, a signal processing module 20, and a digital detection module 11; the calibration module 8 includes a first calibration submodule 80 and a second calibration submodule 83; and the second processing module 3 includes a first processing submodule 30 and a second processing submodule 40.

[0131] The first processing module 1 is connected to the input terminal of the analog-to-digital converter 2; the output terminal of the analog-to-digital converter 2 is connected to the input terminals of the first rate adjustment module 7 and the second rate adjustment module 70; the output terminal of the first rate adjustment module 7 is connected to the input terminal of the first calibration submodule 80; the output terminal of the second rate adjustment module 70 is connected to the input terminal of the second calibration submodule 83; the output terminal of the first calibration submodule 80 is connected to the input terminal of the first processing submodule 30; the output terminal of the second calibration submodule 83 is connected to the input terminal of the second processing submodule 40; the output terminal of the first processing submodule 30 is connected to the signal processing module 20; and the output terminal of the second processing submodule 40 is connected to the digital detection module 11.

[0132] The signal processing procedure of a signal detection circuit can be illustrated as follows:

[0133] For example, the first processor module 1 receives an input signal of a first amplitude and increases the amplitude of the input signal to a second amplitude; the first processing module 1 transmits the input signal of the second amplitude to the analog-to-digital converter 2; the analog-to-digital converter 2 converts the signal of the second amplitude into a digital signal; the analog-to-digital converter 2 transmits the digital signal of the second amplitude to the first rate adjustment module 7 and the second rate adjustment module 70; the first rate adjustment module 7 outputs a first detection signal to the first calibration submodule 80 according to a first output rate; the second rate adjustment module 70 outputs a second detection signal to the second calibration submodule 83 according to a second output rate; the first calibration submodule 80 processes the received signal... After calibration, the signal is output to the first processing submodule 30; the second calibration submodule 83 calibrates the received signal and outputs it to the second processing submodule 40; the first processing submodule 30 restores the received second amplitude digital signal to the first amplitude and transmits it to the signal processing module 20; the second processing submodule 40 restores the received second amplitude digital signal to the first amplitude and transmits it to the digital detection module 11; the signal processing module 20 receives the detection signal output by the first processing submodule 30 and performs power metering based on the detection signal; the digital detection module 11 receives the detection signal output by the second processing submodule 40 and performs overcurrent detection based on the detection signal.

[0134] For example, if the resolution of analog-to-digital converter 2 is 0.1V and the first amplitude of the input signal is 1V, then the input signal represents 10 quantization levels, and the actual voltage corresponding to each quantization level is 0.1V. The first processing module 1 increases the amplitude of the input signal by 10 times, that is, the second amplitude is 10V. In analog-to-digital converter 2 with the same resolution, 10V can correspond to 100 quantization levels, and the voltage corresponding to each quantization level is 0.1V. This 0.1V voltage corresponds to the voltage after the actual voltage is increased by 10 times, so the actual voltage corresponding to each quantization level is 0.01V. When analog-to-digital converter 2 performs analog-to-digital conversion on the input signal with the second amplitude, the actual input voltage represented by each quantization result of analog-to-digital converter 2 changes less, and the detection accuracy is higher. The second processing module 3 restores the digital signal with the second amplitude to the first amplitude, and the signal transmitted by the second processing module 3 to the signal processing module 20 and the digital detection module 11 has higher accuracy. The signal processing module 20 performs power measurement on the received signal, and the output processing result is more accurate; the digital detection module 11 performs overcurrent detection on the received signal, and the output processing result is more accurate. This improves the accuracy of signal detection results.

[0135] In summary, the signal detection circuit provided in this application converts the input signal into a digital signal through an analog-to-digital converter 2, and outputs a detection signal at intervals of different numbers of detection signals through a first rate adjustment module 7 and a second rate adjustment module 70, thereby outputting a first detection signal and a second detection signal at different output rates; the signal processing module 20 receives the first detection signal and performs power metering based on the detection signal; the digital detection module 11 receives the second detection signal and performs overcurrent detection based on the detection signal. This satisfies the integrated requirements of current detection, overcurrent detection, and power metering functions. By adding a first processing module 1 before the analog-to-digital converter 2 to increase the amplitude of the input signal, the analog-to-digital converter 2 is used to convert the amplified input signal into a digital signal. When the analog-to-digital converter 2 converts the amplified input signal, the actual voltage change represented by each quantization level of the analog-to-digital converter 2 is smaller, thereby improving the detection accuracy of the input signal and reducing the error. After the first rate adjustment module 7 and the second rate adjustment module 70, a second processing module 3 is added to restore the amplitude of the output signals of the first rate adjustment module 7 and the second rate adjustment module 70, and output detection signals at different rates, thereby improving the accuracy of the processing results of the signal processing module 20 and the digital detection module 11.

[0136] Figure 5 This is a schematic diagram of the structure of a third signal detection circuit provided in an embodiment of this application. Figure 4 Based on the embodiments, the structure of the signal detection circuit will be described in detail. For example... Figure 5 As shown,

[0137] The first processing module 1 may include, for example, an amplification module 21 and a gain control module 4; the second processing module 3 may include a divider 32.

[0138] The amplification module 21 can be any module that can amplify signals, such as a fixed gain amplifier, a programmable gain amplifier, etc.

[0139] Gain control module 4 can be any module capable of dynamically adjusting gain parameters.

[0140] The divider 32 can be any device capable of dividing one digital value by another. For example, it can be a hardware divider implemented with an integrated circuit, or a divider implemented using a software algorithm in a processor.

[0141] Amplification module 21 is connected to gain control module 4 and analog-to-digital converter 2; gain control module 4 is connected to amplification module 21; first rate adjustment module 7 and second rate adjustment module 70 are connected to analog-to-digital converter 2; divider 32 is connected to first rate adjustment module 7 and second rate adjustment module 70.

[0142] Amplification module 21 amplifies the input signal according to the gain parameter, so that the amplitude of the amplified input signal is a second amplitude, and transmits the second amplitude signal to analog-to-digital converter 2. Amplifying the input signal according to the gain parameter allows for precise control of the amplification factor.

[0143] Furthermore, the gain parameter of the amplification module 21 is adjustable. The amplitude of the input signal may vary considerably, and the adjustable gain parameter allows the amplification module to dynamically adjust the amplification factor according to the amplitude of the input signal, ensuring that the output signal remains within the operating range of subsequent devices. For example, when the input signal amplitude is small, the amplification module 21 can use a larger gain parameter to improve the resolution of signals with smaller amplitudes; when the input signal amplitude is large, the amplification module 21 can use a smaller gain parameter to prevent the output amplitude from exceeding the operating range of subsequent devices.

[0144] The gain control module 4 is used to adjust the gain parameters of the amplification module 21 according to the first amplitude. The gain control module 4 can adjust the gain parameters of the amplification module 21 according to the first amplitude, allowing the amplification module 21 to use different gain parameters for amplifying input signals of different amplitudes. This achieves more precise gain control, improves gain stability, and enhances the adaptability of the amplification module 21. The gain control module 4 can optimize the gain parameters according to the strength of the input signal, ensuring that the output signal is within a suitable dynamic range.

[0145] Furthermore, the magnitude of the gain parameter can be negatively correlated with the magnitude of the first amplitude. For example, the smaller the first amplitude, the larger the gain parameter, which can amplify the signal with a smaller amplitude by a larger factor, further improving the detection accuracy of the signal; the larger the first amplitude, the smaller the gain parameter, which can amplify the signal with a larger amplitude by a smaller factor, making the output signal more stable and ensuring that the output signal is within a suitable dynamic range.

[0146] Divider 32 is used to divide the signals output by the first rate adjustment module 7 and the second rate adjustment module 70 by the gain parameter, so as to restore the signals output by the first rate adjustment module 7 and the second rate adjustment module 70 to the first amplitude.

[0147] Furthermore, the amplification module 21 also includes a reference module 22; the reference module 22 can be any module that can provide DC voltage, such as any of the following: a reference voltage source, a voltage regulator, etc.

[0148] The reference module 22 is connected to the input terminal of the amplifier module 21 and is used to provide a reference level for the input signal. For example, the amplifier module 21 can provide a stable reference point so that the output voltage is within the signal range that the amplifier module 21 can process.

[0149] Furthermore, the reference module 22 may include a voltage source. One end of the voltage source receives the input signal, and the other end of the voltage source is connected to the input terminal of the amplifier module 21. This approach is easy to implement.

[0150] In summary, the signal detection circuit provided in this application increases the amplitude of the input signal by adding an amplification module 21 before the analog-to-digital converter 2, and then uses the analog-to-digital converter 2 to convert the amplified input signal into a digital signal. When the analog-to-digital converter 2 converts the amplified input signal, each quantization level of the converter 2 represents a smaller actual voltage change, thereby improving the detection accuracy of the input signal and reducing errors. Adding a divider 32 after the analog-to-digital converter 2 restores the amplitude of the output signals of the first rate adjustment module 7 and the second rate adjustment module 70 to the first amplitude, improving the accuracy of the output signal. The signal processing module 20 performs power measurement on the received signal, and the digital detection module 11 performs overcurrent detection on the received signal, resulting in a more accurate output overcurrent signal.

[0151] Figure 6 This is a schematic diagram of the structure of the fourth signal detection circuit provided in an embodiment of this application. Figure 4 Based on the embodiments, the structure of the signal detection circuit will be described in detail. For example... Figure 6 As shown,

[0152] The first processing module 1 may include, for example, an addition module 25; the second processing module 3 may include a subtraction module 35.

[0153] The addition module 25 can be any module capable of summing two received signals. For example, it can be an adder.

[0154] The subtraction module 35 can be any module that can calculate the difference between the received signals. For example, it can be a subtractor.

[0155] The addition module 25 is connected to the input terminal of the analog-to-digital converter 2; the subtraction module 35 is connected to the first rate adjustment module 7 and the second rate adjustment module 70.

[0156] The adder module 25 is used to sum the input signal with a preset amplitude to increase the amplitude of the input signal to a second amplitude, and then transmit the signal with the second amplitude to the analog-to-digital converter 2. For example, one end of the adder module 25 receives the input signal, and the other end is connected to a signal source, with the value of the signal source serving as the preset amplitude. The adder module 25 can superimpose the input signal with the signal source to increase the amplitude of the input signal to the second amplitude.

[0157] Analog-to-digital converter 2 is used to convert the output signal of adder module 25 into a digital signal.

[0158] The first rate adjustment module 7 is used to output the output signal of the analog-to-digital converter 2 at a first output rate to obtain the first detection signal.

[0159] The second rate adjustment module 70 is used to output the output signal of the analog-to-digital converter 2 at a second output rate to obtain a second detection signal.

[0160] The subtraction module 35 is used to subtract a preset amplitude from the signals output by the first rate adjustment module 7 and the second rate adjustment module 70, so as to restore the amplitude of the signals output by the first rate adjustment module 7 and the second rate adjustment module 70 to a first amplitude. For example, one end of the subtraction module 35 receives an input signal, and the other end is connected to a signal source, with the value of the signal source serving as the preset amplitude. The subtraction module 35 can subtract the input signal from the signal source to restore the amplitude of the input signal to the first amplitude.

[0161] In summary, the signal detection circuit provided in this application increases the amplitude of the input signal by adding an adder module 25 before the analog-to-digital converter 2, and then uses the analog-to-digital converter 2 to convert the increased input signal into a digital signal. When the analog-to-digital converter 2 converts the increased input signal, each quantization level of the converter represents a smaller actual voltage change, thereby improving the detection accuracy of the input signal and reducing errors. The first rate adjustment module 7 and the second rate adjustment module 70 output the output signal of the analog-to-digital converter 2 at different rates. A subtraction module 35 is added after the first rate adjustment module 7 and the second rate adjustment module 70 to restore the amplitude of the output signals, improving the accuracy of the output signal. The signal processing module 20 performs power measurement on the received signal, and the digital detection module 11 performs overcurrent detection on the received signal, resulting in more accurate power measurement results and overcurrent signals.

[0162] Figure 7 This is a schematic diagram of the structure of the fifth signal detection circuit provided in an embodiment of this application. Figure 5 Based on the embodiments, the structure of the signal detection circuit will be described in detail. For example... Figure 7 As shown,

[0163] The current detection module 10 may further include an input chopper module 5. The input chopper module 5 can be any module capable of increasing the signal frequency, such as a multiplier, mixer, phase-locked loop, charge pump, etc. The input chopper module 5 can increase the signal frequency, for example, by modulating the input signal with a periodic signal. The input chopper module 5 is located at the input terminal of the first processing module 1. The input chopper module 5 is used to increase the frequency of the input signal and transmit the increased frequency input signal to the first processing module 1. The input chopper module 5 suppresses low-frequency noise by increasing the frequency of the input signal.

[0164] Furthermore, the input chopper module 5 is specifically used to perform square wave modulation on the input signal to increase its frequency. Square wave modulation does not require duty cycle control and is easy to implement.

[0165] The input chopper module 5 includes: a first switch module 51; the first switch module 51 can be any module based on high or low level conduction, such as any one of the following: transistor, field-effect transistor (MOSFET), also known as MOS transistor, thyristor, etc.

[0166] One end of the first switching module 51 is connected to the input signal; the other end of the first switching module 51 is connected to the input terminal of the first processing module 1. The first switching module 51 is used to turn on or off in response to a control signal to modulate the input signal with a square wave, thereby increasing the frequency of the input signal. For example, under the action of a control signal, the first switching module 51 periodically switches the signal path to modulate the input signal to a chopping frequency with the same frequency as the control signal, thereby increasing the frequency of the input signal. This can suppress low-frequency noise.

[0167] The control signal for the first switching module 51 is a square wave signal. Under the action of the square wave signal, the first switching module 51 periodically turns on or off, modulating the input signal with a square wave. This method does not require the duty cycle of the control signal and is easy to implement.

[0168] The current detection module 10 also includes an output chopper module 6; the output chopper module 6 can be any module that can reduce the signal frequency. For example, the output chopper module 6 can demodulate the signal modulated at the chopper frequency to the original input signal frequency by quickly switching the input signal.

[0169] The output chopper module 6 is located between the first processing module 1 and the rate adjustment module 7. It is used to reduce the frequency of the received signal and output the signal after the frequency reduction.

[0170] In one example, the output chopper module 6 can be located between the first processing module 1 and the analog-to-digital converter 2. The output chopper module 6 can demodulate the input signal modulated at the chopping frequency back to the original input signal frequency, and modulate the offset voltage and low-frequency noise of the first processing module 1 to a high frequency. This distinguishes the frequencies of the input signal from the noise.

[0171] In another example, the output chopper module 6 can be positioned between the analog-to-digital converter 2 and the rate adjustment module 7. The output chopper module 6 can demodulate the input signal modulated at the chopper frequency back to the original input signal frequency, and modulate the offset voltage and low-frequency noise of the first processing module 1 to a high frequency. This distinguishes the frequencies of the input signal from the noise.

[0172] Furthermore, the output chopper module 6 includes a second switching module 61; the second switching module 61 can be any module based on high or low level conduction, such as any one of the following: transistor, field-effect transistor (MOSFET), also known as MOS transistor, thyristor, etc.

[0173] One end of the second switching module 61 is connected to the output terminal of the first processing module 1; the other end of the second switching module 61 is connected to the input terminal of the analog-to-digital converter 2. The second switching module 61 is used to turn on or off in response to a control signal to reduce the frequency of the received signal and output the signal with the reduced frequency. For example, under the action of a control signal, the second switching module 61 periodically switches the signal path, demodulating the signal modulated at the same chopping frequency as the control signal to the original input signal frequency, thereby reducing the frequency of the input signal. This can restore the original form of the input signal.

[0174] The input signal undergoes two chopping operations, one in the input chopper module 5 and the other in the output chopper module 6. The offset voltage of the first processing module 1 is processed only once by the output chopper module 6. This ensures that the input signal maintains its waveform at the output of the output chopper module 6, and the chopping offset voltage can be eliminated by subsequent filters, thereby suppressing noise and offset voltage. This allows the first processing module 1 to have a higher dynamic range and further improves the overcurrent detection accuracy.

[0175] Figure 7 The signal detection circuit includes: an input chopper module 5, an amplification module 21, a gain control module 4, an analog-to-digital converter 2, an output chopper module 6, a first rate adjustment module 7, a second rate adjustment module 70, a first calibration submodule 80, a second calibration submodule 83, a first subprocessing module 30, a second subprocessing module 40, a signal processing module 20, and a digital detection module 11; wherein the first subprocessing module 30 includes a divider d1 and the second subprocessing module 40 includes a divider d2, as an example for illustration.

[0176] The input terminal of the input chopper module 5 receives the input signal; the output terminal of the input chopper module 5 is connected to the input terminal of the amplification module 21 and the input terminal of the gain control module 4; the output terminal of the gain control module 4 is connected to the gain control terminal of the amplification module 21; the output terminal of the amplification module 21 is connected to the input terminal of the analog-to-digital converter 2; the output terminal of the analog-to-digital converter 2 is connected to the input terminal of the output chopper module 6; the output terminal of the output chopper module 6 is connected to the input terminals of the first rate adjustment module 7 and the second rate adjustment module 70; the output terminal of the first rate adjustment module 7 is connected to the input terminal of the first calibration submodule 80; the output terminal of the first calibration submodule 80 is connected to the input terminal of the divider d1; the output terminal of the divider d1 is connected to the input terminal of the signal processing module 20; the output terminal of the second rate adjustment module 70 is connected to the input terminal of the second calibration submodule 83; the output terminal of the second calibration submodule 83 is connected to the input terminal of the divider d2; the output terminal of the divider d2 is connected to the input terminal of the digital detection module 11.

[0177] The signal processing procedure of a signal detection circuit can be illustrated as follows:

[0178] The input chopper module 5 receives an input signal of the first amplitude. The input chopper module 5 includes a first switch module 51, which is turned on or off under the action of a square wave signal. The polarity of the input signal is rapidly switched alternately at the frequency of the square wave signal to modulate the input signal of the first amplitude, thereby increasing the frequency of the input signal. The input chopper module 5 transmits the modulated signal to the amplification module 21.

[0179] The gain control module 4 adjusts the gain parameter of the amplification module 21 according to the first amplitude.

[0180] The amplification module 21 amplifies the input signal according to the gain parameter, increases the amplitude of the modulated input signal to a second amplitude, and transmits it to the analog-to-digital converter 2.

[0181] The analog-to-digital converter 2 converts the signal of the second amplitude into a digital signal; the analog-to-digital converter 2 transmits the digital signal of the second amplitude to the output chopper module 6.

[0182] The output chopper module 6 is turned on or off under the action of the square wave signal, and the polarity of the input signal is rapidly switched alternately at the frequency of the square wave signal to demodulate the digital signal of the second amplitude and restore the digital signal of the second amplitude back to the original frequency; at the same time, the offset voltage and low frequency noise amplified by the amplification module 21 are modulated to a high frequency; the output chopper module 6 transmits the demodulated digital signal of the second amplitude to the first rate adjustment module 7 and the second rate adjustment module 70.

[0183] The first rate adjustment module 7 outputs a signal to the first calibration submodule 80 at the output rate corresponding to the detection signal required by the signal processing module 20; the second rate adjustment module 70 outputs a signal to the second calibration submodule 83 at the output rate corresponding to the digital detection module 11.

[0184] The first calibration submodule 80 calibrates the received signal and outputs it to the divider d1; the second calibration submodule 83 calibrates the received signal and outputs it to the divider d2.

[0185] Divider d1 restores the received digital signal of the second amplitude to the first amplitude, outputs a detection signal at the first output rate (also known as the first detection signal), and transmits the detection signal at the first output rate to the signal processing module 20; divider d2 restores the received digital signal of the second amplitude to the first amplitude, outputs a detection signal at the second output rate (also known as the second detection signal), and transmits the detection signal at the second output rate to the digital detection module 11.

[0186] The signal processing module 20 receives the first detection signal and performs power metering based on the detection signal; the digital detection module 11 receives the second detection signal and performs overcurrent detection based on the detection signal.

[0187] The signal detection circuit provided in this application embodiment increases the amplitude of the input signal by adding an amplification module 21 before the analog-to-digital converter 2. The amplified input signal is then converted into a digital signal by the analog-to-digital converter 2. When converting the amplified input signal, the actual voltage change represented by each quantization level of the analog-to-digital converter 2 is smaller, thereby improving the detection accuracy of the input signal and reducing errors. The first rate adjustment module 7 and the second rate adjustment module 70 collect different numbers of samples of the input signal and output them at different rates to generate detection signals. The first calibration submodule 80 and the second calibration submodule 83 calibrate the received signal and correct the deviations introduced by the other processing modules. Adding a divider after the first calibration submodule 80 and the second submodule 83 can restore the amplitude amplified by the amplification module 21 and output a detection signal with the same amplitude as the input signal, resulting in more accurate processing results. By adding an input chopper module 5 before the first processing module 1 and an output chopper module 6 after the first processing module 1, noise can be suppressed, allowing the first processing module 1 to have a higher dynamic range and further improving the detection accuracy of the signal processing module. By dynamically adjusting the amplification factor of the amplification module 21 through the gain control module 4, the overcurrent detection accuracy can be further improved, thus enhancing the accuracy of the processing results.

[0188] The structure of the digital detection module 11 is described below.

[0189] Figure 8 This is a schematic diagram of the structure of a digital detection module provided in an embodiment of this application. Figure 8 As shown, the digital detection module 11 may include, for example, a digital comparator 13 and a counting module 14;

[0190] The digital comparator 13 can be any device capable of comparing the magnitudes of two digital signals.

[0191] The counting module 14 can be any module capable of incrementing its count value upon receiving a digital signal and outputting different signals based on the count value. For example, the counting module 14 can increment upon receiving a high level, or the counting module 14 can increment upon receiving a low level.

[0192] Digital comparator 13 is connected to current detection module 10; counting module 14 is connected to digital comparator 13.

[0193] Digital comparator 13 is used to output an overcurrent signal in a first state if an overcurrent is detected, and an overcurrent signal in a second state if no overcurrent is detected. For example, if the received signal exceeds a set overcurrent threshold, digital comparator 13 outputs an overcurrent signal in the first state; if the received signal does not exceed the set overcurrent threshold, it outputs an overcurrent signal in the second state.

[0194] The counting module 14 is used to count the overcurrent signal of the first state continuously output by the overcurrent detection module 11, and generate a state signal representing the overcurrent when the counting result reaches the preset number of overcurrents.

[0195] Furthermore, the counting module 14 may include, for example, a first counter 15 and a result module 16;

[0196] The first counter 15 can be any module that increments its count value when a digital signal is received; the result module 16 can be a module that outputs different signals according to the count value, such as a comparator; for example, the result module 16 can output a high-level signal when the count value reaches a preset count value; the result module 16 can output a low-level signal when the count value is less than the preset count value.

[0197] The first counter 15 is connected to the digital comparator 13; the result module 16 is connected to the first counter 15.

[0198] The first counter 15 is used to count the overcurrent signal of the first state continuously output by the digital comparator 13; the result module 16 is used to generate a state signal representing the overcurrent when the counting result of the first counter 15 reaches a preset number of overcurrents.

[0199] In one example, analog-to-digital converter 2 receives an input signal and converts it into a digital signal; digital comparator 13 performs overcurrent detection on the received signal; if the received signal exceeds a set overcurrent threshold, it outputs an overcurrent signal in a first state, such as a high-level signal; if the received signal does not exceed the set overcurrent threshold, it outputs an overcurrent signal in a second state, such as a low-level signal; the first counter 15 of counting module 14 counts the overcurrent signals in the first state continuously output by digital comparator 13; when the counting result reaches a preset number of overcurrent cycles, the result module 16 of counting module 14 generates a state signal representing the overcurrent, such as a high-level signal; when the counting result does not reach the preset number of overcurrent cycles, the result module 16 of counting module 14 does not generate a state signal representing the overcurrent.

[0200] Furthermore, the counting module 14 is also used to reset the count when the digital comparator 13 outputs an overcurrent signal of the second state. For example, if the preset number of overcurrent events for the counting module 14 is 10, then when the digital comparator 13 continuously outputs 10 or more overcurrent signals of the first state, the counting module 14 generates a state signal representing an overcurrent; if the digital comparator 13 continuously outputs 9 overcurrent signals of the first state, then the counting module 14 generates a state signal representing no overcurrent, and resets the count when it receives the 10th signal which is an overcurrent signal of the second state.

[0201] When the number of overcurrent signals continuously output by the digital comparator 13 in the first state reaches a preset number of overcurrent cycles, the counting module 14 generates an overcurrent state signal, which avoids the problem of misjudgment caused by glitches when the digital comparator detects overcurrent in the received signal, and improves the accuracy of the detection results.

[0202] In summary, the digital detection module 11 provided in this embodiment performs overcurrent detection on the received second detection signal; the counting module 14 generates a status signal representing whether an overcurrent has occurred based on the number of times the digital comparator 13 continuously detects an overcurrent, replacing the digital comparator 13's assumption that an overcurrent has occurred upon detecting a single overcurrent event. This avoids the problem of misjudgment caused by glitches when the digital comparator 13 performs overcurrent detection on the received signal, thus improving the accuracy of the detection results.

[0203] Furthermore, the digital detection module 11 can also output a status signal indicating whether an overcurrent has occurred to a circuit outside the signal detection circuit to trigger that circuit or module to respond to the overcurrent condition. For example, the digital detection module 11 can output the status signal to a protection circuit, controlling the protection circuit to cut off the power supply or load, reduce the motor speed, limit the current, or shut down the motor when the status signal indicates an overcurrent, thereby protecting the equipment or circuit from damage. Alternatively, the digital detection module 11 can output the status signal to an alarm system, triggering the audible and visual alarm of the alarm system when the status signal indicates an overcurrent, to notify the user of the overcurrent situation. To match the operating level of the external circuit, the digital detection module 11 can perform logical processing on the status signal before outputting it.

[0204] For example, the digital detection module 11 may also include: an overcurrent logic module 17;

[0205] The overcurrent logic module 17 can be, for example, any module that performs logic processing on any pair of input signals. For example, it can include any of the following: AND gate, OR gate, NOT gate, Pulse Width Modulation (PWM) module, etc.

[0206] The overcurrent logic module 17 is connected to the counting module 14 and is used to receive the status signal output by the counting module 14 and convert it into an overcurrent output signal. For example, when the status signal indicates an overcurrent, the overcurrent logic module 17 can convert the received input signal into a valid output such as a high level, low level, or PWM signal, thereby controlling the external circuit for overcurrent detection to respond to the overcurrent state.

[0207] Furthermore, the digital detection module 11 also includes an output enable module 18;

[0208] The output enable module 18 can be any module that is turned on based on a high-level or low-level signal, such as a transistor, a field-effect transistor (MOSFET), also known as a MOS transistor, thyristor, etc.

[0209] The output enable module 18 is connected to the overcurrent logic module 17 and is used to control whether the output signal of the overcurrent logic module 17 is output. The output enable module 18 may include, for example, a control terminal connected to an enable signal; when the enable signal is high, the output signal of the overcurrent logic module 17 is allowed to be output; when the enable signal is low, the output signal of the overcurrent logic module 17 is stopped. The output enable module 18 ensures that the overcurrent output signal of the overcurrent logic module 17 will not be accidentally activated during the start-up, stop, or fault recovery process of the signal detection circuit, thereby improving system safety.

[0210] Furthermore, the digital detection module 11 can also indicate the current state of the system, such as whether an overcurrent has occurred.

[0211] For example, the digital detection module 11 also includes: a status indication module 19;

[0212] The status indication module 19 can be any module that can indicate the operating status based on the received signals. For example, it can be a flag register.

[0213] The status indication module 19 is connected to the counting module 14 and is used to indicate the overcurrent status based on the status signal output by the counting module 14. For example, when the status signal output by the counting module 14 indicates an overcurrent, the status indication module 19 changes its recorded value to indicate whether an overcurrent has occurred, and can maintain its status unchanged after an overcurrent occurs until the overcurrent status needs to be cleared. In this way, the processor can monitor the overcurrent status of the system based on the value recorded by the status indication module 19.

[0214] Furthermore, the status indication module 19 may include: a flag register;

[0215] A flag register can be a special register in the processor used to store status information, such as overcurrent status. Overcurrent status information can be represented by a flag indicating whether an overcurrent has occurred.

[0216] A flag register is used to record the overcurrent flag bit as a first value (e.g., 0) when a status signal indicates an overcurrent, and as a second value (e.g., 1) when the overcurrent state is cleared. In one example, when the status signal indicates an overcurrent, the overcurrent flag bit is recorded as 1. The processor can read this overcurrent flag bit to trigger a termination or perform a specific operation in response to the overcurrent event. After processing the overcurrent event, the processor can also clear the overcurrent state in the flag register. For example, the processor can send a software instruction to the flag register to clear the overcurrent flag bit, resetting it to 0. The flag register can continue to monitor and record new overcurrent states.

[0217] Figure 9 This is a schematic diagram of the sixth signal detection circuit provided in an embodiment of this application. Figure 9 As shown,

[0218] The signal detection circuit includes: an amplification module 21, a gain control module 4, an analog-to-digital converter 2, a first rate adjustment module 7, a second rate adjustment module 70, a calibration module 8, a divider 32, a signal processing module 20, a digital comparator 13, a first counter 15, a result module 16, an overcurrent logic module 17, and an output enable module 18.

[0219] The amplification module 21 includes a programmable gain amplifier (PGA); the gain control module 4 includes a gain control module (GCB); the analog-to-digital converter 2 includes an I-ADC (ADC); the first rate adjustment module 7 includes a CIC filter; the second rate adjustment module 70 includes a FAST CIC filter; and the calibration module 8 includes a calibration module.

[0220] Digital comparator 13 includes OC DIG CMP, first counter 15 includes Counter, result module 16 includes Result, overcurrent logic module 17 includes OC Logic, output enable module 18 includes Drive; signal processing module 20 includes Coulomb Count and Current Register (Current SFR).

[0221] The first input terminal SRP is connected to the first input terminal of the programmable gain amplifier PGA and the first input terminal of the gain control module GCB; the second input terminal SRN is connected to the second input terminal of the programmable gain amplifier PGA and the second input terminal of the gain control module GCB; the output terminal of the gain control module GCB is connected to the gain control terminal of the programmable gain amplifier PGA; the output terminal of the programmable gain amplifier PGA is connected to the input terminal of the ADC; the output terminal of the ADC is connected to the input terminals of the CIC filter and the FAST CIC filter; the output terminals of the CIC filter and the FAST CIC filter are connected to the input terminal of the calibration module Correction; the output terminal of the calibration module Correction is connected to the input terminal of the divider 32; the first output terminal of the divider 32 is connected to the input terminal of the digital comparator OC DIG CMP; the output terminal of the digital comparator OC DIG CMP is connected to the input terminal of the first counter Counter; the output terminal of the first counter Counter is connected to the input terminal of the result module Result; the output terminal of the result module Result is connected to the input terminal of the overcurrent logic module OC Logic and the input terminal of the status indicator module Flag SFR; the overcurrent logic module OC... The output of the Logic module is connected to the input of the output enable module Drive; the control terminal of the output enable module Drive is connected to the enable signal Disable Drive; the output enable module Drive outputs an overcurrent output signal to the output terminal OC. The second output of the divider 32 is connected to the Coulomb Count and the Current Register (Current SFR).

[0222] (1) The signal processing procedure for electricity metering can be as follows:

[0223] The voltage drop generated by the DC current through the shunt is input to the first input terminal SRP and the second input terminal SRN.

[0224] The programmable gain amplifier (PGA) receives the input signal of the first amplitude.

[0225] The gain control module GCB adjusts the gain parameters of the programmable gain amplifier PGA based on the first amplitude.

[0226] The programmable gain amplifier (PGA) amplifies the input signal according to the gain parameter, increases the amplitude of the modulated input signal to a second amplitude, and transmits it to the ADC.

[0227] The ADC converts the second-amplitude signal into a digital signal; the ADC then transmits the second-amplitude digital signal to the CIC filter.

[0228] The CIC filter reduces the rate of the second-amplitude digital signal to the first rate before transmitting it to the calibration module.

[0229] The calibration module calibrates the received signal and outputs it to the divider 32.

[0230] Divider 32 divides the received signal by the gain parameter to restore the digital signal of the second amplitude to the first amplitude; divider 32 outputs the signal restored to the first amplitude to the coulomb counter Coulomb Count and the current register CurrentSFR.

[0231] The Coulomb Count measures the amount of electricity based on the received signal.

[0232] (2) The signal processing procedure for digital overcurrent detection can be shown as follows:

[0233] The voltage drop generated by the DC current through the shunt is input to the first input terminal SRP and the second input terminal SRN.

[0234] The programmable gain amplifier (PGA) receives the input signal of the first amplitude.

[0235] The gain control module GCB adjusts the gain parameters of the programmable gain amplifier PGA based on the first amplitude.

[0236] The programmable gain amplifier (PGA) amplifies the input signal according to the gain parameter, increases the amplitude of the modulated input signal to a second amplitude, and transmits it to the ADC.

[0237] The ADC converts the second-amplitude signal into a digital signal; the ADC then transmits the second-amplitude digital signal to the CIC filter and the FAST CIC filter.

[0238] The FAST CIC filter reduces the rate of the second-amplitude digital signal to the second rate before transmitting it to the calibration module.

[0239] The calibration module calibrates the received signal and outputs it to the divider 32.

[0240] Divider 32 divides the received signal by the gain parameter to restore the digital signal of the second amplitude to the first amplitude; divider 32 outputs the signal restored to the first amplitude to digital comparator OC DIG CMP;

[0241] The OC DIG CMP compares the received signal with a set overcurrent threshold. When the amplitude of the received signal exceeds the set overcurrent threshold, it outputs an overcurrent signal in a first state; and when the amplitude of the received signal does not exceed the set overcurrent threshold, it outputs an overcurrent signal in a second state. The OC DIG CMP outputs the overcurrent signal in the first state / the overcurrent signal in the second state to a first counter.

[0242] The first counter, Counter, counts the overcurrent signal in the first state and transmits the counting result to the result module, Result.

[0243] The Result module generates an overcurrent status signal, such as a high level, when the count result of the first counter reaches a preset overcurrent count; and generates an overcurrent-free status signal, such as a low level, when the count result of the first counter does not reach the preset overcurrent count. Upon receiving the overcurrent signal of the second state, the Result module resets the count of the first counter. The Result module sends the status signals to the overcurrent logic module OC Logic and the status indication module Flag SFR.

[0244] The overcurrent logic module OC Logic receives the status signal output by the result module Result and converts it into an overcurrent output signal. For example, when the status signal indicates an overcurrent, the overcurrent logic module OC Logic can convert the received input signal into a valid output such as a high level, low level, or PWM signal, thereby controlling the circuit outside the signal detection circuit to respond to the overcurrent state; the overcurrent logic module OC Logic outputs the overcurrent output signal to the output enable module Drive.

[0245] When the control terminal is high, the output enable module Drive outputs an overcurrent output signal to the output terminal OC; when the control terminal is low, it stops outputting the overcurrent output signal to the output terminal OC.

[0246] The Flag SFR status indicator module records the status signal when the status signal output by the Result module is high, and is used to indicate overcurrent.

[0247] The structure of the first rate adjustment module 7 is illustrated below, taking the first rate adjustment module 7 as an example of a CIC filter.

[0248] Figure 10 This is a schematic diagram of a rate adjustment module provided in an embodiment of this application. Figure 10 As shown,

[0249] The first rate adjustment module 7 may include, for example, an extractor 71; the extractor 71 may be any module that can reduce the signal rate. For example, it may be a second counter.

[0250] The decimator 71, connected to the analog-to-digital converter 2, is used to decimate the detection signal output by the analog-to-digital converter 2 according to a set decimation frequency to obtain the detection signal at the corresponding output rate. For example, the decimator 71 can effectively reduce the signal rate and improve the processing speed of subsequent modules by setting a decimation factor M and outputting a signal every M signals.

[0251] Furthermore, the extractor 71 may include, for example, a second counter; the second counter is connected to the analog-to-digital converter 2 and is used to count the detection signal output by the analog-to-digital converter 2, and when the counting result reaches a counting threshold, output the current detection signal and reset the count. The second counter is used to control the output time of the signal output by the analog-to-digital converter 2. No signal is output when the counting result has not reached the counting threshold; when the counting result reaches the counting threshold, the current detection signal is output. After the second counter is reset, the timing of the next signal's output time can begin. This method is easy to implement.

[0252] The first rate adjustment module 7 may further include a first filter 72. The first filter 72 may be any filter that allows low-frequency signals to pass while impeding high-frequency signals, such as an infinite impulse response filter (IIR), a finite impulse response filter (FIR), etc. The first filter 72 is located at the input of the decimator 71 and is used to suppress high-frequency noise.

[0253] Furthermore, the first filter 72 includes at least one cascaded integrator 73. The integrator 73 can be, for example, any device capable of performing an accumulation operation. The integrator 73 can be used to accumulate the input signal. Cascading at least one integrator 73 together can enhance the low-pass filtering effect.

[0254] The integrator 73 includes an adder 74 and a first delay unit 75; the output of the adder 74 is connected to its input via the first delay unit 75. This method is easy to implement and eliminates the need for a multiplier, thereby improving the processing speed of the received signal.

[0255] The first rate adjustment module 7 may further include a second filter 76. The second filter 76 may be any filter that allows low-frequency signals to pass through while impeding high-frequency signals, such as an infinite impulse response filter (IIR), a finite impulse response filter (FIR), etc. The second filter 76 is located at the output of the decimator 71 and is used to suppress high-frequency noise.

[0256] The second filter 76 includes at least one cascaded comb filter 77. The comb filter 77 can be, for example, any device capable of differential operation. The output of the comb filter 77 is the difference between the current input signal and the delayed input signal, which can eliminate periodic peaks in the frequency response and achieve a flatter frequency response.

[0257] The comb filter 77 includes a subtractor 78 and a second delay unit 79; the first input terminal of the subtractor 78 is connected to the second input terminal of the subtractor 78 through the second delay unit 79. This method is easy to implement and eliminates the need for a multiplier, thereby improving the processing speed of the received signal.

[0258] In one example, the signal output by analog-to-digital converter 2 has a high speed. The signal output by analog-to-digital converter 2 can be slowed down to reduce the data volume and system complexity, while also performing anti-aliasing filtering. The first rate adjustment module 7 receives the signal output by analog-to-digital converter 2, slows down the signal, and then outputs it. The first rate adjustment module 7 includes: a first filter 72, a decimator 71, and a second filter 76. The decimator 71 is positioned between the first filter 72 and the second filter 76. The first filter 72 receives the signal output by analog-to-digital converter 2, the decimator 71 reduces the rate of the received signal, and the second filter 76 outputs the slowed-down signal.

[0259] The first filter 72 includes cascaded n-stage integrators 73. Each n-stage integrator 73 operates at the original frequency and accumulates the input signal. Each integrator 73 is a first-order IIR filter with a transfer function of...

[0260] By cascading n integrators, the roll-off characteristic of the first filter 72 can be enhanced. The roll-off characteristic describes the rate attenuation of a signal in the transition band from the passband to the stopband. The more integrators cascaded, the steeper the roll-off characteristic, and the faster the signal attenuates from the passband to the stopband in the transition band, thus more effectively suppressing frequency components outside the passband.

[0261] The second filter 76 includes a cascaded n-stage comb filter 77. The comb filter 77 performs differential operations on the reduced-rate signal to suppress high-frequency noise and aliasing components. Each stage of the comb filter 77 is a first-order FIR filter with a transfer function of H. C (z)=1-z -D Where D is the differential delay, which can usually be equal to 1.

[0262] The comb filter 77 has the same number of stages as the integrator. The comb filter 77 can suppress high-frequency noise and remove high-frequency noise components that may be introduced during the rate reduction process.

[0263] The second rate adjustment module 70 has the same structure as the first rate adjustment module 7 as the FAST CIC filter. The decimators of the second rate adjustment module 70 and the first rate adjustment module 7 are set with different decimation factors M, so that the first rate adjustment module 7 outputs a signal at a first output rate, and the second rate adjustment module 70 outputs a signal at a second output rate.

[0264] The following is a schematic description of the structure of the input chopper module 5 and the output chopper module 6.

[0265] Figure 11 This is a schematic diagram of a chopper module provided in an embodiment of this application. Figure 11 As shown, the example is an output chopper module 6 located between the first processing module 1 and the analog-to-digital converter 2.

[0266] The input chopper module 5 includes a first switch module 51; the input signals include a first input signal and a second input signal.

[0267] The first switch module 51 includes: a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4; the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 can all be any module based on high or low level conduction, such as any of the following: transistor, field-effect transistor (MOSFET), also known as MOS transistor, thyristor, etc.

[0268] The first switch S1 is connected between the first input signal and the first input terminal of the first processing module 1; the second switch S2 is connected between the first input signal and the second input terminal of the first processing module 1; the third switch S3 is connected between the second input signal and the first input terminal of the first processing module 1; and the fourth switch S4 is connected between the second input signal and the second input terminal of the first processing module 1.

[0269] The first switch S1 and the fourth switch S4 are in the same state. The first switch S1 and the second switch S2 are in opposite states. The first switch S1 and the third switch S3 are in opposite states.

[0270] The second switch module 61 includes: a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8;

[0271] The fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 can all be any module that is turned on based on a high or low level. For example, they can include any of the following: transistors, field-effect transistors (MOSFETs), also known as MOS transistors, thyristors, etc.

[0272] The fifth switch S5 is connected between the first output terminal of the first processing module 1 and the first input terminal of the analog-to-digital converter 2; the sixth switch S6 is connected between the first output terminal of the first processing module 1 and the second input terminal of the analog-to-digital converter 2; the seventh switch S7 is connected between the second output terminal of the first processing module 1 and the first input terminal of the analog-to-digital converter 2; and the eighth switch S8 is connected between the second output terminal of the first processing module 1 and the second input terminal of the analog-to-digital converter 2.

[0273] The fifth switch S5 and the eighth switch S8 have the same switching state, the fifth switch S5 and the sixth switch S6 have opposite switching states, and the fifth switch S5 and the seventh switch S7 have opposite switching states.

[0274] In one example, the input chopper module 5 receives an input signal of the first amplitude. When the control signal is high, the first switch S1 and the fourth switch S4 are turned on, the second switch S2 and the third switch S3 are turned off, and the path between the first input signal and the first input terminal of the first processing module 1 is open; the path between the second input signal and the second input terminal of the first processing module 1 is also open. When the control signal is low, the first switch S1 and the fourth switch S4 are turned off, the second switch S2 and the third switch S3 are turned on, and the path between the first input signal and the second input terminal of the first processing module 1 is open; the path between the second input signal and the first input terminal of the first processing module 1 is also open. When each switch in the first switch module 51 switches between on and off states in response to the control signal, the first input signal and the second input signal are periodically connected to different paths, thereby multiplying the input signal with the control signal to achieve modulation of the input signal. When the control signal is a square wave signal, the input chopper module 5 modulates the input signal with a square wave, shifting the DC signal to a higher frequency, while the low-frequency noise and offset voltage of the input signal remain at a lower frequency.

[0275] The first processing module 1 increases the amplitude of the modulated signal to a second amplitude, while simultaneously increasing the amplitude of the noise and the offset voltage of the first processing module 1.

[0276] Output chopper module 6 receives a signal with a second amplitude. When the control signal is high, switches S5 and S8 are turned on, and switches S6 and S7 are turned off, connecting the first output of the first processing module 1 to the first input of the analog-to-digital converter 2; the second output of the first processing module 1 is also connected to the second input of the analog-to-digital converter 2. When the control signal is low, switches S5 and S8 are turned off, and switches S6 and S7 are turned on, connecting the first output of the first processing module 1 to the second input of the analog-to-digital converter 2; the second output of the first processing module 1 is also connected to the first input of the analog-to-digital converter 2. When the switches in the second switch module 61 switch between on and off states in response to the control signal, the first and second outputs of the first processing module 1 are periodically connected to different paths, thereby multiplying the output signal of the first processing module 1 with the control signal and demodulating the signal modulated at the control signal frequency back to DC or a low frequency. When the modulated signal passes through the output chopper module 6, the switching action of the switch restores the high-frequency modulated signal back to the original low-frequency signal, while modulating the offset voltage and low-frequency noise amplified by the first processing module 1 to a high frequency.

[0277] Figure 11Taking Vin+ as the first input signal and Vin- as the second input signal; the first processing module 1 includes an amplification module 21 and a reference module 22; the amplification module 21 includes a programmable gain amplifier (PGA), and the reference module 22 includes a voltage source (Vos) as an example for illustration. The analog-to-digital converter 2... Figure 11 (Not shown in the diagram). Input chopper module 5 receives the first input signal Vin+ and the second input signal Vin-; one end of voltage source Vos receives the modulation signal output by input chopper module 5, and the other end of voltage source Vos is connected to the input terminal of programmable gain amplifier PGA. The output terminal of programmable gain amplifier PGA is connected to the input terminal of output chopper module 6; the first output terminal Vout+ and the second output terminal Vout- of output chopper module 6 transmit the output signal to analog-to-digital converter 2.

[0278] The input chopper module 5 modulates the received first amplitude input signal into a square wave, modulating the input signal to the frequency of the square wave signal, thereby increasing the frequency of the input signal; the input chopper module 5 transmits the modulated signal to the programmable gain amplifier PGA through the voltage source Vos.

[0279] The programmable gain amplifier (PGA) amplifies the modulated signal according to the gain parameter, increases the amplitude of the signal to a second amplitude, and transmits the digital signal of the second amplitude to the output chopper module 6.

[0280] The output chopper module 6 is turned on or off under the action of the square wave signal, and the polarity of the input signal is rapidly switched alternately at the frequency of the square wave signal to demodulate the digital signal of the second amplitude and restore the digital signal of the second amplitude back to the original frequency; at the same time, the offset voltage and low-frequency noise amplified by the programmable gain amplifier PGA are modulated to the high frequency; the output chopper module 6 transmits the demodulated digital signal of the second amplitude to the analog-to-digital converter 2.

[0281] A low-pass filter is added to the subsequent circuit to effectively block high-frequency components, thereby filtering out the offset voltage and noise modulated to the high frequency and retaining only the input signal with increased amplitude. Since chopper stabilization technology can suppress noise, the input chopper module 5 and the output chopper module 6 can give the first processing module 1 a higher dynamic range, further improving the overcurrent detection accuracy.

[0282] The structure of gain control module 4 is described below.

[0283] Figure 12 This is a schematic diagram of a gain control module provided in an embodiment of this application. Figure 12 As shown, the gain control module 4 includes: a detector 41 and a comparator 42;

[0284] The input terminal of detector 41 receives the input signal and is used to detect the voltage of the input signal;

[0285] The first input terminal of comparator 42 is connected to the output terminal of detector 41, the second input terminal is connected to the reference voltage, and the output terminal is connected to amplifier module 21. Comparator 42 is used to output the gain parameter of amplifier module 21 based on the voltage comparison result between the input signal and the reference voltage.

[0286] In one example, the processor can establish a communication connection with the gain control module 4. The processor writes specific values ​​to the registers of the gain control module 4 via a communication interface such as a Serial Peripheral Interface (SPI). These values ​​store information related to gain control, such as gain parameters and thresholds. After receiving the register write operation, the comparator 42 of the gain control module 4 can read the value in the register and continuously compare the input signal with the threshold in the register. Once the set threshold is reached, the gain parameter is adjusted. Multiple reference voltage thresholds can correspond to different gain levels to determine the amplification factor of the amplifier module 21 that needs to be adjusted. Furthermore, the gain control module 4 can be turned on or off. For example, the gain control function can be enabled or disabled by writing to the registers of the gain control module 4. The gain control module 4 is enabled by default. When the gain control module 4 is disabled, the gain parameter of the amplifier module 21 can be adjusted by configuring the registers of the amplifier module 21 through the processor.

[0287] Furthermore, when the analog-to-digital converter 2 is started, if the gain control function of the gain module 4 is already enabled, the gain control module 4 first performs gain control on the amplification module 21, and after determining the gain parameters, the analog-to-digital converter performs analog-to-digital conversion on the input signal.

[0288] Figure 12 The following is a schematic illustration using an example where detector 41 includes a detector, comparator 42 includes a comparator pump (CMP), and amplification module 21 includes a power amplifier (PGA). The input terminal of the detector receives the input signal Vin2 and is used to detect the voltage of the input signal.

[0289] The first input terminal of the CMP is connected to the output terminal of the Detector, the second input terminal is connected to the reference voltage Vref, and the output terminal is connected to the PGA. The CMP is used to output the gain parameter of the PGA based on the voltage comparison result between the input signal Vin2 and the reference voltage Vref.

[0290] Figure 13 This is a schematic flowchart illustrating the output gain parameters of a gain control module provided in an embodiment of this application. Figure 13As shown, taking the gain control module 4, which includes 8 gain levels, as an example, this paper illustrates how the gain control module 4 outputs gain parameters based on the voltage of the input signal.

[0291] For example, the gain levels of the gain control module 4 may include: 4, 8, 16, 32, 64, 128, 256, 512; the gain control module 4 may set an upper limit threshold and a lower limit threshold; the gain control module 4 amplifies the input voltage according to the set gain level and compares it with the upper limit threshold and the lower limit threshold respectively. If the amplitude of the amplified input voltage is between the upper limit threshold and the lower limit threshold, the gain level is output as a gain parameter to the amplification module 21, and the amplification module 21 amplifies the input signal according to the gain parameter.

[0292] In one example, the default gain level of the gain control module 4 (S1) can be set to 64. The differential voltage of the input signal is amplified 64 times by the detector 41 and transmitted to the comparator 42; the comparator 42 compares the amplified input signal 64 times with the upper threshold and the lower threshold respectively.

[0293] If the signal output by comparator 42 represents an input signal amplified by 64 times that is between the upper and lower thresholds, then the gain control module 4 transmits 64 as a gain parameter to the amplification module 21.

[0294] If the signal output by comparator 42 represents an input signal amplified by 64 times that is lower than the lower threshold, then execute S21;

[0295] If the signal output by comparator 42 represents an input signal amplified by 64 times that is higher than the upper threshold, then S22 is executed.

[0296] S21, the processor adjusts the gain level of the gain control module 4 to 256; the detector 41 amplifies the input signal by 256 times and transmits it to the comparator 42; the comparator 42 compares the amplified input signal by 256 times with the upper threshold and the lower threshold respectively;

[0297] If the signal output by comparator 42 indicates that the input signal amplified by 256 times is between the upper and lower thresholds, then the gain control module 4 transmits 256 as a gain parameter to the amplification module 21.

[0298] If the signal output by comparator 42 represents an input signal amplified by 256 times that is lower than the lower threshold, then S31 is executed; if the signal output by comparator 42 represents an input signal amplified by 256 times that is higher than the upper threshold, then S32 is executed.

[0299] S22, the processor adjusts the gain level of the gain control module 4 to 16; the detector 41 amplifies the input signal by 16 times and transmits it to the comparator 42; the comparator 42 compares the amplified input signal by 16 times with the upper threshold and the lower threshold respectively;

[0300] If the signal output by comparator 42 represents an input signal amplified by 16 times that is between the upper and lower thresholds, then the gain control module 4 transmits 16 as a gain parameter to the amplification module 21.

[0301] If the signal output by comparator 42 represents an input signal amplified 16 times that is lower than the lower threshold, then execute S41;

[0302] If the signal output by comparator 42 represents an input signal amplified by 16 times that is higher than the upper threshold, then S42 is executed.

[0303] S31, the processor adjusts the gain level of the gain control module 4 to 512; the gain control module 4 transmits 512 as a gain parameter to the amplification module 21.

[0304] S32, The processor adjusts the gain level of the gain control module 4 to 128; the gain control module 4 transmits 128 as a gain parameter to the amplification module 21.

[0305] S41, the processor adjusts the gain level of the gain control module 4 to 32; the gain control module 4 transmits 32 as a gain parameter to the amplification module 21.

[0306] S42, the processor adjusts the gain level of the gain control module 4 to 8; the detector 41 amplifies the input signal by 8 times and transmits it to the comparator 42; the comparator 42 compares the amplified input signal by 8 times with the upper limit threshold.

[0307] If the signal output by comparator 42 represents an input signal amplified by 16 times that is lower than the upper limit threshold, then the gain control module 4 transmits 16 as a gain parameter to the amplification module 21.

[0308] If the signal output by comparator 42 represents an input signal amplified by 16 times that is higher than the upper limit threshold, then S51 is executed.

[0309] S51, the processor adjusts the gain level of the gain control module 4 to 4; the gain control module 4 transmits 4 as a gain parameter to the amplification module 21.

[0310] In summary, the signal detection circuit provided in this application embodiment adjusts the gain parameter of the amplification module 21 through the gain control module 4, enabling the amplification module 21 to achieve more precise gain control, improving the stability of the gain, and enhancing the adaptability of the amplification module 21. This allows the amplification module 21 to adjust the gain parameter in a timely manner according to the amplitude of the input signal, ensuring that the output signal is within a suitable dynamic range.

[0311] The following illustration uses the calibration module 8 calibrating the signal output by the first rate adjustment module 7 as an example.

[0312] When the input signal reaches the calibration module 8 after passing through the first rate adjustment module 7, it contains various types of errors, including gain error from the amplification module 21, offset error from the analog-to-digital converter 2, and passband attenuation from the first rate adjustment module 7 itself. These errors affect the accuracy and performance of the output signal to varying degrees. To improve the accuracy of the output signal, the calibration module 8 needs to calibrate the received signal before outputting it. The calibration module 8 calibrates the received signal in three main ways:

[0313] (I) Offset Calibration. Even without an input signal, the output voltage of the analog-to-digital converter 2 may not be zero; this is called the offset voltage of the analog-to-digital converter 2. The magnitude of this offset voltage can be called the offset parameter. Specifically, the calibration module 8 receives the offset parameter of the analog-to-digital converter 2; performs offset calibration on the received signal based on the offset parameter; and outputs the offset-calibrated signal. This offset parameter can, for example, be obtained by the processor acquiring the signal output by the analog-to-digital converter 2 when there is no input signal. In one example, when there is no input signal, the processor acquires N consecutive signals output by the analog-to-digital converter 2; where N is a positive integer; and obtains the offset parameter of the analog-to-digital converter 2 based on the N consecutive output signals. This offset parameter can, for example, be stored in a register, and the calibration module 8 receives the offset parameter by reading the data from the register. Alternatively, the processor directly sends the offset parameter to the calibration module 8, and the calibration module 8 receives the offset parameter. The calibration module 8 performs offset calibration on the received signal, which can correct the error introduced by the analog-to-digital converter 2 when converting the input signal, thereby improving the accuracy of the detection results.

[0314] Furthermore, the received signal is offset calibrated based on the offset parameter. Specifically, this can be achieved by subtracting the received signal from the offset parameter. This method is easy to implement.

[0315] (II) Gain Calibration. The amplification module 21 may generate a gain error, meaning the amplitude of the signal actually output by the amplification module 21 deviates from the amplitude calculated based on the input signal using the set gain parameters. Specifically, the calibration module 8 receives the gain error parameters from the amplification module 21; performs gain calibration on the received signal according to the gain error parameters; and outputs the gain-calibrated signal. These gain error parameters can, for example, be obtained by the processor acquiring the signal output by the analog-to-digital converter 2 or the first rate adjustment module 7 when a known input signal is received. For example, the processor can divide the signal output by the analog-to-digital converter 2 or the first rate adjustment module 7 by the known signal to obtain the actual gain parameter; and divide the set gain parameter by the actual gain parameter to obtain the gain error parameters of the amplification module 21. These gain error parameters can, for example, be stored in a register, and the calibration module 8 receives the gain error parameters of the amplification module 21 by reading the data from the register. Alternatively, the processor can directly send the gain error parameters to the calibration module 8, and the calibration module 8 receives the gain error parameters. By performing gain error calibration on the received signal, the calibration module 8 can correct the errors introduced by the amplification module 21 when amplifying the input signal, thereby improving the accuracy of the detection results.

[0316] Furthermore, the received signal is gain-calibrated based on the gain error parameter. Specifically, this can be achieved by multiplying the received signal by the gain error parameter. This method is easy to implement.

[0317] (III) Passband Compensation. When processing the input signal, the first rate adjustment module 7 may exhibit periodic attenuation characteristics, resulting in passband attenuation. Specifically, the calibration module 8 receives the passband compensation parameters from the first rate adjustment module 7 and performs passband compensation on the signal passing through the first rate adjustment module 7 based on these parameters. These passband compensation parameters can be obtained, for example, from the passband attenuation parameters of the first rate adjustment module 7 obtained by the processor, and the passband compensation parameters can be determined based on these parameters. These passband compensation parameters can be stored, for example, in a register, and the calibration module 8 receives the passband compensation parameters from the first rate adjustment module 7 by reading the data from the register. Alternatively, the processor can directly send the passband compensation parameters to the calibration module 8, and the calibration module 8 receives the passband compensation parameters. By performing passband compensation on the received signal, the calibration module 8 can correct the errors introduced by the first rate adjustment module 7 when processing the input signal, thereby improving the accuracy of the detection results.

[0318] This application also provides a processing method based on the above-described signal detection circuit. The execution entity of this method may be, for example, a processor.

[0319] Figure 14 This is a schematic diagram of the structure of a processing method provided in an embodiment of this application, as shown below. Figure 14 As shown, the method may include, for example, the following steps:

[0320] S1401, The processor acquires the first detection signal and the second detection signal output by the current detection module 10 of the signal detection circuit.

[0321] refer to Figure 3 The signal detection circuit shown includes a current detection module 10, which is used to detect the current of the input signal and output a first detection signal and a second detection signal. For example, the input signal can be an analog voltage signal. The current detection module 10 can convert the analog voltage signal into a digital detection signal by detecting the current of the input signal. The digital detection signal can be used to obtain the current value corresponding to the input signal.

[0322] The processor can acquire the first detection signal and the second detection signal to achieve different processing requirements.

[0323] Different signal processing requirements may necessitate processing signals with varying characteristics. For instance, processing needs requiring precise signal processing results may require higher-resolution detection signal samples to capture more details of the input signal and improve the accuracy of the results, without demanding a fast response time. In this case, the current detection module 10 can be set to a lower decimation frequency, resulting in a longer signal generation time and a lower output rate. Conversely, processing needs requiring rapid signal processing results may require fewer detection signal samples. In this case, the current detection module 10 can be set to a higher decimation frequency, resulting in a shorter signal generation time and a higher output rate. Furthermore, the current detection module 10 can also reduce the resolution of the detection signal to further improve the signal processing speed.

[0324] As mentioned above, the signal detection circuit may include, for example, a first rate adjustment module 7 and a second rate adjustment module 70. The current detection module 10 can output a first detection signal according to a first output rate through the first rate adjustment module 7; the current detection module 10 can output a second detection signal according to a second output rate through the second rate adjustment module 70.

[0325] For example, the first rate adjustment module 7 is a typical current sampling CIC filter, while the second rate adjustment module 70 is a fast CIC filter. The oversampling rate of the second rate adjustment module 70 can be set much lower than that of the first rate adjustment module 7. For instance, if the oversampling rate of the first rate adjustment module 7 is 512 times, and each sampling takes approximately 10 microseconds (µs), then the time required for the first rate adjustment module 7 to output the detection signal is 512 * 10 µs = 5.12 milliseconds (ms). Therefore, the first rate adjustment module 7 can output the detection signal at the first rate every 5.12 ms. Since the second rate adjustment module 70 does not require a high-precision specific current value, but only a signal indicating whether there is an overcurrent, in this embodiment, the oversampling rate of the second rate adjustment module 70 can be set to 8 times. Therefore, the time required for the second rate adjustment module 70 to output the detection signal is 8 * 10 µs = 80 µs. The speed at which the second rate adjustment module 70 outputs the detection signal is 64 times that of the first rate adjustment module 7, i.e., 5120 µs / 80 µs = 64 times. Therefore, the digital detection module 11 performs overcurrent detection on the received detection signal at the second rate, enabling a fast overcurrent detection function.

[0326] The processor can improve processing accuracy by acquiring the first detection signal, and it can improve processing speed by acquiring the second detection signal. Different processing requirements can be achieved by acquiring the first and second detection signals.

[0327] S1402, The processor obtains the power metering result based on the first detection signal, and obtains the overcurrent detection result based on the second detection signal.

[0328] The processor can perform power measurement based on the first detection signal and obtain the power measurement result, specifically including:

[0329] For example, the input signal received by the signal detection circuit can be the voltage drop generated by a DC current passing through a shunt. The processor, according to Ohm's law, divides the first detection signal by the resistance of the shunt, converting the detection signal into a current signal to obtain the current detection result.

[0330] The processor can also calculate the change in power level in real time based on the first detection signal, helping users monitor the energy consumption of devices or systems. In battery-powered systems, the change in power level can also be used to estimate the battery's state, such as the remaining power.

[0331] In one example, the processor can perform time-integration based on the current detection result to obtain the change in electrical quantity. For instance, current is the change in electrical quantity over time; that is, current is the derivative of electrical quantity with respect to time. To obtain the change in electrical quantity, the current needs to be integrated over time. Through integration, the original quantity can be recovered from the derivative. If the current is in amperes and the time is in seconds, the coulomb number of the change in electrical quantity can be obtained.

[0332] The processor can also accumulate the changes in power consumption to obtain the power consumption measurement result.

[0333] For example, after receiving each change in battery level, the processor adds the change in battery level to the current total change in battery level to obtain the updated total change in battery level, thus obtaining the battery level measurement result.

[0334] The total charge change can be transmitted to the battery management system, which can receive the charge change data in real time, thereby monitoring the battery status and helping to dynamically adjust the charging and discharging strategy.

[0335] Alternatively, the total change in battery charge can be stored in a storage module, such as a register. Storing it in a storage module reduces the complexity of data transmission and communication overhead, and the battery management system can read the total change in battery charge when needed.

[0336] The processor can obtain the overcurrent detection result based on the second detection signal.

[0337] For example, an overcurrent threshold can be preset in the processor's internal storage module. The processor compares the second detection signal with the preset overcurrent threshold. If the value of the second detection signal reaches the overcurrent threshold, it is confirmed as an overcurrent; if the value of the second detection signal is less than the overcurrent threshold, it is confirmed as no overcurrent.

[0338] In summary, the processing method provided in this application embodiment performs power measurement by acquiring the first detection signal output by the current detection module 10 of the signal detection circuit; and performs overcurrent detection by acquiring the second detection signal output by the current detection module 10 of the signal detection circuit; thus, it can meet different signal detection requirements and is easy to integrate.

[0339] Optionally, the processor can configure the output rate of the current detection module 10 of the signal detection circuit so that the current detection module 10 outputs detection signals at different output rates. For example, the current detection module 10 can output a detection signal at a set output rate by reading the value of a register; the processor can configure the output rate of the current detection module 10 of the signal detection circuit by writing different output rates to the register. For example, the processor can configure the output rates of the first rate adjustment module 7 and the second rate adjustment module 70 respectively so that the first rate adjustment module 7 and the second rate adjustment module 70 output detection signals at their respective corresponding output rates.

[0340] Figure 15 This is a flowchart illustrating another processing method provided in an embodiment of this application. Figure 15 As shown,

[0341] S1501, The processor acquires the offset parameters of the analog-to-digital converter 2 of the signal detection circuit and sends them to the calibration module 8 of the signal detection circuit, so that the calibration module 8 performs offset calibration on the received signal according to the offset parameters.

[0342] The processor acquires the offset parameters of analog-to-digital converter 2, providing a calibration basis for offset calibration by calibration module 8. This improves the accuracy and stability of the detection signal.

[0343] For example, the processor can send a calibration command to the analog-to-digital converter 2, causing the converter to enter calibration mode. The processor can obtain the offset parameter of the converter by acquiring the deviation between the actual output signal and the theoretical signal. This offset parameter can be sent to the calibration module 8, for example, stored in the register of the calibration module 8; subsequently, when the converter 2 is operating normally, the calibration module 8 can perform offset calibration on the received signal based on the received offset parameter.

[0344] When there is no input signal, the processor can acquire N consecutive signals output by analog-to-digital converter 2, where N is a positive integer; based on the N consecutive output signals, the offset parameters of analog-to-digital converter 2 can be obtained. By acquiring N consecutive signals, the accuracy of the offset parameters can be improved.

[0345] The processor can perform calculations on N continuously output signals, such as calculating the mean or root mean square error of the N signals, to obtain the offset parameters of analog-to-digital converter 2.

[0346] Furthermore, the processor averages the N consecutively output signals to obtain the offset parameters of analog-to-digital converter 2. This method is simple to implement.

[0347] S1502, The processor obtains the gain error parameters of the amplification module 21 of the signal detection circuit and sends them to the calibration module 8 of the signal detection circuit so that the calibration module 8 can perform gain calibration on the received signal according to the gain error parameters.

[0348] The processor obtains the gain error parameters of the amplification module 21, providing a calibration basis for the calibration module 8 to perform gain calibration. This improves the accuracy and stability of the detected signal.

[0349] For example, the processor obtains the gain error parameter of the amplification module 21 based on the set gain parameter and the actual gain parameter; wherein, the actual gain parameter is obtained based on the actual output signal of the amplification module 21 under the set gain parameter. For example, a known signal can be input to the signal detection circuit, and the amplification module 21 detects the signal after amplification under the set gain parameter to obtain the actual output signal. The actual output signal divided by the input known signal yields the actual gain parameter. The processor obtains the gain error parameter of the amplification module 21 based on the deviation between the set gain parameter and the actual gain parameter. This gain error parameter can be sent to the calibration module 8, for example, stored in the register of the calibration module 8, and then the calibration module 8 can perform gain calibration on the received signal based on the received gain error parameter.

[0350] Specifically, the processor can divide the set gain parameter by the actual gain parameter to obtain the gain error parameter of the amplification module 21. Then, the calibration module 8 can multiply the received signal by the gain error parameter to perform gain calibration on the signal.

[0351] S1503, The processor acquires the passband compensation parameters of the first rate adjustment module 7 and the second rate adjustment module 70 of the signal detection circuit, and sends them to the calibration module 8 of the signal detection circuit, so that the calibration module 8 performs passband compensation on the received signal according to the passband compensation parameters.

[0352] The processor acquires the passband compensation parameters from the first rate adjustment module 7 and the second rate adjustment module 70, providing a calibration basis for the calibration module 8 to perform passband compensation. This improves the accuracy and stability of the detection signal.

[0353] In one example, the processor can obtain the passband attenuation parameters of the first rate adjustment module 7 and the second rate adjustment module 70; and determine the passband compensation parameters based on the passband attenuation parameters.

[0354] For example, the processor can obtain the passband attenuation parameters by simulating or theoretically calculating the frequency response of the first rate adjustment module 7 and the second rate adjustment module 70 within the passband. By obtaining the passband attenuation parameters, the frequency range and attenuation amount requiring compensation can be identified. Based on the passband compensation parameters, the parameters of the compensation filter can be designed in the calibration module 8. For example, when the compensation filter is an FIR filter, the order, passband width, and stopband attenuation of the compensation filter can be designed to compensate for the passband attenuation of the rate adjustment module, thereby improving the accuracy of the detection data. These compensation parameters can be sent to the calibration module 8, for example, stored in the register of the calibration module 8. Then, the calibration module 8 can perform passband compensation on the received signal based on the received compensation parameters.

[0355] In summary, the processing method provided in this application embodiment can improve the accuracy of the output signal by obtaining the calibration parameters of the signal detection circuit, enabling the calibration module 8 of the signal detection circuit to calibrate the received signal.

[0356] This application also provides a battery management chip, including a signal detection circuit.

[0357] This application also provides a battery system, including a battery management chip and a battery pack.

[0358] This application also provides a transportation device, including a battery system.

[0359] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A signal detection circuit, characterized in that, include: The current detection module (10) is used to detect the current of the input signal and output a first detection signal and a second detection signal; A signal processing module (20) is connected to the current detection module (10), and the signal processing module (20) is used to perform power measurement based on the first detection signal; A digital detection module (11) is connected to the current detection module (10), and the digital detection module (11) is used to perform overcurrent detection based on the second detection signal.

2. The signal detection circuit according to claim 1, characterized in that, The current detection module (10) includes: An analog-to-digital converter (2) receives an input signal and converts the input signal into a digital signal to obtain a detection signal; The first rate adjustment module (7) is connected to the analog-to-digital converter (2) and is used to output the detection signal at a first output rate to obtain the first detection signal. The second rate adjustment module (70) is connected to the analog-to-digital converter (2) and is used to output the detection signal at a second output rate to obtain the second detection signal; the first output rate and the second output rate are different.

3. The signal detection circuit according to claim 2, characterized in that, The current detection module (10) also includes: The first processing module (1) is connected to the analog-to-digital converter (2) and is used to increase the amplitude of the first amplitude input signal to the second amplitude and transmit the second amplitude input signal to the analog-to-digital converter (2). The second processing module (3) is connected to the first rate adjustment module (7) and the second rate adjustment module (70), and is used to restore the amplitude of the output signal of the first rate adjustment module (7) to the first amplitude and then output it to the signal processing module (20), and restore the amplitude of the output signal of the second rate adjustment module (70) to the first amplitude and then output it to the digital detection module (11).

4. The signal detection circuit according to claim 3, characterized in that, The second processing module (3) includes a first processing submodule (30) and a second processing submodule (40); The first processing submodule (30) is connected to the first rate adjustment module (7) and is used to restore the amplitude of the output signal of the first rate adjustment module (7) to the first amplitude; The second processing submodule (40) is connected to the second rate adjustment module (70) and is used to restore the amplitude of the output signal of the second rate adjustment module (70) to the first amplitude.

5. The signal detection circuit according to claim 4, characterized in that, The current detection module (10) further includes: a calibration module (8); The calibration module (8) is connected to the first rate adjustment module (7), the second rate adjustment module (70), and the second processing module (3); The calibration module (8) is used to calibrate the signals output by the first rate adjustment module (7) and the second rate adjustment module (70) and then output them to the second processing module (3).

6. The signal detection circuit according to claim 5, characterized in that, The calibration module (8) includes: a first calibration submodule (80) and a second calibration submodule (83); One end of the first calibration submodule (80) is connected to the first rate adjustment module (7); the other end of the first calibration submodule (80) is connected to the first processing submodule (30) for calibrating the received signal and then outputting it. One end of the second calibration submodule (83) is connected to the second rate adjustment module (70); the other end of the second calibration submodule (83) is connected to the second processing submodule (40) for calibrating the received signal and then outputting it.

7. The signal detection circuit according to claim 6, characterized in that, The first rate adjustment module (70) includes: an extractor (71), a first filter (72), and a second filter (76); One end of the first filter (72) is connected to the analog-to-digital converter (2), and the other end of the first filter (72) is connected to one end of the decimator (71); the other end of the decimator (71) is connected to the second filter (76). The extractor (71) is used to extract the detection signal output by the analog-to-digital converter (2) according to a set extraction frequency to obtain the first detection signal.

8. The signal detection circuit according to claim 3, characterized in that, The first processing module (1) includes: an amplification module (21) and a gain control module (4); The amplification module (21) is connected to the gain control module (4) and the analog-to-digital converter (2); The amplification module (21) is used to amplify the input signal according to the gain parameter so that the amplitude of the amplified input signal is the second amplitude, and transmit the signal with the second amplitude to the analog-to-digital converter (2); The gain control module (4) is used to adjust the gain parameter of the amplification module (21) according to the first amplitude.

9. The signal detection circuit according to claim 8, characterized in that, The second processing module (3) includes: a divider (32); The divider (32) is connected to the first rate adjustment module (7) and the second rate adjustment module (70), and is used to divide the signals output by the first rate adjustment module (7) and the second rate adjustment module (70) by the gain parameter, so as to restore the signals output by the first rate adjustment module (7) and the second rate adjustment module (70) to the first amplitude.

10. The signal detection circuit according to claim 3, characterized in that, The first processing module (1) includes: an addition module (25); The addition module (25) is connected to the analog-to-digital converter (2) and is used to sum the input signal with a preset amplitude to increase the amplitude of the input signal to the second amplitude, and transmit the signal of the second amplitude to the analog-to-digital converter (2).

11. The signal detection circuit according to claim 10, characterized in that, The second processing module (3) includes: a subtraction module (35); The subtraction module (35) is connected to the first rate adjustment module (7) and the second rate adjustment module (70), and is used to calculate the difference between the signals output by the first rate adjustment module (7) and the second rate adjustment module (70) and the preset amplitude, so as to restore the amplitude of the signals output by the first rate adjustment module (7) and the second rate adjustment module (70) to the first amplitude.

12. The signal detection circuit according to claim 1, characterized in that, The digital detection module (11) includes: a digital comparator (13) and a counting module (14); The digital comparator (13) is connected to the current detection module (10) and is used to output an overcurrent signal in a first state if an overcurrent is detected, and to output an overcurrent signal in a second state if no overcurrent is detected. The counting module (14) is connected to the digital comparator (13) and is used to count the overcurrent signal of the first state continuously output by the digital comparator (13), and generate a state signal representing the overcurrent when the counting result reaches a preset number of overcurrents.

13. The signal detection circuit according to claim 12, characterized in that, The counting module (14) includes: a first counter (15) and a result module (16); The first counter (15) is connected to the digital comparator (13) and is used to count the overcurrent signal of the first state continuously output by the digital comparator (13); The result module (16) is connected to the first counter (15) and is used to generate a status signal representing the overcurrent when the counting result of the first counter (15) reaches a preset number of overcurrent cycles.

14. The signal detection circuit according to claim 12, characterized in that, The digital detection module (11) further includes: an overcurrent logic module (17); The overcurrent logic module (17) is connected to the counting module (14) and is used to receive the status signal output by the counting module (14) and convert it into an overcurrent output signal.

15. The signal detection circuit according to claim 14, characterized in that, The digital detection module (11) further includes: an output enable module (18); The output enable module (18) is connected to the overcurrent logic module (17) and is used to control whether to output the overcurrent output signal.

16. A signal detection method, based on the signal detection circuit as described in any one of claims 1 to 15, characterized in that, include: Obtain the first detection signal and the second detection signal output by the current detection module (10) of the signal detection circuit; The power metering result is obtained based on the first detection signal, and the overcurrent detection result is obtained based on the second detection signal.

17. A battery management chip, characterized in that, include: The signal detection circuit as described in any one of claims 1 to 15.

18. A battery system, characterized in that, include: The battery management chip as described in claim 17, and the battery pack.

19. A transportation device, characterized in that, include: The battery system as described in claim 18.

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