Current detection circuit, method, battery management chip, battery system and device

Abstract

Embodiments of the present application provide a current detection circuit, a method, a battery management chip, a battery system and equipment. The current detection circuit comprises: a first processing module configured to receive an input signal of a first amplitude, and configured to increase the amplitude of the input signal to a second amplitude; an analog-to-digital converter connected with the first processing module, configured to convert an output signal of the first processing module into a digital signal; and a second processing module connected with the analog-to-digital converter, configured to restore the amplitude of the output signal of the analog-to-digital converter to the first amplitude, and obtain a detection signal; the detection signal is used to obtain a current detection result. The method is used to improve the current detection precision.

Description

Technical Field

[0001] This application relates to current detection technology, and more particularly to a current detection circuit, method, battery management chip, battery system, and device. Background Technology

[0002] With the rapid development of new energy vehicles, the detection results of current directly affect the estimation of the remaining capacity of lithium batteries, and thus the user's estimation of the vehicle's driving range. If the current detection results are inaccurate, users may misjudge the remaining capacity and encounter insufficient driving range.

[0003] Currently, a shunt is used to convert DC current into a voltage signal, and then an analog-to-digital converter (ADC) is used to convert the voltage signal into a digital voltage. The current detection result can be obtained from this digital voltage.

[0004] This method suffers from low current detection accuracy. Summary of the Invention

[0005] This application provides a current detection circuit, method, battery management chip, battery system, and device to improve current detection accuracy.

[0006] In a first aspect, embodiments of this application provide a current detection circuit, including: a first processing module (1), which receives an input signal of a first amplitude and is used to increase the amplitude of the input signal to a second amplitude;

[0007] An analog-to-digital converter (2) is connected to the first processing module (1) and is used to convert the output signal of the first processing module (1) into a digital signal.

[0008] The second processing module (3) is connected to the analog-to-digital converter (2) and is used to restore the amplitude of the output signal of the analog-to-digital converter (2) to the first amplitude to obtain a detection signal; the detection signal is used to obtain the current detection result.

[0009] Optionally, the first processing module (1) includes: an amplification module (21) and a gain control module (4);

[0010] The amplification module (21) is connected to the gain control module (4) and the analog-to-digital converter (2);

[0011] The amplification module (21) is used to amplify the input signal according to the gain parameter so that the amplitude of the amplified input signal is the second amplitude, and transmit the signal with the second amplitude to the analog-to-digital converter (2);

[0012] The gain control module (4) is used to adjust the gain parameter of the amplification module (21) according to the first amplitude.

[0013] Optionally, the second processing module (3) includes: a divider (32);

[0014] The divider (32) is connected to the analog-to-digital converter (2) and is used to divide the signal output by the analog-to-digital converter (2) by the gain parameter in order to restore the amplitude of the output signal of the analog-to-digital converter (2) to the first amplitude.

[0015] Optionally, the first processing module (1) includes: an addition module (25);

[0016] The addition module (25) is connected to the analog-to-digital converter (2) and is used to sum the input signal with a preset amplitude to increase the amplitude of the input signal to the second amplitude, and transmit the signal of the second amplitude to the analog-to-digital converter (2).

[0017] Optionally, the second processing module (3) includes: a subtraction module (35);

[0018] The subtraction module (35) is connected to the analog-to-digital converter (2) and is used to calculate the difference between the signal output by the analog-to-digital converter (2) and the preset amplitude, so as to restore the amplitude of the signal output by the analog-to-digital converter (2) to the first amplitude.

[0019] Optionally, the current detection circuit further includes: a metering module (9);

[0020] The metering module (9) is connected to the second processing module (3) and is used to measure the power of the detection signal.

[0021] Optionally, the gain control module (4) includes: a detector (41) and a comparator (42);

[0022] The input terminal of the detector (41) receives the input signal and is used to detect the voltage of the input signal;

[0023] The first input terminal of the comparator (42) is connected to the output terminal of the detector (41), the second input terminal is connected to the reference voltage, and the output terminal is connected to the amplification module (21). The comparator (42) is used to output the gain parameter of the amplification module (21) based on the voltage comparison result between the input signal and the reference voltage.

[0024] Optionally, the first processing module (1) further includes: a reference module (22);

[0025] The reference module (22) is connected to the input terminal of the amplification module (21) and is used to provide a reference level for the input signal.

[0026] Optionally, the current detection circuit further includes: an input chopper module (5) and an output chopper module (6);

[0027] The input chopper module (5) is located at the input end of the first processing module (1);

[0028] The output chopper module (6) is disposed between the first processing module (1) and the second processing module (3);

[0029] The input chopper module (5) is used to increase the frequency of the input signal and transmit the increased frequency input signal to the first processing module (1);

[0030] The output chopper module (6) is used to reduce the frequency of the received signal and output the signal after the frequency reduction.

[0031] Optionally, the input chopper module (5) includes: a first switch (S1), a second switch (S2), a third switch (S3), and a fourth switch (S4); the input signal includes: a first input signal and a second input signal;

[0032] The first switch (S1) is connected between the first input signal and the first input terminal of the first processing module (1); the second switch (S2) is connected between the first input signal and the second input terminal of the first processing module (1); the third switch (S3) is connected between the second input signal and the first input terminal of the first processing module (1); and the fourth switch (S4) is connected between the second input signal and the second input terminal of the first processing module (1).

[0033] The first switch (S1) and the fourth switch (S4) have the same switching state, the first switch (S1) and the second switch (S2) have opposite switching states, and the first switch (S1) and the third switch (S3) have opposite switching states.

[0034] Optionally, the output chopper module (6) includes: a fifth switch (S5), a sixth switch (S6), a seventh switch (S7), and an eighth switch (S8);

[0035] The fifth switch (S5) is connected between the first output terminal of the first processing module (1) and the first input terminal of the analog-to-digital converter (2); the sixth switch (S6) is connected between the first output terminal of the first processing module (1) and the second input terminal of the analog-to-digital converter (2); the seventh switch (S7) is connected between the second output terminal of the first processing module (1) and the first input terminal of the analog-to-digital converter (2); and the eighth switch (S8) is connected between the second output terminal of the first processing module (1) and the second input terminal of the analog-to-digital converter (2).

[0036] The fifth switch (S5) and the eighth switch (S8) have the same switching state, the fifth switch (S5) and the sixth switch (S6) have opposite switching states, and the fifth switch (S5) and the seventh switch (S7) have opposite switching states.

[0037] Optionally, the current detection circuit further includes: a rate adjustment module (7);

[0038] The rate adjustment module (7) is disposed between the analog-to-digital converter (2) and the second processing module (3);

[0039] The rate adjustment module (7) is used to adjust the rate of the received signal before outputting it.

[0040] Optionally, the rate adjustment module (7) includes: a decimator (71), a first filter (72), and a second filter (76);

[0041] The extractor (71) is used to reduce the rate of the received signal before outputting it.

[0042] The first filter (72) is disposed at the input end of the extractor (71) to suppress high-frequency noise;

[0043] The second filter (76) is located at the output of the extractor (71) to suppress high-frequency noise.

[0044] Optionally, the first filter (72) includes at least one cascaded integrator (73); the second filter (76) includes at least one cascaded comb filter (77).

[0045] Optionally, the integrator (73) includes: an adder (74) and a first delay unit (75);

[0046] The comb filter (77) includes: a subtractor (78) and a second delay unit (79);

[0047] The output of the adder (74) is connected to the input of the adder (74) through the first delay unit (75);

[0048] The first input terminal of the subtractor (78) is connected to the second input terminal of the subtractor (78) through the second delay unit (79).

[0049] Optionally, the current detection circuit further includes: a calibration module (8);

[0050] The calibration module (8) is disposed between the analog-to-digital converter (2) and the second processing module (3);

[0051] The calibration module (8) is used to calibrate the received signal and then output it.

[0052] In a second aspect, embodiments of this application provide a current detection method, based on a current detection circuit as described in any of the first aspects, comprising:

[0053] Obtain the detection signal output by the second processing module (3) of the current detection circuit;

[0054] The current detection result is obtained based on the detection signal.

[0055] Thirdly, embodiments of this application provide a battery management chip, including: a current detection circuit as described in any of the first aspects.

[0056] Fourthly, embodiments of this application provide a battery system, including: a battery management chip as described in the third aspect, and a battery pack.

[0057] Optionally, the battery system includes a coulomb counter.

[0058] Fifthly, embodiments of this application provide a transportation device, including a battery system as described in any of the fourth aspects.

[0059] The current detection circuit, method, battery management chip, battery system, and device provided in this application increase the amplitude of the input signal by adding a first processing module 1 before the analog-to-digital converter 2. The analog-to-digital converter 2 then converts the amplified input signal into a digital signal. When the analog-to-digital converter 2 converts the amplified input signal, each quantization level of the analog-to-digital converter 2 represents a smaller actual voltage change, thereby improving the detection accuracy of the input signal and reducing errors. A second processing module 3 is added after the analog-to-digital converter 2 to restore the amplitude of the output signal of the analog-to-digital converter 2 to obtain a detection signal. The accuracy of current detection can be improved by obtaining the current detection result based on the detection signal. Attached Figure Description

[0060] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0061] Figure 1 This is a schematic diagram of a scenario involved in an embodiment of this application;

[0062] Figure 2 This is a schematic diagram of a current detection circuit.

[0063] Figure 3 This is a schematic diagram of a current detection circuit provided in an embodiment of this application;

[0064] Figure 4 This is a schematic diagram of another current detection circuit provided in an embodiment of this application;

[0065] Figure 5 This is a schematic diagram of the third current detection circuit provided in the embodiments of this application;

[0066] Figure 6 This is a schematic diagram of the structure of the fourth current detection circuit provided in the embodiments of this application;

[0067] Figure 7 This is a schematic diagram of the structure of the fifth current detection circuit provided in the embodiments of this application;

[0068] Figure 8 This is a schematic diagram of the structure of a chopper module provided in an embodiment of this application;

[0069] Figure 9 This is a schematic diagram of the structure of a rate adjustment module provided in an embodiment of this application;

[0070] Figure 10 This is a schematic diagram of the structure of a gain control module provided in an embodiment of this application;

[0071] Figure 11 A schematic flowchart illustrating the output gain parameters of a gain control module provided in an embodiment of this application;

[0072] Figure 12 A schematic flowchart of a current detection method provided in an embodiment of this application;

[0073] Figure 13 A schematic flowchart of another current detection method provided in an embodiment of this application;

[0074] Figure 14 This is a flowchart illustrating the third current detection method provided in the embodiments of this application.

[0075] Explanation of reference numerals in the attached figures:

[0076] 1: First processing module; 2: Analog-to-digital converter; 21: Amplification module; 22: Reference module; 25: Adder module; 3: Second processing module; 32: Divider; 35: Subtraction module; 4: Gain control module; 41: Detector; 42: Comparator; 5: Input chopper module; 51: First switch module; 6: Output chopper module; 61: Second switch module; 7: Rate adjustment module; 71: Decimator; 72: First filter; 73: Integrator; 74: Adder; 75: First delay unit; 76: Second filter; 77: Comb filter; 78: Subtractor; 79: Second delay unit; 8: Calibration module; 9: Metrology module; S1: First switch; S2: Second switch; S3: Third switch; S4: Fourth switch; S5: Fifth switch; S6: Sixth switch; S7: Seventh switch; S8: Eighth switch.

[0077] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0078] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0079] Figure 1 This is a schematic diagram of a scenario involved in an embodiment of this application, such as... Figure 1 As shown, the specific application scenario of this application is to detect the current of a battery.

[0080] With the rapid development of new energy vehicles, estimating the State of Charge (SOC) of lithium batteries has become increasingly important. SOC represents the percentage of the remaining capacity of a lithium battery relative to its actual maximum usable capacity. Users can estimate the vehicle's driving range based on the SOC. If the SOC estimate is inaccurate, users may experience insufficient driving range due to misjudging the remaining battery capacity, negatively impacting the user experience.

[0081] As a key part of the battery management system, current detection results directly affect the accuracy of lithium battery SOC.

[0082] Currently, a shunt is used to convert DC current into a voltage signal, and then a high-precision analog-to-digital converter, such as a 16-bit analog-to-digital converter, is used to convert the voltage signal into a digital voltage. After the digital voltage is calibrated by a calibration module, the current detection result is obtained by calculation using a coulomb counter.

[0083] This method suffers from low current detection accuracy.

[0084] In conclusion, improving the accuracy of current detection has become an urgent problem to be solved.

[0085] Figure 2 This is a schematic diagram of a current detection circuit. Figure 2 As shown, the DC current is converted into a voltage signal via a shunt. A high-precision analog-to-digital converter (ADC) (e.g., a 20-bit ADC) is used instead of a 16-bit ADC to convert the voltage signal into a digital voltage. The digital voltage is then calibrated and used to calculate the current detection result using a coulomb counter.

[0086] As the bit depth of an analog-to-digital converter (ADC) increases, ultra-high-precision ADCs typically require longer conversion times to ensure accuracy at each quantization level. This results in a relatively slow conversion rate. Furthermore, higher bit depths in the ADC place greater demands on the bandwidth of the input signal, and consequently, reduce the maximum analog input frequency the ADC can handle. This approach suffers from low conversion efficiency, impacting processing speed.

[0087] In conclusion, how to improve the accuracy of current detection without reducing conversion efficiency has become an urgent problem to be solved.

[0088] In view of this, embodiments of this application provide a current detection circuit. By adding a first processing module before the analog-to-digital converter (ADC) to increase the amplitude of the input voltage, the ADC converts the amplified input signal into a digital voltage. When the ADC converts the amplified input signal, the actual voltage change represented by each quantization level of the ADC is smaller, thereby improving the voltage detection accuracy and reducing errors. A second processing module is added after the ADC to restore the amplitude of the ADC's output voltage. The current detection result is obtained based on the voltage after amplitude restoration, thereby improving the current detection accuracy.

[0089] It should be understood that the embodiments of this application can be used not only for current detection of lithium batteries in vehicles, but also for current detection of any energy storage element.

[0090] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0091] Figure 3 This is a schematic diagram of a current detection circuit provided in an embodiment of this application, as shown below. Figure 3 As shown, it includes: a first processing module 1, an analog-to-digital converter 2, and a second processing module 3;

[0092] The first processing module 1 can be any module that can increase the amplitude of the input signal, such as any of the following: a fixed gain amplifier, a programmable gain amplifier, a transformer, an adder module, etc.

[0093] The analog-to-digital converter 2 can be any device that can convert analog signals into digital signals. For example, it can include any of the following: successive approximation register ADC, Σ-Δ (Sigma-Delta) ADC, flash ADC, dual-slope ADC, etc.

[0094] The second processing module 3 can be any module that can reduce the amplitude of the input signal, such as any of the following: divider, voltage divider, transformer, subtraction module, etc.

[0095] The first processing module 1 receives an input signal of a first amplitude and uses it to increase the amplitude of the input signal to a second amplitude; the input signal may be, for example, a voltage signal, which may be obtained by converting DC current by a shunt.

[0096] Analog-to-digital converter 2, connected to the first processing module 1, is used to convert the output signal of the first processing module 1 into a digital signal;

[0097] The second processing module 3, connected to the analog-to-digital converter 2, is used to restore the amplitude of the output signal of the analog-to-digital converter 2 to a first amplitude to obtain a detection signal; the detection signal is used to obtain the current detection result. For example, the detection signal can be output to the metering module, or it can be output to the metering module after passing through a low-pass filter. The metering module may include, for example, a coulomb meter, a controller, etc. The metering module can convert the detection signal into current based on the detection signal to obtain the current detection result.

[0098] The signal processing procedure of a current detection circuit can be illustrated as follows:

[0099] The first processor module 1 receives an input signal of the first amplitude and increases the amplitude of the input signal to the second amplitude; the first processing module 1 transmits the input signal of the second amplitude to the analog-to-digital converter 2; the analog-to-digital converter 2 converts the signal of the second amplitude into a digital signal; the analog-to-digital converter 2 transmits the digital signal of the second amplitude to the second processing module 3; the second processing module 3 restores the digital signal of the second amplitude to the first amplitude to obtain a detection signal.

[0100] For example, if the resolution of analog-to-digital converter 2 is 0.1V and the first amplitude of the input signal is 1V, then the input signal represents 10 quantization levels, and the actual voltage corresponding to each quantization level is 0.1V. The first processing module 1 increases the amplitude of the input signal by a factor of 10, resulting in a second amplitude of 10V. In analog-to-digital converter 2 with the same resolution, 10V can correspond to 100 quantization levels, and the voltage corresponding to each quantization level is 0.1V. This 0.1V voltage corresponds to the voltage after the actual voltage is increased by a factor of 10, so the actual voltage corresponding to each quantization level is 0.01V. When analog-to-digital converter 2 performs analog-to-digital conversion on the second amplitude input signal, the actual input voltage represented by each quantization result of analog-to-digital converter 2 changes less, resulting in higher detection accuracy. The second processing module 3 restores the digital signal of the second amplitude to the first amplitude, resulting in a more accurate detection signal. The current detection result obtained from the detection signal is more accurate, improving the precision of the current detection result.

[0101] In this embodiment, the first processing module 1 is used in conjunction with a general-purpose high-precision analog-to-digital converter for current detection, thus avoiding the problem of reduced conversion efficiency when using an ultra-high-precision analog-to-digital converter.

[0102] In summary, the current detection circuit provided in this application increases the amplitude of the input signal by adding a first processing module 1 before the analog-to-digital converter 2, and then uses the analog-to-digital converter 2 to convert the increased input signal into a digital signal. When the analog-to-digital converter 2 converts the increased input signal, the actual voltage change represented by each quantization level of the analog-to-digital converter 2 is smaller, thereby improving the detection accuracy of the input signal and reducing errors. Adding a second processing module 3 after the analog-to-digital converter 2 restores the amplitude of the output signal of the analog-to-digital converter 2 to obtain the detection signal. Obtaining the current detection result based on the detection signal can improve the accuracy of current detection.

[0103] Figure 4 This is a schematic diagram of another current detection circuit provided in an embodiment of this application, as shown below. Figure 4 As shown, in this embodiment... Figure 3 Based on the embodiments, the current detection circuit will be described in detail.

[0104] The current detection circuit includes: a first processing module 1, an analog-to-digital converter 2, and a second processing module 3;

[0105] The first processing module 1 may include, for example, an amplification module 21 and a gain control module 4; the second processing module 3 may include a divider 32.

[0106] The amplification module 21 can be any module that can amplify signals, such as a fixed gain amplifier, a programmable gain amplifier, etc.

[0107] Gain control module 4 can be any module capable of dynamically adjusting gain parameters.

[0108] The divider 32 can be any device capable of dividing one digital value by another. For example, it can be a hardware divider implemented with an integrated circuit, or a divider implemented using a software algorithm in a processor.

[0109] Amplification module 21 is connected to gain control module 4 and analog-to-digital converter 2; gain control module 4 is connected to amplification module 21; divider 32 is connected to analog-to-digital converter 2.

[0110] Amplification module 21 amplifies the input signal according to a gain parameter, ensuring the amplified input signal has a second amplitude, and then transmits this second-amplitude signal to analog-to-digital converter 2. Amplifying the input signal according to the gain parameter allows for precise control of the amplification factor. Furthermore, the gain parameter of amplification module 21 is adjustable. Since the amplitude of the input signal may vary considerably, adjustable gain parameters allow amplification module 21 to dynamically adjust the amplification factor based on the input signal amplitude, ensuring the output signal remains within the operating range of subsequent devices. For example, when the input signal amplitude is small, a larger gain parameter can improve the resolution of the small-amplitude signal; conversely, when the input signal amplitude is large, a smaller gain parameter can prevent the output amplitude from exceeding the operating range of subsequent devices.

[0111] The gain control module 4 is used to adjust the gain parameters of the amplification module 21 according to the first amplitude. The gain control module 4 can adjust the gain parameters of the amplification module 21 based on the first amplitude, allowing the amplification module 21 to use different gain parameters for amplifying input signals of different amplitudes. This achieves more precise gain control, improves gain stability, and enhances the adaptability of the amplification module 21. The gain control module 4 can optimize the gain parameters in a timely manner according to the strength of the input signal, ensuring that the output signal is within a suitable dynamic range.

[0112] The magnitude of the gain parameter can be negatively correlated with the magnitude of the first amplitude. For example, the smaller the first amplitude, the larger the gain parameter, which can amplify a signal with a smaller amplitude by a larger factor, further improving the detection accuracy of the signal; the larger the first amplitude, the smaller the gain parameter, which can amplify a signal with a larger amplitude by a smaller factor, making the output signal more stable and ensuring that the output signal is within the appropriate dynamic range.

[0113] Analog-to-digital converter 2 is used to convert the output signal of amplifier module 21 into a digital signal.

[0114] Divider 32 is used to divide the signal output by analog-to-digital converter 2 by the gain parameter to restore the amplitude of the output signal of analog-to-digital converter 2 to the first amplitude. Divider 32 and amplification module 21 use the same gain parameter, that is, the factor by which the divider 32 reduces the signal is equal to the factor by which the amplification module 21 amplifies the signal, which is easy to implement.

[0115] Furthermore, the first processing module 1 also includes a reference module 22; the reference module 22 can be any module that can provide DC voltage, such as any of the following: a reference voltage source, a voltage regulator, etc.

[0116] The reference module 22 is connected to the input terminal of the amplifier module 21 and is used to provide a reference level for the input signal. For example, the amplifier module 21 can provide a stable reference point so that the output voltage is within the signal range that the amplifier module 21 can process.

[0117] Furthermore, the reference module 22 may include a voltage source. One end of the voltage source receives the input signal, and the other end of the voltage source is connected to the input terminal of the amplifier module 21. This approach is easy to implement.

[0118] In summary, the current detection circuit provided in this application increases the amplitude of the input signal by adding an amplification module 21 before the analog-to-digital converter 2, and then uses the analog-to-digital converter 2 to convert the amplified input signal into a digital signal. When the analog-to-digital converter 2 converts the amplified input signal, the actual voltage change represented by each quantization level of the analog-to-digital converter 2 is smaller, thereby improving the detection accuracy of the input signal and reducing errors. Adding a divider 32 after the analog-to-digital converter 2 restores the amplitude of the output signal of the analog-to-digital converter 2 to obtain the detection signal. Obtaining the current detection result based on the detection signal can improve the accuracy of current detection.

[0119] Figure 5 This is a schematic diagram of the third current detection circuit provided in the embodiments of this application, as shown below. Figure 5 As shown, in this embodiment... Figure 3 Based on the embodiments, the current detection circuit will be described in detail.

[0120] The current detection circuit includes: a first processing module 1, an analog-to-digital converter 2, and a second processing module 3;

[0121] The first processing module 1 may include, for example, an addition module 25; the second processing module 3 may include a subtraction module 35.

[0122] The addition module 25 can be any module capable of summing two received signals. For example, it can be an adder.

[0123] The subtraction module 35 can be any module that can calculate the difference between the received signals. For example, it can be a subtractor.

[0124] The addition module 25 is connected to the input terminal of the analog-to-digital converter 2; the subtraction module 35 is connected to the analog-to-digital converter 2.

[0125] The adder module 25 is used to sum the input signal with a preset amplitude to increase the amplitude of the input signal to a second amplitude, and then transmit the signal with the second amplitude to the analog-to-digital converter 2. For example, one end of the adder module 25 receives the input signal, and the other end is connected to a signal source, with the value of the signal source serving as the preset amplitude. The adder module 25 can superimpose the input signal with the signal source to increase the amplitude of the input signal to the second amplitude.

[0126] Analog-to-digital converter 2 is used to convert the output signal of adder module 25 into a digital signal.

[0127] The subtraction module 35 is used to subtract the signal output by the analog-to-digital converter 2 from a preset amplitude, so as to restore the amplitude of the output signal of the analog-to-digital converter 2 to a first amplitude. For example, one end of the subtraction module 35 receives the input signal, and the other end is connected to a signal source, with the value of the signal source serving as the preset amplitude. The subtraction module 35 can subtract the input signal from the signal source to restore the amplitude of the input signal to the first amplitude.

[0128] In summary, the current detection circuit provided in this application increases the amplitude of the input signal by adding an adder module 25 before the analog-to-digital converter 2, and then uses the analog-to-digital converter 2 to convert the increased input signal into a digital signal. When the analog-to-digital converter 2 converts the increased input signal, the actual voltage change represented by each quantization level of the analog-to-digital converter 2 is smaller, thereby improving the detection accuracy of the input signal and reducing errors. Adding a subtraction module 35 after the analog-to-digital converter 2 restores the amplitude of the output signal of the analog-to-digital converter 2 to obtain the detection signal. Obtaining the current detection result based on the detection signal can improve the accuracy of current detection.

[0129] Figure 6 This is a schematic diagram of the structure of the fourth current detection circuit provided in the embodiments of this application, as shown below. Figure 6 As shown, in Figure 4Based on the embodiments, the current detection circuit will be described in detail.

[0130] Furthermore, the current detection circuit may also include a metering module 9; the metering module 9 may be any module capable of measuring electrical energy, such as any of the following: coulomb counter, processor, etc.

[0131] The metering module 9 is connected to the second processing module 3 and is used to measure the power of the detection signal.

[0132] Furthermore, the metering module 9 may include a coulomb meter. After converting the detection signal into a current signal, the coulomb meter integrates the current signal over time to measure the amount of electricity.

[0133] Coulomb counters calculate power consumption by integrating the current flowing through a circuit. Typically, a coulomb counter receives a voltage value, converts it to a current value, and then integrates it over time. This voltage value must be the input voltage. To improve current detection accuracy, related current detection circuits often increase the amplitude of the input signal and then perform analog-to-digital conversion (ADC) on this increased signal. This reduces the amount of change in the actual input voltage represented by each quantization result of the ADC. However, this method essentially alters the output voltage value, leading to a mismatch between current detection and coulomb counter measurement requirements. This proposed solution improves current detection accuracy by first increasing the amplitude of the input signal, then converting the analog signal to a digital signal. Finally, it restores the digital signal to a voltage with the same amplitude as the input signal, making it well-suited for coulomb counters and easy to integrate.

[0134] The current detection circuit may further include an input chopper module 5. The input chopper module 5 can be any module capable of increasing the signal frequency, such as a multiplier, mixer, phase-locked loop, charge pump, etc. The input chopper module 5 can increase the signal frequency, for example, by modulating the input signal with a periodic signal. The input chopper module 5 is located at the input terminal of the first processing module 1. The input chopper module 5 is used to increase the frequency of the input signal and transmit the increased frequency input signal to the first processing module 1. The input chopper module 5 suppresses low-frequency noise by increasing the frequency of the input signal.

[0135] Furthermore, the input chopper module 5 is specifically used to perform square wave modulation on the input signal to increase its frequency. Square wave modulation does not require duty cycle control and is easy to implement.

[0136] The input chopper module 5 includes: a first switch module 51; the first switch module 51 can be any module based on high or low level conduction, such as any one of the following: transistor, field-effect transistor (MOSFET), also known as MOS transistor, thyristor, etc.

[0137] One end of the first switching module 51 is connected to the input signal; the other end of the first switching module 51 is connected to the input terminal of the first processing module 1. The first switching module 51 is used to turn on or off in response to a control signal to modulate the input signal with a square wave, thereby increasing the frequency of the input signal. For example, under the action of a control signal, the first switching module 51 periodically switches the signal path to modulate the input signal to a chopping frequency with the same frequency as the control signal, thereby increasing the frequency of the input signal. This can suppress low-frequency noise.

[0138] The control signal for the first switching module 51 is a square wave signal. Under the action of the square wave signal, the first switching module 51 periodically turns on or off, modulating the input signal with a square wave. This method does not require the duty cycle of the control signal and is easy to implement.

[0139] The current detection circuit also includes an output chopper module 6; the output chopper module 6 can be any module that can reduce the signal frequency. For example, the output chopper module 6 can demodulate the signal modulated at the chopping frequency to the original input signal frequency by quickly switching the input signal.

[0140] The output chopper module 6 is located between the first processing module 1 and the second processing module 3. It is used to reduce the frequency of the received signal and output the signal after the frequency reduction.

[0141] In one example, the output chopper module 6 can be located between the first processing module 1 and the analog-to-digital converter 2. The output chopper module 6 can demodulate the input signal modulated at the chopping frequency back to the original input signal frequency, and modulate the offset voltage and low-frequency noise of the first processing module 1 to a high frequency. This distinguishes the frequencies of the input signal from the noise.

[0142] In another example, the output chopper module 6 can be located between the analog-to-digital converter 2 and the second processing module 3. The output chopper module 6 can demodulate the input signal modulated at the chopping frequency back to the original input signal frequency, and modulate the offset voltage and low-frequency noise of the first processing module 1 to a high frequency. This distinguishes the frequencies of the input signal from the noise.

[0143] Furthermore, the output chopper module 6 includes a second switching module 61; the second switching module 61 can be any module based on high or low level conduction, such as any one of the following: transistor, field-effect transistor (MOSFET), also known as MOS transistor, thyristor, etc.

[0144] One end of the second switching module 61 is connected to the output terminal of the first processing module 1; the other end of the second switching module 61 is connected to the input terminal of the analog-to-digital converter 2. The second switching module 61 is used to turn on or off in response to a control signal to reduce the frequency of the received signal and output the signal with the reduced frequency. For example, under the action of a control signal, the second switching module 61 periodically switches the signal path, demodulating the signal modulated at the same chopping frequency as the control signal to the original input signal frequency, thereby reducing the frequency of the input signal. This can restore the original form of the input signal.

[0145] The input signal undergoes two chopping operations, one in the input chopper module 5 and the other in the output chopper module 6. The offset voltage of the first processing module 1 is processed by the output chopper module 6, thus requiring only one chopping operation. This ensures the input signal maintains its waveform at the output of the output chopper module 6, and the chopping offset voltage can be eliminated by subsequent filters, thereby suppressing noise and offset voltage. This allows the first processing module 1 to have a higher dynamic range, further improving current detection accuracy.

[0146] Furthermore, the current detection circuit also includes a rate adjustment module 7; the rate adjustment module 7 can be any module capable of adjusting the rate of the signal. For example, it can include any of the following: a cascaded integrator-comb filter (CIC) filter, a half-sideband filter, etc.

[0147] The rate adjustment module 7 is located between the analog-to-digital converter 2 and the second processing module 3; the rate adjustment module 7 is used to adjust the rate of the received signal before outputting it. For example, the rate adjustment module 7 can reduce the signal rate by decimation, that is, outputting a signal every few signals, which can improve the signal processing rate of subsequent modules; or, the rate adjustment module 7 can increase the signal rate by interpolation, that is, inserting signals between input signals, which can achieve rate compatibility between different modules.

[0148] The current detection circuit also includes a calibration module 8; the calibration module 8 can be any module capable of calibrating the received signal. The calibration module 8 is located between the analog-to-digital converter 2 and the second processing module 3; the calibration module 8 is used to calibrate the received signal before outputting it. By calibrating the received signal through the calibration module 8, deviations introduced by the signal in the other processing modules of the current detection circuit before transmission to the calibration module 8 can be corrected, improving the accuracy of the output signal and thus improving the accuracy of current detection.

[0149] Figure 6 The following diagram illustrates a current detection circuit comprising: input chopper module 5, amplification module 21, gain control module 4, analog-to-digital converter 2, output chopper module 6, rate adjustment module 7, calibration module 8, divider 32, and metering module 9. The input terminal of input chopper module 5 receives the input signal; the output terminal of input chopper module 5 is connected to the input terminals of amplification module 21 and gain control module 4; the output terminal of gain control module 4 is connected to the gain control terminal of amplification module 21; the output terminal of amplification module 21 is connected to the input terminal of analog-to-digital converter 2; the output terminal of analog-to-digital converter 2 is connected to the input terminal of output chopper module 6; the output terminal of output chopper module 6 is connected to the input terminal of rate adjustment module 7; the output terminal of rate adjustment module 7 is connected to the input terminal of calibration module 8; the output terminal of calibration module 8 is connected to the input terminal of divider 32; and the output terminal of divider 32 is connected to metering module 9. Control signals are connected to the control terminals of input chopper module 5 and output chopper module 6.

[0150] The signal processing procedure of a current detection circuit can be illustrated as follows:

[0151] The input chopper module 5 receives an input signal of the first amplitude. The input chopper module 5 includes a first switch module 51, which is turned on or off under the action of a square wave signal. The polarity of the input signal is rapidly switched alternately at the frequency of the square wave signal to modulate the input signal of the first amplitude, thereby increasing the frequency of the input signal. The input chopper module 5 transmits the modulated signal to the amplification module 21.

[0152] The gain control module 4 adjusts the gain parameter of the amplification module 21 according to the first amplitude.

[0153] Amplification module 21 amplifies the input signal according to the gain parameter, increasing the amplitude of the modulated input signal to a second amplitude, and then transmits it to analog-to-digital converter 2. Analog-to-digital converter 2 converts the signal with the second amplitude into a digital signal; analog-to-digital converter 2 then transmits the digital signal with the second amplitude to output chopper module 6.

[0154] The output chopper module 6 is turned on or off under the action of the square wave signal, and the polarity of the input signal is rapidly switched alternately at the frequency of the square wave signal to demodulate the digital signal of the second amplitude and restore the digital signal of the second amplitude back to the original frequency; at the same time, the offset voltage and low frequency noise amplified by the amplification module 21 are modulated to the high frequency; the output chopper module 6 transmits the demodulated digital signal of the second amplitude to the rate adjustment module 7.

[0155] The rate adjustment module 7 reduces the rate of the demodulated second amplitude digital signal and transmits it to the calibration module 8.

[0156] After calibrating the received signal, the calibration module 8 outputs the result to the divider 32.

[0157] Divider 32 divides the received signal by the gain parameter to restore the digital signal of the second amplitude to the first amplitude, thus obtaining the detection signal; the detection signal is used to obtain the current detection result.

[0158] The metering module 9 measures the amount of electricity based on the detection signal.

[0159] In summary, the current detection circuit provided in this application increases the amplitude of the input signal by adding an amplification module 21 before the analog-to-digital converter 2, and then uses the analog-to-digital converter 2 to convert the amplified input signal into a digital signal. When the analog-to-digital converter 2 converts the amplified input signal, the actual voltage change represented by each quantization level of the analog-to-digital converter 2 is smaller, thereby improving the detection accuracy of the input signal and reducing errors. Adding a divider 32 after the analog-to-digital converter 2 restores the amplitude of the output signal of the analog-to-digital converter 2 to obtain the detection signal. Obtaining the current detection result based on the detection signal improves the accuracy of current detection. Adding an input chopper module 5 before the first processing module 1 and an output chopper module 6 after the first processing module 1 suppresses noise, allowing the first processing module 1 to have a higher dynamic range, further improving the current detection accuracy. Reducing the signal rate through the rate adjustment module 7 increases the processing speed of subsequent devices and improves processing efficiency. Calibrating the signal through the calibration module 8 improves the accuracy of current detection. Dynamically adjusting the amplification factor of the amplification module 21 through the gain control module 4 further improves the current detection accuracy. By restoring the digital signal to a voltage with the same amplitude as the input signal, it is well-suited for coulomb counters and is easy to integrate.

[0160] Figure 7 This is a schematic diagram of the structure of the fifth current detection circuit provided in the embodiments of this application, as shown below. Figure 7As shown, the current detection circuit includes: input chopper module 5, amplification module 21, gain control module 4, analog-to-digital converter 2, output chopper module 6, rate adjustment module 7, calibration module 8, divider 32, and metering module 9. This is illustrated using an example.

[0161] The amplification module 21 includes a programmable gain amplifier (PGA); the gain control module 4 includes a gain control module (GCB); the analog-to-digital converter 2 includes a Σ-Δ ADC (ADC for short); the rate adjustment module 7 includes a CIC filter; the calibration module 8 includes a calibration module (Correction); and the measurement module 9 includes a coulomb counter (Coulomb Count).

[0162] The input terminal of input chopper module 5 receives the input signal; the output terminal of input chopper module 5 is connected to the input terminal of programmable gain amplifier (PGA) and the input terminal of gain control module (GCB); the output terminal of programmable gain amplifier (PGA) is connected to the input terminal of ADC; the output terminal of ADC is connected to the input terminal of output chopper module 6; the output terminal of output chopper module 6 is connected to the input terminal of CIC filter; the output terminal of CIC filter is connected to the input terminal of calibration module (Correction); the output terminal of calibration module (Correction) is connected to the input terminal of divider 32; the output terminal of divider 32 is connected to coulomb counter (Coulomb Count). The control terminals of input chopper module 5 and output chopper module 6 are connected to the control signal DIG Chopper.

[0163] The signal processing procedure of a current detection circuit can be illustrated as follows:

[0164] The voltage drop generated by the DC current through the shunt is input to the first input terminal A1 and the second input terminal A2.

[0165] The input chopper module 5 receives an input signal of the first amplitude; it performs square wave modulation on the input signal of the first amplitude to modulate the input signal to the frequency of the square wave signal, thereby increasing the frequency of the input signal; the input chopper module 5 transmits the modulated signal to the programmable gain amplifier PGA.

[0166] The gain control module GCB adjusts the gain parameters of the programmable gain amplifier PGA based on the first amplitude, thereby controlling the amplification factor of the programmable gain amplifier PGA.

[0167] The programmable gain amplifier (PGA) amplifies the input signal according to the gain parameter, increases the amplitude of the modulated input signal to a second amplitude, and transmits it to the ADC.

[0168] The ADC converts the second amplitude signal into a digital signal; the ADC transmits the second amplitude digital signal to the output chopper module 6.

[0169] The output chopper module 6 is turned on or off under the action of the square wave signal, and the polarity of the input signal is rapidly switched alternately at the frequency of the square wave signal to demodulate the digital signal of the second amplitude and restore the digital signal of the second amplitude back to the original frequency; at the same time, the offset voltage and low-frequency noise amplified by the programmable gain amplifier PGA are modulated to the high frequency; the output chopper module 6 transmits the demodulated digital signal of the second amplitude to the CIC filter.

[0170] The CIC filter reduces the rate of the demodulated second-amplitude digital signal before transmitting it to the calibration module.

[0171] The calibration module calibrates the received signal and outputs it to the divider 32.

[0172] Divider 32 divides the received signal by the gain parameter, restoring the second-amplitude digital signal to the first amplitude to obtain the detection signal. The detection signal is used to obtain the current detection result. Divider 32 transmits the detection signal to the Coulomb Count and outputs it after filtering by a low-pass filter (LPF).

[0173] The coulomb count measures electrical quantity based on the detected signal. For example, the coulomb count uses a counter to integrate the detected signal and time to obtain the cumulative current over time, thus determining how many coulombs flowed. The structure of the input chopper module 5 and the output chopper module 6 is illustrated below.

[0174] Figure 8 This is a schematic diagram of a chopper module provided in an embodiment of this application. Figure 8 As shown, the example is an output chopper module 6 located between the first processing module 1 and the analog-to-digital converter 2.

[0175] The input chopper module 5 includes a first switch module 51; the input signals include a first input signal and a second input signal.

[0176] The first switch module 51 includes: a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4; the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 can all be any module based on high or low level conduction, such as any of the following: transistor, field-effect transistor (MOSFET), also known as MOS transistor, thyristor, etc.

[0177] The first switch S1 is connected between the first input signal and the first input terminal of the first processing module 1; the second switch S2 is connected between the first input signal and the second input terminal of the first processing module 1; the third switch S3 is connected between the second input signal and the first input terminal of the first processing module 1; and the fourth switch S4 is connected between the second input signal and the second input terminal of the first processing module 1.

[0178] The first switch S1 and the fourth switch S4 are in the same state. The first switch S1 and the second switch S2 are in opposite states. The first switch S1 and the third switch S3 are in opposite states.

[0179] The second switch module 61 includes: a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8;

[0180] The fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 can all be any module that is turned on based on a high or low level. For example, they can include any of the following: transistors, field-effect transistors (MOSFETs), also known as MOS transistors, thyristors, etc.

[0181] The fifth switch S5 is connected between the first output terminal of the first processing module 1 and the first input terminal of the analog-to-digital converter 2; the sixth switch S6 is connected between the first output terminal of the first processing module 1 and the second input terminal of the analog-to-digital converter 2; the seventh switch S7 is connected between the second output terminal of the first processing module 1 and the first input terminal of the analog-to-digital converter 2; and the eighth switch S8 is connected between the second output terminal of the first processing module 1 and the second input terminal of the analog-to-digital converter 2.

[0182] The fifth switch S5 and the eighth switch S8 are in the same state, the fifth switch S5 and the sixth switch S6 are in opposite states, and the fifth switch S5 and the seventh switch S7 are in opposite states.

[0183] In one example, the input chopper module 5 receives an input signal of the first amplitude. When the control signal is high, the first switch S1 and the fourth switch S4 are turned on, the second switch S2 and the third switch S3 are turned off, and the path between the first input signal and the first input terminal of the first processing module 1 is open; the path between the second input signal and the second input terminal of the first processing module 1 is also open. When the control signal is low, the first switch S1 and the fourth switch S4 are turned off, the second switch S2 and the third switch S3 are turned on, and the path between the first input signal and the second input terminal of the first processing module 1 is open; the path between the second input signal and the first input terminal of the first processing module 1 is also open. When each switch in the first switch module 51 switches between on and off states in response to the control signal, the first input signal and the second input signal are periodically connected to different paths, thereby multiplying the input signal with the control signal to achieve modulation of the input signal. When the control signal is a square wave signal, the input chopper module 5 modulates the input signal with a square wave, shifting the DC signal to a higher frequency, while the low-frequency noise and offset voltage of the input signal remain at a lower frequency.

[0184] The first processing module 1 increases the amplitude of the modulated signal to a second amplitude, while simultaneously increasing the amplitude of the noise and the offset voltage of the first processing module 1.

[0185] Output chopper module 6 receives a signal with a second amplitude. When the control signal is high, switches S5 and S8 are turned on, and switches S6 and S7 are turned off, connecting the first output of the first processing module 1 to the first input of the analog-to-digital converter 2; the second output of the first processing module 1 is also connected to the second input of the analog-to-digital converter 2. When the control signal is low, switches S5 and S8 are turned off, and switches S6 and S7 are turned on, connecting the first output of the first processing module 1 to the second input of the analog-to-digital converter 2; the second output of the first processing module 1 is also connected to the first input of the analog-to-digital converter 2. When the switches in the second switch module 61 switch between on and off states in response to the control signal, the first and second outputs of the first processing module 1 are periodically connected to different paths, thereby multiplying the output signal of the first processing module 1 with the control signal and demodulating the signal modulated at the control signal frequency back to DC or a low frequency. When the modulated signal passes through the output chopper module 6, the switching action of the switch restores the high-frequency modulated signal back to the original low-frequency signal, while modulating the offset voltage and low-frequency noise amplified by the first processing module 1 to a high frequency.

[0186] Figure 8Taking Vin+ as the first input signal and Vin- as the second input signal; the first processing module 1 includes an amplification module 21 and a reference module 22; the amplification module 21 includes a programmable gain amplifier (PGA), and the reference module 22 includes a voltage source (Vos) as an example for illustration. The analog-to-digital converter 2... Figure 8 (Not shown in the diagram). Input chopper module 5 receives the first input signal Vin+ and the second input signal Vin-; one end of voltage source Vos receives the modulation signal output by input chopper module 5, and the other end of voltage source Vos is connected to the input terminal of programmable gain amplifier PGA. The output terminal of programmable gain amplifier PGA is connected to the input terminal of output chopper module 6; the first output terminal Vout+ and the second output terminal Vout- of output chopper module 6 transmit the output signal to analog-to-digital converter 2.

[0187] The input chopper module 5 modulates the received first amplitude input signal into a square wave, modulating the input signal to the frequency of the square wave signal, thereby increasing the frequency of the input signal; the input chopper module 5 transmits the modulated signal to the programmable gain amplifier PGA through the voltage source Vos.

[0188] The programmable gain amplifier (PGA) amplifies the modulated signal according to the gain parameter, increases the amplitude of the signal to a second amplitude, and transmits the digital signal of the second amplitude to the output chopper module 6.

[0189] The output chopper module 6 is turned on or off under the action of a square wave signal, rapidly alternating the polarity of the input signal at the frequency of the square wave signal to demodulate the digital signal of the second amplitude and restore it to its original frequency. Simultaneously, it modulates the offset voltage and low-frequency noise amplified by the programmable gain amplifier (PGA) to a higher frequency. The output chopper module 6 then transmits the demodulated digital signal of the second amplitude to the analog-to-digital converter 2. A low-pass filter in the subsequent circuit effectively blocks high-frequency components, thus filtering out the high-frequency modulated offset voltage and noise, retaining only the input signal with increased amplitude. Because chopper stabilization technology can suppress noise, the input chopper module 5 and the output chopper module 6 enable the first processing module 1 to have a higher dynamic range, further improving the current detection accuracy.

[0190] The following diagram illustrates the structure of the rate adjustment module 7, using the CIC filter as an example.

[0191] Figure 9 This is a schematic diagram of a rate adjustment module provided in an embodiment of this application. Figure 9 As shown,

[0192] The rate adjustment module 7 may include, for example, an extractor 71; the extractor 71 may be any module that can reduce the signal rate, for example, a counter.

[0193] The decimator 71 is used to reduce the rate of the received signal before outputting it. For example, the decimator 71 can output a signal every M signals by setting a decimation factor M, effectively reducing the signal rate and improving the processing speed of subsequent modules.

[0194] Furthermore, the extractor 71 may include, for example, a counter; the counter performs counting and, when the counting result reaches a counting threshold, outputs the signal from the analog-to-digital converter 2 and resets the count. The counter is used to control the output time of the signal from the analog-to-digital converter 2. When the counting result has not reached the counting threshold, no signal is output; when the counting result reaches the counting threshold, the signal from the analog-to-digital converter 2 is output. After the counter is reset, timing for the next signal output can begin. This method is easy to implement.

[0195] The rate adjustment module 7 may further include a first filter 72; the first filter 72 may be any filter that allows low-frequency signals to pass through while blocking high-frequency signals, such as any of the following: an infinite impulse response filter (IIR), a finite impulse response filter (FIR), etc. The first filter 72 is located at the input of the decimator 71 and is used to suppress high-frequency noise.

[0196] Furthermore, the first filter 72 includes at least one cascaded integrator 73. The integrator 73 can be, for example, any device capable of performing an accumulation operation. The integrator 73 can be used to accumulate the input signal. Cascading at least one integrator 73 together can enhance the low-pass filtering effect.

[0197] The integrator 73 includes an adder 74 and a first delay unit 75; the output of the adder 74 is connected to its input via the first delay unit 75. This method is easy to implement and eliminates the need for a multiplier, thereby improving the processing speed of the received signal.

[0198] The rate adjustment module 7 may further include a second filter 76. The second filter 76 can be any filter that allows low-frequency signals to pass while impeding high-frequency signals, such as an infinite impulse response filter (IIR), a finite impulse response filter (FIR), etc. The second filter 76 is located at the output of the decimator 71 and is used to suppress high-frequency noise.

[0199] The second filter 76 includes at least one cascaded comb filter 77. The comb filter 77 can be, for example, any device capable of differential operation. The output of the comb filter 77 is the difference between the current input signal and the delayed input signal, which can eliminate periodic peaks in the frequency response and achieve a flatter frequency response.

[0200] The comb filter 77 includes a subtractor 78 and a second delay unit 79; the first input terminal of the subtractor 78 is connected to the second input terminal of the subtractor 78 through the second delay unit 79. This method is easy to implement and does not require a multiplier, thus improving the processing speed of the received signal.

[0201] In one example, the signal output by analog-to-digital converter 2 has a high speed. The signal output by analog-to-digital converter 2 can be slowed down to reduce the data volume and system complexity, while also performing anti-aliasing filtering. The rate adjustment module 7 receives the signal Vin1 output by analog-to-digital converter 2, slows down the signal, and then outputs it. The rate adjustment module 7 includes: a first filter 72, a decimator 71, and a second filter 76. The decimator 71 is positioned between the first filter 72 and the second filter 76. The first filter 72 receives the signal output by analog-to-digital converter 2, the decimator 71 reduces the rate of the received signal, and the second filter 76 outputs the slowed-down signal Vout1.

[0202] The first filter 72 includes cascaded n-stage integrators 73. Each n-stage integrator 73 operates at the original frequency and accumulates the input signal. Each integrator 73 is a first-order IIR filter with a transfer function of...

[0203] By cascading n integrators, the roll-off characteristic of the first filter 72 can be enhanced. The roll-off characteristic describes the rate attenuation of a signal in the transition band from the passband to the stopband. The more integrators cascaded, the steeper the roll-off characteristic, and the faster the signal attenuates from the passband to the stopband in the transition band, thus more effectively suppressing frequency components outside the passband.

[0204] The second filter 76 includes a cascaded n-stage comb filter 77. The comb filter 77 performs differential operations on the reduced-rate signal to suppress high-frequency noise and aliasing components. Each stage of the comb filter 77 is a first-order FIR filter with a transfer function of H. C (z)=1-z -D Where D is the differential delay, which can usually be equal to 1.

[0205] The comb filter 77 has the same number of stages as the integrator. The comb filter 77 can suppress high-frequency noise and remove high-frequency noise components that may be introduced during the rate reduction process.

[0206] The structure of gain control module 4 is described below.

[0207] Figure 10 This is a schematic diagram of a gain control module provided in an embodiment of this application. Figure 10 As shown, the gain control module 4 includes: a detector 41 and a comparator 42;

[0208] The input terminal of detector 41 receives the input signal and is used to detect the voltage of the input signal;

[0209] The first input terminal of comparator 42 is connected to the output terminal of detector 41, the second input terminal is connected to a reference voltage, and the output terminal is connected to amplification module 21. Comparator 42 is used to output the gain parameter of amplification module 21 based on the voltage comparison result between the input signal and the reference voltage. In one example, the processor can establish a communication connection with gain control module 4. The processor writes specific values ​​to the register of gain control module 4 through a communication interface such as a Serial Peripheral Interface (SPI). These values ​​are used to store information related to gain control, such as gain parameters and thresholds. After receiving the register write operation, comparator 42 can read the value in the register and continuously compare the input signal with the threshold in the register. Once the set threshold is reached, the gain parameter is adjusted. Multiple reference voltage thresholds can correspond to different gain levels to determine the amplification factor of amplification module 21 that needs to be adjusted. Furthermore, gain control module 4 can be turned on or off. For example, the gain control function can be enabled or disabled by the processor writing to the register of gain control module 4. Gain control module 4 is enabled by default. When the gain control module 4 is in the off state, the gain parameters of the amplifier module 21 can be adjusted by configuring the registers of the amplifier module 21 through the processor.

[0210] Furthermore, when the analog-to-digital converter 2 is started, if the gain control function of the gain module 4 is already enabled, the gain control module 4 first performs gain control on the amplification module 21, and after determining the gain parameters, the analog-to-digital converter performs analog-to-digital conversion on the input signal.

[0211] Figure 10 The following is a schematic illustration using an example where detector 41 includes a detector, comparator 42 includes a comparator pump (CMP), and amplification module 21 includes a power amplifier (PGA). The input terminal of the detector receives the input signal Vin2 and is used to detect the voltage of the input signal.

[0212] The first input terminal of the CMP is connected to the output terminal of the Detector, the second input terminal is connected to the reference voltage Vref, and the output terminal is connected to the PGA. The CMP is used to output the gain parameter of the PGA based on the voltage comparison result between the input signal Vin2 and the reference voltage Vref.

[0213] Figure 11 This is a schematic flowchart illustrating the output gain parameters of a gain control module provided in an embodiment of this application. Figure 11 As shown, taking the gain control module 4, which includes 8 gain levels, as an example, this paper illustrates how the gain control module 4 outputs gain parameters based on the voltage of the input signal.

[0214] For example, the gain levels of the gain control module 4 may include: 4, 8, 16, 32, 64, 128, 256, 512; the gain control module 4 may set an upper limit threshold and a lower limit threshold; the gain control module 4 amplifies the input voltage according to the set gain level and compares it with the upper limit threshold and the lower limit threshold respectively. If the amplitude of the amplified input voltage is between the upper limit threshold and the lower limit threshold, the gain level is output as a gain parameter to the amplification module 21, and the amplification module 21 amplifies the input signal according to the gain parameter.

[0215] In one example, the default gain level of the gain control module 4 (S1) can be set to 64. The differential voltage of the input signal is amplified 64 times by the detector 41 and transmitted to the comparator 42; the comparator 42 compares the amplified input signal 64 times with the upper threshold and the lower threshold respectively.

[0216] If the signal output by comparator 42 represents an input signal amplified by 64 times that is between the upper and lower thresholds, then the gain control module 4 transmits 64 as a gain parameter to the amplification module 21.

[0217] If the signal output by comparator 42 represents an input signal amplified by 64 times that is lower than the lower threshold, then execute S21;

[0218] If the signal output by comparator 42 represents an input signal amplified by 64 times that is higher than the upper threshold, then S22 is executed.

[0219] S21, the processor adjusts the gain level of the gain control module 4 to 256; the detector 41 amplifies the input signal by 256 times and transmits it to the comparator 42; the comparator 42 compares the amplified input signal by 256 times with the upper threshold and the lower threshold respectively;

[0220] If the signal output by comparator 42 indicates that the input signal amplified by 256 times is between the upper and lower thresholds, then the gain control module 4 transmits 256 as a gain parameter to the amplification module 21.

[0221] If the signal output by comparator 42 represents an input signal amplified by 256 times that is lower than the lower threshold, then S31 is executed; if the signal output by comparator 42 represents an input signal amplified by 256 times that is higher than the upper threshold, then S32 is executed.

[0222] S22, the processor adjusts the gain level of the gain control module 4 to 16; the detector 41 amplifies the input signal by 16 times and transmits it to the comparator 42; the comparator 42 compares the amplified input signal by 16 times with the upper threshold and the lower threshold respectively;

[0223] If the signal output by comparator 42 represents an input signal amplified by 16 times that is between the upper and lower thresholds, then the gain control module 4 transmits 16 as a gain parameter to the amplification module 21.

[0224] If the signal output by comparator 42 represents an input signal amplified 16 times that is lower than the lower threshold, then execute S41;

[0225] If the signal output by comparator 42 represents an input signal amplified by 16 times that is higher than the upper threshold, then S42 is executed.

[0226] S31, the processor adjusts the gain level of the gain control module 4 to 512; the gain control module 4 transmits 512 as a gain parameter to the amplification module 21.

[0227] S32, The processor adjusts the gain level of the gain control module 4 to 128; the gain control module 4 transmits 128 as a gain parameter to the amplification module 21.

[0228] S41, the processor adjusts the gain level of the gain control module 4 to 32; the gain control module 4 transmits 32 as a gain parameter to the amplification module 21.

[0229] S42, the processor adjusts the gain level of the gain control module 4 to 8; the detector 41 amplifies the input signal by 8 times and transmits it to the comparator 42; the comparator 42 compares the amplified input signal by 8 times with the upper limit threshold.

[0230] If the signal output by comparator 42 represents an input signal amplified by 16 times that is lower than the upper limit threshold, then the gain control module 4 transmits 16 as a gain parameter to the amplification module 21.

[0231] If the signal output by comparator 42 represents an input signal amplified by 16 times that is higher than the upper limit threshold, then S51 is executed.

[0232] S51, the processor adjusts the gain level of the gain control module 4 to 4; the gain control module 4 transmits 4 as a gain parameter to the amplification module 21.

[0233] In summary, the current detection circuit provided in this application embodiment adjusts the gain parameter of the amplification module 21 through the gain control module 4, enabling the amplification module 21 to achieve more precise gain control, improving the stability of the gain, and enhancing the adaptability of the amplification module 21. This allows the amplification module 21 to adjust the gain parameter in a timely manner according to the amplitude of the input signal, ensuring that the output signal is within a suitable dynamic range.

[0234] The following is a schematic explanation of how calibration module 8 calibrates the received signal. When the input signal reaches calibration module 8 after passing through rate adjustment module 7, it contains various types of errors, including gain error from amplification module 21, offset error from analog-to-digital converter 2, and passband attenuation from rate adjustment module 7 itself. These errors affect the accuracy and performance of the output signal to varying degrees. To improve the accuracy of the output signal, calibration module 8 needs to calibrate the received signal before outputting it. Calibration module 8 calibrates the received signal in three main ways:

[0235] (I) Offset Calibration. Even without an input signal, the output voltage of the analog-to-digital converter 2 may not be zero; this is called the offset voltage of the analog-to-digital converter 2. The magnitude of this offset voltage can be called the offset parameter. Specifically, the calibration module 8 receives the offset parameter of the analog-to-digital converter 2; performs offset calibration on the received signal based on the offset parameter; and outputs the offset-calibrated signal. This offset parameter can, for example, be obtained by the processor acquiring the signal output by the analog-to-digital converter 2 when there is no input signal. In one example, when there is no input signal, the processor acquires N consecutive signals output by the analog-to-digital converter 2; where N is a positive integer; and obtains the offset parameter of the analog-to-digital converter 2 based on the N consecutive output signals. This offset parameter can, for example, be stored in a register, and the calibration module 8 receives the offset parameter by reading the data from the register. Alternatively, the processor directly sends the offset parameter to the calibration module 8, and the calibration module 8 receives the offset parameter. The calibration module 8 performs offset calibration on the received signal, which can correct the error introduced by the analog-to-digital converter 2 when converting the input signal, thereby improving the accuracy of the detection results.

[0236] Furthermore, the received signal is offset calibrated based on the offset parameter. Specifically, this can be achieved by subtracting the received signal from the offset parameter. This method is easy to implement.

[0237] (II) Gain Calibration. The amplification module 21 may generate a gain error, meaning the amplitude of the signal actually output by the amplification module 21 deviates from the amplitude calculated based on the input signal using the set gain parameters. Specifically, the calibration module 8 receives the gain error parameters from the amplification module 21; performs gain calibration on the received signal based on the gain error parameters; and outputs the gain-calibrated signal. These gain error parameters can, for example, be obtained by the processor acquiring the signal output by the analog-to-digital converter 2 or the rate adjustment module 7 when a known input signal is received. For instance, the processor can divide the signal output by the analog-to-digital converter 2 or the rate adjustment module 7 by the known signal to obtain the actual gain parameter; and divide the set gain parameter by the actual gain parameter to obtain the gain error parameters of the amplification module 21. These gain error parameters can, for example, be stored in a register, and the calibration module 8 receives the gain error parameters of the amplification module 21 by reading the data from the register. Alternatively, the processor can directly send the gain error parameters to the calibration module 8, and the calibration module 8 receives the gain error parameters. By performing gain error calibration on the received signal, the calibration module 8 can correct the errors introduced by the amplification module 21 when amplifying the input signal, thereby improving the accuracy of the detection results.

[0238] Furthermore, the received signal is gain-calibrated based on the gain error parameter. Specifically, this can be achieved by multiplying the received signal by the gain error parameter. This method is easy to implement.

[0239] (III) Passband Compensation. When processing the input signal, the rate adjustment module 7 may exhibit periodic attenuation characteristics, resulting in passband attenuation. Specifically, the calibration module 8 receives the passband compensation parameters from the rate adjustment module 7 and performs passband compensation on the signal passing through the rate adjustment module 7 based on these parameters. These passband compensation parameters can be obtained, for example, from the passband attenuation parameters of the rate adjustment module 7 obtained by the processor, and the passband compensation parameters can be determined based on these parameters. These passband compensation parameters can be stored, for example, in a register, and the calibration module 8 receives the passband compensation parameters from the rate adjustment module 7 by reading the data from the register. Alternatively, the processor can directly send the passband compensation parameters to the calibration module 8, and the calibration module 8 receives the passband compensation parameters. By performing passband compensation on the received signal, the calibration module 8 can correct the errors introduced by the rate adjustment module 7 when processing the input signal, thereby improving the accuracy of the detection results.

[0240] This application also provides a current detection method based on the aforementioned current detection circuit. The execution entity of this method can be, for example, a metering module, a processor, or a coulomb counter. This application embodiment uses a processor as an example for illustrative purposes.

[0241] Figure 12 This is a schematic flowchart illustrating a current detection method provided in an embodiment of this application. Figure 12As shown, the method may include, for example, the following steps:

[0242] S1201, The processor obtains the detection signal output by the second processing module 3 of the current detection circuit.

[0243] refer to Figure 3 The current detection circuit shown includes a first processor module 1 receiving an input signal of a first amplitude and increasing the amplitude of the input signal to a second amplitude; the first processing module 1 transmitting the input signal of the second amplitude to an analog-to-digital converter 2; the analog-to-digital converter 2 converting the signal of the second amplitude into a digital signal; the analog-to-digital converter 2 transmitting the digital signal of the second amplitude to a second processing module 3; and the second processing module 3 restoring the digital signal of the second amplitude to the first amplitude to obtain a detection signal.

[0244] For example, the processor can be connected to the second processing module 3. The detection signal output by the second processing module 3 can be, for example, a voltage signal, which the processor receives.

[0245] S1202 The processor obtains the current detection result based on the detection signal.

[0246] When analog-to-digital converter 2 performs analog-to-digital conversion on the second amplitude input signal, each quantization result of analog-to-digital converter 2 represents a smaller change in the actual input voltage, resulting in higher detection accuracy. The second processing module 3 restores the second amplitude digital signal to the first amplitude, obtaining a more accurate detection signal. Based on the detection signal, the processor obtains a more accurate current detection result, improving the precision of the current detection.

[0247] In summary, the current detection method provided in this application obtains the detection signal output by the second processing module 3 of the current detection circuit, and then obtains the current detection result based on the detection signal. Since the detection signal output by the second processing module 3 has high accuracy, the accuracy of the current detection result can be improved.

[0248] Figure 13 This is a schematic flowchart of another current detection method provided in an embodiment of this application. As shown in the figure, in Figure 12 Based on the examples, the current detection method will be described in detail.

[0249] S1301, The processor obtains the detection signal output by the second processing module 3 of the current detection circuit.

[0250] S1302 The processor converts the detection signal into a current signal to obtain the current detection result.

[0251] For example, the input signal received by the current detection circuit can be the voltage drop generated by the DC current passing through the shunt. The current detection circuit amplifies the voltage drop generated by the shunt, converts it into a digital signal, and then restores the amplitude of the digital signal. Thus, the amplitude of the detected signal is the same as the amplitude of the voltage drop generated by the DC current passing through the shunt. The processor, according to Ohm's law, divides the detected signal by the resistance of the shunt, converting the detected signal into a current signal, and obtains the current detection result.

[0252] S1303 The processor obtains the change in power based on the current detection results.

[0253] After receiving the current detection results, the processor can also calculate the change in power consumption in real time, helping users monitor the energy consumption of devices or systems. In battery-powered systems, the change in power consumption can also be used to estimate the battery's state, such as the remaining power.

[0254] In one example, the processor can perform time-integration based on the current detection result to obtain the change in electrical quantity. For instance, current is the change in electrical quantity over time; that is, current is the derivative of electrical quantity with respect to time. To obtain the change in electrical quantity, the current needs to be integrated over time. Through integration, the original quantity can be recovered from the derivative. If the current is in amperes and the time is in seconds, the coulomb number of the change in electrical quantity can be obtained.

[0255] S1304. The processor obtains the total change in power based on the change in power level.

[0256] By obtaining the total change in power, the processor can provide the total energy consumption of a device or system over a specific period of time. In battery-powered systems, calculating the total change in power helps estimate the remaining battery capacity.

[0257] For example, the processor can accumulate the changes in battery level to obtain the total change in battery level. That is, after obtaining each change in battery level, the processor can add the change in battery level to the current total change in battery level to obtain the updated total change in battery level.

[0258] The total charge change can be transmitted to the battery management system, which can receive the charge change data in real time, thereby monitoring the battery status and helping to dynamically adjust the charging and discharging strategy.

[0259] Alternatively, the total change in battery charge can be stored in a storage module, such as a register. Storing it in a storage module reduces the complexity of data transmission and communication overhead, and the battery management system can read the total change in battery charge when needed.

[0260] S1305, The processor detects whether the storage module is overflowing.

[0261] For example, the processor can detect whether the storage module has overflowed when reading from it, or the storage module can have an overflow flag set, which is then set to indicate an overflow to the processor. Detecting storage module overflow can improve the accuracy of recorded data.

[0262] If so, proceed to step S1306.

[0263] S1306, The processor clears at least a portion of the data on the total power change in the storage module.

[0264] For example, when a processor detects a memory module overflow, it can clear all data in the memory module, thus increasing storage space; or it can clear only some data in the memory module, such as clearing the already read power change from the total power change data, while keeping the unread power change data. This ensures that each read operation continues from where the last read ended, avoiding data loss or duplicate reads.

[0265] The processor can subtract the previously read total battery change from the current total battery change. If the current total battery change has not been read, the processor latches the current total battery change and does not perform accumulation.

[0266] Furthermore, the processor can count the number of times the accumulation is performed, obtaining a count value. If the count value reaches a preset value, it is confirmed that the storage capacity of the storage module is insufficient. When the storage module overflows, the accumulated count corresponding to the already read power change amount can also be cleared from the current count value.

[0267] In one example, a coulomb counter can integrate up to n received signals to obtain the total change in electrical charge; for example, n can be 256. A counter records the number of integrations; the number of integrations can be stored in a first register, and the integration result can be stored in a second register. The current number of integrations can be obtained by reading the first register; the real-time total change in electrical charge measured by the coulomb counter can be read by reading the second register. The second register can be, for example, a 24-bit register. During reading, the values ​​of the first and second registers are latched to prevent the values ​​in the registers from accumulating during the reading process.

[0268] The coulomb counter clear instruction can clear the counter's count value and the coulomb counter's accumulated value up to the last read. However, the accumulated coulomb counter value and the counter's count value between the last read and receiving the clear instruction need to be retained and continue to accumulate. For example, the processor can read the coulomb counter's accumulated value and the counter's count value between two detection signals or within one detection signal cycle.

[0269] Furthermore, the coulomb counter clear instruction can subtract the most recently read value. After the coulomb counter clear instruction is completed, the latched read value is cleared, meaning that a read instruction needs to be sent again before the next coulomb counter clear instruction.

[0270] The following example illustrates how to clear the counter's count value and the coulomb counter's accumulated value up to the last read.

[0271] For example, the processor can use a counter to count the number of times the count is accumulated. For instance, an 8-bit counter can have a maximum count of 255. This value can be preset to 255. When the counter reaches 255, it indicates that the storage capacity of the memory module is insufficient. For example, at this point, the total change in stored power in the memory module is M1.

[0272] For example, if the count value when the storage module was last read was 200, and the total power change stored in the storage module was M2, subtracting the count value from the previous read value from the current count value updates the count value to 55. Subtracting the previous read value from the current total power change stored in the storage module updates the total power change stored in the storage module to M1-M2. If the difference between the current count value and the previous read value is a preset value, it is determined that the current total power change has not been read. For example, if the count value when the storage module was last read was 0, and the current count value is 255, it is determined that the current total power change has not been read.

[0273] In another example, the processor can also determine that the storage module has insufficient storage capacity when the counter overflows.

[0274] For example, an 8-bit counter with a maximum count of 255 will return to zero when incremented by one, i.e., after counting 257 times, generating an overflow signal. Upon receiving this overflow signal, the processor confirms that the memory module's storage capacity is insufficient.

[0275] When the storage module overflows, the maximum count of the counter can be subtracted from the count value at the time of the last read of the storage module. The maximum count of the 8-bit counter is 256. For example, if the count value at the time of the last read of the storage module was 200, subtracting the count value at the time of the last read of the storage module from the maximum count will update the count value to 56.

[0276] In summary, the current detection method provided in this application obtains the detection signal output by the second processing module 3 of the current detection circuit, and then obtains the current detection result based on the detection signal. Since the detection signal output by the second processing module 3 has high accuracy, the accuracy of the current detection result can be improved. Based on the current detection result, the change in electrical quantity is obtained, which can further improve the detection accuracy of the change in electrical quantity.

[0277] Figure 14 This is a flowchart illustrating the third current detection method provided in an embodiment of this application. Figure 14 As shown,

[0278] S1401, The processor acquires the offset parameters of the analog-to-digital converter 2 of the current detection circuit and sends them to the calibration module 8 of the current detection circuit, so that the calibration module 8 performs offset calibration on the received signal according to the offset parameters.

[0279] The processor acquires the offset parameters of analog-to-digital converter 2, providing a calibration basis for offset calibration by calibration module 8. This improves the accuracy and stability of the detection signal.

[0280] For example, the processor can send a calibration command to the analog-to-digital converter 2, causing the converter to enter calibration mode. The processor can obtain the offset parameter of the converter by acquiring the deviation between the actual output signal and the theoretical signal. This offset parameter can be sent to the calibration module 8, for example, stored in the register of the calibration module 8; subsequently, when the converter 2 is operating normally, the calibration module 8 can perform offset calibration on the received signal based on the received offset parameter.

[0281] When there is no input signal, the processor can acquire N consecutive signals output by analog-to-digital converter 2, where N is a positive integer; based on the N consecutive output signals, the offset parameters of analog-to-digital converter 2 can be obtained. By acquiring N consecutive signals, the accuracy of the offset parameters can be improved.

[0282] The processor can perform calculations on N continuously output signals, such as calculating the mean or root mean square error of the N signals, to obtain the offset parameters of analog-to-digital converter 2.

[0283] Furthermore, the processor averages the N consecutively output signals to obtain the offset parameters of analog-to-digital converter 2. This method is simple to implement.

[0284] S1402, The processor obtains the gain error parameters of the amplification module 21 of the current detection circuit and sends them to the calibration module 8 of the current detection circuit so that the calibration module 8 can perform gain calibration on the received signal according to the gain error parameters.

[0285] The processor obtains the gain error parameters of the amplification module 21, providing a calibration basis for the calibration module 8 to perform gain calibration. This improves the accuracy and stability of the detected signal.

[0286] For example, the processor obtains the gain error parameter of the amplification module 21 based on the set gain parameter and the actual gain parameter; wherein the actual gain parameter is obtained based on the actual output signal of the amplification module 21 under the set gain parameter. For example, a known signal can be input to the current detection circuit, and the amplification module 21 detects the signal after amplification under the set gain parameter to obtain the actual output signal. The actual output signal divided by the input known signal yields the actual gain parameter. The processor obtains the gain error parameter of the amplification module 21 based on the deviation between the set gain parameter and the actual gain parameter. This gain error parameter can be sent to the calibration module 8, for example, stored in the register of the calibration module 8, and then the calibration module 8 can perform gain calibration on the received signal based on the received gain error parameter.

[0287] Specifically, the processor can divide the set gain parameter by the actual gain parameter to obtain the gain error parameter of the amplification module 21. Then, the calibration module 8 can multiply the received signal by the gain error parameter to perform gain calibration on the signal.

[0288] S1403, The processor obtains the passband compensation parameters of the rate adjustment module 7 of the current detection circuit and sends them to the calibration module 8 of the current detection circuit, so that the calibration module 8 performs passband compensation on the received signal according to the passband compensation parameters.

[0289] The passband compensation parameters acquired by the processor's rate adjustment module 7 provide a calibration basis for the calibration module 8 to perform passband compensation, thereby improving the accuracy and stability of the detection signal.

[0290] In one example, the processor can obtain the passband attenuation parameters of the rate adjustment module 7; and determine the passband compensation parameters based on the passband attenuation parameters.

[0291] For example, the processor can obtain the passband attenuation parameters by simulating or theoretically calculating the frequency response of the rate adjustment module 7 within the passband. By obtaining the passband attenuation parameters, the frequency range and attenuation amount requiring compensation can be identified. Based on the passband compensation parameters, the parameters of the compensation filter can be designed in the calibration module 8. For example, when the compensation filter is an FIR filter, the order, passband width, and stopband attenuation of the compensation filter can be designed to compensate for the passband attenuation of the rate adjustment module, thereby improving the accuracy of the detection data. These compensation parameters can be sent to the calibration module 8, for example, stored in the register of the calibration module 8. Then, the calibration module 8 can perform passband compensation on the received signal based on the received compensation parameters.

[0292] In summary, the current detection method provided in this application embodiment can improve the accuracy of the output signal by calibrating the received signal through the calibration module 8 of the current detection circuit by obtaining the calibration parameters of the current detection circuit.

[0293] This application also provides a battery management chip, including a current detection circuit.

[0294] This application also provides a battery system, including a battery management chip and a battery pack.

[0295] Optionally, the battery system includes a coulomb counter.

[0296] Coulomb counters calculate power consumption by integrating the current flowing through a circuit. Typically, a coulomb counter receives a voltage value, converts it to a current value, and then integrates it over time. This voltage value must be the input voltage. To improve current detection accuracy, related current detection circuits often increase the amplitude of the input signal and then perform analog-to-digital conversion (ADC) on this increased signal. This reduces the amount of change in the actual input voltage represented by each quantization result of the ADC. However, this method essentially alters the output voltage value, leading to a mismatch between current detection and coulomb counter measurement requirements. This proposed solution improves current detection accuracy by first increasing the amplitude of the input signal, then converting the analog signal to a digital signal. Finally, it restores the digital signal to a voltage with the same amplitude as the input signal, making it well-suited for coulomb counters and easy to integrate.

[0297] This application also provides a transportation device, including a battery system.

[0298] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A current detection circuit, characterized in that, include: The first processing module (1) receives an input signal of a first amplitude and increases the amplitude of the input signal to a second amplitude. An analog-to-digital converter (2) is connected to the first processing module (1) and is used to convert the output signal of the first processing module (1) into a digital signal. The second processing module (3) is connected to the analog-to-digital converter (2) and is used to restore the amplitude of the output signal of the analog-to-digital converter (2) to the first amplitude to obtain a detection signal; the detection signal is used to obtain the current detection result.

2. The current detection circuit according to claim 1, characterized in that, The first processing module (1) includes: an amplification module (21) and a gain control module (4); The amplification module (21) is connected to the gain control module (4) and the analog-to-digital converter (2); The amplification module (21) is used to amplify the input signal according to the gain parameter so that the amplitude of the amplified input signal is the second amplitude, and transmit the signal with the second amplitude to the analog-to-digital converter (2); The gain control module (4) is used to adjust the gain parameter of the amplification module (21) according to the first amplitude.

3. The current detection circuit according to claim 2, characterized in that, The second processing module (3) includes: a divider (32); The divider (32) is connected to the analog-to-digital converter (2) and is used to divide the signal output by the analog-to-digital converter (2) by the gain parameter in order to restore the amplitude of the output signal of the analog-to-digital converter (2) to the first amplitude.

4. The current detection circuit according to claim 1, characterized in that, The first processing module (1) includes: an addition module (25); The addition module (25) is connected to the analog-to-digital converter (2) and is used to sum the input signal with a preset amplitude to increase the amplitude of the input signal to the second amplitude, and transmit the signal of the second amplitude to the analog-to-digital converter (2).

5. The current detection circuit according to claim 4, characterized in that, The second processing module (3) includes: a subtraction module (35); The subtraction module (35) is connected to the analog-to-digital converter (2) and is used to calculate the difference between the signal output by the analog-to-digital converter (2) and the preset amplitude, so as to restore the amplitude of the signal output by the analog-to-digital converter (2) to the first amplitude.

6. The current detection circuit according to claim 1, characterized in that, The current detection circuit further includes: a metering module (9); The metering module (9) is connected to the second processing module (3) and is used to measure the power of the detection signal.

7. The current detection circuit according to claim 2, characterized in that, The gain control module (4) includes: a detector (41) and a comparator (42); The input terminal of the detector (41) receives the input signal and is used to detect the voltage of the input signal; The first input terminal of the comparator (42) is connected to the output terminal of the detector (41), the second input terminal is connected to the reference voltage, and the output terminal is connected to the amplification module (21). The comparator (42) is used to output the gain parameter of the amplification module (21) based on the voltage comparison result between the input signal and the reference voltage.

8. The current detection circuit according to claim 2, characterized in that, The first processing module (1) further includes: a reference module (22); The reference module (22) is connected to the input terminal of the amplification module (21) and is used to provide a reference level for the input signal.

9. The current detection circuit according to claim 1, characterized in that, The current detection circuit further includes: an input chopper module (5) and an output chopper module (6); The input chopper module (5) is located at the input end of the first processing module (1); The output chopper module (6) is disposed between the first processing module (1) and the second processing module (3); The input chopper module (5) is used to increase the frequency of the input signal and transmit the increased frequency input signal to the first processing module (1); The output chopper module (6) is used to reduce the frequency of the received signal and output the signal after the frequency reduction.

10. The current detection circuit according to claim 9, characterized in that, The input chopper module (5) includes: a first switch (S1), a second switch (S2), a third switch (S3), and a fourth switch (S4); the input signal includes: a first input signal and a second input signal; The first switch (S1) is connected between the first input signal and the first input terminal of the first processing module (1); the second switch (S2) is connected between the first input signal and the second input terminal of the first processing module (1); the third switch (S3) is connected between the second input signal and the first input terminal of the first processing module (1); and the fourth switch (S4) is connected between the second input signal and the second input terminal of the first processing module (1). The first switch (S1) and the fourth switch (S4) have the same switching state, the first switch (S1) and the second switch (S2) have opposite switching states, and the first switch (S1) and the third switch (S3) have opposite switching states.

11. The current detection circuit according to claim 9, characterized in that, The output chopper module (6) includes: a fifth switch (S5), a sixth switch (S6), a seventh switch (S7), and an eighth switch (S8); The fifth switch (S5) is connected between the first output terminal of the first processing module (1) and the first input terminal of the analog-to-digital converter (2); the sixth switch (S6) is connected between the first output terminal of the first processing module (1) and the second input terminal of the analog-to-digital converter (2); the seventh switch (S7) is connected between the second output terminal of the first processing module (1) and the first input terminal of the analog-to-digital converter (2); and the eighth switch (S8) is connected between the second output terminal of the first processing module (1) and the second input terminal of the analog-to-digital converter (2). The fifth switch (S5) and the eighth switch (S8) have the same switching state, the fifth switch (S5) and the sixth switch (S6) have opposite switching states, and the fifth switch (S5) and the seventh switch (S7) have opposite switching states.

12. The current detection circuit according to any one of claims 1 to 11, characterized in that, The current detection circuit further includes: a rate adjustment module (7); The rate adjustment module (7) is disposed between the analog-to-digital converter (2) and the second processing module (3); The rate adjustment module (7) is used to adjust the rate of the received signal before outputting it.

13. The current detection circuit according to claim 12, characterized in that, The rate adjustment module (7) includes: a decimator (71), a first filter (72), and a second filter (76); The extractor (71) is used to reduce the rate of the received signal before outputting it. The first filter (72) is disposed at the input end of the extractor (71) to suppress high-frequency noise; The second filter (76) is located at the output of the extractor (71) to suppress high-frequency noise.

14. The current detection circuit according to claim 13, characterized in that, The first filter (72) includes at least one cascaded integrator (73); the second filter (76) includes at least one cascaded comb filter (77).

15. The current detection circuit according to claim 14, characterized in that, The integrator (73) includes: an adder (74) and a first delay unit (75); The comb filter (77) includes: a subtractor (78) and a second delay unit (79); The output of the adder (74) is connected to the input of the adder (74) through the first delay unit (75); The first input terminal of the subtractor (78) is connected to the second input terminal of the subtractor (78) through the second delay unit (79).

16. The current detection circuit according to any one of claims 1 to 11, characterized in that, The current detection circuit further includes: a calibration module (8); The calibration module (8) is disposed between the analog-to-digital converter (2) and the second processing module (3); The calibration module (8) is used to calibrate the received signal and then output it.

17. A current detection method, based on the current detection circuit as described in any one of claims 1 to 16, characterized in that, include: Obtain the detection signal output by the second processing module (3) of the current detection circuit; The current detection result is obtained based on the detection signal.

18. A battery management chip, characterized in that, include: The current detection circuit as described in any one of claims 1 to 16.

19. A battery system, characterized in that, include: The battery management chip as described in claim 18, and the battery pack.

20. The battery system according to claim 19, characterized in that, The battery system includes: a coulomb counter.

21. A transportation device, characterized in that, include: The battery system as described in claim 19 or 20.

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