Overcurrent detection circuit, method, battery management chip, battery system and device

Abstract

Embodiments of the present application provide an overcurrent detection circuit, method, battery management chip, battery system and device. The overcurrent detection circuit comprises: an overcurrent detection module configured to receive an input signal and perform overcurrent detection on the received signal; and a timing module connected to the overcurrent detection module and configured to generate a state signal according to a duration of a single overcurrent detected by the overcurrent detection module; the state signal is used to represent whether overcurrent occurs. The method is used to improve the accuracy of the overcurrent detection result.

Description

Technical Field

[0001] This application relates to overcurrent detection technology, and more particularly to an overcurrent detection circuit, method, battery management chip, battery system, and device. Background Technology

[0002] Overcurrent detection is crucial in battery management systems (BMS), playing a key role in ensuring stable battery performance, improving safety, and extending battery life. By detecting overcurrent anomalies, the BMS can promptly identify them, allowing for dynamic adjustments to the charging and discharging currents to prevent battery damage from overcurrent.

[0003] Currently, an analog comparator is used to compare the input signal with an overcurrent threshold, and an overcurrent is detected when the input signal exceeds the overcurrent threshold. This method suffers from inaccurate overcurrent detection results. Summary of the Invention

[0004] This application provides an overcurrent detection circuit, method, battery management chip, battery system, and device to improve the accuracy of overcurrent detection results.

[0005] In a first aspect, embodiments of this application provide an overcurrent detection circuit, including:

[0006] The overcurrent detection module (91) receives the input signal and is used to perform overcurrent detection on the received signal;

[0007] The timing module (94) is connected to the overcurrent detection module (91) and is used to generate a status signal based on the duration of a single overcurrent detected by the overcurrent detection module (91); the status signal is used to characterize whether there is an overcurrent.

[0008] Optionally, the timing module (94) includes: a delay filter (95) and a result module (96);

[0009] The delay filter (95) is connected to the overcurrent detection module (91) and is used to time the duration of a single overcurrent pulse output by the overcurrent detection module (91).

[0010] The result module (96) is connected to the delay filter (95) and is used to generate a state signal characterizing the overcurrent when the timing result of the delay filter (95) reaches a preset overcurrent duration.

[0011] Optionally, the delay filter (95) includes: a first counter (97) and a first register (98);

[0012] The first counter (97) is connected to the first register (98) and the result module (96) and is used to time the duration of a single overcurrent pulse output by the overcurrent detection module (91) according to the timing duration stored in the first register (98).

[0013] Optionally, the delay filter (95) includes: a first counter (97) and a first register (98);

[0014] The first counter (97) is connected to the first register (98), the result module (96), and the overcurrent detection module (91), and is used to time the duration of a single overcurrent pulse output by the overcurrent detection module (91) according to the overcurrent duration corresponding to the first register (98).

[0015] Optionally, the overcurrent detection module (91) includes: an analog comparator (93);

[0016] The analog comparator (93) is connected to the timing module (94) and is used to output an overcurrent pulse to the timing module (94) if the received signal exceeds the set overcurrent threshold.

[0017] Optionally, the overcurrent detection module (91) further includes: a second register (90) and a multiplexer (99);

[0018] The multiplexer (99) is connected to the second register (90) and the analog comparator (93);

[0019] The second register (90) is used to store the gear position indication signal; the multiplexer (99) is used to select and output the corresponding overcurrent threshold from multiple overcurrent thresholds according to the gear position indication signal and output it to the analog comparator (93).

[0020] Optionally, the overcurrent detection module (91) includes: an analog-to-digital converter (2) and a digital comparator (13);

[0021] The analog-to-digital converter (2) receives the input signal and converts the input signal into a digital signal;

[0022] The digital comparator (13) is connected to the analog-to-digital converter (2) and the timing module (94). If the received signal exceeds the set overcurrent threshold, it outputs a first-state overcurrent signal to the timing module (94); if the received signal does not exceed the set overcurrent threshold, it outputs a second-state overcurrent signal to the timing module (94).

[0023] Optionally, the overcurrent detection module (91) further includes:

[0024] The first processing module (1) is connected to the analog-to-digital converter (2) and is used to increase the amplitude of the first amplitude input signal to the second amplitude and transmit the second amplitude input signal to the analog-to-digital converter (2).

[0025] The second processing module (3) is connected to the analog-to-digital converter (2) and the timing module (94) and is used to restore the amplitude of the output signal of the analog-to-digital converter (2) to the first amplitude and then transmit it to the timing module (94).

[0026] Optionally, the first processing module (1) includes: an amplification module (21) and a gain control module (4);

[0027] The amplification module (21) is connected to the gain control module (4) and the analog-to-digital converter (2);

[0028] The amplification module (21) is used to amplify the input signal according to the gain parameter so that the amplitude of the amplified input signal is the second amplitude, and transmit the signal with the second amplitude to the analog-to-digital converter (2);

[0029] The gain control module (4) is used to adjust the gain parameter of the amplification module (21) according to the first amplitude.

[0030] Optionally, the second processing module (3) includes: a divider (32);

[0031] The divider (32) is connected to the analog-to-digital converter (2) and the timing module (94) and is used to divide the signal output by the analog-to-digital converter (2) by the gain parameter so as to restore the signal output by the analog-to-digital converter (2) and output it to the timing module (94).

[0032] Optionally, the overcurrent detection circuit further includes: an overcurrent logic module (17);

[0033] The overcurrent logic module (17) is connected to the timing module (94) and is used to receive the status signal output by the timing module (94) and convert it into an overcurrent output signal.

[0034] Optionally, the overcurrent detection circuit further includes: an output enable module (18);

[0035] The output enable module (18) is connected to the overcurrent logic module (17) and is used to control whether to output the overcurrent output signal.

[0036] Optionally, the overcurrent detection circuit further includes: a status indication module (19);

[0037] The status indication module (19) is connected to the timing module (94) and is used to indicate the overcurrent status according to the status signal output by the timing module (94).

[0038] In a second aspect, embodiments of this application provide an overcurrent detection method based on an overcurrent detection circuit as described in any of the first aspects, comprising: acquiring a status signal output by a timing module (94) of the overcurrent detection circuit;

[0039] The overcurrent detection result is obtained based on the status signal.

[0040] Thirdly, embodiments of this application provide a battery management chip, including: an overcurrent detection circuit as described in any of the first aspects.

[0041] Fourthly, embodiments of this application provide a battery system, including a battery management chip as described in the third aspect, and a battery pack.

[0042] Fifthly, embodiments of this application provide a transportation device including the battery system described in the fourth aspect.

[0043] The overcurrent detection circuit, method, battery management chip, battery system, and device provided in this application embodiment perform overcurrent detection on the received signal through an overcurrent detection module 91; and generate a status signal representing whether an overcurrent has occurred based on the duration of a single overcurrent detected by the overcurrent detection module 91 through a timing module 94, replacing the overcurrent detection module 91's immediate confirmation of overcurrent upon detection. This avoids the problem of misjudgment caused by glitches when the overcurrent detection module 91 performs overcurrent detection on the received signal, thus improving the accuracy of the detection results. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0045] Figure 1 This is a schematic diagram of a scenario involved in an embodiment of this application;

[0046] Figure 2 This is a schematic diagram of an overcurrent detection circuit provided in an embodiment of this application;

[0047] Figure 3 This is a schematic diagram of another overcurrent detection circuit provided in an embodiment of this application;

[0048] Figure 4 This is a schematic diagram of the structure of the third overcurrent detection circuit provided in the embodiments of this application;

[0049] Figure 5This is a schematic diagram of the structure of the fourth overcurrent detection circuit provided in the embodiments of this application;

[0050] Figure 6 This is a schematic diagram of the structure of the fifth overcurrent detection circuit provided in the embodiments of this application;

[0051] Figure 7 This is a schematic diagram of the sixth overcurrent detection circuit provided in the embodiments of this application;

[0052] Figure 8 This is a schematic diagram of the structure of a chopper module provided in an embodiment of this application;

[0053] Figure 9 This is a schematic diagram of the structure of a rate adjustment module provided in an embodiment of this application;

[0054] Figure 10 This is a schematic diagram of the structure of a gain control module provided in an embodiment of this application;

[0055] Figure 11 A schematic flowchart illustrating the output gain parameters of a gain control module provided in an embodiment of this application;

[0056] Figure 12 A flowchart illustrating an overcurrent detection method provided in an embodiment of this application;

[0057] Figure 13 A flowchart illustrating another overcurrent detection method provided in this application embodiment;

[0058] Figure 14 This is a flowchart illustrating the third overcurrent detection method provided in this application embodiment.

[0059] Explanation of reference numerals in the attached figures:

[0060] 1: First processing module; 13: Digital comparator; 17: Overcurrent logic module; 18: Output enable module; 19: Status indicator module; 2: Analog-to-digital converter; 21: Amplifier module; 22: Reference module; 3: Second processing module; 31: Restore module; 32: Divider; 4: Gain control module; 41: Detector; 42: Comparator; 5: Input chopper module; 51: First switch module; 6: Output chopper module; 61: Second switch module; 7: Rate adjustment module; 71: Decimator; 72: First filter; 73: Integrator; 74: Adder; 75: ... 76: Delay unit; 77: Second filter; 78: Comb filter; 79: Subtractor; 8: Calibration module; 90: Second register; 91: Overcurrent detection module; 92: Decision module; 93: Analog comparator; 94: Timing module; 95: Delay filter; 96: Result module; 97: First counter; 98: First register; 99: Multiplexer; S1: First switch; S2: Second switch; S3: Third switch; S4: Fourth switch; S5: Fifth switch; S6: Sixth switch; S7: Seventh switch; S8: Eighth switch.

[0061] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0062] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0063] Figure 1 This is a schematic diagram of a scenario involved in an embodiment of this application, such as... Figure 1 As shown, the specific application scenario of this application is to detect whether the battery is experiencing overcurrent.

[0064] Overcurrent detection is of great importance in battery management systems, as it plays a key role in ensuring stable battery performance, improving safety, and extending battery life.

[0065] Excessive current during charging can damage the internal electrode materials of the battery, affecting its capacity and lifespan. Overcurrent detection allows for adjustment of the charging current, ensuring it remains within a safe range and guaranteeing a proper charging process.

[0066] During discharge, excessive current can cause unstable battery output voltage, affecting the normal operation of the equipment. Overcurrent detection can monitor the discharge current in real time. Once an overcurrent condition is detected, measures can be taken to reduce the load or disconnect the circuit to maintain a stable battery discharge state.

[0067] In electric vehicles, by performing overcurrent detection, the battery management system can also quickly disconnect the battery from the drive system when overcurrent occurs due to short circuits or overloads, thus protecting the safety of the vehicle and its passengers.

[0068] Existing overcurrent detection circuits convert the battery's current signal into an analog voltage signal through a sampling resistor. An analog comparator then compares the analog voltage signal with an overcurrent threshold. If the analog voltage signal exceeds the overcurrent threshold, an overcurrent is confirmed.

[0069] Because the battery current may be affected by electromagnetic interference, switching noise, or current spikes, causing glitches, the analog comparator may erroneously output a signal indicating overcurrent, mistakenly confirming that an overcurrent has occurred. This results in inaccurate overcurrent detection.

[0070] In conclusion, improving the accuracy of overcurrent detection has become an urgent problem to be solved.

[0071] In view of this, this application provides an overcurrent detection circuit that confirms an overcurrent only when the duration of a single overcurrent detected by the overcurrent detection module exceeds a certain duration. This replaces the method where the overcurrent detection module confirms an overcurrent simply by detecting an overcurrent. This avoids the problem of misjudgment caused by glitches when the overcurrent detection module performs overcurrent detection on the received signal, thus improving the accuracy of the detection results.

[0072] The overcurrent detection circuit provided in this application embodiment can be used to detect overcurrent in vehicles, and can also be used to detect overcurrent in any electrical device or energy storage element.

[0073] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0074] Figure 2 This is a schematic diagram of an overcurrent detection circuit provided in an embodiment of this application, as shown below. Figure 2 As shown, it includes: an overcurrent detection module 91 and a timing module 94;

[0075] The overcurrent detection module 91 can be any module capable of performing overcurrent detection on the received signal. For example, it can be a module that can directly perform overcurrent detection on the received analog signal; or it can be a module that first converts the received analog signal into a digital signal and then performs overcurrent detection on the digital signal.

[0076] The timing module 94 can be any module capable of measuring and recording the duration of a signal. For example, it can include any of the following: a counter, a timer, etc.

[0077] The overcurrent detection module 91 receives input signals and is used to perform overcurrent detection on the received signals.

[0078] The timing module 94, connected to the overcurrent detection module 91, is used to generate a status signal based on the duration of a single overcurrent detected by the overcurrent detection module 91; the status signal is used to characterize whether an overcurrent has occurred.

[0079] For example, the overcurrent detection module 91 can preset an overcurrent threshold. For instance, if the received signal is less than the overcurrent threshold, the input current can be considered to be within a safe operating range; if the received signal is greater than the overcurrent threshold, the input current can be considered to have exceeded the maximum allowable current.

[0080] The timing module 94 can preset an overcurrent duration. For example, if the duration of a single overcurrent detected by the overcurrent detection module 91 is less than the overcurrent duration, it can be considered a current spike caused by external interference, not a real overcurrent, and a state signal indicating no overcurrent is generated. If the duration of a single overcurrent detected by the overcurrent detection module 91 is greater than the overcurrent duration, it can be considered a real overcurrent event, and a state signal indicating overcurrent is generated. Therefore, based on the duration of a single overcurrent, a brief current spike can be distinguished from a real overcurrent event, thereby improving the accuracy of the overcurrent detection results.

[0081] In one example, the overcurrent detection module 91 is specifically used to output an overcurrent pulse if an overcurrent is detected; the pulse width of the overcurrent pulse represents the duration of the overcurrent. For example, the overcurrent detection module 91 outputs a low-level signal when no overcurrent is detected; outputs a high-level signal when an overcurrent is detected; and outputs a low-level signal when the overcurrent state returns to the non-overcurrent state. Thus, the overcurrent detection module 91 outputs a high-level pulse signal when an overcurrent is detected.

[0082] The timing module 94 is specifically used to generate a status signal based on the pulse width of the overcurrent pulse. Since the pulse width of the overcurrent pulse characterizes the duration of the overcurrent, a narrow pulse width can be considered a current spike, possibly caused by external interference; a wide pulse width can be considered a genuine overcurrent event. Therefore, based on the pulse width of the overcurrent pulse, a brief current spike can be distinguished from a genuine overcurrent event, thereby improving the accuracy of overcurrent detection results.

[0083] In another example, the overcurrent detection module 91 can output an overcurrent signal, which indicates whether the overcurrent detection module 91 has detected an overcurrent; the overcurrent signal can be, for example, a digital signal. For example, if the overcurrent detection module 91 detects an overcurrent, it can output an overcurrent signal in a first state; if the overcurrent detection module 91 does not detect an overcurrent, it can output an overcurrent signal in a second state; the duration of the overcurrent signal in the first state indicates the duration of the overcurrent. For example, the overcurrent signal in the first state can be represented by 1, and the overcurrent signal in the second state can be represented by 0.

[0084] The timing module 94 is specifically used to generate a status signal based on the duration of the overcurrent signal. Since the duration of the overcurrent signal in the first state characterizes the duration of the overcurrent, a short duration can be considered a current spike, possibly caused by external interference; a longer duration can be considered a genuine overcurrent event. Therefore, based on the duration of the overcurrent signal, a brief current spike can be distinguished from a genuine overcurrent event, thereby improving the accuracy of the overcurrent detection results.

[0085] The signal processing procedure for overcurrent detection current can be illustrated as follows:

[0086] The overcurrent detection module 91 receives the input signal and performs overcurrent detection on the received signal. The timing module 94 generates a status signal indicating overcurrent when the duration of a single overcurrent detected by the current detection module 91 exceeds a certain duration; conversely, it generates a status signal indicating no overcurrent when the duration of a single overcurrent detected by the current detection module 91 does not reach the certain duration. This avoids glitches in the output signal of the overcurrent detection module 91 being mistakenly identified as overcurrent, leading to inaccurate overcurrent detection results. This improves the accuracy of overcurrent detection results. When a current instantaneously overcurrent occurs, the timing module 94 can observe the current change trend within a certain time. If the current recovers to the normal range within a short time, the overcurrent protection action is not triggered, thereby improving the system's reliability.

[0087] In summary, the overcurrent detection circuit provided in this application embodiment performs overcurrent detection on the received signal through the overcurrent detection module 91; and generates a status signal representing whether an overcurrent has occurred based on the duration of a single overcurrent detected by the overcurrent detection module 91 through the timing module 94, replacing the overcurrent detection module 91's method of confirming the occurrence of an overcurrent upon detection. This avoids the problem of misjudgment caused by glitches when the overcurrent detection module 91 performs overcurrent detection on the received signal, thus improving the accuracy of the detection results.

[0088] Figure 3 This is a schematic diagram of another overcurrent detection circuit provided in an embodiment of this application. Figure 3 As shown, in this embodiment... Figure 2 Based on the embodiments, the overcurrent detection circuit will be described in detail.

[0089] In one example, the overcurrent detection module 91 is specifically used to output an overcurrent pulse if an overcurrent is detected; the pulse width of the overcurrent pulse represents the duration of the overcurrent. The timing module 94 is specifically used to generate a status signal based on the pulse width of the overcurrent pulse.

[0090] The overcurrent detection module 91 may include: an analog comparator 93;

[0091] Analog comparator 93 can be, for example, any device that can compare the magnitudes of two analog voltage signals and output a digital signal indicating which signal has a higher input voltage. For instance, analog comparator 93 may include two inputs: a positive input (also called a non-inverting input) and a negative input (also called an inverting input); these two inputs receive two analog voltage signals to be compared. The output is typically a digital signal representing the comparison result: a high level when the positive input voltage is higher than the negative input voltage, and a low level when the positive input voltage is lower than the negative input voltage.

[0092] Analog comparator 93 is used to output an overcurrent pulse if the received signal exceeds a set overcurrent threshold.

[0093] For example, the overcurrent threshold can be stored in a register, and the analog comparator 93 can receive the overcurrent threshold by reading the value of the register; or, the input of the analog comparator 93 can be connected to a reference voltage to receive the overcurrent threshold.

[0094] In one example, analog comparator 93 can receive an input signal through its positive input terminal and an overcurrent threshold through its negative input terminal. When the received signal exceeds the set overcurrent threshold, analog comparator 93 can output a high-level signal; when the received signal does not exceed the set overcurrent threshold, analog comparator 93 can output a low-level signal. Thus, when the received signal exceeds the set overcurrent threshold, an overcurrent pulse is output.

[0095] In another example, analog comparator 93 can receive an input signal through its negative input terminal and an overcurrent threshold through its positive input terminal. When the received signal exceeds the set overcurrent threshold, analog comparator 93 can output a low-level signal; when the received signal does not exceed the set overcurrent threshold, analog comparator 93 can output a high-level signal. Thus, an overcurrent pulse is output when the received signal exceeds the set overcurrent threshold. This embodiment illustrates the example where analog comparator 93 outputs a high-level signal when the received signal exceeds the set overcurrent threshold and a low-level signal when the received signal does not exceed the set overcurrent threshold.

[0096] The timing module 94 is used to time the duration of a single overcurrent pulse output by the overcurrent detection module 91, and to generate a status signal characterizing the overcurrent when the timing result reaches the preset overcurrent duration.

[0097] For example, the timing module 94 can trigger timing at the start time of the output of a single overcurrent pulse by the overcurrent detection module 91, record the duration of the single overcurrent pulse, and if the overcurrent pulse maintains the overcurrent state, the timing will stop when the timing result reaches the preset overcurrent duration, and the timing module 94 will generate a status signal characterizing the overcurrent.

[0098] Alternatively, the timing module 94 can trigger timing at the start of a single overcurrent pulse output by the overcurrent detection module 91, record the duration of the single overcurrent pulse, and if the state of the overcurrent pulse flips before the preset overcurrent duration is reached, the timing module 94 is triggered to stop timing. The timing module 94 generates a state signal indicating that no overcurrent has occurred.

[0099] Alternatively, the timing module 94 can trigger timing at the start of the output of a single overcurrent pulse from the overcurrent detection module 91, and stop timing when the timing result reaches the preset overcurrent duration. At the moment the timing stops, the timing module 94 will check the status of the signal output by the overcurrent detection module 91 again. If the signal output by the overcurrent detection module 91 is an overcurrent pulse, the timing module 94 will generate a status signal indicating overcurrent. If the signal output by the overcurrent detection module 91 is a non-overcurrent pulse, the timing module 94 will generate a status signal indicating no overcurrent.

[0100] Furthermore, the timing module 94 is also used to reset after the overcurrent pulse ends. The timing module 94 can continue to monitor and respond to new overcurrent pulses.

[0101] Furthermore, the timing module 94 may include a delay filter 95 and a result module 96.

[0102] The delay filter 95 can be any device capable of delaying the output of a received signal. For example, it can include any of the following: a shift register, a first-in-first-out buffer, etc. The result module 96 can be any module capable of triggering the output of a high-level or low-level signal based on the timing result. The delay filter 95 is used to time the duration of a single overcurrent pulse output by the overcurrent detection module 91; the result module 96, connected to the delay filter 95, is used to generate a status signal characterizing the overcurrent when the timing result of the delay filter 95 reaches a preset overcurrent duration.

[0103] In one example, the delay filter 95 triggers timing when it receives an overcurrent pulse and stops timing when it receives a non-overcurrent pulse. If the timing result reaches the preset overcurrent duration, the result module 96 is triggered to generate a status signal representing the overcurrent; if the timing result does not reach the preset overcurrent duration, the result module 96 does not generate a status signal representing the overcurrent, or generates a status signal representing the non-overcurrent.

[0104] In another example, the delay filter 95 triggers timing when it receives an overcurrent pulse, and stops timing when the timing result reaches the preset overcurrent duration. During this period, the delay filter 95 does not detect the state of the received signal. After the timing ends, the trigger result module 96 detects the signal output by the overcurrent detection module 91. If it is an overcurrent pulse, it generates a state signal representing the overcurrent. If it is a non-overcurrent pulse, it does not generate a state signal representing the overcurrent, or it generates a non-overcurrent state signal.

[0105] For example, the delay filter 95 can preset an overcurrent duration, which can be configured in a register. The delay filter 95 obtains the preset overcurrent duration by reading the register. The delay filter 95 can adjust the overcurrent duration according to different levels of system interference. For example, when system interference is severe, the duration of interference pulses in the input signal is long, so a longer overcurrent duration can be configured for the delay filter 95; or, when system interference is low, the duration of interference pulses in the output signal is short, so a shorter overcurrent duration can be configured for the delay filter. For example, the overcurrent duration can be divided into 16 levels within the range of 0-100 milliseconds (ms), for example, the default level can be 100ms. Each level can be distinguished by encoding, with different levels encoded with different codes, and the encoded value corresponding to the overcurrent duration level is written into the register. The delay filter 95 obtains the corresponding encoded value by reading from the register. Internally, the delay filter 95 can store the correspondence between the overcurrent duration and the encoded value. Based on the encoded value read from the register, the delay filter 95 can obtain the preset overcurrent duration. The correspondence between the various overcurrent duration levels is shown in Table 1 for example:

[0106] Table 1

[0107]

[0108] When the duration of a single overcurrent pulse output by the overcurrent detection module 91 reaches the preset overcurrent duration, the timing module 94 generates a status signal representing the overcurrent, which avoids the problem of misjudgment caused by glitches when the overcurrent detection module 91 performs overcurrent detection on the received signal, and improves the accuracy of the overcurrent detection result.

[0109] In summary, the overcurrent detection circuit provided in this application embodiment performs overcurrent detection on the received signal through the overcurrent detection module 91 and outputs an overcurrent pulse; the timing module 94 generates a status signal representing whether an overcurrent has occurred based on the pulse width of the overcurrent pulse, replacing the overcurrent detection module 91 in confirming the occurrence of an overcurrent upon detection. This avoids the problem of misjudgment caused by glitches when the overcurrent detection module 91 performs overcurrent detection on the received signal, thus improving the accuracy of the detection results.

[0110] Furthermore, the overcurrent detection circuit can also output a status signal indicating whether an overcurrent has occurred to an external circuit to trigger that circuit or module to respond to the overcurrent condition. For example, the overcurrent detection circuit can output a status signal to a protection circuit, which, when the status signal indicates an overcurrent, controls the protection circuit to cut off the power supply or load, reduce motor speed, limit current, or shut down the motor, thus protecting the equipment or circuit from damage. Alternatively, the overcurrent detection circuit can output a status signal to an alarm system, triggering the alarm system's audible and visual alarms when the status signal indicates an overcurrent, to notify the user of the overcurrent situation. To match the operating level of the external circuit, the overcurrent detection circuit can perform logical processing on the status signal before outputting it.

[0111] For example, the overcurrent detection circuit may also include: an overcurrent logic module 17;

[0112] The overcurrent logic module 17 can be, for example, any module that performs logic processing on any pair of input signals. For example, it can include any of the following: AND gate, OR gate, NOT gate, Pulse Width Modulation (PWM) module, etc.

[0113] The overcurrent logic module 17 is connected to the timing module 94 and is used to receive the status signal output by the timing module 94 and convert it into an overcurrent output signal. For example, when the status signal indicates an overcurrent, the overcurrent logic module 17 can convert the received input signal into a valid output such as a high level, low level, or PWM signal, thereby controlling the external circuit for overcurrent detection to respond to the overcurrent state.

[0114] Furthermore, the overcurrent detection circuit also includes: an output enable module 18;

[0115] The output enable module 18 can be any module that is turned on based on a high-level or low-level signal, such as a transistor, a field-effect transistor (MOSFET), also known as a MOS transistor, thyristor, etc.

[0116] The output enable module 18 is connected to the overcurrent logic module 17 and is used to control whether an overcurrent output signal is output. The output enable module 18 may include, for example, a control terminal connected to an enable signal; when the enable signal is high, the overcurrent output signal output by the overcurrent logic module 17 is allowed; when the enable signal is low, the overcurrent output signal output by the overcurrent module 17 is stopped. The output enable module 18 ensures that the overcurrent output signal of the overcurrent logic module 17 is not accidentally activated during the start-up, shutdown, or fault recovery process of the overcurrent detection circuit, thereby improving system safety.

[0117] Furthermore, the overcurrent detection circuit can also indicate the current state of the system, such as whether an overcurrent has occurred.

[0118] For example, the overcurrent detection circuit also includes: a status indication module 19;

[0119] The status indication module 19 can be any module that can indicate the operating status based on the received signals. For example, it can be a flag register.

[0120] The status indication module 19 is connected to the timing module 94 and is used to indicate the overcurrent status based on the status signal output by the timing module 94. For example, when the status signal output by the timing module 94 indicates an overcurrent, the status indication module 19 changes its recorded value to indicate whether an overcurrent has occurred, and can maintain its status unchanged after an overcurrent occurs until the overcurrent status needs to be cleared. In this way, the processor can monitor the overcurrent status of the system based on the value recorded by the status indication module 19.

[0121] Furthermore, the status indication module 19 may include: a flag register;

[0122] A flag register can be a special register in the processor used to store status information, such as overcurrent status. Overcurrent status information can be represented by a flag indicating whether an overcurrent has occurred.

[0123] A flag register is used to record the overcurrent flag bit in the flag register as a first value, such as 0, when a status signal indicates an overcurrent; and to record the overcurrent flag bit in the flag register as a second value, such as 1, when the overcurrent state is cleared. In one example, when the status signal indicates an overcurrent, the overcurrent flag bit is recorded as 1. The processor can read this overcurrent flag bit to trigger a termination or perform a specific operation in response to the overcurrent event. After processing the overcurrent event, the processor can also clear the overcurrent state in the flag register. For example, the processor can send a software instruction to the flag register to clear the overcurrent flag bit, resetting the overcurrent flag bit in the flag register to 0. The flag register can continue to monitor and record new overcurrent states.

[0124] Figure 4 A schematic diagram of the third overcurrent detection circuit provided in the embodiments of this application is shown below. Figure 4 As shown, in this embodiment... Figure 3 Based on the embodiments, the overcurrent detection circuit will be described in detail.

[0125] In one example, the overcurrent detection module 91 is specifically used to output a first-state overcurrent signal if an overcurrent is detected, and a second-state overcurrent signal if no overcurrent is detected; the duration of the first-state overcurrent signal represents the duration of the overcurrent. The timing module 94 is specifically used to generate a status signal based on the duration of the overcurrent signal.

[0126] The overcurrent detection module 91 may include, for example, an analog-to-digital converter 2 and a digital comparator 13;

[0127] The analog-to-digital converter 2 can be any device that can convert analog signals into digital signals. For example, it can include any of the following: successive approximation register ADC, Δ-Σ (Delta-Sigma) ADC, flash ADC, dual-slope ADC, etc.

[0128] Digital comparator 13 can be any device capable of comparing the magnitudes of two digital signals. For example, digital comparator 13 may include two inputs: a positive input (also called a non-inverting input) and a negative input (also called an inverting input); these two inputs receive two digital voltage signals to be compared. The output is typically a digital signal representing the comparison result; the output is high when the positive input voltage is higher than the negative input voltage, and low when the positive input voltage is lower than the negative input voltage.

[0129] Analog-to-digital converter 2 receives the input signal and converts it into a digital signal;

[0130] Digital comparator 13, connected to analog-to-digital converter 2, is used to output an overcurrent signal in a first state if the received signal exceeds a set overcurrent threshold, and to output an overcurrent signal in a second state if the received signal does not exceed the set overcurrent threshold.

[0131] For example, the overcurrent threshold can be stored in a register, and the digital comparator 13 can receive the overcurrent threshold by reading the value of the register; or, the input of the digital comparator 13 can be connected to a reference voltage to receive the overcurrent threshold.

[0132] In one example, the digital comparator 13 can receive an input signal through its positive input terminal and an overcurrent threshold through its negative input terminal. In this case, the overcurrent signal in the first state can be a high-level signal, and the overcurrent signal in the second state can be a low-level signal. In another example, the digital comparator 13 can receive an input signal through its negative input terminal and an overcurrent threshold through its positive input terminal. In this case, the overcurrent signal in the first state can be a low-level signal, and the overcurrent signal in the second state can be a high-level signal. This embodiment of the application illustrates the example where the overcurrent signal in the first state is a high-level signal and the overcurrent signal in the second state is a low-level signal.

[0133] Furthermore, the overcurrent detection module 91 may also include: a first processing module 1 and a second processing module 3;

[0134] The first processing module 1 can be any module that can increase the amplitude of the input signal, such as any of the following: a fixed gain amplifier, a programmable gain amplifier, a transformer, a superimposed input signal source, etc.

[0135] The second processing module 3 can be any module that can reduce the amplitude of the input signal, such as any of the following: divider, voltage divider, transformer, or input signal source that subtracts superimposed signals.

[0136] The first processing module 1 receives an input signal of a first amplitude and uses it to increase the amplitude of the input signal to a second amplitude; the input signal may be, for example, a voltage signal, which may be obtained by converting DC current by a shunt.

[0137] Analog-to-digital converter 2, connected to the first processing module 1, is used to convert the output signal of the first processing module 1 into a digital signal;

[0138] The second processing module 3 is connected to the analog-to-digital converter 2 and is used to restore the amplitude of the output signal of the analog-to-digital converter 2 to the first amplitude.

[0139] Digital comparator 13, connected to the second processing module 3, is used to perform overcurrent detection on the received signal.

[0140] The timing module 94, connected to the digital comparator 13, generates a status signal based on the duration of the overcurrent signal. The status signal is used to characterize whether an overcurrent has occurred.

[0141] The signal processing procedure of the overcurrent detection circuit can be illustrated as follows:

[0142] The first processing module 1 receives an input signal of a first amplitude and amplifies it to a second amplitude. The first processing module 1 then transmits the second amplitude input signal to an analog-to-digital converter 2. The analog-to-digital converter 2 converts the second amplitude signal into a digital signal. The analog-to-digital converter 2 transmits the second amplitude digital signal to a second processing module 3. The second processing module 3 restores the second amplitude digital signal to the first amplitude. The second processing module 3 then transmits the restored first amplitude signal to a digital comparator 13. The digital comparator 13 performs overcurrent detection on the received signal. The timing module 94 generates a status signal based on the duration of the overcurrent signal output by the digital comparator 13. This avoids glitches in the overcurrent signal output by the digital comparator 13 being mistakenly identified as an overcurrent, leading to inaccurate overcurrent detection results. This improves the accuracy of the overcurrent detection results.

[0143] For example, if the resolution of analog-to-digital converter 2 is 0.1V and the first amplitude of the input signal is 1V, then the input signal represents 10 quantization levels, and the actual voltage corresponding to each quantization level is 0.1V. The first processing module 1 increases the amplitude of the input signal by 10 times, that is, the second amplitude is 10V. In analog-to-digital converter 2 with the same resolution, 10V can correspond to 100 quantization levels, and the voltage corresponding to each quantization level is 0.1V. This 0.1V voltage corresponds to the voltage after the actual voltage is increased by 10 times, so the actual voltage corresponding to each quantization level is 0.01V. When analog-to-digital converter 2 performs analog-to-digital conversion on the input signal with the second amplitude, the actual input voltage represented by each quantization result of analog-to-digital converter 2 changes less, and the detection accuracy is higher. The second processing module 3 restores the digital signal with the second amplitude to the first amplitude, and the signal transmitted by the second processing module 3 to the digital comparator 13 has higher accuracy. The digital comparator 13 performs overcurrent detection on the received signal, and the output overcurrent signal is more accurate. The timing module 94 generates a state signal representing whether there is an overcurrent based on the overcurrent signal more accurately. This further improves the accuracy of overcurrent detection results.

[0144] In summary, the overcurrent detection circuit provided in this application converts the input signal into a digital signal using an analog-to-digital converter 2; a digital comparator 13 performs overcurrent detection on the received signal; and a timing module 94 generates a status signal indicating whether an overcurrent has occurred based on the duration of the overcurrent signal detected by the digital comparator 13, replacing the digital comparator 13's confirmation of overcurrent upon detecting a single overcurrent event. This avoids the problem of misjudgment caused by glitches when the digital comparator 13 performs overcurrent detection on the received signal, thus improving the accuracy of the detection results. By adding a first processing module 1 before the analog-to-digital converter 2, the amplitude of the input signal is increased; the analog-to-digital converter 2 performs analog-to-digital conversion on the signal with the increased amplitude with higher accuracy; and by adding a second processing module 3 after the analog-to-digital converter 2, the amplitude of the output signal of the analog-to-digital converter 2 is restored, improving the accuracy of the output signal. The digital comparator 13 performs overcurrent detection on the received signal, and the output overcurrent signal is more accurate. The timing module 94 generates a status signal indicating whether an overcurrent has occurred more accurately based on the overcurrent signal. This further improves the accuracy of the overcurrent detection results.

[0145] Figure 5 This is a schematic diagram of the structure of the fourth overcurrent detection circuit provided in the embodiments of this application, as shown below. Figure 5 As shown, in this embodiment... Figure 4 Based on the embodiments, the overcurrent detection circuit will be described in detail.

[0146] The overcurrent detection circuit may include: an analog-to-digital converter 2, a digital comparator 13, a timing module 94, a first processing module 1, and a second processing module 3;

[0147] The first processing module 1 receives an input signal of a first amplitude and uses it to increase the amplitude of the input signal to a second amplitude; the input signal may be, for example, a voltage signal, which may be obtained by converting DC current by a shunt.

[0148] Analog-to-digital converter 2, connected to the first processing module 1, is used to convert the output signal of the first processing module 1 into a digital signal;

[0149] The second processing module 3 is connected to the analog-to-digital converter 2 and is used to restore the amplitude of the output signal of the analog-to-digital converter 2 to the first amplitude.

[0150] Digital comparator 13, connected to the second processing module 3, is used to perform overcurrent detection on the received signal.

[0151] The timing module 94, connected to the digital comparator 13, generates a status signal based on the duration of the overcurrent signal. The status signal is used to characterize whether an overcurrent has occurred.

[0152] The first processing module 2 may include, for example, an amplification module 21 and a gain control module 4; the second processing module 3 may include a divider 32.

[0153] The amplification module 21 can be any module that can amplify signals, such as a fixed gain amplifier, a programmable gain amplifier, etc.

[0154] Gain control module 4 can be any module capable of dynamically adjusting gain parameters.

[0155] The divider 32 can be any device capable of dividing one digital value by another. For example, it can be a hardware divider implemented with an integrated circuit, or a divider implemented using a software algorithm in a processor.

[0156] Amplification module 21 is connected to gain control module 4 and analog-to-digital converter 2; gain control module 4 is connected to amplification module 21; divider 32 is connected to analog-to-digital converter 2 and digital comparator 13.

[0157] Amplification module 21 amplifies the input signal according to the gain parameter, so that the amplitude of the amplified input signal is a second amplitude, and transmits the second amplitude signal to analog-to-digital converter 2. Amplifying the input signal according to the gain parameter allows for precise control of the amplification factor.

[0158] Furthermore, the gain parameter of the amplification module 21 is adjustable. The amplitude of the input signal may vary considerably, and the adjustable gain parameter allows the amplification module 21 to dynamically adjust the amplification factor according to the amplitude of the input signal, ensuring that the output signal remains within the operating range of subsequent devices. For example, when the input signal amplitude is small, the amplification module 21 can use a larger gain parameter to improve the resolution of signals with smaller amplitudes; when the input signal amplitude is large, the amplification module 21 can use a smaller gain parameter to prevent the output amplitude from exceeding the operating range of subsequent devices.

[0159] The gain control module 4 is used to adjust the gain parameters of the amplification module 21 according to the first amplitude. The gain control module 4 can adjust the gain parameters of the amplification module 21 according to the first amplitude, allowing the amplification module 21 to use different gain parameters for amplifying input signals of different amplitudes. This achieves more precise gain control, improves gain stability, and enhances the adaptability of the amplification module 21. The gain control module 4 can optimize the gain parameters according to the strength of the input signal, ensuring that the output signal is within a suitable dynamic range.

[0160] Furthermore, the magnitude of the gain parameter is negatively correlated with the magnitude of the first amplitude. For example, the smaller the first amplitude, the larger the gain parameter, which can amplify a signal with a smaller amplitude by a larger factor, thereby improving the detection accuracy of the signal; the larger the first amplitude, the smaller the gain parameter, which can amplify a signal with a larger amplitude by a smaller factor, making the output signal more stable and ensuring that the output signal is within the appropriate dynamic range.

[0161] Furthermore, the amplification module 21 also includes a reference module 22; the reference module 22 can be any module that can provide DC voltage, such as any of the following: a reference voltage source, a voltage regulator, etc.

[0162] The reference module 22 is connected to the input terminal of the amplifier module 21 and is used to provide a reference level for the input signal. For example, the amplifier module 21 can provide a stable reference point so that the output voltage is within the signal range that the amplifier module 21 can process.

[0163] Furthermore, the reference module 22 may include a voltage source. One end of the voltage source receives the input signal, and the other end of the voltage source is connected to the input terminal of the amplifier module 21. This approach is easy to implement.

[0164] The overcurrent detection circuit may further include an input chopper module 5. The input chopper module 5 can be any module capable of increasing the signal frequency, such as a multiplier, mixer, phase-locked loop, charge pump, etc. The input chopper module 5 can increase the signal frequency, for example, by modulating the input signal with a periodic signal. The input chopper module 5 is located at the input terminal of the first processing module 1. The input chopper module 5 is used to increase the frequency of the input signal and transmit the increased frequency input signal to the first processing module 1. The input chopper module 5 suppresses low-frequency noise by increasing the frequency of the input signal.

[0165] Furthermore, the input chopper module 5 is specifically used to perform square wave modulation on the input signal to increase its frequency. Square wave modulation does not require duty cycle control and is easy to implement.

[0166] The input chopper module 5 includes: a first switch module 51; the first switch module 51 can be any module based on high or low level conduction, such as any one of the following: transistor, field-effect transistor (MOSFET), also known as MOS transistor, thyristor, etc.

[0167] One end of the first switching module 51 is connected to the input signal; the other end of the first switching module 51 is connected to the input terminal of the first processing module 1. The first switching module 51 is used to turn on or off in response to a control signal to modulate the input signal with a square wave, thereby increasing the frequency of the input signal. For example, under the action of a control signal, the first switching module 51 periodically switches the signal path to modulate the input signal to a chopping frequency with the same frequency as the control signal, thereby increasing the frequency of the input signal. This can suppress low-frequency noise.

[0168] The control signal for the first switching module 51 is a square wave signal. Under the action of the square wave signal, the first switching module 51 periodically turns on or off, modulating the input signal with a square wave. This method does not require the duty cycle of the control signal and is easy to implement.

[0169] The overcurrent detection circuit also includes an output chopper module 6; the output chopper module 6 can be any module that can reduce the signal frequency. For example, the output chopper module 6 can demodulate the signal modulated at the chopping frequency to the original input signal frequency by quickly switching the input signal.

[0170] The output chopper module 6 is located between the first processing module 1 and the second processing module 2. It is used to reduce the frequency of the received signal and output the signal after the frequency reduction.

[0171] In one example, the output chopper module 6 can be located between the first processing module 1 and the analog-to-digital converter 2. The output chopper module 6 can demodulate the input signal modulated at the chopping frequency back to the original input signal frequency, and modulate the offset voltage and low-frequency noise of the first processing module 1 to a high frequency. This distinguishes the frequencies of the input signal from the noise.

[0172] In another example, the output chopper module 6 can be located between the analog-to-digital converter 2 and the second processing module 3. The output chopper module 6 can demodulate the input signal modulated at the chopping frequency back to the original input signal frequency, and modulate the offset voltage and low-frequency noise of the first processing module 1 to a high frequency. This distinguishes the frequencies of the input signal from the noise.

[0173] Furthermore, the output chopper module 6 includes a second switching module 61; the second switching module 61 can be any module based on high or low level conduction, such as any one of the following: transistor, field-effect transistor (MOSFET), also known as MOS transistor, thyristor, etc.

[0174] One end of the second switching module 61 is connected to the output terminal of the first processing module 1; the other end of the second switching module 61 is connected to the input terminal of the analog-to-digital converter 2. The second switching module 61 is used to turn on or off in response to a control signal to reduce the frequency of the received signal and output the signal with the reduced frequency. For example, under the action of a control signal, the second switching module 61 periodically switches the signal path, demodulating the signal modulated at the same chopping frequency as the control signal to the original input signal frequency, thereby reducing the frequency of the input signal. This can restore the original form of the input signal.

[0175] The input signal undergoes two chopping operations, one in the input chopper module 5 and the other in the output chopper module 6. The offset voltage of the first processing module 1 is processed only once by the output chopper module 6. This ensures that the input signal maintains its waveform at the output of the output chopper module 6, and the chopping offset voltage can be eliminated by subsequent filters, thereby suppressing noise and offset voltage. This allows the first processing module 1 to have a higher dynamic range and further improves the overcurrent detection accuracy.

[0176] Furthermore, the overcurrent detection circuit also includes a rate adjustment module 7; the rate adjustment module 7 can be any module capable of adjusting the rate of the signal. For example, it can include any of the following: a cascaded integrator-comb filter (CIC) filter, a half-sideband filter, etc.

[0177] The rate adjustment module 7 is located between the analog-to-digital converter 2 and the second processing module 3; the rate adjustment module 7 is used to adjust the rate of the received signal before outputting it. For example, the rate adjustment module 7 can reduce the signal rate by decimation, that is, outputting a signal every few signals, which can improve the signal processing rate of subsequent modules; or, the rate adjustment module 7 can increase the signal rate by interpolation, that is, inserting signals between input signals, which can achieve rate compatibility between different modules.

[0178] The overcurrent detection circuit also includes a calibration module 8; the calibration module 8 can be any module capable of calibrating the received signal. The calibration module 8 is located between the analog-to-digital converter 2 and the second processing module 3; the calibration module 8 is used to calibrate the received signal before outputting it. By calibrating the received signal through the calibration module 8, deviations introduced by the signal in the other processing modules of the overcurrent detection circuit before transmission to the calibration module 8 can be corrected, improving the accuracy of the output signal and thus improving the accuracy of overcurrent detection.

[0179] Figure 5The following is a schematic illustration of an overcurrent detection circuit, which includes: input chopper module 5, amplification module 21, gain control module 4, analog-to-digital converter 2, output chopper module 6, rate adjustment module 7, calibration module 8, divider 32, digital comparator 13, delay filter 95, result module 96, overcurrent logic module 17, output enable module 18, and status indication module 19.

[0180] The input terminal of input chopper module 5 receives the input signal; the output terminal of input chopper module 5 is connected to the input terminal of amplifier module 21 and the input terminal of gain control module 4; the output terminal of gain control module 4 is connected to the gain control terminal of amplifier module 21; the output terminal of amplifier module 21 is connected to the input terminal of analog-to-digital converter 2; the output terminal of analog-to-digital converter 2 is connected to the input terminal of output chopper module 6; the output terminal of output chopper module 6 is connected to the input terminal of rate adjustment module 7; the output terminal of rate adjustment module 7 is connected to the input terminal of calibration module 8; the output terminal of calibration module 8 is connected to the input terminal of decompression module 8. The input terminal of divider 32 is connected to the input terminal of digital comparator 13; the output terminal of digital comparator 13 is connected to the input terminal of delay filter 95; the output terminal of delay filter 95 is connected to the input terminal of result module 96; the output terminal of result module 96 is connected to the input terminal of overcurrent logic module 17 and the input terminal of status indicator module 19; the output terminal of overcurrent logic module 17 is connected to the input terminal of output enable module 18; the control terminal of output enable module 18 is connected to an enable signal; the output terminal of output enable module 18 outputs an overcurrent output signal. The control terminals of input chopper module 5 and output chopper module 6 are connected to control signals.

[0181] The signal processing procedure of the overcurrent detection circuit can be illustrated as follows:

[0182] The input chopper module 5 receives an input signal of the first amplitude. The input chopper module 5 includes a first switch module 51, which is turned on or off under the action of a square wave signal. The polarity of the input signal is rapidly switched alternately at the frequency of the square wave signal to modulate the input signal of the first amplitude, thereby increasing the frequency of the input signal. The input chopper module 5 transmits the modulated signal to the amplification module 21.

[0183] The gain control module 4 adjusts the gain parameter of the amplification module 21 according to the first amplitude.

[0184] The amplification module 21 amplifies the input signal according to the gain parameter, increases the amplitude of the modulated input signal to a second amplitude, and transmits it to the analog-to-digital converter 2.

[0185] The analog-to-digital converter 2 converts the signal of the second amplitude into a digital signal; the analog-to-digital converter 2 transmits the digital signal of the second amplitude to the output chopper module 6.

[0186] The output chopper module 6 is turned on or off under the action of the square wave signal, and the polarity of the input signal is rapidly switched alternately at the frequency of the square wave signal to demodulate the digital signal of the second amplitude and restore the digital signal of the second amplitude back to the original frequency; at the same time, the offset voltage and low frequency noise amplified by the amplification module 21 are modulated to the high frequency; the output chopper module 6 transmits the demodulated digital signal of the second amplitude to the rate adjustment module 7.

[0187] The rate adjustment module 7 reduces the rate of the demodulated second amplitude digital signal and transmits it to the calibration module 8.

[0188] After calibrating the received signal, the calibration module 8 outputs the result to the divider 32.

[0189] Divider 32 divides the received signal by the gain parameter to restore the digital signal of the second amplitude to the first amplitude; the signal restored to the first amplitude by divider 32 is output to digital comparator 13.

[0190] The digital comparator 13 compares the received signal with a set overcurrent threshold. When the amplitude of the received signal exceeds the set overcurrent threshold, it outputs an overcurrent signal in a first state; and when the amplitude of the received signal does not exceed the set overcurrent threshold, it outputs an overcurrent signal in a second state. The digital comparator 13 outputs the overcurrent signal in the first state / the overcurrent signal in the second state to the delay filter 95.

[0191] In one example, when the battery is charging, the differential voltage corresponding to the input signal may be negative, meaning the value of the signal output by analog-to-digital converter 2 may be relatively low. The larger the current, the smaller the signal output by analog-to-digital converter 2. For digital comparator 13, the overcurrent threshold may include an undervoltage threshold. If the signal amplitude received by digital comparator 13 exceeds the set overcurrent threshold, it indicates that the signal amplitude received by digital comparator 13 is less than the set undervoltage threshold. If the signal amplitude received by digital comparator 13 does not exceed the set overcurrent threshold, it indicates that the signal amplitude received by digital comparator 13 is greater than the set undervoltage threshold.

[0192] In another example, when the battery is discharging, the differential voltage corresponding to the input signal may be positive, meaning the value of the signal output by analog-to-digital converter 2 may be relatively high. The greater the current, the larger the signal output by analog-to-digital converter 2. For digital comparator 13, the overcurrent threshold may include the overvoltage threshold. If the signal amplitude received by digital comparator 13 exceeds the set overcurrent threshold, it indicates that the signal amplitude received by digital comparator 13 is less than the set overvoltage threshold. If the signal amplitude received by digital comparator 13 does not exceed the set overcurrent threshold, it indicates that the signal amplitude received by digital comparator 13 is greater than the set overvoltage threshold.

[0193] The delay filter 95 performs timing on the overcurrent signal in the first state; when the delay filter 95 receives the overcurrent signal in the second state, it resets the timing; when the timing duration of the overcurrent signal in the first state exceeds the preset duration, the delay filter 95 sends a result trigger signal to the result module 16, and the result trigger signal can be, for example, a high-level signal.

[0194] When the result module 16 receives the result trigger signal output by the delay filter 95, it generates a status signal characterizing the overcurrent, which can be, for example, a high level. The result module 16 sends the status signal to the overcurrent logic module 17 and the status indication module 19.

[0195] The overcurrent logic module 17 receives the status signal output by the timing module 94 and converts it into an overcurrent output signal. For example, when the status signal indicates an overcurrent, the overcurrent logic module 17 can convert the received input signal into a high-level, low-level, or PWM signal as an effective output, thereby controlling the external circuit for overcurrent detection to respond to the overcurrent state; the overcurrent logic module 17 outputs the overcurrent output signal to the output enable module 18.

[0196] When the control terminal is high, the output enable module 18 outputs the output signal of the overcurrent logic module 17; when the control terminal is low, the output signal of the overcurrent module 17 is stopped.

[0197] The status indicator module 19 records the status signal when the status signal output by the result module 16 is high, and uses it to indicate overcurrent.

[0198] The overcurrent detection circuit provided in this application embodiment increases the amplitude of the input signal by adding an amplification module 21 before the analog-to-digital converter 2. The analog-to-digital converter 2 then converts the amplified input signal into a digital signal. When converting the amplified input signal, the actual voltage change represented by each quantization level of the analog-to-digital converter 2 is smaller, thereby improving the detection accuracy of the input signal and reducing errors. A divider 32 is added after the analog-to-digital converter 2 to restore the amplitude of the output signal, improving the accuracy of the output signal. Adding an input chopper module 5 before the first processing module 1 and an output chopper module 6 after the first processing module 1 suppresses noise, allowing the first processing module 1 to have a higher dynamic range, further improving the overcurrent detection accuracy. Reducing the signal rate through the rate adjustment module 7 increases the processing speed of subsequent devices, improving processing efficiency. Calibration module 8 calibrates the signal, improving the accuracy of overcurrent detection. Dynamically adjusting the amplification factor of the amplification module 21 through the gain control module 4 further improves the overcurrent detection accuracy. Digital comparator 13 performs overcurrent detection on the received signal, resulting in a more accurate output overcurrent signal. Timing module 94 generates a more accurate status signal indicating whether an overcurrent has occurred based on the overcurrent signal. This further improves the accuracy of the overcurrent detection results.

[0199] Figure 6 A schematic diagram of the structure of the fifth overcurrent detection circuit provided in the embodiments of this application is shown below. Figure 6 As shown,

[0200] The overcurrent detection circuit includes: analog comparator 93, delay filter 95, result module 96, overcurrent logic module 17, output enable module 18, status indicator module 19, and the output terminal OC is used as an example for illustration.

[0201] Analog comparator 93 includes ANA CMP; delay filter 95 includes Relay Filter; result module 96 includes Result; overcurrent logic module 17 includes OC Logic; output enable module 18 includes Drive; and status indicator module 19 includes Flag SFR.

[0202] The first input terminal SRP is connected to the first input terminal of the analog comparator ANA CMP; the second input terminal SRN is connected to the second input terminal of the analog comparator ANA CMP; the output terminal of the analog comparator ANA CMP is connected to the input terminal of the delay filter Relay Filter; the output terminal of the delay filter Relay Filter is connected to the input terminal of the result module Result; the output terminal of the result module Result is connected to the input terminal of the overcurrent logic module OC Logic and the input terminal of the status indicator module Flag SFR; the output terminal of the overcurrent logic module OC Logic is connected to the input terminal of the output enable module Drive; the control terminal of the output enable module Drive is connected to the enable signal Disable Drive; the output enable module Drive outputs an overcurrent output signal to the output terminal OC.

[0203] The signal processing procedure for overcurrent detection can be illustrated as follows:

[0204] The analog comparator ANA CMP receives the input signal of the first amplitude;

[0205] The analog comparator ANA CMP performs overcurrent detection based on the input signal; if the received signal exceeds the set overcurrent threshold, it outputs an overcurrent pulse; the analog comparator ANA CMP outputs the overcurrent pulse to the delay filter Relay Filter;

[0206] The Relay Filter performs timing on the overcurrent signal in the first state; when the Relay Filter receives the overcurrent signal in the second state, it resets the timing; when the timing duration of the overcurrent signal in the first state exceeds a preset duration, the Relay Filter sends a result trigger signal to the Result module. The result trigger signal can be, for example, a high-level signal.

[0207] When the Result module receives the result trigger signal from the Relay Filter, it generates a status signal representing an overcurrent, which can be a high level, for example. The Result module then sends the status signal to the Overcurrent Logic module (OC Logic) and the Status Indicator module (Flag SFR).

[0208] The overcurrent logic module OC Logic receives the status signal output by the result module Result and converts it into an overcurrent output signal. For example, when the status signal indicates an overcurrent, the overcurrent logic module OC Logic can convert the received input signal into a valid output such as a high level, low level, or PWM signal, thereby controlling the external circuitry for overcurrent detection to respond to the overcurrent state; the overcurrent logic module OC Logic outputs the overcurrent output signal to the output enable module Drive.

[0209] When the control terminal of the output enable module Drive is high, it outputs the output signal of the overcurrent logic module OCLogic to the output terminal OC; when the control terminal is low, it stops outputting the output signal of the overcurrent logic module OCLogic to the output terminal OC.

[0210] The Flag SFR status indicator module records the status signal when the status signal output by the Result module is high, and is used to indicate overcurrent.

[0211] The structure of delay filter 95 is illustrated below.

[0212] Figure 7 This is a schematic diagram of the sixth overcurrent detection circuit provided in an embodiment of this application. Figure 7 As shown,

[0213] The delay filter 95 includes: a first counter 97 and a first register 98;

[0214] The first counter 97 can be, for example, a programmable counter. The first counter 97 can be configured according to user needs to perform counting operations.

[0215] The first register 98 can be any device capable of storing information.

[0216] The first counter 97 is connected to the first register 98, the result module 96, and the overcurrent detection module 91. It is used to time the duration of a single overcurrent pulse output by the overcurrent detection module 91 according to the overcurrent duration corresponding to the first register 98.

[0217] Furthermore, the overcurrent detection module 91 also includes: a second register 90 and a multiplexer 99;

[0218] Multiplexer 99 is connected to second register 90 and analog comparator 93;

[0219] The second register 90 is used to store the gear position indication signal; the multiplexer 99 is used to select the corresponding overcurrent threshold from multiple overcurrent thresholds according to the gear position indication signal and output it to the analog comparator 93.

[0220] Figure 7The overcurrent detection circuit includes: an analog comparator 93, a first counter 97, a first register 98, a result module 96, a multiplexer 99, and a second register 90; wherein the analog comparator 93 includes ANA CMP; the first counter 97 includes a Configurable Counter; the first register includes Reg2[3:0]; the result module 96 includes Result; the multiplexer 99 includes MUX; and the second register 90 includes Reg1[2:0] as an example for illustration.

[0221] The first input terminal SRP is connected to the first input terminal of the analog comparator ANA CMP; the second input terminal SRN is connected to the second input terminal of the analog comparator ANA CMP; the output terminal of the analog comparator ANA CMP is connected to the input terminal of the Configurable Counter and the first input terminal of the result module Result; the output terminal of the Configurable Counter is connected to the second input terminal of the result module Result; the output terminal of the result module Result outputs a status signal indicating whether there is an overcurrent; the configuration terminal of the analog comparator ANA CMP is connected to the multiplexer MUX. The input terminals of the multiplexer are connected to the eight overcurrent threshold positions Vref0 to Vref7 and the second register Reg1[2:0].

[0222] The signal processing procedure for overcurrent detection can be illustrated as follows:

[0223] (1) The analog comparator ANA CMP receives the input signal of the first amplitude;

[0224] (2) The analog comparator ANA CMP performs overcurrent detection based on the input signal; if the received signal exceeds the set overcurrent threshold, it outputs an overcurrent pulse; the analog comparator ANA CMP outputs the overcurrent pulse to the Configurable Counter and the Result module.

[0225] For example, the analog comparator ANA CMP internally provides eight different voltage reference values, obtained from a bandgap reference or DAC voltage division, corresponding to eight different overcurrent thresholds. The multiplexer MUX selects an overcurrent threshold from the eight overcurrent threshold positions Vref0 to Vref7 based on the value of the second register Reg1[2:0] and transmits it to the analog comparator ANA CMP. The analog comparator ANA CMP determines the overcurrent threshold from the eight internally stored voltage reference values ​​based on the overcurrent threshold position. Then, the analog comparator ANA CMP compares the input signal with the overcurrent threshold and outputs an overcurrent pulse.

[0226] The overcurrent threshold for a specific range is determined by the multiplexer MUX based on the magnitude of the differential voltage output between SRP and SRN. The specific overcurrent ranges are shown in Table 2.

[0227] Table 2

[0228] gear 0 1 2 3 4 5 6 7 (default) Overcurrent threshold (mV) 62.5 75 87.5 100 112.5 125 137.5 150

[0229] (3) The Configurable Counter performs timing for the overcurrent signal in the first state; when the Configurable Counter receives the overcurrent signal in the second state, it resets the timing. For example, the Configurable Counter can internally configure 16 overcurrent duration levels. The Configurable Counter can select one of the 16 overcurrent duration levels based on the value of the first register Reg2[3:0]. The Configurable Counter internally stores the correspondence between the overcurrent duration levels and the preset overcurrent duration. Therefore, the Configurable Counter can determine the corresponding preset overcurrent duration based on the value of the first register Reg2[3:0]. When the timing duration of the overcurrent signal in the first state exceeds the preset duration, the Configurable Counter sends a result trigger signal to the result module Result. The result trigger signal can be, for example, a high-level signal.

[0230] (4) When the Result module receives the result trigger signal output by the Configurable Counter, it generates a status signal representing the overcurrent, which can be a high level, for example. For example, when the Result module receives the result trigger signal output by the Configurable Counter, the analog comparator ANA CMP still outputs an overcurrent pulse, which can be a high level signal, for example. The Result module can be an AND gate, for example. After performing an AND operation between the result trigger signal output by the Configurable Counter and the overcurrent pulse output by the analog comparator ANA CMP, the overcurrent status signal is output.

[0231] Afterwards, the Result module can send status signals to the overcurrent logic module OC Logic and the status indication module Flag SFR.

[0232] The following is a schematic description of the structure of the input chopper module 5 and the output chopper module 6.

[0233] Figure 8 This is a schematic diagram of a chopper module provided in an embodiment of this application. Figure 8As shown, the example is an output chopper module 6 located between the first processing module 1 and the analog-to-digital converter 2.

[0234] The input chopper module 5 includes a first switch module 51; the input signals include a first input signal and a second input signal.

[0235] The first switch module 51 includes: a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4; the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 can all be any module based on high or low level conduction, such as any of the following: transistor, field-effect transistor (MOSFET), also known as MOS transistor, thyristor, etc.

[0236] The first switch S1 is connected between the first input signal and the first input terminal of the first processing module 1; the second switch S2 is connected between the first input signal and the second input terminal of the first processing module 1; the third switch S3 is connected between the second input signal and the first input terminal of the first processing module 1; and the fourth switch S4 is connected between the second input signal and the second input terminal of the first processing module 1.

[0237] The first switch S1 and the fourth switch S4 are in the same state. The first switch S1 and the second switch S2 are in opposite states. The first switch S1 and the third switch S3 are in opposite states.

[0238] The second switch module 61 includes: a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8;

[0239] The fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 can all be any module that is turned on based on a high or low level. For example, they can include any of the following: transistors, field-effect transistors (MOSFETs), also known as MOS transistors, thyristors, etc.

[0240] The fifth switch S5 is connected between the first output terminal of the first processing module 1 and the first input terminal of the analog-to-digital converter 2; the sixth switch S6 is connected between the first output terminal of the first processing module 1 and the second input terminal of the analog-to-digital converter 2; the seventh switch S7 is connected between the second output terminal of the first processing module 1 and the first input terminal of the analog-to-digital converter 2; and the eighth switch S8 is connected between the second output terminal of the first processing module 1 and the second input terminal of the analog-to-digital converter 2.

[0241] The fifth switch S5 and the eighth switch S8 have the same switching state, the fifth switch S5 and the sixth switch S6 have opposite switching states, and the fifth switch S5 and the seventh switch S7 have opposite switching states.

[0242] In one example, the input chopper module 5 receives an input signal of the first amplitude. When the control signal is high, the first switch S1 and the fourth switch S4 are turned on, the second switch S2 and the third switch S3 are turned off, and the path between the first input signal and the first input terminal of the first processing module 1 is open; the path between the second input signal and the second input terminal of the first processing module 1 is also open. When the control signal is low, the first switch S1 and the fourth switch S4 are turned off, the second switch S2 and the third switch S3 are turned on, and the path between the first input signal and the second input terminal of the first processing module 1 is open; the path between the second input signal and the first input terminal of the first processing module 1 is also open. When each switch in the first switch module 51 switches between on and off states in response to the control signal, the first input signal and the second input signal are periodically connected to different paths, thereby multiplying the input signal with the control signal to achieve modulation of the input signal. When the control signal is a square wave signal, the input chopper module 5 modulates the input signal with a square wave, shifting the DC signal to a higher frequency, while the low-frequency noise and offset voltage of the input signal remain at a lower frequency.

[0243] The first processing module 1 increases the amplitude of the modulated signal to a second amplitude, while simultaneously increasing the amplitude of the noise and the offset voltage of the first processing module 1.

[0244] Output chopper module 6 receives a signal with a second amplitude. When the control signal is high, switches S5 and S8 are turned on, and switches S6 and S7 are turned off, connecting the first output of the first processing module 1 to the first input of the analog-to-digital converter 2; the second output of the first processing module 1 is also connected to the second input of the analog-to-digital converter 2. When the control signal is low, switches S5 and S8 are turned off, and switches S6 and S7 are turned on, connecting the first output of the first processing module 1 to the second input of the analog-to-digital converter 2; the second output of the first processing module 1 is also connected to the first input of the analog-to-digital converter 2. When the switches in the second switch module 61 switch between on and off states in response to the control signal, the first and second outputs of the first processing module 1 are periodically connected to different paths, thereby multiplying the output signal of the first processing module 1 with the control signal and demodulating the signal modulated at the control signal frequency back to DC or a low frequency. When the modulated signal passes through the output chopper module 6, the switching action of the switch restores the high-frequency modulated signal back to the original low-frequency signal, while modulating the offset voltage and low-frequency noise amplified by the first processing module 1 to a high frequency.

[0245] Figure 8 Taking Vin+ as the first input signal and Vin- as the second input signal; the first processing module 1 includes an amplification module 21 and a reference module 22; the amplification module 21 includes a programmable gain amplifier (PGA), and the reference module 22 includes a voltage source (Vos) as an example for illustration. The analog-to-digital converter 2... Figure 8 (Not shown in the diagram). Input chopper module 5 receives the first input signal Vin+ and the second input signal Vin-; one end of voltage source Vos receives the modulation signal output by input chopper module 5, and the other end of voltage source Vos is connected to the input terminal of programmable gain amplifier PGA. The output terminal of programmable gain amplifier PGA is connected to the input terminal of output chopper module 6; the first output terminal Vout+ and the second output terminal Vout- of output chopper module 6 transmit the output signal to analog-to-digital converter 2.

[0246] The input chopper module 5 modulates the received first amplitude input signal into a square wave, modulating the input signal to the frequency of the square wave signal, thereby increasing the frequency of the input signal; the input chopper module 5 transmits the modulated signal to the programmable gain amplifier PGA through the voltage source Vos.

[0247] The programmable gain amplifier (PGA) amplifies the modulated signal according to the gain parameter, increases the amplitude of the signal to a second amplitude, and transmits the digital signal of the second amplitude to the output chopper module 6.

[0248] The output chopper module 6 is turned on or off under the action of the square wave signal, and the polarity of the input signal is rapidly switched alternately at the frequency of the square wave signal to demodulate the digital signal of the second amplitude and restore the digital signal of the second amplitude back to the original frequency; at the same time, the offset voltage and low-frequency noise amplified by the programmable gain amplifier PGA are modulated to the high frequency; the output chopper module 6 transmits the demodulated digital signal of the second amplitude to the analog-to-digital converter 2.

[0249] A low-pass filter is added to the subsequent circuit to effectively block high-frequency components, thereby filtering out the offset voltage and noise modulated to the high frequency and retaining only the input signal with increased amplitude. Since chopper stabilization technology can suppress noise, the input chopper module 5 and the output chopper module 6 can give the first processing module 1 a higher dynamic range, further improving the overcurrent detection accuracy.

[0250] The following diagram illustrates the structure of the rate adjustment module 7, using the CIC filter as an example.

[0251] Figure 9 This is a schematic diagram of a rate adjustment module provided in an embodiment of this application. Figure 9 As shown,

[0252] The rate adjustment module 7 may include, for example, an extractor 71; the extractor 71 may be any module that can reduce the signal rate. For example, it may be a second counter.

[0253] The decimator 71 is used to reduce the rate of the received signal before outputting it. For example, the decimator 71 can output a signal every M signals by setting a decimation factor M, effectively reducing the signal rate and improving the processing speed of subsequent modules.

[0254] Furthermore, the extractor 71 may include, for example, a second counter; the second counter is used to perform counting, and when the counting result reaches a counting threshold, outputs the signal from the analog-to-digital converter 2 and resets the count. The second counter is used to control the output time of the signal from the analog-to-digital converter 2. When the counting result has not reached the counting threshold, no signal is output; when the counting result reaches the counting threshold, the signal from the analog-to-digital converter 2 is output. After the second counter is reset, timing for the output time of the next signal can begin. This method is easy to implement.

[0255] The rate adjustment module 7 may further include a first filter 72; the first filter 72 may be any filter that allows low-frequency signals to pass through while blocking high-frequency signals, such as any of the following: an infinite impulse response filter (IIR), a finite impulse response filter (FIR), etc. The first filter 72 is located at the input of the decimator 71 and is used to suppress high-frequency noise.

[0256] Furthermore, the first filter 72 includes at least one cascaded integrator 73. The integrator 73 can be, for example, any device capable of performing an accumulation operation. The integrator 73 can be used to accumulate the input signal. Cascading at least one integrator 73 together can enhance the low-pass filtering effect.

[0257] The integrator 73 includes an adder 74 and a first delay unit 75; the output of the adder 74 is connected to its input via the first delay unit 75. This method is easy to implement and eliminates the need for a multiplier, thereby improving the processing speed of the received signal.

[0258] The rate adjustment module 7 may further include a second filter 76. The second filter 76 can be any filter that allows low-frequency signals to pass while impeding high-frequency signals, such as an infinite impulse response filter (IIR), a finite impulse response filter (FIR), etc. The second filter 76 is located at the output of the decimator 71 and is used to suppress high-frequency noise.

[0259] The second filter 76 includes at least one cascaded comb filter 77. The comb filter 77 can be, for example, any device capable of differential operation. The output of the comb filter 77 is the difference between the current input signal and the delayed input signal, which can eliminate periodic peaks in the frequency response and achieve a flatter frequency response.

[0260] The comb filter 77 includes a subtractor 78 and a second delay unit 79; the first input terminal of the subtractor 78 is connected to the second input terminal of the subtractor 78 through the second delay unit 79. This method is easy to implement and eliminates the need for a multiplier, thereby improving the processing speed of the received signal.

[0261] In one example, the signal output by analog-to-digital converter 2 has a high speed. The signal output by analog-to-digital converter 2 can be slowed down to reduce the data volume and system complexity, while also performing anti-aliasing filtering. The rate adjustment module 7 receives the signal output by analog-to-digital converter 2, slows down the signal, and then outputs it. The rate adjustment module 7 includes: a first filter 72, a decimator 71, and a second filter 76. The decimator 71 is positioned between the first filter 72 and the second filter 76. The first filter 72 receives the signal output by analog-to-digital converter 2, the decimator 71 reduces the rate of the received signal, and the second filter 76 outputs the slowed-down signal.

[0262] The first filter 72 includes cascaded n-stage integrators 73. Each n-stage integrator 73 operates at the original frequency and accumulates the input signal. Each integrator 73 is a first-order IIR filter with a transfer function of...

[0263] By cascading n integrators, the roll-off characteristic of the first filter 72 can be enhanced. The roll-off characteristic describes the rate attenuation of a signal in the transition band from the passband to the stopband. The more integrators cascaded, the steeper the roll-off characteristic, and the faster the signal attenuates from the passband to the stopband in the transition band, thus more effectively suppressing frequency components outside the passband.

[0264] The second filter 76 includes a cascaded n-stage comb filter 77. The comb filter 77 performs differential operations on the reduced-rate signal to suppress high-frequency noise and aliasing components. Each stage of the comb filter 77 is a first-order FIR filter with a transfer function of H. C (z)=1-z -D Where D is the differential delay, which can usually be equal to 1.

[0265] The comb filter 77 has the same number of stages as the integrator. The comb filter 77 can suppress high-frequency noise and remove high-frequency noise components that may be introduced during the rate reduction process.

[0266] The structure of gain control module 4 is described below.

[0267] Figure 10 This is a schematic diagram of a gain control module provided in an embodiment of this application. Figure 10 As shown, the gain control module 4 includes: a detector 41 and a comparator 42;

[0268] The input terminal of detector 41 receives the input signal and is used to detect the voltage of the input signal;

[0269] The first input terminal of comparator 42 is connected to the output terminal of detector 41, the second input terminal is connected to the reference voltage, and the output terminal is connected to amplifier module 21. Comparator 42 is used to output the gain parameter of amplifier module 21 based on the voltage comparison result between the input signal and the reference voltage.

[0270] In one example, the processor can establish a communication connection with the gain control module 4. The processor writes specific values ​​to the registers of the gain control module 4 via a communication interface such as a Serial Peripheral Interface (SPI). These values ​​store information related to gain control, such as gain parameters and thresholds. After receiving the register write operation, the comparator 42 of the gain control module 4 can read the value in the register and continuously compare the input signal with the threshold in the register. Once the set threshold is reached, the gain parameter is adjusted. Multiple reference voltage thresholds can correspond to different gain levels to determine the amplification factor of the amplifier module 21 that needs to be adjusted. Furthermore, the gain control module 4 can be turned on or off. For example, the gain control function can be enabled or disabled by writing to the registers of the gain control module 4. The gain control module 4 is enabled by default. When the gain control module 4 is disabled, the gain parameter of the amplifier module 21 can be adjusted by configuring the registers of the amplifier module 21 through the processor.

[0271] Furthermore, when the analog-to-digital converter 2 is started, if the gain control function of the gain module 4 is already enabled, the gain control module 4 first performs gain control on the amplification module 21, and after determining the gain parameters, the analog-to-digital converter performs analog-to-digital conversion on the input signal.

[0272] Figure 10 The following is a schematic illustration using an example where detector 41 includes a detector, comparator 42 includes a comparator pump (CMP), and amplification module 21 includes a power amplifier (PGA). The input terminal of the detector receives the input signal Vin2 and is used to detect the voltage of the input signal.

[0273] The first input terminal of the CMP is connected to the output terminal of the Detector, the second input terminal is connected to the reference voltage Vref, and the output terminal is connected to the PGA. The CMP is used to output the gain parameter of the PGA based on the voltage comparison result between the input signal Vin2 and the reference voltage Vref.

[0274] Figure 11 This is a schematic flowchart illustrating the output gain parameters of a gain control module provided in an embodiment of this application. Figure 11 As shown, taking the gain control module 4, which includes 8 gain levels, as an example, this paper illustrates how the gain control module 4 outputs gain parameters based on the voltage of the input signal.

[0275] For example, the gain levels of the gain control module 4 may include: 4, 8, 16, 32, 64, 128, 256, 512; the gain control module 4 may set an upper limit threshold and a lower limit threshold; the gain control module 4 amplifies the input voltage according to the set gain level and compares it with the upper limit threshold and the lower limit threshold respectively. If the amplitude of the amplified input voltage is between the upper limit threshold and the lower limit threshold, the gain level is output as a gain parameter to the amplification module 21, and the amplification module 21 amplifies the input signal according to the gain parameter.

[0276] In one example, the default gain level of the gain control module 4 (S1) can be set to 64. The differential voltage of the input signal is amplified 64 times by the detector 41 and transmitted to the comparator 42; the comparator 42 compares the amplified input signal 64 times with the upper threshold and the lower threshold respectively.

[0277] If the signal output by comparator 42 represents an input signal amplified by 64 times that is between the upper and lower thresholds, then the gain control module 4 transmits 64 as a gain parameter to the amplification module 21.

[0278] If the signal output by comparator 42 represents an input signal amplified by 64 times that is lower than the lower threshold, then execute S21;

[0279] If the signal output by comparator 42 represents an input signal amplified by 64 times that is higher than the upper threshold, then S22 is executed.

[0280] S21, the processor adjusts the gain level of the gain control module 4 to 256; the detector 41 amplifies the input signal by 256 times and transmits it to the comparator 42; the comparator 42 compares the amplified input signal by 256 times with the upper threshold and the lower threshold respectively;

[0281] If the signal output by comparator 42 indicates that the input signal amplified by 256 times is between the upper and lower thresholds, then the gain control module 4 transmits 256 as a gain parameter to the amplification module 21.

[0282] If the signal output by comparator 42 represents an input signal amplified by 256 times that is lower than the lower threshold, then S31 is executed; if the signal output by comparator 42 represents an input signal amplified by 256 times that is higher than the upper threshold, then S32 is executed.

[0283] S22, the processor adjusts the gain level of the gain control module 4 to 16; the detector 41 amplifies the input signal by 16 times and transmits it to the comparator 42; the comparator 42 compares the amplified input signal by 16 times with the upper threshold and the lower threshold respectively;

[0284] If the signal output by comparator 42 represents an input signal amplified by 16 times that is between the upper and lower thresholds, then the gain control module 4 transmits 16 as a gain parameter to the amplification module 21.

[0285] If the signal output by comparator 42 represents an input signal amplified 16 times that is lower than the lower threshold, then execute S41;

[0286] If the signal output by comparator 42 represents an input signal amplified by 16 times that is higher than the upper threshold, then S42 is executed.

[0287] S31, the processor adjusts the gain level of the gain control module 4 to 512; the gain control module 4 transmits 512 as a gain parameter to the amplification module 21.

[0288] S32, The processor adjusts the gain level of the gain control module 4 to 128; the gain control module 4 transmits 128 as a gain parameter to the amplification module 21.

[0289] S41, the processor adjusts the gain level of the gain control module 4 to 32; the gain control module 4 transmits 32 as a gain parameter to the amplification module 21.

[0290] S42, the processor adjusts the gain level of the gain control module 4 to 8; the detector 41 amplifies the input signal by 8 times and transmits it to the comparator 42; the comparator 42 compares the amplified input signal by 8 times with the upper limit threshold.

[0291] If the signal output by comparator 42 represents an input signal amplified by 16 times that is lower than the upper limit threshold, then the gain control module 4 transmits 16 as a gain parameter to the amplification module 21.

[0292] If the signal output by comparator 42 represents an input signal amplified by 16 times that is higher than the upper limit threshold, then S51 is executed.

[0293] S51, the processor adjusts the gain level of the gain control module 4 to 4; the gain control module 4 transmits 4 as a gain parameter to the amplification module 21.

[0294] In summary, the overcurrent detection circuit provided in this application embodiment adjusts the gain parameter of the amplification module 21 through the gain control module 4, enabling the amplification module 21 to achieve more precise gain control, improving the stability of the gain, and enhancing the adaptability of the amplification module 21. This allows the amplification module 21 to adjust the gain parameter in a timely manner according to the amplitude of the input signal, ensuring that the output signal is within a suitable dynamic range.

[0295] The following is a schematic explanation of how calibration module 8 calibrates the received signal. When the input signal reaches calibration module 8 after passing through rate adjustment module 7, it contains various types of errors, including gain error from amplification module 21, offset error from analog-to-digital converter 2, and passband attenuation from rate adjustment module 7 itself. These errors affect the accuracy and performance of the output signal to varying degrees. To improve the accuracy of the output signal, calibration module 8 needs to calibrate the received signal before outputting it. Calibration module 8 calibrates the received signal in three main ways:

[0296] (I) Offset Calibration. Even without an input signal, the output voltage of the analog-to-digital converter 2 may not be zero; this is called the offset voltage of the analog-to-digital converter 2. The magnitude of this offset voltage can be called the offset parameter. Specifically, the calibration module 8 receives the offset parameter of the analog-to-digital converter 2; performs offset calibration on the received signal based on the offset parameter; and outputs the offset-calibrated signal. This offset parameter can, for example, be obtained by the processor acquiring the signal output by the analog-to-digital converter 2 when there is no input signal. In one example, when there is no input signal, the processor acquires N consecutive signals output by the analog-to-digital converter 2; where N is a positive integer; and obtains the offset parameter of the analog-to-digital converter 2 based on the N consecutive output signals. This offset parameter can, for example, be stored in a register, and the calibration module 8 receives the offset parameter by reading the data from the register. Alternatively, the processor directly sends the offset parameter to the calibration module 8, and the calibration module 8 receives the offset parameter. The calibration module 8 performs offset calibration on the received signal, which can correct the error introduced by the analog-to-digital converter 2 when converting the input signal, thereby improving the accuracy of the detection results.

[0297] Furthermore, the received signal is offset calibrated based on the offset parameter. Specifically, this can be achieved by subtracting the received signal from the offset parameter. This method is easy to implement.

[0298] (II) Gain Calibration. The amplification module 21 may generate a gain error, meaning the amplitude of the signal actually output by the amplification module 21 deviates from the amplitude calculated based on the input signal using the set gain parameters. Specifically, the calibration module 8 receives the gain error parameters from the amplification module 21; performs gain calibration on the received signal based on the gain error parameters; and outputs the gain-calibrated signal. These gain error parameters can, for example, be obtained by the processor acquiring the signal output by the analog-to-digital converter 2 or the rate adjustment module 7 when a known input signal is received. For instance, the processor can divide the signal output by the analog-to-digital converter 2 or the rate adjustment module 7 by the known signal to obtain the actual gain parameter; and divide the set gain parameter by the actual gain parameter to obtain the gain error parameters of the amplification module 21. These gain error parameters can, for example, be stored in a register, and the calibration module 8 receives the gain error parameters of the amplification module 21 by reading the data from the register. Alternatively, the processor can directly send the gain error parameters to the calibration module 8, and the calibration module 8 receives the gain error parameters. By performing gain error calibration on the received signal, the calibration module 8 can correct the errors introduced by the amplification module 21 when amplifying the input signal, thereby improving the accuracy of the detection results.

[0299] Furthermore, the received signal is gain-calibrated based on the gain error parameter. Specifically, this can be achieved by multiplying the received signal by the gain error parameter. This method is easy to implement.

[0300] (III) Passband Compensation. When processing the input signal, the rate adjustment module 7 may exhibit periodic attenuation characteristics, resulting in passband attenuation. Specifically, the calibration module 8 receives the passband compensation parameters from the rate adjustment module 7 and performs passband compensation on the signal passing through the rate adjustment module 7 based on these parameters. These passband compensation parameters can be obtained, for example, from the passband attenuation parameters of the rate adjustment module 7 obtained by the processor, and the passband compensation parameters can be determined based on these parameters. These passband compensation parameters can be stored, for example, in a register, and the calibration module 8 receives the passband compensation parameters from the rate adjustment module 7 by reading the data from the register. Alternatively, the processor can directly send the passband compensation parameters to the calibration module 8, and the calibration module 8 receives the passband compensation parameters. By performing passband compensation on the received signal, the calibration module 8 can correct the errors introduced by the rate adjustment module 7 when processing the input signal, thereby improving the accuracy of the detection results.

[0301] This application also provides an overcurrent detection method based on the above-described overcurrent detection circuit. The execution entity of this method can be, for example, a processor.

[0302] Figure 12 This is a flowchart illustrating an overcurrent detection method provided in an embodiment of this application. Figure 12 As shown, the method may include, for example, the following steps:

[0303] S1201, The processor acquires the status signal output by the timing module 94 of the overcurrent detection circuit.

[0304] refer to Figure 2 The overcurrent detection circuit shown includes an overcurrent detection module 91 that detects overcurrent in the received signal; and a timing module 94 that generates a status signal based on the duration of a single overcurrent detected by the overcurrent detection module 91. The status signal is used to characterize whether an overcurrent has occurred. For example, the status signal can be a level signal; when characterizing an overcurrent, the status signal is 1; when characterizing no overcurrent, the status signal is 0.

[0305] For example, the processor can be connected to the timing module 94. The timing module 94 sends a status signal to the processor, which receives the status signal; or the processor reads the status signal from the timing module 94 to obtain the status signal.

[0306] S1202. The processor obtains the overcurrent detection result based on the status signal.

[0307] For example, a processor can obtain the overcurrent detection result by reading the level of a status signal. For instance, if the processor reads a status signal level of 1, it confirms that the overcurrent detection result is an overcurrent; if the processor reads a status signal level of 0, it confirms that the overcurrent detection result is no overcurrent.

[0308] In summary, the overcurrent detection method provided in this application obtains the overcurrent detection result by acquiring the status signal output by the timing module 94 of the overcurrent detection circuit. Since the status signal output by the timing module 94 has high accuracy in indicating whether an overcurrent has occurred, the accuracy of the overcurrent detection result can be improved.

[0309] Figure 13 This is a schematic flowchart of another overcurrent detection method provided in an embodiment of this application. Figure 13 As shown, in Figure 12 Based on the examples, the overcurrent detection method will be described in detail.

[0310] S1301, The processor configures the overcurrent detection module 91 with an overcurrent threshold so that the overcurrent detection module 91 performs overcurrent detection based on the received signal and the overcurrent threshold.

[0311] For example, the processor can be configured with a larger overcurrent threshold for the overcurrent detection module 91, so that the overcurrent detection module 91 detects the overcurrent when the overcurrent of the input signal is large, thus avoiding triggering unnecessary overcurrent protection; and the processor can also be configured with a smaller overcurrent threshold for the overcurrent detection module 91, so that the overcurrent detection module 91 detects the overcurrent when the overcurrent of the input signal is small, thereby improving the safety of the system.

[0312] In one example, the overcurrent detection module 91 includes an analog comparator 93.

[0313] Multiple overcurrent thresholds of the overcurrent detection module 91 can be stored in a register. Users can also adjust the comparator feedback resistor by adjusting the value of the externally matched sampling resistor to adjust the overcurrent threshold of the analog comparator 93.

[0314] Analog comparator 93 automatically turns on upon power-on, automatically turns off upon entering hibernation, and automatically turns on again upon returning to power-on standby mode. The processor can configure analog comparator 93 through registers, such as configuring overcurrent thresholds. During the operation of analog comparator 93, when the processor changes the register configuration, analog comparator 93 can respond to the changed configuration in real time.

[0315] In another example, the overcurrent detection module 91 includes an analog-to-digital converter 2 and a digital comparator 13.

[0316] The processor can control the digital comparator 13 to start and stop via instructions, and configure it via registers, such as configuring overcurrent thresholds. The digital comparator 13 can start / continue operation based on its current register configuration upon receiving a start instruction from the processor. During the operation of the digital comparator 13, changes to the register configuration by the processor do not affect the current detection of the digital comparator 13. That is, the configuration of the digital comparator 13 can depend only on the register configuration at the time of receiving the start instruction from the processor. If it is necessary to change the configuration while the digital comparator 13 is operating normally, the processor must first stop the digital comparator 13, change the register configuration, and then restart the digital comparator 13.

[0317] In one example, after the processor sends an enable instruction to digital comparator 13, it should reset digital comparator 13 to clear the effects of the previous overcurrent detection by digital comparator 13. For example, the processor can reset the following: overcurrent detection result flag, overcurrent detection filter threshold count, overcurrent detection manual control register, etc.

[0318] Before enabling digital comparator 13, the processor also needs to be configured to operate analog-to-digital converter 2 in continuous sampling mode.

[0319] For example, the analog-to-digital converter 2 can operate in different modes, such as continuous sampling mode, single sampling mode, etc. When the analog-to-digital converter 2 operates in continuous sampling mode, it can continuously receive the input signal and convert it into a digital signal for output. This allows the overcurrent detection module 91 to continuously detect overcurrent in the input signal.

[0320] In one example, if the overcurrent detection module 91 is enabled when the analog-to-digital converter 2 is not in continuous sampling mode, the processor can set the overcurrent fault flag bit, and the overcurrent detection module 91 will fail to be enabled; at the same time, the processor can use the overcurrent status flag bit to indicate the status of the overcurrent detection module 91.

[0321] S1302, The processor configures the overcurrent duration of the timing module 94 so that the timing module 94 generates a status signal based on the duration of a single overcurrent detected by the overcurrent detection module 91 and the overcurrent duration; the status signal is used to characterize whether an overcurrent has occurred.

[0322] For example, the processor can configure the overcurrent duration of the timing module 94 according to system requirements. For instance, the processor can configure the timing module 94 to have a larger overcurrent duration. When the overcurrent detection module 91 detects a single overcurrent with a longer duration, the timing module 94 generates a status signal representing the overcurrent. This can be applied to scenarios with high system interference levels, improving the accuracy of the overcurrent detection results. Alternatively, the processor can configure the timing module 94 to have a smaller overcurrent duration. When the overcurrent detection module 91 detects a single overcurrent with a shorter duration, the timing module 94 generates a status signal representing the overcurrent. This can be applied to scenarios with low system interference levels, improving the detection speed of the overcurrent detection results.

[0323] S1303, The processor acquires the status signal output by the timing module 94 of the overcurrent detection circuit.

[0324] S1304. The processor obtains the overcurrent detection result based on the status signal.

[0325] In summary, the overcurrent detection method provided in this application can achieve a balance between safe operation and stability by configuring the overcurrent threshold and the number of overcurrent cycles. It obtains the overcurrent detection result by acquiring the status signal output by the timing module 94 of the overcurrent detection circuit. Since the status signal output by the timing module 94 has high accuracy in indicating whether an overcurrent has occurred, the accuracy of the overcurrent detection result can be improved.

[0326] Figure 14 This is a flowchart illustrating the third overcurrent detection method provided in this application embodiment. Figure 14 As shown,

[0327] S1401, The processor obtains the offset parameters of the analog-to-digital converter 2 of the overcurrent detection circuit and sends them to the calibration module 8 of the overcurrent detection circuit so that the calibration module 8 performs offset calibration on the received signal according to the offset parameters.

[0328] The processor acquires the offset parameters of analog-to-digital converter 2, providing a calibration basis for offset calibration by calibration module 8. This improves the accuracy and stability of the detection signal.

[0329] For example, the processor can send a calibration command to the analog-to-digital converter 2, causing the converter to enter calibration mode. The processor can obtain the offset parameter of the converter by acquiring the deviation between the actual output signal and the theoretical signal. This offset parameter can be sent to the calibration module 8, for example, stored in the register of the calibration module 8; subsequently, when the converter 2 is operating normally, the calibration module 8 can perform offset calibration on the received signal based on the received offset parameter.

[0330] When there is no input signal, the processor can acquire N consecutive signals output by analog-to-digital converter 2, where N is a positive integer; based on the N consecutive output signals, the offset parameters of analog-to-digital converter 2 can be obtained. By acquiring N consecutive signals, the accuracy of the offset parameters can be improved.

[0331] The processor can perform calculations on N continuously output signals, such as calculating the mean or root mean square error of the N signals, to obtain the offset parameters of analog-to-digital converter 2.

[0332] Furthermore, the processor averages the N consecutively output signals to obtain the offset parameters of analog-to-digital converter 2. This method is simple to implement.

[0333] S1402, The processor obtains the gain error parameters of the amplification module 21 of the overcurrent detection circuit and sends them to the calibration module 8 of the overcurrent detection circuit so that the calibration module 8 can perform gain calibration on the received signal according to the gain error parameters.

[0334] The processor obtains the gain error parameters of the amplification module 21, providing a calibration basis for the calibration module 8 to perform gain calibration. This improves the accuracy and stability of the detected signal.

[0335] For example, the processor obtains the gain error parameter of the amplification module 21 based on the set gain parameter and the actual gain parameter; wherein the actual gain parameter is obtained based on the actual output signal of the amplification module 21 under the set gain parameter. For example, a known signal can be input to the overcurrent detection circuit, and the amplification module 21 detects the signal after amplification under the set gain parameter to obtain the actual output signal. The actual output signal divided by the input known signal yields the actual gain parameter. The processor obtains the gain error parameter of the amplification module 21 based on the deviation between the set gain parameter and the actual gain parameter. This gain error parameter can be sent to the calibration module 8, for example, stored in the register of the calibration module 8, and then the calibration module 8 can perform gain calibration on the received signal based on the received gain error parameter.

[0336] Specifically, the processor can divide the set gain parameter by the actual gain parameter to obtain the gain error parameter of the amplification module 21. Then, the calibration module 8 can multiply the received signal by the gain error parameter to perform gain calibration on the signal.

[0337] S1403, The processor obtains the passband compensation parameters of the rate adjustment module 7 of the overcurrent detection circuit and sends them to the calibration module 8 of the overcurrent detection circuit, so that the calibration module 8 performs passband compensation on the received signal according to the passband compensation parameters.

[0338] The passband compensation parameters acquired by the processor's rate adjustment module 7 provide a calibration basis for the calibration module 8 to perform passband compensation, thereby improving the accuracy and stability of the detection signal.

[0339] In one example, the processor can obtain the passband attenuation parameters of the rate adjustment module 7; and determine the passband compensation parameters based on the passband attenuation parameters.

[0340] For example, the processor can obtain the passband attenuation parameters by simulating or theoretically calculating the frequency response of the rate adjustment module 7 within the passband. By obtaining the passband attenuation parameters, the frequency range and attenuation amount requiring compensation can be identified. Based on the passband compensation parameters, the parameters of the compensation filter can be designed in the calibration module 8. For example, when the compensation filter is an FIR filter, the order, passband width, and stopband attenuation of the compensation filter can be designed to compensate for the passband attenuation of the rate adjustment module, thereby improving the accuracy of the detection data. These compensation parameters can be sent to the calibration module 8, for example, stored in the register of the calibration module 8. Then, the calibration module 8 can perform passband compensation on the received signal based on the received compensation parameters.

[0341] In summary, the overcurrent detection method provided in this application embodiment can improve the accuracy of the output signal by calibrating the received signal through the calibration module 8 of the overcurrent detection circuit by obtaining the calibration parameters of the overcurrent detection circuit.

[0342] This application also provides a battery management chip, including an overcurrent detection circuit.

[0343] This application also provides a battery system, including: a battery management chip and a battery pack.

[0344] This application also provides a transportation device, including a battery system.

[0345] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. An overcurrent detection circuit, characterized in that, include: The overcurrent detection module (91) receives the input signal and is used to perform overcurrent detection on the received signal; The timing module (94) is connected to the overcurrent detection module (91) and is used to generate a status signal based on the duration of a single overcurrent detected by the overcurrent detection module (91); the status signal is used to characterize whether there is an overcurrent.

2. The overcurrent detection circuit according to claim 1, characterized in that, The timing module (94) includes: a delay filter (95) and a result module (96); The delay filter (95) is connected to the overcurrent detection module (91) and is used to time the duration of a single overcurrent pulse output by the overcurrent detection module (91). The result module (96) is connected to the delay filter (95) and is used to generate a state signal characterizing the overcurrent when the timing result of the delay filter (95) reaches a preset overcurrent duration.

3. The overcurrent detection circuit according to claim 2, characterized in that, The delay filter (95) includes: a first counter (97) and a first register (98); The first counter (97) is connected to the first register (98), the result module (96), and the overcurrent detection module (91), and is used to time the duration of a single overcurrent pulse output by the overcurrent detection module (91) according to the overcurrent duration corresponding to the first register (98).

4. The overcurrent detection circuit according to claim 1, characterized in that, The overcurrent detection module (91) includes: an analog comparator (93); The analog comparator (93) is connected to the timing module (94) and is used to output an overcurrent pulse to the timing module (94) if the received signal exceeds the set overcurrent threshold.

5. The overcurrent detection circuit according to claim 4, characterized in that, The overcurrent detection module (91) further includes: a second register (90) and a multiplexer (99); The multiplexer (99) is connected to the second register (90) and the analog comparator (93); The second register (90) is used to store the gear position indication signal; the multiplexer (99) is used to select and output the corresponding overcurrent threshold from multiple overcurrent thresholds according to the gear position indication signal and output it to the analog comparator (93).

6. The overcurrent detection circuit according to claim 1, characterized in that, The overcurrent detection module (91) includes: an analog-to-digital converter (2) and a digital comparator (13); The analog-to-digital converter (2) receives the input signal and converts the input signal into a digital signal; The digital comparator (13) is connected to the analog-to-digital converter (2) and the timing module (94). If the received signal exceeds the set overcurrent threshold, it outputs a first-state overcurrent signal to the timing module (94); if the received signal does not exceed the set overcurrent threshold, it outputs a second-state overcurrent signal to the timing module (94).

7. The overcurrent detection circuit according to claim 6, characterized in that, The overcurrent detection module (91) also includes: The first processing module (1) is connected to the analog-to-digital converter (2) and is used to increase the amplitude of the first amplitude input signal to the second amplitude and transmit the second amplitude input signal to the analog-to-digital converter (2). The second processing module (3) is connected to the analog-to-digital converter (2) and the timing module (94) and is used to restore the amplitude of the output signal of the analog-to-digital converter (2) to the first amplitude and then transmit it to the timing module (94).

8. The overcurrent detection circuit according to claim 7, characterized in that, The first processing module (1) includes: an amplification module (21) and a gain control module (4); The amplification module (21) is connected to the gain control module (4) and the analog-to-digital converter (2); The amplification module (21) is used to amplify the input signal according to the gain parameter so that the amplitude of the amplified input signal is the second amplitude, and transmit the signal with the second amplitude to the analog-to-digital converter (2); The gain control module (4) is used to adjust the gain parameter of the amplification module (21) according to the first amplitude.

9. The overcurrent detection circuit according to claim 8, characterized in that, The second processing module (3) includes: a divider (32); The divider (32) is connected to the analog-to-digital converter (2) and the timing module (94) and is used to divide the signal output by the analog-to-digital converter (2) by the gain parameter so as to restore the signal output by the analog-to-digital converter (2) and output it to the timing module (94).

10. The overcurrent detection circuit according to any one of claims 1 to 9, characterized in that, The overcurrent detection circuit further includes: an overcurrent logic module (17); The overcurrent logic module (17) is connected to the timing module (94) and is used to receive the status signal output by the timing module (94) and convert it into an overcurrent output signal.

11. The overcurrent detection circuit according to claim 10, characterized in that, The overcurrent detection circuit further includes: an output enable module (18); The output enable module (18) is connected to the overcurrent logic module (17) and is used to control whether to output the overcurrent output signal.

12. The overcurrent detection circuit according to any one of claims 1 to 9, characterized in that, The overcurrent detection circuit further includes: a status indication module (19); The status indication module (19) is connected to the timing module (94) and is used to indicate the overcurrent status according to the status signal output by the timing module (94).

13. An overcurrent detection method, based on the overcurrent detection circuit as described in any one of claims 1 to 12, characterized in that, include: Obtain the status signal output by the timing module (94) of the overcurrent detection circuit; The overcurrent detection result is obtained based on the status signal.

14. A battery management chip, characterized in that, include: The overcurrent detection circuit as described in any one of claims 1 to 12.

15. A battery system, characterized in that, include: The battery management chip as described in claim 14, and the battery pack.

16. A transportation device, characterized in that, include: The battery system as described in claim 15.

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