A method, apparatus, and system for testing a dielectric material

Abstract

The application discloses a dielectric material testing method, device and system, and belongs to the technical field of quantum chip characterization. The dielectric material testing method comprises the following steps: forming a first metal layer and a second metal layer which are spaced apart on the surface of a substrate; preparing a dielectric layer and a third metal layer which are sequentially stacked on part of the surface of the first metal layer, and electrically connecting the third metal layer and the second metal layer through a conductive element; and obtaining the relative dielectric constant of the dielectric layer according to the parallel-plate capacitor formed by the first metal layer, the dielectric layer and the third metal layer at the stacking position. In the manner, the parallel-plate capacitor can be tested through the first metal layer and the second metal layer, and the relative dielectric constant of the dielectric layer can be obtained according to the capacitance information.

Description

Technical Field

[0001] This application belongs to the field of quantum chip characterization technology, and in particular relates to a testing method, apparatus and system for dielectric materials. Background Technology

[0002] In the critical process of developing superconducting quantum chip technology, accurately characterizing the relative permittivity of specific thin films is an extremely important step. For example, the accurate determination of the relative permittivity of Al2O3 thin films prepared by ALD (atomic layer deposition) or SiO2 thin films prepared by PECVD (plasma-enhanced chemical vapor deposition) plays a crucial supporting role in achieving performance in subsequent process development.

[0003] In traditional techniques, the parallel-plate capacitance method is generally used to accurately characterize the relative permittivity of a specific thin film. The principle is that the capacitance of a parallel-plate capacitor is related to the area of ​​the plates, the distance between the plates, and the permittivity of the dielectric material between the plates. By measuring the capacitance of the parallel-plate capacitor when the plates are in a vacuum (or air, with a relative permittivity approximately 1) and when a specific dielectric thin film is placed inside, the relative permittivity of the specific thin film can be calculated using a formula.

[0004] However, in traditional methods for measuring the capacitance of parallel-plate capacitors, the probes of the capacitance testing device can easily puncture the plates, causing conductivity between the upper and lower plates and making it impossible to effectively measure the capacitance value. Alternatively, it is necessary to add test leads to the upper and lower plates separately and measure the capacitance value through the test leads, which is undoubtedly relatively complicated. Therefore, there is an urgent need for an accurate and convenient method to characterize the relative permittivity of a specific thin film. Summary of the Invention

[0005] The purpose of this application is to provide a testing method, apparatus, and system for dielectric materials to solve the problem of accurately and conveniently characterizing the relative permittivity of a specific thin film in the prior art. It can quickly test the relative permittivity of a specific thin film and greatly avoid the problem of capacitor failure caused by testing.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for testing dielectric materials, comprising:

[0007] A first metal layer and a second metal layer spaced apart are formed on the substrate surface;

[0008] A dielectric layer and a third metal layer are sequentially stacked on a portion of the surface of the first metal layer, and the third metal layer is electrically connected to the second metal layer through a conductive element.

[0009] The relative permittivity of the dielectric layer is obtained from the parallel-plate capacitor constructed at the stacking point of the first metal layer, the dielectric layer, and the third metal layer.

[0010] Preferably, the method for forming a spaced-apart first metal layer and a second metal layer on the substrate surface includes:

[0011] Prepare a metal layer covering the surface of the substrate;

[0012] The metal layer is etched to form a channel that divides the metal layer into a first metal layer and a second metal layer.

[0013] Preferably, the method for preparing a dielectric layer and a third metal layer sequentially stacked on a portion of the surface of the first metal layer is as follows:

[0014] The dielectric layer is formed on a portion of the surface of the first metal layer near the second metal layer;

[0015] A third metal layer is formed on the surface of the dielectric layer opposite to the first metal layer.

[0016] Preferably, the method for forming a third metal layer on the surface of the dielectric layer opposite to the first metal layer is as follows:

[0017] A photoresist layer is formed that covers the dielectric layer and has a window exposing at least a portion of the dielectric layer;

[0018] The third metal layer is formed on the surface of the dielectric layer through the window.

[0019] Preferably, the second metal layer includes a plurality of second sub-layers, and the third metal layer includes a plurality of third sub-layers;

[0020] The number of the second sub-layer and the third sub-layer are the same, and they are electrically connected one-to-one through the conductive element;

[0021] And / or, at least one of the third sublayers has a different area than the other third sublayers.

[0022] This application also provides a method for testing dielectric materials, including:

[0023] A dielectric layer and a third metal layer are sequentially stacked on a portion of the surface of a metal thin film formed on a substrate.

[0024] The area of ​​the metal thin film not covered by the dielectric layer is etched to form a first metal layer including the portion of the surface and a second metal layer spaced apart from the first metal layer, and the third metal layer is electrically connected to the second metal layer through a conductive element;

[0025] The relative permittivity of the dielectric layer is obtained from the parallel-plate capacitor constructed at the stacking point of the first metal layer, the dielectric layer, and the third metal layer.

[0026] This application also provides a dielectric layer testing apparatus, comprising:

[0027] The substrate has a first metal layer and a second metal layer separated from each other on its surface.

[0028] A dielectric layer and a third metal layer are stacked on a portion of the surface of the first metal layer; and

[0029] A conductive element that electrically connects the third metal layer and the second metal layer.

[0030] Preferably, the second metal layer includes a plurality of second sub-layers, and the third metal layer includes a plurality of third sub-layers;

[0031] The number of the second sub-layer and the third sub-layer are the same, and they are electrically connected one-to-one through the conductive element;

[0032] And / or, at least one of the third sublayers has a different area than the other third sublayers.

[0033] This application also provides a system for testing dielectric layers, comprising: the aforementioned testing apparatus;

[0034] A testing device is used to test and obtain the capacitance information of a parallel plate capacitor constructed by the first metal layer, the dielectric layer, and the third metal layer. The capacitance information includes at least: the overlap area of ​​the first metal layer, the dielectric layer, and the third metal layer, the capacitance value of the parallel plate capacitor, and the thickness of the dielectric layer.

[0035] A computing device for calculating, at least based on the capacitance information, the relative permittivity of the dielectric layer.

[0036] Preferably, the testing device includes two probes, one probe for penetrating the area of ​​the first metal layer not covered by the dielectric layer, and the other probe for penetrating the second metal layer.

[0037] Compared with the prior art, this application prepares a parallel plate capacitor in which the first metal layer, as the bottom plate of the capacitor, is not completely covered by the dielectric layer, and the second metal layer is electrically connected to the third metal layer, which is the top plate of the capacitor. The capacitance information of the capacitor can be obtained by testing the area not covered by the first metal layer and the second metal layer together, and the relative permittivity of the dielectric layer can be obtained based on the capacitance information. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a conventional parallel-plate capacitor provided in the embodiments of this application;

[0039] Figure 2This is a schematic diagram illustrating the steps of the testing method for dielectric materials provided in the embodiments of this application;

[0040] Figure 3 This is a front view of the structure of a parallel plate capacitor provided in an embodiment of this application;

[0041] Figure 4 A top view of another parallel-plate capacitor provided in an embodiment of this application;

[0042] Figure 5 This is a partial system schematic diagram for testing dielectric layers provided in an embodiment of this application.

[0043] Explanation of reference numerals in the attached drawings: 1-substrate, 2-first metal layer, 3-second metal layer, 4-dielectric layer, 5-third metal layer, 6-conductive element. Detailed Implementation

[0044] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0045] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0046] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0048] In the fabrication process of superconducting quantum chips, testing the relative permittivity of specific thin films is crucial. This plays an important role in optimizing the design of superconducting quantum chips, reducing losses, improving signal transmission efficiency, screening materials, and supporting simulation modeling. It is a key step in improving the performance of superconducting quantum chips.

[0049] Please refer to Figure 1 In traditional techniques, the parallel-plate capacitance method is a commonly used method for measuring the relative permittivity of a specific thin film. The method involves preparing a capacitor with a parallel-plate structure and using a corresponding capacitance measuring instrument (such as an LCR bridge) to test the capacitance of the parallel-plate capacitor without the thin film inserted under specific frequency and voltage conditions. Then, a thin film sample is inserted between the parallel-plate capacitors, and the capacitance is measured again using the capacitance measuring instrument. Finally, the relative permittivity of this specific thin film can be calculated based on the two capacitance measurements and the basic parameters of the parallel-plate capacitor.

[0050] However, when testing the capacitance of a parallel-plate capacitor, the electrode plates are very thin. When using a capacitance measuring instrument, the probe may penetrate the plates, causing a short circuit between the upper and lower plates, thus preventing an accurate capacitance reading. To avoid this, a traditional method involves adding test leads to the upper and lower plates. The capacitance measuring instrument's probe is electrically connected to these leads for testing. However, the resistivity of the test leads themselves, as well as the resistance of the connection between them and the plates, is often significant. Therefore, this method may result in inaccurate capacitance readings, making it impossible to accurately characterize the relative permittivity of the thin film.

[0051] refer to Figure 2 As shown in one embodiment of this application, this application provides a method for testing dielectric materials, the method steps of which include:

[0052] S1: A first metal layer 2 and a second metal layer 3 are formed on the surface of the substrate 1, spaced apart;

[0053] S2: A dielectric layer 4 and a third metal layer 5 are sequentially stacked on a portion of the surface of the first metal layer 2, and the third metal layer 5 is electrically connected to the second metal layer 3 through a conductive element 6.

[0054] S3: The relative permittivity of the dielectric layer 4 is obtained based on the parallel plate capacitor constructed at the stacking point of the first metal layer 2, the dielectric layer 4, and the third metal layer 5.

[0055] In this embodiment, a parallel-plate capacitor is first prepared, which can be used to test the relative permittivity of a specific thin film. More precisely, the material to be tested is prepared as the dielectric layer 4 of the parallel-plate capacitor, and then the relative permittivity of the dielectric layer 4 can be calculated based on the capacitance information of this capacitor.

[0056] When fabricating a parallel-plate capacitor, the first step is to determine the material to be used as the substrate 1. Generally, the substrate 1 material needs to have good insulation properties and high insulation resistance to prevent charge leakage between the capacitor plates, reduce energy loss, and thus ensure stable capacitor performance. It also needs a suitable dielectric constant; a higher dielectric constant can increase the capacitor's capacitance, but it may also introduce other unforeseen problems. Furthermore, it must have good mechanical properties, possessing sufficient strength and hardness to support the plates and maintain their relative positional stability. Additionally, it needs good thermal and chemical stability to prevent damage from various external environmental factors. Therefore, the substrate 1 can be selected from materials such as ceramics, polymers, metal oxides, and silicon-based materials.

[0057] Then, a first metal layer 2 and a second metal layer 3 are formed on the surface of the substrate 1. The two can be prepared by the same coating step or separately. It should be noted that at least the first metal layer 2 is prepared to the bottom electrode thickness preset by the parallel plate capacitor.

[0058] For example, the first metal layer 2 and the second metal layer 3 can be prepared using physical vapor deposition or chemical vapor deposition. Among them, the most typical technique in physical vapor deposition is magnetron sputtering, that is, the target material is placed in a vacuum chamber, and the target material is bombarded by ions, so that the target material atoms are sputtered out and deposited on the surface of the substrate 1 to form a thin film. This method can precisely control the thickness and composition of the thin film to prepare a high-quality thin film.

[0059] It is important to note that the substrate 1 surface needs to undergo rigorous cleaning and pretreatment before coating to remove oil, impurities, and oxide layers, ensuring good adhesion between the first metal layer 2 and the second metal layer 3 and the substrate 1 surface. Methods such as chemical cleaning or plasma cleaning can be used. Then, during the coating process, various parameters need to be precisely controlled, such as coating temperature, vacuum level, sputtering power, and gas flow rate, to accurately control the growth rate, crystal structure, surface morphology, and performance of the first and second metal layers 2 and 3. Finally, the quality of the first and second metal layers 2 and 3 needs to be inspected, such as using a profilometer or ellipsometry to measure their thickness.

[0060] After the first metal layer 2 and the second metal layer 3 are prepared, a dielectric layer 4 and a third metal layer 5 are prepared on a portion of the surface of the first metal layer 2, that is, the other portion of the surface of the first metal layer 2 is not covered by the dielectric layer 4 and the third metal layer 5. The first metal layer 2 is prepared as the bottom electrode of the capacitor, or the first metal layer 2 is integrally formed with the bottom electrode of the capacitor. Therefore, the capacitor can be tested on the area of ​​the first metal layer 2 that is not covered, thereby avoiding damage to the dielectric layer 4 during testing. Even the auxiliary equipment with amplification effect can be eliminated during testing.

[0061] Unlike existing technologies, the third metal layer 5 is also electrically connected to the second metal layer 3 via a conductive element 6. The conductive element 6 can be a wire, a connecting bridge, or other device structure that enables two-point electrical connection. Since the third metal layer 5 serves as the top plate of the capacitor, when performing capacitance testing, because the third metal layer 5 is also electrically connected to the second metal layer 3 via the conductive element 6, the second metal layer 3 can be directly tested for electrical connection, thus avoiding damage to the third metal layer 5 (top plate) and preventing capacitor failure.

[0062] like Figure 3 As shown, in the device prepared based on the above information, the first metal layer 2, the dielectric layer 4, and the third metal layer 5 are stacked to form a parallel plate capacitor, and the capacitance information of the capacitor can be obtained by testing the second metal layer 3 and the first metal not covered by the dielectric layer.

[0063] Specifically, the capacitance value of a capacitor can be expressed by the formula C = ε. o ε s S / d represents the capacitance, where C represents the capacitance and ε represents the capacitance. o ε is the vacuum permittivity. s Let S be the relative permittivity of dielectric layer 4, S be the stacked area of ​​the first metal layer 2, dielectric layer 4, and third metal layer 5, and d be the spacing between the first metal layer 2 and the third metal layer 5 (the thickness of dielectric layer 4). Therefore, capacitance is directly proportional to the relative permittivity and the plate area, and inversely proportional to the plate spacing. For example, the capacitance C can be obtained by measuring the CV curve of a parallel-plate capacitor using a dedicated capacitance meter (e.g., a semiconductor characteristic analyzer), and then the thickness d of dielectric layer 4 can be measured using an ellipsometry. The relative permittivity of dielectric layer 4 can then be calculated.

[0064] In a specific embodiment, the method for forming a spaced-apart first metal layer 2 and second metal layer 3 on the surface of substrate 1 includes:

[0065] Prepare a metal layer covering the surface of substrate 1;

[0066] The etching of the metal layer forms a channel that divides the metal layer into a first metal layer 2 and a second metal layer 3.

[0067] According to the method described in the foregoing embodiments, a metal layer covering the surface of the substrate 1 is formed, and the material of the metal layer can be a metal such as niobium.

[0068] A uniform positive photoresist is spin-coated onto the surface of the metal layer, and the channel pattern on the photomask is transferred to the photoresist and exposed and developed. For etching the niobium metal layer, dry etching can be used. Commonly used etching gases include chlorine-containing gases such as chlorine (Cl2) and boron trichloride (BCl3), and inert gases such as helium (He). For example, a mixture of Cl2 and BCl3 can be used, where Cl2 provides the active chlorine atoms required for etching and reacts chemically with the niobium metal; BCl3 can assist etching and adjust the etching rate and selectivity; and He can be used to adjust the properties of the plasma and improve etching uniformity. In another optional embodiment, wet etching can also be used to etch the metal layer to achieve segmentation.

[0069] In another embodiment of this application, the method for preparing a dielectric layer 4 and a third metal layer 5 sequentially stacked on a portion of the surface of the first metal layer 2 is as follows:

[0070] The dielectric layer 4 is formed on a portion of the surface of the first metal layer 2 near the second metal layer 3;

[0071] A third metal layer 5 is formed on the surface of the dielectric layer 4 that is opposite to the first metal layer 2.

[0072] More specifically, a photoresist layer is first formed on the surface of the first metal layer 2. Then, the photoresist layer is etched to form a window exposing a portion of the surface of the first metal layer 2 near the second metal layer 3. Finally, a dielectric layer 4 is formed on the surface of the first metal layer through the window. The photoresist layer also covers the second metal layer 3 and the aforementioned channel. Then, an exposure and development process is applied to the photoresist layer, exposing a portion of the first metal layer 2, with this portion of the first metal layer 2 close to the second metal layer 3, so as to facilitate the electrical connection between the top plate of the fabricated parallel plate capacitor and the second metal layer 3.

[0073] For example, the material of dielectric layer 4 can be aluminum oxide, and aluminum oxide dielectric layer 4 is grown using atomic layer deposition (ALD) or chemical vapor deposition (CVD) methods. Taking ALD as an example, the substrate is placed in an ALD device, and an aluminum source (such as trimethylaluminum) and an oxygen source (such as water vapor or ozone) are introduced. The two gases are alternately pulsed to grow an aluminum oxide film layer by layer on the substrate surface.

[0074] It should be noted that the relative stacking areas of the first metal layer 2, dielectric layer 4, and third metal layer 5 are the same as the preset values, that is, the relative area of ​​the parallel plate capacitor is controllable, which is beneficial for subsequent measurement and calculation of various capacitance values ​​of the capacitor.

[0075] Based on the foregoing embodiments, the method for preparing a dielectric layer 4 and a third metal layer 5 sequentially stacked on a portion of the surface of the first metal layer 2 is as follows:

[0076] Step 1: Form the dielectric layer 4 on the surface of the first metal layer 2 near the second metal layer 3;

[0077] The second step is to prepare a third metal layer 5 on the surface of the dielectric layer 4 that is opposite to the first metal layer 2.

[0078] In practice, a photoresist layer covering the dielectric layer 4 is first formed; then the photoresist layer is etched to form a window that exposes at least part of the dielectric layer 4; finally, a third metal layer 5 is formed within the window.

[0079] When etching photoresist to form a window, it is important to note that the size of the window is smaller than the size of dielectric layer 4, and the window is within the edge of dielectric layer 4. Therefore, the relative overlapping area of ​​the parallel plate capacitors is equal to the area of ​​the window.

[0080] In such Figure 4 In another embodiment shown, the windows can be configured as multiple non-overlapping windows. The third metal layer 5 formed on the surface of the dielectric layer 4 through the windows also includes multiple third sublayers. In this case, multiple parallel plate capacitors can be fabricated at once, and the overlapping area corresponding to each parallel plate can be considered as the area size of each third sublayer. Furthermore, since the third metal layer 5 and the second metal layer 3 are electrically connected through the conductive element 6, the second metal layer 3 is also correspondingly fabricated to include multiple second sublayers, and the number of second and third sublayers is the same. Each second sublayer is electrically connected to one third sublayer in a one-to-one correspondence through the conductive element 6. For example, the conductive element 6 can be an electrical wire.

[0081] Furthermore, when fabricating the third metal layer 5 on the surface of the dielectric layer 4, in order to achieve the comparison of multiple capacitors and to more accurately test the relative permittivity of the dielectric layer 4, at least one of the third sublayers can be designed to have a different size than the other third sublayers, or even each third sublayer can have a different size. This allows multiple parallel plate capacitors with different overlapping areas to be fabricated simultaneously to achieve the comparison purpose and to ensure the relative permittivity of the dielectric layer 4 to the greatest extent.

[0082] In another optional embodiment, a method for testing the dielectric layer 4 is also provided, the method comprising:

[0083] A dielectric layer 4 and a third metal layer 5 are sequentially stacked on a portion of the surface of a metal thin film formed on the surface of substrate 1;

[0084] The area of ​​the metal thin film not covered by the dielectric layer 4 is etched to form a first metal layer 2 including the partial surface and a second metal layer 3 spaced apart from the first metal layer 2, and the third metal layer 5 is electrically connected to the second metal layer 3 through a conductive element 6;

[0085] The relative permittivity of dielectric layer 4 is obtained from the parallel plate capacitor constructed at the stacking point of the first metal layer 2, the dielectric layer 4, and the third metal layer 5.

[0086] First, a uniformly thick metal layer, such as niobium, is formed on the surface of substrate 1 using methods such as magnetron sputtering. Then, a dielectric layer 4 and a third metal layer 5 are sequentially fabricated on the surface of the metal layer facing away from substrate 1. It is important to note that the dielectric layer 4 only covers a portion of the surface of the metal layer. The metal layer, dielectric layer 4, and third metal layer 5 form a parallel plate capacitor at their overlap. Furthermore, the third metal layer 5 can be configured as multiple spaced sublayers, each with a different size, thereby enabling the fabrication of multiple parallel plate capacitors in a single operation.

[0087] After the parallel plate is prepared, the metal layers are etched and divided to form a separated first metal layer 2 and second metal layer 3. Part of the surface of the first metal layer 2 is covered by a dielectric layer 4, and the second metal layer 3 is electrically connected to the third metal layer 5 through a conductive element 6.

[0088] When testing the relative permittivity of dielectric layer 4, the capacitance information of the parallel plate capacitor can be obtained by measuring the areas not covered by the second metal layer 3 and the first metal layer 2, and then the relative permittivity of dielectric layer 4 can be calculated using the capacitance information.

[0089] In this application, Figure 5 In one embodiment shown, a testing apparatus for dielectric layer 4 is also provided, the apparatus comprising:

[0090] A substrate 1 has a first metal layer 2 and a second metal layer 3 separated from each other on its surface;

[0091] A dielectric layer 4 and a third metal layer 5 are stacked on a portion of the surface of the first metal layer 2; and

[0092] The conductive element 6 is electrically connected to the third metal layer 5 and the second metal layer 3.

[0093] Specifically, the first metal layer 2, the dielectric layer 4, and the third metal layer 5 form a parallel-plate capacitor at the stacking point. The third metal layer 5 can be configured to include multiple third sublayers, each of which, along with the dielectric layer 4 and the first metal layer 2, forms a parallel-plate capacitor at the stacking point. Furthermore, the size and area of ​​one or more third sublayers can be set differently to obtain multiple parallel-plate capacitors of different models. This allows for comparison during subsequent testing, enabling more accurate calculation of the relative permittivity of the dielectric layer 4.

[0094] Furthermore, to enable testing of the parallel-plate capacitor, the second metal layer 3 is manufactured to include multiple second sublayers, with the number of second sublayers matching the number of third sublayers. These sublayers are electrically connected in a one-to-one correspondence via conductive elements 6. Here, the conductive element 6 can be a wire or similar structure used to achieve the electrical connection between the two layers.

[0095] In one embodiment of this application, a system for testing a dielectric layer 4 is also provided, including the testing apparatus for the dielectric layer 4 described in the foregoing embodiments, a testing device, and a computing device. The testing apparatus is used to test and obtain capacitance information of a parallel-plate capacitor constructed by the first metal layer 2, the dielectric layer 4, and the third metal layer 5; the computing device is used to calculate, at least based on the capacitance information, the relative permittivity of the dielectric layer 4. The capacitance information includes at least: the overlap area between the third metal layer 5 and the dielectric layer 4, the capacitance value of the parallel-plate capacitor, and the thickness of the dielectric layer 4.

[0096] The overlapping area of ​​the third metal layer 5 and the dielectric layer 4 can be observed using an optical microscope on a parallel plate capacitor under magnification. The length and width of the overlapping portion can be measured using the microscope's built-in scale or image analysis software, and then the overlapping area can be calculated using the formula for the area of ​​a rectangle. Alternatively, an electron microscope can be used for testing, offering better resolution and allowing for more precise observation of the substrate's microstructure and dimensions.

[0097] The capacitance value of a parallel plate capacitor can be tested using a capacitance testing instrument. By applying an AC signal of a certain frequency and amplitude to the capacitor, the voltage and current across the capacitor are measured. Based on the definition of capacitance and related circuit principles, the capacitance value can be calculated. For example, the capacitance C can be obtained by measuring the CV curve using a semiconductor characteristic analyzer.

[0098] The thickness of dielectric layer 4 can be measured using methods such as ellipsometer measurement or step meter measurement. For example, a parallel plate capacitor is placed on the sample stage of the ellipsometer, and the position and angle of the sample are adjusted so that the light accurately illuminates the surface of dielectric layer 4. Then, the ellipsometer is started to measure the polarization parameters after reflection. Finally, based on the measured polarization parameters and the preset optical model of dielectric layer 4, the thickness of dielectric layer 4 is calculated using the software that comes with the ellipsometer.

[0099] In this embodiment, the testing device includes at least a semiconductor parameter analyzer for testing the capacitance value of a parallel-plate capacitor. Specifically, the capacitance value is calculated by accurately measuring the applied AC voltage, AC current, and AC signal frequency. The two probes of the semiconductor parameter analyzer are inserted into the portion of the first metal layer 2 not covered by the dielectric layer 4 and the second metal layer 3, respectively. After setting the parameters, the measurement function of the semiconductor parameter analyzer is activated. The instrument automatically applies an AC signal and measures the corresponding current and voltage values, then obtains the capacitance value based on the aforementioned principle.

[0100] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0101] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A method for testing dielectric materials, characterized in that, include: A first metal layer (2) and a second metal layer (3) are formed on the surface of a substrate (1) at intervals; A dielectric layer (4) and a third metal layer (5) are sequentially stacked on a portion of the surface of the first metal layer (2), and the third metal layer (5) is electrically connected to the second metal layer (3) through a conductive element (6); The relative permittivity of the dielectric layer (4) is obtained from the parallel plate capacitor constructed at the stacking point of the first metal layer (2), the dielectric layer (4) and the third metal layer (5).

2. The test method according to claim 1, characterized in that, The method of forming a spaced-apart first metal layer (2) and second metal layer (3) on the surface of a substrate (1) includes: Prepare a metal layer covering the surface of the substrate (1); The metal layer is etched to form a channel that divides the metal layer into a first metal layer (2) and a second metal layer (3).

3. The test method according to claim 1, characterized in that, The method for preparing a dielectric layer (4) and a third metal layer (5) sequentially stacked on a portion of the surface of the first metal layer (2) is as follows: The dielectric layer (4) is formed on a portion of the surface of the first metal layer (2) near the second metal layer (3); A third metal layer (5) is formed on the surface of the dielectric layer (4) that is opposite to the first metal layer (2).

4. The test method according to claim 3, characterized in that, The method for forming a third metal layer (5) on the surface of the dielectric layer (4) opposite to the first metal layer (2) is as follows: A photoresist layer is formed covering the dielectric layer (4) and having a window exposing at least a portion of the dielectric layer (4); The third metal layer (5) is formed on the surface of the dielectric layer (4) through the window.

5. The test method according to any one of claims 1 to 4, characterized in that, The second metal layer (3) includes a plurality of second sublayers, and the third metal layer (5) includes a plurality of third sublayers; The number of the second sub-layer and the third sub-layer are the same, and they are electrically connected one-to-one through the conductive element (6); And / or, at least one of the third sublayers has a different area than the other third sublayers.

6. A method for testing dielectric materials, characterized in that, include: A dielectric layer (4) and a third metal layer (5) are sequentially stacked on a portion of the surface of the metal thin film formed on the substrate (1); The area of ​​the metal thin film not covered by the dielectric layer (4) is etched to form a first metal layer (2) including the partial surface and a second metal layer (3) spaced apart from the first metal layer (2), and the third metal layer (5) is electrically connected to the second metal layer (3) through a conductive element (6); The relative permittivity of the dielectric layer (4) is obtained from the parallel plate capacitor constructed at the stacking point of the first metal layer (2), the dielectric layer (4) and the third metal layer (5).

7. A testing apparatus for a dielectric layer (4), characterized in that, include: A substrate (1) has a first metal layer (2) and a second metal layer (3) separated from each other on its surface; A dielectric layer (4) and a third metal layer (5) are stacked on a portion of the surface of the first metal layer (2); as well as The conductive element (6) electrically connects the third metal layer (5) and the second metal layer (3).

8. The testing apparatus according to claim 7, characterized in that, The second metal layer (3) includes a plurality of second sublayers, and the third metal layer (5) includes a plurality of third sublayers; The number of the second sub-layer and the third sub-layer are the same, and they are electrically connected one-to-one through the conductive element (6); And / or, at least one of the third sublayers has a different area than the other third sublayers.

9. A system for testing a dielectric layer (4), characterized in that, include: The testing apparatus as described in claim 8; The testing device is used to test and obtain the capacitance information of the parallel plate capacitor constructed by the first metal layer (2), the dielectric layer (4) and the third metal layer (5). The capacitance information includes at least: the overlapping area of ​​the first metal layer (2), the dielectric layer (4) and the third metal, the capacitance value of the parallel plate capacitor and the thickness of the dielectric layer (4). A computing device is used to calculate, at least based on the capacitance information, the relative permittivity of the dielectric layer (4).

10. The system according to claim 9, characterized in that, The testing device includes two probes, one of which is used to penetrate the area of ​​the first metal layer (2) not covered by the dielectric layer (4), and the other probe is used to penetrate the second metal layer (3).

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