Method and apparatus for evaluating dynamic stress of power semiconductor device turn-off, and electronic device

Abstract

The application discloses a kind of power semiconductor device shutdown dynamic stress evaluation method, device and electronic equipment.The method comprises: obtaining the gate voltage waveform in the process of power semiconductor device shutdown, identifying shutdown miller platform interval and extracting shutdown miller platform voltage characteristic value;Based on the shutdown miller platform voltage characteristic value and the preset mapping relationship corresponding to the current working condition, determine at least one of the evaluation value of the overvoltage amplitude, current change rate, voltage change rate and shutdown loss shutdown dynamic stress parameter;According to the evaluation value and the corresponding safety limit value, determine the safety working margin, and generate gate drive parameter adjustment instruction or protection instruction based on the safety working margin, to adjust subsequent shutdown process or trigger protection action.The application can indirectly evaluate high-voltage side shutdown dynamic stress by using low-voltage side gate voltage characteristics, and provide quantitative basis for gate drive parameter adjustment and hierarchical protection.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device condition monitoring and drive protection technology, and in particular to a method, apparatus and electronic device for evaluating the dynamic stress of power semiconductor device shutdown. Background Technology

[0002] In high-voltage, high-power power electronic equipment, power semiconductor devices experience dynamic stresses during turn-off, including collector-emitter voltage overshoot, rate of change of current, rate of change of voltage, and turn-off losses. These dynamic stresses directly affect whether the device operates within a safe operating range and the reliability of the system. Current technologies for assessing turn-off dynamic stress typically rely on direct measurement of the collector-emitter voltage and collector current. For high-voltage, high-current, and multi-chip parallel press-fit power semiconductor devices, this measurement method places high demands on the sensor's insulation performance, bandwidth, common-mode rejection capability, and installation location. Furthermore, it is susceptible to the effects of parasitic parameters in the commutation circuit and electromagnetic interference, making it difficult to directly apply to long-term online monitoring in practical equipment.

[0003] Existing research has utilized the coupling relationship between gate voltage and the main power circuit for overcurrent detection. For example, Li et al., in their paper "Indirect IGBT Over-Current Detection Technique Via Gate Voltage Monitoring and Analysis," proposed indirectly identifying IGBT overcurrent by monitoring the gate voltage and triggering protection based on the detection results. This type of scheme typically uses gate voltage thresholds or characteristic points as the basis for judgment, enabling overcurrent or short-circuit state identification. However, it primarily outputs discrete state judgment results, making it difficult to obtain quantitative assessments of turn-off dynamic stress parameters such as voltage overshoot, current change rate, voltage change rate, and turn-off losses. Furthermore, it is difficult to determine the device's remaining margin relative to the safety boundary based on these parameters.

[0004] In actual operation, power semiconductor devices may experience transient operating points exceeding their rated current due to sudden load changes, fault ride-through, or short-term overload. Rated current is typically used to characterize the device's continuous operating capability but cannot independently reflect transient turn-off safety under specific DC bus voltage, device temperature, and gate drive conditions. Using only whether the turn-off current exceeds the rated value as the basis for protection may lead to overly conservative protection strategies and may underestimate the actual turn-off risk when the DC bus voltage increases, device temperature changes, or gate drive parameter mismatches occur. Therefore, it is necessary to utilize readily available gate voltage characteristics on the drive side, especially the voltage characteristics during the turn-off Miller plateau phase, and combine this with operating condition information such as DC bus voltage, device temperature, and gate drive parameters to assess the turn-off dynamic stress and safe operating margin of power semiconductor devices. This provides a basis for adjusting gate drive parameters, setting protection thresholds, and implementing tiered protection. Summary of the Invention

[0005] The purpose of this invention is to provide a method, apparatus, and electronic device for evaluating the dynamic stress of power semiconductor devices during turn-off. This method indirectly quantifies and evaluates the turn-off stress on the high-voltage side using the low-voltage side gate signal, avoiding the difficulties of direct measurement on the high-voltage side and improving the accuracy and reliability of device safety margin evaluation under overcurrent conditions.

[0006] The technical solution of this invention is as follows:

[0007] A method for evaluating the dynamic stress during the turn-off of a power semiconductor device includes the following steps:

[0008] Step 1: Obtain the gate voltage waveform of the power semiconductor device during the turn-off process;

[0009] Step 2: Determine the turn-off Miller plateau interval based on the gate voltage waveform, and extract the turn-off Miller plateau voltage feature value corresponding to the turn-off Miller plateau interval;

[0010] Step 3: Based on the voltage characteristic value of the shutdown Miller platform and the preset mapping relationship corresponding to the current operating condition, determine the evaluation value of at least one shutdown dynamic stress parameter.

[0011] Step 4: Based on the evaluated values ​​of the shutdown dynamic stress parameters and the corresponding safety limits, determine the safe operating margin of the power semiconductor device;

[0012] Step 5: Generate gate drive parameter adjustment instructions or protection instructions based on the safety operating margin to adjust the subsequent shutdown process of the power semiconductor device or trigger protection actions.

[0013] The preset mapping relationship represents the correspondence between the turn-off Miller plateau voltage characteristic value and the turn-off dynamic stress parameter.

[0014] Based on the above technical solutions, the present invention may also employ the following further technical solutions, or combine these further technical solutions:

[0015] The process of determining the turn-off Miller plateau interval and extracting the turn-off Miller plateau voltage characteristic values ​​includes:

[0016] Based on the voltage change rate of the gate voltage waveform and preset identification conditions, the start and end times of the turn-off Miller plateau interval are determined.

[0017] The gate-emitter voltage between the start and end times is averaged, and the resulting average value is used as the characteristic value of the turn-off Miller plateau voltage.

[0018] Furthermore, the characteristic value of the turn-off Miller plateau voltage can be expressed as:

[0019] ,

[0020] Among them, V MP-off Let v be the characteristic value of the turn-off Miller plateau voltage, and t1 and t2 be the start and end times of the turn-off Miller plateau interval, respectively. GE (t) represents the gate-emitter voltage waveform.

[0021] The preset mapping relationship between the characteristic value of the turn-off Miller plateau voltage and the evaluation value of the turn-off dynamic stress parameter is expressed as follows:

[0022] ,

[0023] in, For the evaluation value of the i-th shut-off dynamic stress parameter, F k,i Let be the preset mapping function corresponding to the i-th shut-off dynamic stress parameter under the k-th working condition, where k is the mapping relationship number corresponding to different working conditions.

[0024] The shutdown dynamic stress parameters include at least one of overvoltage amplitude, current change rate, voltage change rate, and shutdown loss.

[0025] Furthermore, the preset mapping relationship is established in the following way:

[0026] A power semiconductor device is subjected to a shutdown test under multiple DC bus voltage and multiple shutdown current conditions, wherein the multiple shutdown current conditions include at least an overcurrent shutdown condition.

[0027] Collect the gate voltage waveform, collector-emitter voltage waveform, and collector current waveform under various test conditions;

[0028] The turn-off Miller plateau voltage characteristic value is extracted based on the gate voltage waveform, and the corresponding measured values ​​of the turn-off dynamic stress parameters are determined based on the collector-emitter voltage waveform and the collector current waveform.

[0029] Based on the characteristic values ​​of the turn-off Miller plateau voltage under each test condition and the corresponding measured values ​​of the turn-off dynamic stress parameters, the preset mapping relationship is established.

[0030] In one implementation, the preset mapping function is represented by a linear model as follows:

[0031] ,

[0032] Among them, a k,i and b k,i The model coefficients are the corresponding model coefficients for the i-th shut-off dynamic stress parameter under the k-th working condition. These model coefficients are obtained by pre-calibration based on the corresponding test conditions.

[0033] Furthermore, the evaluation values ​​of the turn-off dynamic stress parameters are determined for the overcurrent turn-off condition, including:

[0034] Compare the current shutdown current with the rated current threshold.

[0035] When the current shutdown current is greater than the rated current threshold, the power semiconductor device is determined to be in an overcurrent shutdown condition.

[0036] Based on the current DC bus voltage, determine the preset mapping function or model coefficients corresponding to the overcurrent shutdown condition;

[0037] The shutdown Miller platform voltage characteristic value is input into the corresponding preset mapping function to obtain the shutdown dynamic stress parameter evaluation value.

[0038] The rated current threshold is used to identify overcurrent shutdown conditions and select the corresponding preset mapping function, and is not directly used as a criterion for determining whether a power semiconductor device has failed.

[0039] Determining the safe operating margin based on the evaluation values ​​of the shut-off dynamic stress parameters includes:

[0040] The evaluation value of the i-th shut-off dynamic stress parameter is compared with the corresponding safety limit to determine the individual safety margin of the i-th shut-off dynamic stress parameter.

[0041] The overall safety margin is determined based on the minimum value among the individual safety margins.

[0042] The individual safety margin and the overall safety operating margin are respectively expressed as follows:

[0043]

[0044]

[0045] Among them, M i S represents the individual safety margin of the i-th shut-off dynamic stress parameter. i,lim Let M be the safety limit value corresponding to the i-th shut-off dynamic stress parameter, and M be the comprehensive safety margin.

[0046] Based on the comprehensive safety margin, gate drive parameter adjustment instructions or protection instructions are generated, including:

[0047] When the overall safety margin is lower than the preset adjustment threshold, a gate drive parameter adjustment command is generated.

[0048] When the overall safety margin is lower than the preset protection threshold, at least one of the following is generated: an alarm signal, a protection trigger signal, and a fault lockout signal.

[0049] The gate drive parameter adjustment command is used to adjust the turn-off gate resistance, switch multi-level turn-off strategies, or implement soft turn-off; the protection command is used to block the drive pulse, trigger protection turn-off, or perform fault lockout.

[0050] The power semiconductor device is a press-fit insulated gate bipolar transistor module.

[0051] The present invention also provides an evaluation device for the dynamic stress of power semiconductor device turn-off, including a waveform acquisition module, a feature extraction module, a stress evaluation module, a margin calculation module, and a drive adjustment and protection module.

[0052] The waveform acquisition module is used to acquire the gate voltage waveform of the power semiconductor device during the turn-off process.

[0053] The feature extraction module is used to determine the turn-off Miller plateau range based on the gate voltage waveform and extract the turn-off Miller plateau voltage feature values.

[0054] The stress assessment module is used to determine the assessment value of the shutdown dynamic stress parameter based on the characteristic value of the shutdown Miller platform voltage and the preset mapping relationship corresponding to the current operating condition.

[0055] The margin calculation module is used to determine the comprehensive safety margin based on the evaluation value of the shutdown dynamic stress parameter and the corresponding safety limit.

[0056] The drive adjustment and protection module is used to generate gate drive parameter adjustment instructions or protection instructions based on the comprehensive safety margin, so as to adjust the subsequent shutdown process of the power semiconductor device or trigger protection actions.

[0057] The present invention also provides an electronic device, including a memory and a processor.

[0058] The memory stores a computer program, and when the processor executes the computer program, it implements the aforementioned method for evaluating the dynamic stress of power semiconductor device shutdown.

[0059] Compared with the prior art, the present invention has the following beneficial effects:

[0060] (1) The present invention extracts the turn-off Miller plateau voltage characteristic value during the turn-off process of power semiconductor devices, and obtains at least one evaluation value among the overvoltage amplitude, current change rate, voltage change rate and turn-off loss based on the preset mapping relationship between the characteristic value and the turn-off dynamic stress parameter. Thus, the low-voltage gate signal on the drive side is used to indirectly evaluate the turn-off dynamic stress on the high-voltage side, reducing the dependence on direct measurement of high-voltage and high-speed voltage and current, as well as the requirements for sensor insulation, bandwidth and anti-interference capability.

[0061] (2) The present invention uses the average value of the gate-emitter voltage within the turn-off Miller plateau interval as the voltage characteristic value, which can reduce the influence of transient oscillation, sampling deviation and measurement noise. By calibrating the preset mapping relationship under multiple DC bus voltage and multiple turn-off current conditions, and calling the corresponding mapping function or model coefficient for overcurrent turn-off conditions, the stability and adaptability of turn-off dynamic stress assessment can be improved.

[0062] (3) This invention compares the evaluation value of the turn-off dynamic stress parameter with the corresponding safety limit to determine the individual safety margin and the comprehensive safety operating margin, and generates gate drive parameter adjustment instructions or protection instructions based on the comprehensive safety operating margin. This method does not use whether the turn-off current exceeds the rated value as the sole fault criterion, and can provide a quantitative basis for turn-off gate resistance adjustment, multi-stage turn-off, soft turn-off, alarm and protection actions, improving the adaptability of the drive protection strategy to short-term overload, load change and overcurrent turn-off conditions. Attached Figure Description

[0063] Figure 1 This is a schematic diagram of the closed-loop structure of the power semiconductor device turn-off dynamic stress assessment and drive protection of the present invention.

[0064] Figure 2 This is a schematic diagram illustrating the working principle of the dual-pulse test;

[0065] Figure 3 It is a transient waveform diagram of VCE and IC shutdown under 3600V bus voltage and 2000A shutdown condition;

[0066] Figure 4 This is a schematic diagram of the turn-off gate voltage waveforms under a 3600V bus voltage and multiple load currents from 1400A to 3850A.

[0067] Figure 5This is a schematic diagram of the VCE and IC turn-off waveforms under a 3600V bus voltage and multiple load currents from 1400A to 3850A.

[0068] Figure 6 This is a mapping relationship between the characteristic values ​​of the turn-off Miller plateau voltage and various turn-off dynamic stress parameters under different DC bus voltages. Among them, (a) is the mapping relationship curve between the characteristic values ​​of the turn-off Miller plateau voltage and the overvoltage amplitude. Figure 6 (b) is the mapping curve between the characteristic value of the turn-off Miller plateau voltage and the turn-off loss; (c) is the mapping curve between the characteristic value of the turn-off Miller plateau voltage and the rate of change of current; (d) is the mapping curve between the characteristic value of the turn-off Miller plateau voltage and the rate of change of voltage.

[0069] Figure 7 This is a topology diagram of a dual-pulse test circuit. Detailed Implementation

[0070] The present invention will be further described below with reference to the accompanying drawings and embodiments, but this should not be construed as limiting the present invention.

[0071] Example 1: This example provides a method for evaluating the turn-off dynamic stress of power semiconductor devices. The evaluation method indirectly quantifies and determines the evaluation value of the turn-off dynamic stress parameter by monitoring the low-voltage side turn-off Miller plateau voltage characteristic value, which is used for dynamic performance evaluation and safety monitoring of power semiconductor devices. The method mainly includes the following steps:

[0072] Step 1: Obtain the gate voltage waveform of the power semiconductor device during the turn-off process.

[0073] Specifically, when a power semiconductor device is turned off, the gate-emitter voltage undergoes a complete change from a high level to a low level. Due to the charge transfer effect of the gate-collector capacitance, a turn-off Miller plateau region with a small rate of voltage change is formed in the gate voltage waveform.

[0074] The gate voltage waveform can be acquired by an isolation voltage acquisition circuit or output by a gate driver with gate voltage acquisition function. The acquired gate voltage signal is sequentially processed by limiting, filtering, level conversion and analog-to-digital conversion to obtain a digital gate voltage waveform for feature extraction.

[0075] Furthermore, the sampling rate and sampling bandwidth of the gate voltage should be able to distinguish the turn-off Miller plateau range. For power semiconductor devices with different switching speeds, the sampling rate, filter bandwidth, and sampling range can be adjusted according to their turn-off time.

[0076] Step 2: Determine and extract the turn-off Miller plateau voltage characteristic value based on the gate voltage waveform.

[0077] Specifically, the turn-off Miller plateau stage is determined by the gate-collector capacitance C. gc Charge transfer occurs during this stage. GE The change is relatively slow, while the collector-emitter voltage V CE The rapid rise allows the gate circuit to pass through C gc It reflects the turn-off state of the main power circuit. Further, based on the voltage change rate of the gate voltage waveform or a preset voltage window, the start and end times of the turn-off Miller plateau interval are determined.

[0078] More specifically, when the gate voltage enters a preset voltage window and the absolute value of the gate voltage change rate is less than a preset change rate threshold, the corresponding moment is determined as the start moment of the turn-off Miller plateau interval; when the gate voltage leaves the preset voltage window, or the absolute value of the gate voltage change rate no longer meets the preset change rate threshold, the corresponding moment is determined as the end moment of the turn-off Miller plateau interval.

[0079] Let the start time of the Miller plateau turn-off interval be t1 and the end time be t2. Then the interval can satisfy:

[0080] ,

[0081] Among them, v GE Here, ε represents the gate-emitter voltage, and ε is a preset rate of change threshold. After determining the turn-off Miller plateau interval, the gate-emitter voltage between the start and end times is averaged, and the resulting average value is used as the characteristic value of the turn-off Miller plateau voltage. The characteristic value of the turn-off Miller plateau voltage is expressed as:

[0082] ,

[0083] Furthermore, averaging the gate-emitter voltage within the turn-off Miller plateau region can reduce the impact of local oscillations, sampling timing deviations, and measurement noise on the feature extraction results. For cases where the turn-off Miller plateau is not obvious or where local oscillations exist, the gate voltage waveform can be filtered or sample-and-hold processed before averaging.

[0084] Step 3: Based on the shutdown Miller platform voltage characteristic value and the preset mapping relationship corresponding to the current operating condition, determine the evaluation value of at least one shutdown dynamic stress parameter, and based on the evaluation value of the shutdown dynamic stress parameter and the corresponding safety limit, determine the safe operating margin of the power semiconductor device.

[0085] Specifically, the turn-off dynamic stress parameters include at least one of overvoltage amplitude, current rate of change, voltage rate of change, and turn-off loss, and the evaluation values ​​of each turn-off dynamic stress parameter can constitute a stress evaluation vector:

[0086] ,

[0087] in, To evaluate the dynamic stress parameters for shutdown, ΔV CE Let |di / dt| be the overvoltage amplitude, |di / dt| be the absolute value of the collector current change rate, and dv / dt be the collector-emitter voltage change rate. off To shut down losses.

[0088] The preset mapping relationship is used to characterize the correspondence between the turn-off Miller plateau voltage characteristic value and the turn-off dynamic stress parameter. The preset mapping relationship can be stored in the form of a mapping function, model coefficients, or a lookup table. The i-th turn-off dynamic stress parameter evaluation value is expressed as:

[0089] ,

[0090] Furthermore, in one specific embodiment, the preset mapping function is represented by a linear model as follows:

[0091] ,

[0092] Among them, a k,i and b k,i These are the model coefficients corresponding to the i-th shut-off dynamic stress parameter under the k-th working condition, and the model coefficients are obtained through pre-conducted shut-off tests and data calibration.

[0093] Specifically, during online evaluation, the corresponding mapping relationship number k is determined based on the current DC bus voltage, and a preset mapping function or model coefficient corresponding to the mapping relationship number is called. The real-time extracted turn-off Miller plateau voltage characteristic value is input into the preset mapping function to obtain the corresponding turn-off dynamic stress parameter evaluation value.

[0094] Furthermore, the current shutdown current is compared with the rated current threshold. When the current shutdown current is greater than the rated current threshold, the power semiconductor device is determined to be in an overcurrent shutdown condition, and a pre-calibrated mapping function for the overcurrent shutdown condition is invoked. The rated current threshold is used to identify the overcurrent shutdown condition and select the corresponding preset mapping function, and is not directly used as a criterion for determining whether the power semiconductor device has failed.

[0095] After obtaining the evaluation values ​​of each shut-off dynamic stress parameter, the evaluation value of the i-th shut-off dynamic stress parameter is compared with its corresponding safety limit to determine the individual safety margin of the i-th shut-off dynamic stress parameter. The individual safety margin is expressed as:

[0096] ,

[0097] The safety limits can be determined based on the datasheet of the power semiconductor device, the safe operating area boundary, the test calibration results and the system reliability requirements, and can be set separately for different turn-off dynamic stress parameters.

[0098] Specifically, when M i When M > 0, it indicates that the evaluated value of the i-th shut-off dynamic stress parameter is lower than the corresponding safety limit; when M i When M = 0, it indicates that the evaluated value has reached the corresponding safety limit; when M i When the value is less than 0, it indicates that the evaluation value exceeds the corresponding safety limit.

[0099] Furthermore, the minimum value among the individual safety margins is taken as the overall safety operating margin, thereby characterizing the main limiting factors in the current turn-off process. When the overall safety operating margin is large, it indicates that each turn-off dynamic stress parameter is kept at a certain distance from the corresponding safety limit; when the overall safety operating margin decreases to the corresponding control threshold, the overall safety operating margin is passed to the subsequent drive adjustment and protection links to generate gate drive parameter adjustment instructions or protection instructions.

[0100] Step 4: Based on the comprehensive safety margin, generate gate drive parameter adjustment instructions or protection instructions to adjust the subsequent shutdown process of the power semiconductor device or trigger protection actions.

[0101] Specifically, preset adjustment thresholds M are set respectively. th Preset alarm threshold M warn and preset protection threshold M trip And the thresholds satisfy the following:

[0102] ,

[0103] When the overall safety margin M is not lower than the preset adjustment threshold M th When this occurs, it indicates that the current turn-off dynamic stress is within the allowable range, and the current gate drive parameters are maintained.

[0104] When the overall safety margin M is lower than the preset adjustment threshold M th At that time, a gate drive parameter adjustment instruction is generated. The gate drive parameter adjustment instruction is used to perform at least one of turn-off gate resistance adjustment, multi-stage turn-off, or soft turn-off to reduce dynamic stress during subsequent turn-off processes.

[0105] Furthermore, the currently mainly restricted turn-off dynamic stress parameters are determined based on each individual safety margin, and the corresponding gate drive adjustment mode is selected based on the main restricted turn-off dynamic stress parameters.

[0106] Specifically, when the individual safety margin corresponding to the overvoltage amplitude or current change rate is at its minimum, the turn-off speed can be reduced by increasing the turn-off gate resistance, switching to a larger turn-off gate resistance earlier, or extending the soft turn-off time, thereby suppressing collector-emitter voltage overshoot and current change rate. Since increasing the turn-off gate resistance may lead to increased turn-off losses, when the individual safety margin corresponding to turn-off losses is small, the switching timing of multi-stage turn-off can be adjusted according to actual operating conditions, or protection commands can be directly generated, avoiding adjustment solely by increasing the turn-off gate resistance.

[0107] In one specific implementation, when the overvoltage magnitude or current change rate is the primary limiting parameter, the target turn-off gate resistance can be expressed as:

[0108] ,

[0109] According to the above adjustment relationship, when the overall safety margin is lower than the preset adjustment threshold, the smaller the overall safety margin, the larger the target turn-off gate resistance; when the overall safety margin is not lower than the preset adjustment threshold, the target turn-off gate resistance remains at the initial turn-off gate resistance.

[0110] Furthermore, when the overall safety margin M is lower than the preset alarm threshold M warn When the overall safety margin M is lower than the preset protection threshold M, an alarm signal is generated to alert the upper-level controller or status monitoring system that the current power semiconductor device's shutdown dynamic stress is approaching the safety limit. trip When this occurs, a protection command is generated. This protection command is used to execute at least one of protection shutdown, drive pulse blocking, or fault lockout to prevent the power semiconductor device from continuing to experience shutdown dynamic stress exceeding safety limits.

[0111] Furthermore, to avoid frequent switching of gate drive parameters due to fluctuations in the overall safety margin around the corresponding threshold, hysteresis ranges or duration criteria can be set for preset adjustment thresholds, preset alarm thresholds, and preset protection thresholds. Only when the overall safety margin is continuously lower than the corresponding threshold for a preset time will a corresponding gate drive parameter adjustment command, alarm signal, or protection command be generated.

[0112] Through the above control process, gate drive parameter adjustment, alarm and protection actions can be executed sequentially according to the changes in turn-off dynamic stress and safety margin, thereby forming a closed loop from the turn-off dynamic stress assessment results to gate drive control and fault protection.

[0113] Example 2: This example is based on the evaluation method described in Example 1. Taking the press-fit insulated gate bipolar transistor module as the object, a preset mapping relationship between the turn-off Miller plateau voltage characteristic value and the turn-off dynamic stress parameter is established through a double-pulse test.

[0114] This embodiment uses the domestically produced 4.5kV / 2kA press-fit insulated gate bipolar transistor module TG2000SW45ZC manufactured by CRRC Times Semiconductor Co., Ltd. as an example for illustration. The dual-pulse test circuit is as follows: Figure 7 As shown, the dual-pulse test circuit includes a high-voltage DC power supply, a DC bus capacitor, a buffer capacitor, a load inductor, the device under test, a freewheeling diode, and voltage and current measuring devices.

[0115] Specifically, the DC bus capacitor provides transient energy for the switching process, the buffer capacitor suppresses voltage overshoot during turn-off, and the load inductor establishes the test current. The gate of the upper half-bridge transistor is shorted, and its anti-parallel diode acts as the freewheeling diode of the load inductor; the lower half-bridge transistor acts as the device under test, and a dual-pulse gate drive signal is applied.

[0116] In this embodiment, the rated parameters of the DC bus capacitor are 5.6kV and 2.25mF, the rated parameters of the buffer capacitor are 5kV and 2.2μF, the on-gate resistance is 1.8Ω, the two off-gate resistances are 8.2Ω and 2.2Ω respectively, the load inductance is 60μH, and the initial device temperature is 25℃. The above devices and test parameters are used to illustrate this embodiment and do not constitute a limitation on the scope of protection of this invention.

[0117] Figure 2 The working principle of the dual-pulse test is illustrated. Specifically, during the first pulse conduction period, the DC bus voltage is applied across the load inductor, causing the load current to rise approximately linearly. After the first pulse is turned off, the load current continues to flow through the freewheeling diode. The second pulse conducts again, causing the load current to continue to rise and turning off the device under test at a set time, thereby obtaining the turn-off transient waveform under the corresponding turn-off current.

[0118] By adjusting the duration of the first and second pulses, the shutdown current of the device under test can be made to cover 1400A~3850A; by adjusting the high-voltage DC power supply, the DC bus voltage can be set to 2800V, 3000V, 3200V, 3400V and 3600V respectively, thereby obtaining test data under multiple DC bus voltage and multiple shutdown current conditions.

[0119] Furthermore, this embodiment focuses on the turn-off process at the end of the second pulse. Under various test conditions, the gate-emitter voltage, collector-emitter voltage, and collector current are simultaneously acquired, and the turn-off Miller plateau interval is determined according to the method described in Embodiment 1, and the characteristic values ​​of the turn-off Miller plateau voltage are extracted.

[0120] Figure 3The transient waveforms of collector-emitter voltage and collector current during turn-off are shown when the DC bus voltage is 3600V and the turn-off current is 2000A. Based on these transient waveforms, the overvoltage amplitude, current rate of change, voltage rate of change, and turn-off loss are determined.

[0121] More specifically, the overvoltage amplitude is determined based on the difference between the peak collector-emitter voltage and the DC bus voltage during the turn-off process; the current change rate is determined based on the slope of the collector current change within the preset turn-off interval; the voltage change rate is determined based on the slope of the collector-emitter voltage change; and the turn-off loss is determined based on the time integral of the product of the collector-emitter voltage and the collector current within the turn-off interval.

[0122] The same parameter extraction rules are used for each test condition to obtain the corresponding turn-off Miller platform voltage characteristic value, overvoltage amplitude, current change rate, voltage change rate and turn-off loss, and form a calibration dataset for establishing a preset mapping relationship.

[0123] Furthermore, Figure 4 The gate-emitter voltage turn-off waveforms are shown when the DC bus voltage is 3600V and the turn-off current is 1400A~3850A. Figure 4 It can be seen that as the turn-off current increases, the turn-off Miller plateau voltage and its corresponding time position change. After entering the overcurrent turn-off region, the change in the turn-off Miller plateau voltage becomes more obvious, indicating that the turn-off Miller plateau voltage can reflect changes in the turn-off current and the state of the main power circuit.

[0124] Figure 5 The collector-emitter voltage and collector current turn-off waveforms are shown within the same DC bus voltage and turn-off current range. Figure 5 It can be seen that the voltage overshoot, current drop process, and tail current pattern differ under different turn-off current conditions. As the turn-off current increases, the turn-off waveforms of the collector-emitter voltage and collector current change accordingly; the waveform changes become more significant after entering the overcurrent turn-off region. Therefore, it is not appropriate to simply extrapolate the overcurrent turn-off dynamic stress based on the variation pattern under lower current conditions.

[0125] In this embodiment, test data within the range of 1400A to 3850A are used to analyze the overall pattern of the turn-off waveform as the current changes. The data used to establish the preset mapping relationship are mainly selected from the overcurrent turn-off condition, and an independent mapping model for the rated current region is not established separately.

[0126] Furthermore, for each DC bus voltage condition, the corresponding relationships between the turn-off Miller plateau voltage characteristic value and the overvoltage amplitude, turn-off loss, current change rate and voltage change rate are fitted to obtain the corresponding preset mapping function and model coefficients.

[0127] Specifically, multiple sets of turn-off Miller plateau voltage characteristic values ​​obtained under the same DC bus voltage are combined with the corresponding turn-off dynamic stress parameters to form a calibration data sequence, and a linear fitting method is used to establish the corresponding mapping relationship. For different DC bus voltages, the corresponding model coefficients are determined and distinguished by different mapping relationship numbers.

[0128] Figure 6 The mapping relationship between the turn-off Miller plateau voltage characteristic values ​​and various turn-off dynamic stress parameters under different DC bus voltages is shown. Among them, Figure 6 (a) illustrates the mapping relationship between the characteristic value of the turn-off Miller plateau voltage and the overvoltage magnitude. Figure 6 (b) illustrates the mapping relationship between the turn-off Miller plateau voltage characteristic and the turn-off loss. Figure 6 (c) shows the mapping relationship between the characteristic value of the turn-off Miller plateau voltage and the rate of change of current. Figure 6 (d) illustrates the mapping relationship between the characteristic value of the turn-off Miller plateau voltage and the rate of voltage change. (From...) Figure 6 It can be seen that, under the same DC bus voltage conditions, there are corresponding variation patterns between the turn-off Miller plateau voltage characteristic value and each turn-off dynamic stress parameter. Within the test range of this embodiment, the data of each group generally show an approximately linear relationship, indicating that the turn-off Miller plateau voltage characteristic value can be used as a gate-side characteristic quantity characterizing the overcurrent turn-off dynamic stress of the press-fit insulated gate bipolar transistor module.

[0129] Furthermore, the positions and model coefficients of the mapping curves differ under different DC bus voltage conditions. Therefore, preset mapping functions can be calibrated for different DC bus voltages, and the corresponding mapping relationship numbers, model coefficients, and applicable operating conditions can be stored in the evaluation device.

[0130] In the actual evaluation process, when the power semiconductor device is in the overcurrent shutdown condition, the corresponding mapping relationship number is determined according to the current DC bus voltage, and the corresponding preset mapping function is called; then, the real-time extracted shutdown Miller plateau voltage characteristic value is input into the preset mapping function to obtain the corresponding shutdown dynamic stress parameter evaluation value.

[0131] If the current DC bus voltage is between two calibrated bus voltages, interpolation can be performed based on the model coefficients corresponding to the adjacent bus voltages, or the preset mapping function closest to the current DC bus voltage can be called. The model selection method can be determined based on the evaluation accuracy and processor computing power.

[0132] It should be noted that the DC bus voltage, turn-off current, device temperature, and gate drive parameters in this embodiment are specific test conditions. For different types of power semiconductor devices, different device temperatures, or different gate drive parameters, calibration data should be re-acquired according to the test and calibration process described in this embodiment, and corresponding preset mapping relationships should be established.

[0133] Through the above testing and calibration process, the correspondence between the characteristic values ​​of the turn-off Miller plateau voltage and each turn-off dynamic stress parameter under the overcurrent turn-off condition can be obtained, providing a model basis for the turn-off dynamic stress assessment and safe operating margin calculation described in Example 1.

[0134] Example 3: This example provides an evaluation device and electronic device for the dynamic stress of power semiconductor devices during shutdown, used to implement the dynamic stress evaluation method for shutdown described in Example 1.

[0135] The evaluation device includes a waveform acquisition module, a feature extraction module, a stress evaluation module, a margin calculation module, and a drive adjustment and protection module.

[0136] Specifically, the waveform acquisition module is used to acquire the gate voltage waveform of the power semiconductor device during the turn-off process. The waveform acquisition module may include a gate voltage acquisition circuit, a signal conditioning circuit, and an analog-to-digital converter circuit. The gate voltage acquisition circuit is connected between the gate and emitter of the power semiconductor device and is used to acquire the gate-emitter voltage; the signal conditioning circuit is used to limit, filter, scale, or level-convert the acquired gate voltage signal; and the analog-to-digital converter circuit is used to convert the processed gate voltage signal into a digital gate voltage waveform.

[0137] Furthermore, the gate voltage acquisition circuit can employ an isolated acquisition method or be integrated into a gate driver with gate voltage acquisition functionality. The sampling rate and bandwidth of the waveform acquisition module are set according to the turn-off speed of the power semiconductor device, so that the acquired gate voltage waveform can distinguish the turn-off Miller plateau range.

[0138] The feature extraction module is connected to the waveform acquisition module and is used to receive the digital gate voltage waveform, determine the turn-off Miller plateau range, and extract the turn-off Miller plateau voltage feature values.

[0139] More specifically, the feature extraction module determines the start and end times of the turn-off Miller plateau interval based on the gate voltage change rate or a preset voltage window, and averages the gate-emitter voltage between the start and end times to obtain the turn-off Miller plateau voltage characteristic value. The feature extraction module can also digitally filter the gate voltage waveform before interval identification and averaging to reduce the impact of local oscillations and measurement noise on the feature extraction results.

[0140] The stress assessment module is connected to the feature extraction module and is used to receive the voltage feature value of the turn-off Miller platform and determine the assessment value of the turn-off dynamic stress parameter based on the preset mapping relationship corresponding to the current operating condition.

[0141] Specifically, the stress assessment module stores or calls pre-calibrated mapping functions and model coefficients for different operating conditions. During stress assessment, the module determines the corresponding mapping relationship number based on the current DC bus voltage and inputs the turn-off Miller plateau voltage characteristic value into the corresponding preset mapping function to obtain at least one assessment value among overvoltage amplitude, current rate of change, voltage rate of change, and turn-off loss.

[0142] Furthermore, when the current shutdown current exceeds the rated current threshold, the stress assessment module determines that the power semiconductor device is in an overcurrent shutdown condition and calls a pre-calibrated mapping function for the overcurrent shutdown condition. The rated current threshold is used to identify the overcurrent shutdown condition and select the corresponding mapping function, and is not directly used as a criterion for determining whether the power semiconductor device has failed.

[0143] The margin calculation module is connected to the stress assessment module and is used to compare the assessment values ​​of each shut-off dynamic stress parameter with the corresponding safety limits, determine the individual safety margin of each shut-off dynamic stress parameter, and take the minimum value among the individual safety margins as the comprehensive safety operating margin.

[0144] Specifically, the safety limits are determined based on the power semiconductor device's datasheet, safe operating area boundaries, test calibration results, and system reliability requirements. The margin calculation module determines the main limiting parameters during the current shutdown process based on the comprehensive safety operating margin and outputs the comprehensive safety operating margin to the drive regulation and protection module.

[0145] The drive adjustment and protection module is connected to the margin calculation module and is used to generate gate drive parameter adjustment instructions or protection instructions based on the comprehensive safety margin.

[0146] Furthermore, when the overall safety margin is lower than a preset adjustment threshold, the drive adjustment and protection module generates a gate drive parameter adjustment instruction to perform at least one of gate resistance adjustment, multi-stage shutdown, or soft shutdown; when the overall safety margin is lower than a preset alarm threshold, an alarm signal is generated; when the overall safety margin is lower than a preset protection threshold, a protection instruction is generated to perform at least one of protection shutdown, drive pulse blocking, or fault locking.

[0147] In one specific embodiment, the gate drive parameter adjustment command, alarm signal, or protection command is transmitted to the gate drive side via an isolation transmission circuit and executed by an adjustable gate drive circuit or a fault protection circuit to adjust the subsequent turn-off process of the power semiconductor device or trigger a protection action.

[0148] Thus, the evaluation device forms a closed-loop processing procedure for acquiring gate voltage waveforms, extracting turn-off Miller plateau voltage characteristics, evaluating turn-off dynamic stress, calculating safety margin, and executing drive regulation or protection.

[0149] Furthermore, this embodiment also provides an electronic device, which includes a memory and a processor.

[0150] The memory is used to store computer programs, preset mapping functions, model coefficients, safety limits, rated current thresholds, and control thresholds. The memory can also be used to cache gate voltage sampling data, turn-off Miller plateau voltage characteristic values, turn-off dynamic stress parameter evaluation values, and safety margins.

[0151] Specifically, the memory can be volatile memory, non-volatile memory, or a combination of both. The preset mapping function and model coefficients can be stored according to the mapping relationship numbers corresponding to different DC bus voltages, so that the processor can call them according to the current operating conditions.

[0152] The processor is used to read and execute the computer program to achieve gate voltage waveform acquisition, turn-off Miller plateau interval identification, turn-off Miller plateau voltage characteristic value calculation, preset mapping function call, turn-off dynamic stress parameter evaluation, safe operating margin calculation, and drive adjustment and protection decision-making.

[0153] More specifically, the processor reads the gate voltage sampling data and determines the turn-off Miller plateau range according to preset identification conditions; averages the gate voltage sampling values ​​within the range to obtain the turn-off Miller plateau voltage characteristic value; calls the corresponding preset mapping function according to the current DC bus voltage to obtain the turn-off dynamic stress parameter evaluation value; determines the comprehensive safety margin based on the evaluation value and the safety limit; and outputs at least one of the following when the comprehensive safety margin reaches the corresponding control condition: a gate drive parameter adjustment command, an alarm signal, or a protection command.

[0154] The processor may be a digital signal processor, a field-programmable gate array, a microcontroller, or other controllers with data processing capabilities. The electronic device may be located in the gate driver board of a power semiconductor device, the main controller of a power conversion equipment, a status monitoring device, or a dual-pulse test platform.

[0155] Furthermore, the waveform acquisition module, feature extraction module, stress assessment module, margin calculation module, and drive adjustment and protection module can be implemented by corresponding hardware circuits, or by the processor executing a computer program stored in the memory. Depending on the hardware resources and real-time requirements of the electronic device, some functional modules can also be integrated into the same processor or intelligent gate driver.

[0156] It should be noted that the division of functional modules in this embodiment is for illustrating the corresponding functions and does not constitute a limitation on the physical structure and location of each functional module. Where the corresponding functions can be implemented, each functional module can be set independently, or they can be combined or integrated.

[0157] The above description is merely a specific embodiment of the present invention. This embodiment uses a press-fit insulated gate bipolar transistor module as an example for illustration. For other voltage-controlled power semiconductor devices with Miller plateau characteristics, the present invention can be implemented by re-establishing the corresponding preset mapping relationship. The model form of the preset mapping relationship, the identification method of the Miller plateau turn-off interval, the storage method of the model coefficients, and the drive adjustment or protection strategy can be adjusted according to the device type and application conditions. The scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A method for evaluating the dynamic stress during the turn-off of a power semiconductor device, characterized in that, include: Obtain the gate voltage waveform during the turn-off process of a power semiconductor device; The turn-off Miller plateau range is determined based on the gate voltage waveform, and the characteristic values ​​of the turn-off Miller plateau voltage are extracted. Based on the characteristic value of the turn-off Miller platform voltage and the preset mapping relationship corresponding to the current operating condition, an evaluation value of at least one turn-off dynamic stress parameter is determined. The safety margin is determined based on the evaluated values ​​of the shut-off dynamic stress parameters and the corresponding safety limits; Based on the safety margin, gate drive parameter adjustment instructions or protection instructions are generated to adjust the subsequent shutdown process of the power semiconductor device or trigger protection actions. The preset mapping relationship represents the correspondence between the turn-off Miller plateau voltage characteristic value and the turn-off dynamic stress parameter.

2. The method for evaluating the dynamic stress of power semiconductor devices during turn-off according to claim 1, characterized in that, Determine the Miller plateau interval for shutdown and extract voltage characteristic values, including: The start and end times of the turn-off Miller plateau interval are determined based on the voltage change rate of the gate voltage waveform and the preset limit. Calculate the average gate-emitter voltage between the start and end times, and use the average value as the characteristic value of the turn-off Miller plateau voltage.

3. The method for evaluating the dynamic stress of power semiconductor devices during turn-off according to claim 1, characterized in that, The characteristic value of the turn-off Miller plateau voltage and the evaluation value of the turn-off dynamic stress parameter satisfy a preset mapping relationship, which is expressed as follows: ， in, V is the evaluation value of the i-th shut-off dynamic stress parameter. MP-off To turn off the Miller plateau voltage characteristic value, F k,i is the preset mapping function corresponding to the i-th shut-off dynamic stress parameter, and k is the mapping relationship number corresponding to different working conditions.

4. The method for evaluating the dynamic stress of power semiconductor devices during turn-off according to claim 1, characterized in that, The preset mapping relationship is established in the following way: Perform power semiconductor device shutdown tests under multiple DC bus voltage and multiple shutdown current conditions; Extract the characteristic values ​​of the turn-off Miller plateau voltage and the corresponding turn-off dynamic stress parameters under each test condition; A preset mapping relationship is established based on the characteristic value of the turn-off Miller plateau voltage and the corresponding turn-off dynamic stress parameter. The preset mapping relationship is represented by a linear fitting model as follows: ， in, V is the evaluation value of the i-th shut-off dynamic stress parameter. MP-off To turn off the Miller plateau voltage characteristic value, a k,i and b k,i The model coefficients are obtained by pre-calibrating according to the corresponding test conditions, and k is the mapping relationship number corresponding to different test conditions.

5. The method for evaluating the dynamic stress of power semiconductor devices during turn-off according to claim 4, characterized in that, Based on voltage characteristic values ​​and preset mapping relationships, the turn-off dynamic stress of power semiconductor devices is evaluated, including: Determine whether the current shutdown current is greater than the rated current threshold. If the current shutdown current is greater than the rated current threshold, the power semiconductor device is determined to be in an overcurrent shutdown condition; a preset mapping function or model coefficient corresponding to the overcurrent shutdown condition is determined based on the current DC bus voltage, and the shutdown Miller plateau voltage characteristic value is input into the preset mapping function to determine the shutdown dynamic stress parameter evaluation value; The rated current threshold is used to identify overcurrent shutdown conditions and is not directly used as a fault determination condition.

6. The method for evaluating the dynamic stress of power semiconductor devices during turn-off according to claim 1, characterized in that, The shutdown dynamic stress parameters include at least one of overvoltage amplitude, current rate of change, voltage rate of change, and shutdown loss. Based on the evaluation value of the nth shut-off dynamic stress parameter and its corresponding safety limit, the individual safety margin of the nth shut-off dynamic stress parameter is determined, and the individual safety margin is expressed as: ， The overall safety operating margin is determined based on the minimum value among the individual safety margins, and the overall safety operating margin is expressed as follows: ， Among them, M i This represents the individual safety margin for the i-th shut-off dynamic stress parameter. S is the evaluation value of the i-th shut-off dynamic stress parameter. i,lim Let M be the safety limit value corresponding to the i-th shut-off dynamic stress parameter, and M be the comprehensive safety margin.

7. The method for evaluating the dynamic stress of power semiconductor devices during turn-off according to claim 1, characterized in that, The generation of drive adjustment commands or protection commands based on the safety margin includes: When the overall safety margin is lower than the preset adjustment threshold, a gate drive parameter adjustment instruction is generated. The gate drive parameter adjustment instruction is used to adjust the turn-off gate resistance, switch the multi-level turn-off strategy, or implement soft turn-off. An alarm signal is generated when the overall safety margin is lower than a preset alarm threshold. When the overall safety margin is lower than the preset protection threshold, a protection trigger or fault lockout signal is generated.

8. The method for evaluating the dynamic stress of power semiconductor device turn-off according to any one of claims 1 to 7, characterized in that, The power semiconductor device is a press-fit insulated gate bipolar transistor module.

9. An evaluation device for the dynamic stress of power semiconductor device turn-off, characterized in that, include: The waveform acquisition module is used to acquire the gate voltage waveform of the power semiconductor device during the turn-off process. The feature extraction module is used to determine the turn-off Miller plateau interval based on the gate voltage waveform and extract the turn-off Miller plateau voltage feature values. The stress assessment module is used to determine the assessment value of the turn-off dynamic stress parameter based on the characteristic value of the turn-off Miller platform voltage and the preset mapping relationship corresponding to the current operating condition. The margin calculation module is used to determine the comprehensive safety margin based on the evaluation value of the shut-off dynamic stress parameter and the corresponding safety limit. The drive adjustment and protection module is used to generate gate drive parameter adjustment instructions or protection instructions based on the comprehensive safety margin, so as to adjust the subsequent shutdown process of the power semiconductor device or trigger protection actions.

10. An electronic device, characterized in that, Including memory and processor; The memory stores a computer program, and when the processor executes the computer program, it implements the method for evaluating the dynamic stress of power semiconductor device turn-off as described in any one of claims 1 to 8.

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