Chip baking duration determination method, system and computer readable storage medium

Abstract

The embodiment of the application discloses a chip baking duration determination method and system and a computer readable storage medium, relates to the technical field of semiconductor chip packaging testing, and the method comprises the following steps: according to the packaging structure type of batch sample chips, the batch sample chips are classified into new architecture products or traditional architecture products; the new architecture products are preprocessed based on a first flow comprising small sample moisture absorption screening, and the preliminary baking duration of the new architecture products is determined; the traditional architecture products are preprocessed based on a pre-trained baking duration prediction model, and the preliminary baking duration of the traditional architecture products is determined; the preliminary baking duration of the new architecture products and the preliminary baking duration of the traditional architecture products are verified based on a second flow comprising large sample reliability verification, and the target baking duration for mass production is confirmed according to the result obtained by verification. The application realizes high reliability of the chip mass production baking duration.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor chip packaging and testing, and in particular to a method, system, and computer-readable storage medium for determining the baking time of chips. Background Technology

[0002] Materials used in semiconductor packaging devices, such as molding compounds, substrates, and underfill adhesives, are hygroscopic. During storage, transportation, and exposure in the workshop, these devices continuously absorb moisture from the air. When the devices enter the high-temperature reflow soldering process, the internal moisture will instantly vaporize and expand, which can easily lead to fatal defects such as package delamination, chip cracking, solder ball detachment, and electrical performance failure.

[0003] Current industry solutions rely on relevant standards and employ fixed, conservative baking times for dehumidification based on the device's MSL level and package thickness. Furthermore, the standards typically only provide a basic testing framework for moisture absorption and desorption, without specifying detailed parameters, sample size requirements, or multi-dimensional reliability verification standards for mass production scenarios.

[0004] Current technologies using fixed, conservative baking times fail to account for differences in package structure (bare die, 2.5D, with STF, with lid, etc.), commonly resulting in over-baking. This leads to high oven occupancy, significantly extended production cycles, and severe capacity waste. Furthermore, the industry lacks quantitative analysis methods based on moisture absorption-desorption curves. Baking times rely on standardized approaches, failing to accurately match the dehumidification characteristics of individual products. Moreover, the absence of pre-verification, mid-term verification, and post-verification reliability checks makes it impossible to guarantee the structural integrity and electrical performance stability of devices after multiple reflow soldering cycles.

[0005] Therefore, there is an urgent need for a solution that combines effective verification with reasonable baking time to address the above problems. Summary of the Invention

[0006] This application proposes a method, system, and computer-readable storage medium for determining the baking time of a chip, in order to address the deficiencies of the prior art.

[0007] According to a first aspect of the embodiments of this application, a method for determining the baking time of a chip is provided, comprising: Based on the packaging structure type of the batch sample chips, the batch sample chips are classified as new architecture products or traditional architecture products. The new architecture product is preprocessed based on a first process including small-sample moisture-absorbing screening, and the initial baking time of the new architecture product is determined. The traditional architecture product is preprocessed based on a pre-trained baking time prediction model, and the initial baking time of the traditional architecture product is determined. Based on the second process, which includes large-sample reliability verification, the initial baking time of the new architecture product and the initial baking time of the traditional architecture product are verified, and the target baking time for mass production is confirmed based on the verification results.

[0008] In some implementations, classifying the batch of sample chips as either new architecture products or traditional architecture products includes: Chips using 2.5D packaging, 3D packaging, or packaging structures including integrated heat sinks and bottom filler are classified as the new architecture products in the batch of sample chips. Chips in the batch of sample chips that are packaged using conventional ball grid arrays or standard chip size are classified as conventional architecture products.

[0009] In some implementations, the preprocessing of the new architecture product based on a first step including small-sample moisture-absorbing screening, and the determination of the initial baking time for the new architecture product, includes: The sample chip representing the new architecture product was subjected to saturated moisture absorption treatment; The sample chip after moisture absorption treatment was baked using at least two different candidate baking times. After baking, each sample chip was subjected to open-bag lifetime exposure simulation and multiple reflow soldering temperature cycle simulation. Defect detection is performed on each sample chip that has completed the open-bag lifetime exposure simulation and multiple reflow soldering temperature cycle simulation, and a preliminary baking time is selected from at least two candidate baking times based on the large number of detection results.

[0010] In some embodiments, the method further includes: A moisture content diffusion model was established based on chip material properties and baking temperature. In conjunction with the auxiliary evaluation of the moisture content diffusion model, the operation of selecting one of at least two candidate baking times as the initial baking time based on a large number of detection results of the defect detection is carried out.

[0011] In some embodiments, the method further includes: Collect historical production data, wherein each piece of historical production data includes at least a set of feature variables and a target baking time, wherein the feature variables are multiple process and material characteristics of the corresponding sample chip; Using machine learning algorithms, a baking time prediction model is built based on the feature variables as input and the target baking time as output. The baking time prediction model is then trained to obtain the pre-trained baking time prediction model.

[0012] In some embodiments, the plurality of process and material characteristics include at least six of the following characteristics: substrate supplier, substrate material, substrate thickness, wafer thickness, molding compound type, package thickness, chip size, number of solder balls, whether a heat sink is included, whether an underfill adhesive is included, and humidity sensitivity level.

[0013] In some implementations, the second process, which includes large-sample reliability verification, verifies the initial baking time of the new architecture product and the initial baking time of the traditional architecture product, and determines the target baking time for mass production based on the verification results, including: The batch of sample chips were completely dried and subjected to multi-dimensional initial quality inspection. The samples that pass the initial inspection are brought to a saturated moisture-absorbing state, and then baked to remove moisture based on the initial baking time; After baking and dehumidification, each sample chip was subjected to open-bag lifetime exposure simulation and multiple reflow soldering temperature cycle simulation, and a multi-dimensional final quality inspection was performed. The effectiveness of the initial baking time is confirmed by comparing the initial inspection results obtained from the multi-dimensional quality inspection with the final inspection results obtained from the multi-dimensional quality inspection. Based on the results of the validity verification, the target baking time for mass production was confirmed.

[0014] In some implementations, the testing items for the multi-dimensional initial quality inspection or the multi-dimensional final quality inspection are the same, and the testing items include one or more of the following: visual inspection, electrical performance open / short circuit test, ultrasonic scanning inspection, solder joint shear force test, and cross-sectional intermetallic compound analysis.

[0015] According to a second aspect of this application, a chip baking time determination system is provided, comprising: The sample classification module is used to classify the batch of sample chips into new architecture products or traditional architecture products according to the packaging structure type of the batch of sample chips. The duration acquisition module is used to preprocess the new architecture product based on a first process including small sample moisture absorption screening, and determine the initial baking time of the new architecture product; and to preprocess the traditional architecture product based on a pre-trained baking time prediction model, and determine the initial baking time of the traditional architecture product. The verification and confirmation module is used to verify the initial baking time of the new architecture product and the initial baking time of the traditional architecture product based on a second process including large-sample reliability verification, and to confirm the target baking time for mass production based on the verification results.

[0016] According to a third aspect of this application, a computer-readable storage medium is provided, which stores a chip baking time determination system as described above. When the chip baking time determination system is executed by a processor, it implements the steps of the chip baking time determination method as described above.

[0017] The beneficial effects of the chip baking time determination method, system, and computer-readable storage medium in the embodiments of this application include at least the following: This application systematically addresses the core contradiction of balancing development efficiency and process reliability in semiconductor packaging baking process development by combining classification processing, path optimization, and unified verification. Specifically, this application first distinguishes between new architecture products lacking data accumulation and traditional architecture products with abundant data through technology classification, thereby matching the most suitable initial time determination path for each. For new architecture products, a small-sample screening based on physical experiments is used to ensure process reliability exploration without prior knowledge; for traditional architecture products, model prediction based on historical data training is used to achieve rapid and intelligent estimation of process parameters, significantly improving development efficiency. Crucially, regardless of whether the initial time comes from experiments or predictions, this application's embodiments are ultimately decided by the same rigorous large-sample reliability verification process. This not only compensates for the black-box uncertainty risk that may exist in the model prediction path, but also provides mass-production-level reliability endorsement for the conclusions of the experimental screening path, thus ensuring that the final confirmed mass-production baking time has both high reliability and superior development efficiency, achieving a balance between quality and speed. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a method for determining the baking time of a chip according to an embodiment of this application. Figure 2 This is a schematic diagram of a chip baking time determination system according to an embodiment of this application; Figure 3 This is a schematic flowchart of humidity study 1 according to an embodiment of this application; Figure 4 This is a schematic flowchart of humidity study 2 according to an embodiment of this application; Figure 5 This is a schematic diagram illustrating the process of confirming the baking time of the chip in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and with various variations and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0020] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed embodiments of the present application, but merely to illustrate selected embodiments of the present application. Other embodiments obtained by those skilled in the art based on the embodiments of the present application without inventive effort are all within the scope of protection of the embodiments of the present application.

[0021] This application discloses a method, system, and computer-readable storage medium for determining the baking time of a chip. The method for determining the baking time of a chip is implemented based on a system for determining the baking time of a chip, which is configured on a computer-readable storage medium. This application is applicable to the baking verification and time determination of batch chips. The purpose is to adopt a technical solution that combines two-step humidity research, rapid prediction by AI machine learning, and closed-loop verification throughout the entire process. First, the optimal baking time (preliminary baking time) is determined through basic research with a small sample, and then the mass production applicability is verified through a large sample. Traditional architecture products can directly predict the preliminary baking time through AI, while new architecture products are executed according to the complete process, ultimately achieving accurate baking time, standardized verification, and efficient mass production.

[0022] See attached document Figure 1 The diagram illustrates a flowchart of a chip baking time determination method according to an embodiment of this application. The chip baking time determination method includes the following steps S1 to S3.

[0023] Step S1: Based on the packaging structure type of the batch of sample chips, classify the batch of sample chips into new architecture products or traditional architecture products.

[0024] In some implementations, classifying the batch of sample chips as either a new architecture product or a conventional architecture product includes: classifying chips in the batch of sample chips that use 2.5D packaging, 3D packaging, or packaging structures that include an integrated heat sink and underfill as new architecture products; and classifying chips in the batch of sample chips that use conventional ball grid array packaging or standard chip size packaging as conventional architecture products.

[0025] Step S1 serves as the starting point for decision-making and the basis for logical branches in this application's embodiments. This classification is not a simple product naming distinction, but rather a process path decision based on technical feasibility, data foundation, and development efficiency. As semiconductor packaging technology evolves towards high density, heterogeneous integration, and multifunctionality, new architecture products such as 2.5D, 3D, integrated heat sinks (Lid), and underfill have emerged. These products have complex structures, numerous material interfaces, and significantly different moisture absorption and thermomechanical behaviors compared to traditional products. Furthermore, they often lack sufficient, mass-produced, and validated baking history data, making it impossible to directly rely on predictive models built upon historical data. Conversely, for traditional architecture products (such as conventional ball grid array packaging and standard chip-size packaging), their structures are mature, their processes are stable, and a large amount of production data and corresponding effective baking parameters have been accumulated, providing a foundation for establishing reliable predictive models. Therefore, the technical objective of step S1 is to select the most efficient and reliable initial baking time determination path for a product based on its packaging structure category at the early stages of product development: selecting a screening path based on physical experiments for new architecture products and a data-driven predictive path for traditional architecture products. This classification ensures a balance between overall efficiency and reliability in the embodiments of this application.

[0026] Step S2 involves preprocessing the new architecture product based on a first process including small-sample moisture-absorbing screening, and determining the initial baking time of the new architecture product; and preprocessing the traditional architecture product based on a pre-trained baking time prediction model, and determining the initial baking time of the traditional architecture product.

[0027] In some implementations, the preprocessing of the new architecture product based on a first process including small-sample moisture absorption screening and determining the initial baking time of the new architecture product includes: saturating a sample chip representing the new architecture product with moisture absorption; baking the sample chip after moisture absorption using at least two different candidate baking times; sequentially performing open-bag lifetime exposure simulation and multiple reflow soldering temperature cycle simulation on each baked sample chip; performing defect detection on each sample chip that has completed the open-bag lifetime exposure simulation and multiple reflow soldering temperature cycle simulation, and selecting one of the at least two candidate baking times as the initial baking time based on the results of a large number of defect detections.

[0028] In some implementations, the method further includes: establishing a moisture content diffusion model based on chip material properties and baking temperature; and, in conjunction with the auxiliary evaluation of the moisture content diffusion model, performing the operation of selecting one of at least two candidate baking times as the initial baking time based on a large number of detection results of the defect detection.

[0029] In some implementations, the method further includes: collecting historical production data, wherein each piece of historical production data includes at least a set of feature variables and a target baking time, the feature variables being multiple process and material characteristics of the corresponding sample chip; using a machine learning algorithm, based on the feature variables as input and the target baking time as output, building a baking time prediction model and training the baking time prediction model to obtain the pre-trained baking time prediction model.

[0030] In some implementations, the plurality of process and material characteristics include at least six of the following characteristics: substrate supplier, substrate material, substrate thickness, wafer thickness, molding compound type, package thickness, chip size, number of solder balls, whether a heat sink is included, whether an underfill is included, and humidity sensitivity level.

[0031] Step S2 in this application is the core differentiating process in the embodiments of this application. It employs an optimized technical path to obtain a preliminary, verifiable baking time parameter for different product categories. For new architecture products (based on the first process), i.e., the small sample screening process, the technical principle lies in simulating the humidity and thermal stress experienced by the chip in the subsequent surface mount process through physical experiments, thereby screening out the shortest baking time that can guarantee reliability. Specifically, this process includes: performing standard saturated moisture absorption treatment on a small number of representative samples to simulate their exposure to the workshop environment reaching the upper limit of humidity sensitivity requirements; subsequently, baking and dehumidifying these samples using multiple different candidate baking times; next, strictly performing simulated open-bag workshop lifespan and multiple reflow soldering temperature and humidity cycles on the baked samples to apply extreme thermomechanical stress; finally, evaluating the chip reliability under each candidate time using various non-destructive and destructive testing methods (such as visual inspection, electrical testing, ultrasonic scanning, etc.), and selecting the candidate time with no failures or the fewest defects as the preliminary baking time. Furthermore, a moisture content diffusion model is used to simulate the internal humidity changes of the chip during the baking process, to help understand the dehumidification kinetics and optimize the selection of candidate baking times, thereby improving the scientific rigor and efficiency of the screening. This application's baking time prediction model is a machine learning model built upon a large amount of historical production data. The construction process of this baking time prediction model includes: collecting detailed data records of various traditional architecture chips that have been successfully mass-produced in the past. Each record contains a set of input feature variables (i.e., the chip's process and material characteristics) and an output, a target baking time that has been verified to be effective in practice. This application's embodiment lists multiple dimensions of parameters, such as substrate, wafer, molding compound, and packaging structure, which are all key factors affecting the chip's hygroscopicity, thermal conductivity, and final thermomechanical stress. These data are used to train a selected machine learning algorithm (such as a gradient boosting decision tree), enabling the baking time prediction model to learn the complex mapping relationship from feature combinations to the optimal baking time. When applied, simply input the above combination of features of the new product, and the model can quickly reason based on the learned rules and give a preliminary prediction of the baking time, avoiding time-consuming experimental cycles and realizing a rapid, data-driven preliminary setting of the baking process for traditional architecture products.

[0032] Step S3: Based on the second process, which includes large-sample reliability verification, the initial baking time of the new architecture product and the initial baking time of the traditional architecture product are verified, and the target baking time for mass production is confirmed based on the verification results.

[0033] In some implementations, the second process, which includes large-sample reliability verification, verifies the initial baking time for the new architecture product and the initial baking time for the traditional architecture product. Based on the verification results, the target baking time for mass production is confirmed. This includes: completely drying the batch of sample chips and performing multi-dimensional initial quality inspection; bringing the samples that pass the initial inspection to a saturated moisture-absorbing state and baking to dehumidify based on the initial baking time; sequentially performing open-bag lifetime exposure simulation and multiple reflow soldering temperature cycle simulation on each sample chip after baking and dehumidification, and performing multi-dimensional final quality inspection; confirming the validity of the initial baking time by comparing the initial inspection results obtained from the multi-dimensional initial quality inspection with the final inspection results obtained from the multi-dimensional final quality inspection; and confirming the target baking time for mass production based on the confirmed validity.

[0034] In some implementations, the testing items for the multi-dimensional initial quality inspection or the multi-dimensional final quality inspection are consistent, including one or more of the following: visual inspection, electrical performance open / short circuit test, ultrasonic scanning inspection, solder joint shear force test, and cross-sectional intermetallic compound analysis.

[0035] Step S3 in this application is the final and mandatory reliability verification checkpoint to ensure that the initial baking time can be safely used for mass production. Regardless of whether the initial baking time originates from high-cost experimental screening or high-efficiency model prediction, before it is confirmed as a mass production parameter, this embodiment of the application strictly controls this necessary second process, which has more stringent conditions, for decisional verification. This ensures the absolute reliability of the final process parameters and is also the core of connecting the two differentiated initial paths and outputting a unique and reliable mass production parameter. Unlike the exploratory screening of the first process, this process is a confirmatory decision, and its design is more statistically significant and the conditions are closer to the worst case. The second process includes: First, a larger batch of samples undergoes complete drying and comprehensive initial inspection to establish a quality baseline and eliminate initial defects. Then, the samples are subjected to a standardized extreme moisture absorption process to ensure they reach their theoretical maximum moisture content. Next, the samples are baked using a pre-validated initial baking time. After baking, the samples undergo simulated actual assembly processes, including opening the bag for exposure and multiple reflow soldering temperature and humidity cycles, to induce potential failures such as interface delamination and cracking. Finally, a final inspection is performed, identical to the initial inspection. The validation logic involves comparing the results of the initial and final inspections. If the test results show that, after undergoing complete humidity and thermal stress, the key quality indicators of the samples (such as solder joint strength and internal structural integrity) do not show statistically significant deterioration, then the initial baking time is deemed effective in ensuring product reliability and can be directly confirmed as the final target baking time (i.e., the mass production baking time). Conversely, if failures occur, it proves that the initial time is insufficient, and the information needs to be fed back to readjust the initial time determination. This step S3 ensures that the process parameters obtained from the two different paths are endorsed by the same high-standard, high-confidence reliability testing system before being released to the production line.

[0036] This application systematically addresses the core contradiction of balancing development efficiency and process reliability in semiconductor packaging baking process development by combining classification processing, path optimization, and unified verification. Specifically, this application first distinguishes between new architecture products lacking data accumulation and traditional architecture products with abundant data through technology classification, thereby matching the most suitable initial time determination path for each. For new architecture products, a small-sample screening based on physical experiments is used to ensure process reliability exploration without prior knowledge; for traditional architecture products, model prediction based on historical data training is used to achieve rapid and intelligent estimation of process parameters, significantly improving development efficiency. Crucially, regardless of whether the initial time comes from experiments or predictions, this application's embodiments are ultimately decided by the same rigorous large-sample reliability verification process. This not only compensates for the black-box uncertainty risk that may exist in the model prediction path, but also provides mass-production-level reliability endorsement for the conclusions of the experimental screening path, thus ensuring that the final confirmed mass-production baking time has both high reliability and superior development efficiency, achieving a balance between quality and speed.

[0037] See attached document Figure 2 As shown in the embodiment of this application, the chip baking time determination system includes: a sample classification module 210, a time acquisition module 220, and a verification and confirmation module 230.

[0038] The sample classification module 210 is used to classify the batch of sample chips into new architecture products or traditional architecture products according to the packaging structure type of the batch of sample chips.

[0039] The duration acquisition module 220 is used to preprocess the new architecture product based on a first process including small sample moisture-absorbing screening and determine the initial baking time of the new architecture product, and to preprocess the traditional architecture product based on a pre-trained baking time prediction model and determine the initial baking time of the traditional architecture product.

[0040] The verification and validation module 230 is used to verify the initial baking time of the new architecture product and the initial baking time of the traditional architecture product based on a second process including large-sample reliability verification, and to confirm the target baking time for mass production based on the verification results.

[0041] The computer-readable storage medium disclosed in this application embodiment stores a chip baking time determination system as described above. When the chip baking time determination system is executed by a processor, it implements the steps of the chip baking time determination method as described above.

[0042] To further illustrate the embodiments of this application and facilitate a better understanding of the embodiments of this application by those skilled in the art, the technical solutions of the embodiments of this application will be clearly and completely described below in conjunction with modules 1 to 3 in specific embodiments. Obviously, the described embodiments are only some of the embodiments of this application, and not all of them.

[0043] The overall execution steps of this specific embodiment include: product architecture determination, basic screening / AI prediction, large-sample mass production verification, and locking the mass production baking time.

[0044] This specific embodiment consists of three core modules: Module 1, Module 2, and Module 3. Module 1 corresponds to the operation of performing Humidity Study 1 (the basic screening stage, a mandatory stage for new architecture products), which includes the basic screening stage (including small sample moisture absorption to desorption operations, and initial screening for the optimal baking time X, i.e., the initial baking time X). Module 2 corresponds to the operation of step S2 in this embodiment, and is used to perform the AI ​​machine learning prediction branch (an optional stage for traditional architecture products), i.e., to replace Humidity Study 1 and directly output the optimal baking time X, i.e., the initial baking time X. Module 3 corresponds to the operation of step S3 in this embodiment (the large-sample verification process, a mandatory stage for all sample chips), and is used to perform Humidity Study 2, i.e., to perform the large-sample verification stage (reliability verification of the initial baking time X).

[0045] Module 1 is applicable to at least the following new architecture products with no historical data, such as 2.5D / 3D advanced packaging and novel structures. The core objectives of Module 1 include at least: quantifying moisture absorption and desorption characteristics, determining the initial baking time X, and providing parameter basis for large-sample verification.

[0046] See attached document Figure 3 As shown, the operation of module 1 (which can also be understood as the "preprocessing of the new architecture product based on the first process including small sample moisture absorption screening and determining the initial baking time of the new architecture product" in step S2 of the above-mentioned embodiment of this application) includes at least seven first-level sub-steps: pre-validation process, humidity reset and dry weight calibration, moisture absorption curve plotting and desorption curve plotting, initial baking time X determination, bag opening exposure simulation process, multiple reflow soldering simulation process and post-validation process.

[0047] The first-level sub-step pre-verification process includes: selecting 50 good cells of the target device, completing 100% visual inspection (VM), open / short circuit electrical performance testing (OS testing), and ultrasonic scanning microscopy inspection (CSAM) to confirm that all samples are free from visual defects, electrical performance abnormalities, and internal delamination problems, rejecting defective products, and locking in qualified test samples.

[0048] The first-level sub-step of humidity reset and dry weight calibration includes: placing 50 qualified samples in an oven at 125℃±5 / -0℃ for 48 hours to completely reset the humidity level inside the device and remove all residual moisture; after baking, the samples are grouped into 24 Class I samples (for weighing and plotting) and 26 Class II samples (for sealing and verification); the dry weight of the Class I samples is immediately weighed, and the total dry weight value A is calculated as the dehumidification baseline value.

[0049] The first-level sub-step for drawing the moisture absorption curve includes: placing Class I and Class II samples in a constant temperature and humidity environment of 30℃ / 60%RH for moisture absorption treatment, with a total moisture absorption time of 360 hours (i.e., 15 days); weighing the samples at preset time intervals according to Class I samples, calculating the total wet weight B of 24 samples, recording the moisture absorption weight change data, and drawing the moisture absorption curve of the target device based on the data to clarify the device's moisture absorption rate and saturation moisture absorption capacity.

[0050] The desorption curve plotting and initial baking time X determination for the first-level sub-steps include the following headphone sub-steps A to D.

[0051] The second-level sub-step A includes: placing the moisture-saturated Class I and Class II samples back into an oven at 125℃+5 / -0℃ for baking and dehumidification; weighing the Class I samples at preset time intervals; recording the dehumidification weight change data; and plotting the desorption curve of the device.

[0052] The second-level sub-step B includes: based on the desorption curve of the type I sample, obtaining the relationship between the dryness of the sample and the baking time at different times, and the dryness calculation formula is = 1 - (current weight - A) / (BA) * 100%.

[0053] The second-level sub-step C includes: taking out the Class II samples that have reached the preset baking interval node, immediately sealing them in a moisture-proof bag (MBB), terminating the baking process and sealing the samples for subsequent verification.

[0054] The second-level sub-step D includes: determining the optimal baking time X by combining the dryness index with the subsequent reflow soldering verification results.

[0055] The first-level sub-step of opening the bag and simulating exposure includes: placing the sealed II sample in a constant temperature and humidity environment of 30℃ / 60%RH according to the humidity sensitivity level (MSL) of the target device to simulate the exposure scenario of opening the bag in the workshop; among which, the simulated exposure time for MSL3 level devices is 180 (168h+12h) hours, and the simulated exposure time for MSL4 level devices is 84 (72h+12h) hours.

[0056] The first-level sub-step involves multiple reflow soldering simulation processes, including: completing 5 cycles of reflow soldering on the sample after exposure simulation according to the customer's standard reflow soldering curve to simulate the client's production application scenario; after completing 3 reflow soldering cycles, the sample is subjected to CSAM testing to complete the interim verification. After confirming that there is no internal delamination, the remaining 2 reflow soldering cycles are completed.

[0057] The verification process following the first-level sub-step includes: performing 100% visual inspection (VM), open / short circuit electrical performance testing (OS test), and ultrasonic scanning microscopy (CSAM) on all samples that have completed 5 reflow soldering cycles to verify whether the samples have visual damage, electrical performance failure, internal delamination, or other issues, and to confirm the reliability of the preliminary optimal baking time X.

[0058] Module 2 is applicable to at least the following traditional architecture products: conventional BGA with STF, standard die, etc.; the core purpose of Module 2 is at least to omit basic screening and directly and quickly predict the initial baking time X.

[0059] The operation of module 2 (which can also be understood as "preprocessing the traditional architecture product based on the pre-trained baking time prediction model and determining the initial baking time of the traditional architecture product" in step S2 of the above embodiment of this application) includes at least three first-level sub-steps: feature engineering and data modeling, algorithm selection and model training, and prediction and inference.

[0060] The first-level sub-step, feature engineering and data modeling, includes the following second-level sub-steps A' to C'.

[0061] The second-level sub-step A' is the data acquisition step, which includes: collecting 14 key influencing factors from historical projects as feature variables (X1-X14). These include: substrate supplier / material, substrate thickness, wafer thickness / type, number / material of solder balls, package type (whether with Lid / STF / 2.5D), MSL level, molding compound type, etc.

[0062] The second-level sub-step B' is the target variable step, which includes: the degree of dryness Y after baking.

[0063] The second-level sub-step C' is the data cleaning step, which includes: denoising the historical experimental data, removing outliers, and constructing a high-quality training dataset. Table 1 below shows the specific parameters of some training datasets.

[0064] Table 1: Specific parameters of some training datasets

[0065] The first-level sub-step algorithm selection and model training include the following second-level sub-steps A'' to C''.

[0066] The second-level sub-step A'' is the algorithm selection step, which includes: adopting an ensemble learning algorithm, preferably XGBoost (Extreme Gradient Boosting) or Random Forest.

[0067] The second-level sub-step B'' is the model building step, which includes: the algorithm maps the complex nonlinear physical process (hygroscopic-desorption) into a mathematical function Y=F(X1, X2, ..., X14) by constructing multiple decision trees.

[0068] The second-level sub-step C'' is the model training step, which includes: inputting historical features and corresponding baking time / dryness, allowing the model to automatically learn the weight of each factor on the baking time.

[0069] The first-level sub-steps of prediction and reasoning include the following second-level sub-steps A''' to C'''.

[0070] The second-level sub-step A''' includes: when a new product (traditional architecture) is introduced, input its characteristic parameters (material properties, structural parameters).

[0071] The second-level sub-step B''' includes: setting the target dryness (e.g., Y=0.9Y=0.9Y=0.9, which is 90% dryness).

[0072] The second-level sub-step C''' includes: directly outputting the predicted optimal baking time X.

[0073] In this embodiment of the application, the process performed by Model 2 replaces the physical experiment of Module 1, shortening the R&D cycle from several weeks to minutes.

[0074] The core objectives of Module 3 include at least: verifying the mass production applicability, reliability, and stability of the initial baking time X, and ultimately locking in the mass production parameters.

[0075] In this embodiment, the baking time prediction model outputs a preliminary baking time value for a specific product by comprehensively calculating multi-dimensional process and material characteristic parameters (such as chip size, substrate thickness, molding compound type, etc.). The specific construction process and internal feature weight distribution of the baking time prediction model can be verified and analyzed by corresponding data analysis tools to further verify the effectiveness and accuracy of the prediction mechanism in the actual process decision-making process.

[0076] See attached document Figure 4As shown, the operation of module 3 (which can also be understood as "based on the second process including large sample reliability verification, verifying the initial baking time of the new architecture product and the initial baking time of the traditional architecture product, and confirming the target baking time for mass production based on the verification results") includes at least seven first-level sub-steps: sample expansion pre-verification process, humidity reset process, extreme moisture absorption process, fixed-length baking desorption process, bag opening exposure simulation process, multiple reflow soldering simulation process, and full-dimensional post-verification process.

[0077] The first-level sub-step of sample expansion and pre-verification includes: expanding the sample size and completing full-dimensional pre-verification of all samples. The testing items include: appearance inspection (VM), open circuit / short circuit electrical performance test (OS test), ultrasonic scanning microscopy (CSAM), solder ball shear force test (sampling), and intermetallic compound (IMC) microscopic inspection (sampling). This confirms that all samples are free of appearance, electrical performance, solderability, and microstructural defects, and locks in qualified test samples.

[0078] The first-level sub-step humidity reset process includes: placing qualified samples in an oven at 125℃±5 / -0℃ for 48 hours to completely reset the internal humidity level of the device and ensure that the initial state of the samples is consistent.

[0079] The first-level sub-step extreme moisture absorption process includes: placing the sample with completed humidity reset in a constant temperature and humidity environment of 30℃ / 60%RH for extreme moisture absorption treatment, with a total moisture absorption time of 720 hours (i.e. 30 days), simulating the most stringent moisture absorption scenario of the device.

[0080] The first-level sub-step fixed-length baking desorption process includes: placing the sample that has completed the ultimate moisture absorption in an oven at 125℃±5 / -0℃, and baking and dehumidifying it using the optimal baking time X determined in the first stage to complete the removal of moisture from the device.

[0081] The first-level sub-step of the bag opening and exposure simulation process includes: consistent with the Model 1 step, completing the bag opening and exposure simulation for the corresponding duration in an environment of 30℃ / 60%RH according to the MSL level of the target device.

[0082] The first-level sub-step involves multiple reflow soldering simulation processes, including: consistent with the first-level model step, completing 5 cycles of reflow soldering simulation, extracting some units after 3 reflow soldering cycles for CSAM mid-term verification, and completing the remaining 2 reflow soldering cycles after confirming that there are no abnormalities.

[0083] The first-level sub-step is a full-dimensional post-verification process, which includes: performing full-dimensional inspections on all samples that have completed 5 reflow soldering cycles, which are completely consistent with the pre-verification. This includes visual inspection (VM), open / short circuit electrical performance testing (OS testing), ultrasonic scanning microscopy (CSAM), solder ball shear force testing, and intermetallic compound (IMC) microscopic inspection. The performance data of the samples before and after baking and before and after reflow soldering are compared to confirm that the optimal baking time X will not cause any performance degradation to the device and can completely avoid the risks of delamination and cracking during the reflow soldering process. Finally, the optimal baking time for mass production of the target device is determined.

[0084] See attached document Figure 5 As shown, the overall process determination rules of this application embodiment are as follows: New architecture products (2.5D / 3D, novel packaging) are implemented based on Humidity Study 1 and Humidity Study 2; traditional architecture products (conventional BGA, with STF, standard die) are implemented based on AI prediction and Humidity Study 2.

[0085] This application's embodiments achieve precise determination of baking time and significant improvement in production capacity. By establishing the moisture absorption-desorption curve for a specific product, the minimum necessary baking time is determined. Compared to the conservative time of traditional standards (such as JEDEC), this application's embodiments can shorten the baking time by 20%-50%, directly releasing oven capacity and significantly reducing production costs. This application's embodiments, driven by AI, achieve a dramatic reduction in the R&D cycle. For traditional architecture products, machine learning models directly predict the baking time, completely skipping the weeks-long moisture absorption-desorption physical experiment stage, achieving a leap from experience-based trial and error to data-driven approaches. This application's embodiments construct a comprehensive verification and determination system encompassing pre-verification, mid-term verification, and post-verification, with multi-dimensional testing ensuring that devices remain undamaged and perform stably after multiple reflow soldering cycles.

[0086] The above statements are merely specific implementations of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any simple modifications, changes, and equivalent changes made by those skilled in the art to the above embodiments based on the technical essence of the embodiments of this application within the scope of the technology disclosed in the embodiments of this application shall still fall within the protection scope of the technical solution of the embodiments of this application.

Claims

1. A method for determining the baking time of a chip, characterized in that, include: Based on the packaging structure type of the batch sample chips, the batch sample chips are classified as new architecture products or traditional architecture products. The new architecture product is preprocessed based on a first process including small-sample moisture-absorbing screening, and the initial baking time of the new architecture product is determined. The traditional architecture product is preprocessed based on a pre-trained baking time prediction model, and the initial baking time of the traditional architecture product is determined. Based on the second process, which includes large-sample reliability verification, the initial baking time of the new architecture product and the initial baking time of the traditional architecture product are verified, and the target baking time for mass production is confirmed based on the verification results.

2. The method according to claim 1, characterized in that, The process of classifying the batch of sample chips into new architecture products or traditional architecture products includes: Chips using 2.5D packaging, 3D packaging, or packaging structures including integrated heat sinks and bottom filler are classified as the new architecture products in the batch of sample chips. Chips in the batch of sample chips that are packaged using conventional ball grid arrays or standard chip size are classified as conventional architecture products.

3. The method according to claim 1, characterized in that, The first preprocessing of the new architecture product, based on a small-sample moisture-absorbing screening process, and the determination of the initial baking time for the new architecture product, includes: The sample chip representing the new architecture product was subjected to saturated moisture absorption treatment; The sample chip after moisture absorption treatment was baked using at least two different candidate baking times. After baking, each sample chip was subjected to open-bag lifetime exposure simulation and multiple reflow soldering temperature cycle simulation. Defect detection is performed on each sample chip that has completed the open-bag lifetime exposure simulation and multiple reflow soldering temperature cycle simulation, and a preliminary baking time is selected from at least two candidate baking times based on the large number of detection results.

4. The method according to claim 3, characterized in that, The method further includes: A moisture content diffusion model was established based on chip material properties and baking temperature. In conjunction with the auxiliary evaluation of the moisture content diffusion model, the operation of selecting one of at least two candidate baking times as the initial baking time based on a large number of detection results of the defect detection is carried out.

5. The method according to claim 1, characterized in that, The method further includes: Collect historical production data, wherein each piece of historical production data includes at least a set of feature variables and a target baking time, wherein the feature variables are multiple process and material characteristics of the corresponding sample chip; Using machine learning algorithms, a baking time prediction model is built based on the feature variables as input and the target baking time as output. The baking time prediction model is then trained to obtain the pre-trained baking time prediction model.

6. The method according to claim 5, characterized in that, The multiple process and material characteristics include the following features At least six items are required: substrate supplier, substrate material, substrate thickness, wafer thickness, molding compound type, package thickness, chip size, number of solder balls, whether a heat sink is included, whether an underfill is included, and humidity sensitivity level.

7. The method according to claim 1, characterized in that, The second process, based on large-sample reliability verification, verifies the initial baking time of the new architecture product and the initial baking time of the traditional architecture product, and determines the target baking time for mass production based on the verification results, including: The batch of sample chips were completely dried and subjected to multi-dimensional initial quality inspection. The samples that pass the initial inspection are brought to a saturated moisture-absorbing state, and then baked to remove moisture based on the initial baking time; After baking and dehumidification, each sample chip was subjected to open-bag lifetime exposure simulation and multiple reflow soldering temperature cycle simulation, and a multi-dimensional final quality inspection was performed. The effectiveness of the initial baking time is confirmed by comparing the initial inspection results obtained from the multi-dimensional quality inspection with the final inspection results obtained from the multi-dimensional quality inspection. Based on the results of the validity verification, the target baking time for mass production was confirmed.

8. The method according to claim 7, characterized in that, The testing items for the multi-dimensional initial quality inspection or the multi-dimensional final quality inspection are consistent, and the testing items include one or more of the following: visual inspection, electrical performance open / short circuit test, ultrasonic scanning inspection, solder joint shear force test, and cross-sectional intermetallic compound analysis.

9. A chip baking time determination system, characterized in that, include: The sample classification module is used to classify the batch of sample chips into new architecture products or traditional architecture products according to the packaging structure type of the batch of sample chips. The duration acquisition module is used to preprocess the new architecture product based on a first process including small sample moisture absorption screening, and determine the initial baking time of the new architecture product; and to preprocess the traditional architecture product based on a pre-trained baking time prediction model, and determine the initial baking time of the traditional architecture product. The verification and confirmation module is used to verify the initial baking time of the new architecture product and the initial baking time of the traditional architecture product based on a second process including large-sample reliability verification, and to confirm the target baking time for mass production based on the verification results.

10. A computer-readable storage medium storing thereon a chip baking time determination system as described in claim 9, characterized in that, When the chip baking time determination system is executed by the processor, it implements the steps of the chip baking time determination method as described in any one of claims 1 to 8.

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