A method for dynamically monitoring inter-die clock skew in a system-in-package

Abstract

The application discloses a kind of dynamic monitoring methods of clock skew between dies in system-in-package, comprising: deployment delay chain sensor, while the time of arrival of at least three dies capture source clock, record the time difference value with reference clock edge, form original sequence;The time difference value in sequence is compared two by two, if the maximum extreme value exceeds the physical time window width corresponding to system synchronization tolerance, then determine that there is clock skew event;The die corresponding to the maximum difference value is determined as the latest arrival chip, the die corresponding to the minimum difference value is determined as the earliest arrival chip, and the skew source is located as the transmission path between the two;Independent application analog high-frequency switching signal, measure the switching delay cumulative value of buffer chain, calculate equivalent delay increment;If the increment is greater than the physical time window width, then output the latest arrival chip identification, the earliest arrival chip identification and the increment value.The application can accurately locate the skew source and evaluate the path delay under high frequency, and the output monitoring result can guide calibration.

Description

Technical Field

[0001] This invention relates to the field of dynamic monitoring technology for chip system-in-package (SoC) technology, and in particular to a dynamic monitoring method for clock skew between dies in SoC. Background Technology

[0002] System-in-package (SiP) technology, by integrating multiple dies within a single package, can significantly reduce module size, lower power consumption, and increase bandwidth. However, with the increase in the number of integrated dies (typically three or more), the signal synchronization problem between dies becomes increasingly prominent. Clock skew—the time difference in arrival times of the same source clock at different dies—has become a core bottleneck restricting stable system operation. When there are three or more dies in a multi-die system, the source of clock skew is no longer unique; it may occur between any two transmission paths. Furthermore, factors such as the physical length, material uniformity, and temperature gradient of different paths are coupled, making the dynamic changes in skew difficult to predict. If the source of skew cannot be accurately monitored and located, the data sampling window under high-frequency operation may be disrupted, leading to transmission errors or even system crashes. Therefore, how to achieve dynamic monitoring of clock skew between dies within a SiP, especially the accurate location of the skew source, has become a key technical problem urgently needing to be solved in this field.

[0003] To address the aforementioned issues, several solutions exist in the existing technology. For example, Fudan University's patent CN103248341B proposes a skew detection and deskew adjustment circuit suitable for VLSI on-chip clock systems. This circuit uses an early phase detection module to determine the phase sequence of two clock signals, then uses an offset detection module to measure the specific skew value, and finally uses a configurable delay circuit to compensate for the skew. This solution works effectively in scenarios with dual clock sources (such as two dies or two clock domains). Its detection process relies on the clock signal during normal system operation, and the output is the skew value, which is directly used to control the subsequent delay compensation circuit. However, this solution reveals significant limitations when extended to a system-in-package environment with three or more dies. First, when multiple dies exist within the system, clock skew can exist between any two dies. This solution can only detect the relative skew between one path and another, failing to identify the path with the most severe skew from multiple time differences, and even less able to pinpoint the specific source of the skew—that is, which die received the earliest clock, which received the latest, and the location of the transmission path between them within the package. Second, this solution only detects the skew status at the current operating frequency, unable to assess the delay characteristics of the same transmission path at higher frequencies. In practical applications, the system may operate at different frequencies or face high-frequency transient interference, and the currently measured skew is insufficient to reflect the path's performance under extreme conditions. Furthermore, the output of this solution is only the skew value. For systems containing multiple dies, this information cannot guide subsequent calibration operations, because even if designers know the magnitude of the skew, they cannot determine which segment of the path's delay should be adjusted. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the problems of existing technologies for multi-die system-in-package (SiP) where only the skew of dual-channel clocks can be detected but the source of skew cannot be located; only the skew state at the current operating frequency can be detected but the path delay characteristics under high-frequency extreme conditions cannot be evaluated; and the output information is only the skew value and cannot guide subsequent calibration operations. The present invention provides a dynamic monitoring method for inter-die clock skew in SiP, which can accurately locate the transmission path where the skew source is located by synchronously capturing and comparing the data of multiple delay chain sensors, and actively measuring the equivalent delay increment of the path under high-frequency operating conditions by independently applying analog high-frequency signals. Finally, the monitoring results include the location identifier of the skew source and the quantized delay value, providing a clear and operable technical basis for clock skew calibration of multi-die systems.

[0005] To address the aforementioned technical problems, this invention provides a dynamic monitoring method for inter-die clock skew in a system-in-package (SIPP), comprising the following steps: Delay chain sensors are deployed at the clock inputs of at least three dies within the system-in-package. Each delay chain sensor simultaneously captures the actual arrival time of the same source clock signal at each die clock input and records the time difference between each actual arrival time and the reference clock edge, forming an original sequence containing at least three time differences. The time difference values ​​in the original sequence are compared pairwise to obtain multiple time difference extreme values. If the maximum value among the multiple time difference extreme values ​​exceeds the width of the physical time window corresponding to the system synchronization tolerance, it is determined that there is a clock skew event. When a clock skew event is determined, the die corresponding to the largest time difference in the original sequence is identified as the die with the latest clock signal arrival, the die corresponding to the smallest time difference is identified as the die with the earliest clock signal arrival, and the source of the skew is located as the signal transmission path between the latest and earliest arriving dies. A simulated high-frequency switching signal is independently applied to the located signal transmission path. The equivalent delay increment of the signal transmission path under high-frequency operating conditions is calculated by measuring the cumulative value of the switching delay of the buffer chain connected in series on the signal transmission path. The measurement is independent of the normal clock of the system. The equivalent delay increment is compared with the physical time window width. If the equivalent delay increment is greater than the physical time window width, the identifier of the latest arriving slice, the identifier of the earliest arriving slice, and the value of the equivalent delay increment are output as dynamic monitoring results.

[0006] In one embodiment of the present invention, the delay chain sensor is composed of multiple inverters connected in series. The output of each inverter is connected to the data input of a flip-flop, and the clock input of the flip-flop is connected to the source clock signal. The actual arrival time of the source clock signal propagating along the inverter chain is determined by reading the output state of each flip-flop.

[0007] In one embodiment of the present invention, the reference clock edge is the rising edge of the source clock signal at the reference die, and the time difference is obtained by subtracting the actual arrival time of the delay chain sensor output at each die from the arrival time of the reference clock edge.

[0008] In one embodiment of the present invention, the pairwise comparison operation is implemented in the following way: the time difference values ​​in the original sequence are sequentially input into the comparator circuit, the first input terminal of the comparator circuit receives the current time difference value, the second input terminal receives the stored extreme value, and the output terminal updates the larger or smaller value stored in the register. After traversing all elements of the original sequence, the maximum and minimum values ​​stored in the register are the maximum and minimum values ​​among the multiple time difference extreme values.

[0009] In one embodiment of the present invention, the width of the physical time window corresponding to the system synchronization tolerance is jointly determined by the system operating frequency and the signal establishment and hold time requirements, specifically expressed as: W=T cycle ·K, where W is the width of the physical time window, T cycle The system clock cycle is K, which is a preset tolerance coefficient. The value of K ranges from 0.05 to 0.2.

[0010] In one embodiment of the present invention, the analog high-frequency switching signal is generated by an on-chip ring oscillator, which includes a closed loop consisting of an odd number of inverters connected in series. Its oscillation frequency is higher than the normal operating frequency of the system. The output of the ring oscillator is connected to the input of the located signal transmission path through a selection switch.

[0011] In one embodiment of the present invention, the specific method for measuring the cumulative switching delay value of the buffer chain connected in series on the signal transmission path is as follows: an analog high-frequency switching signal is simultaneously input to the signal transmission path and the reference path. The reference path is composed of buffers of the same level as the signal transmission path but not affected by the factor of uneven packaging. The phase difference between the output end of the signal transmission path and the output end of the reference path is measured and converted into a time quantity to obtain the cumulative switching delay value.

[0012] In one embodiment of the present invention, the phase difference is measured by a time-to-digital converter circuit, which includes a delay chain composed of multiple delay units and a thermometer code encoder. The input end of the delay chain receives the output signal of the signal transmission path. The output end of each delay unit in the delay chain is connected to the data input end of a set of flip-flops. The clock end of the flip-flops receives the output signal of the reference path. The delay time corresponding to the phase difference is determined according to the high-low level transition position in the output state of the flip-flops.

[0013] In one embodiment of the present invention, the specific implementation of the measurement independent of the normal system clock is as follows: during the application of an analog high-frequency switching signal, the input of the normal system clock to the located signal transmission path is paused, the connection between the system clock and the signal transmission path is cut off through a clock gating circuit, and the connection is restored after the measurement is completed.

[0014] In one embodiment of the present invention, the identifier of the latest arriving chip, the identifier of the earliest arriving chip, and the value of the equivalent delay increment are output in the following manner: the die number corresponding to the latest arriving chip and the earliest arriving chip is written into the first field and the second field of the output register, the binary code of the equivalent delay increment is written into the third field of the output register, and the output register is output to the outside through the test access port of the system-in-package or a dedicated output pin.

[0015] The technical solution of the present invention has the following advantages compared with the prior art: The dynamic monitoring method for inter-die clock skew in a system-in-package (SiP) described in this invention, by deploying delay chain sensors within the multi-die SiP, can accurately capture the arrival time of each die's clock and identify the die with the earliest and latest clock signal arrival, thereby precisely locating the source of skew. Furthermore, by independently applying analog high-frequency switching signals and measuring the equivalent delay increment, this application can evaluate the performance of the location path under high-frequency operating conditions, overcoming the limitation of existing technologies that cannot evaluate delay characteristics under extreme conditions. Therefore, this application has the advantages of real-time monitoring of clock skew changes in a multi-die system, precise location of the physical source path of skew, and evaluation of delay characteristics under high-frequency operating conditions. Attached Figure Description

[0016] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein: Figure 1 This is a flowchart of the steps of the dynamic monitoring method for inter-die clock skew in the system-in-package of the present invention; Figure 2 This is a flowchart of the steps for obtaining the time difference in this invention; Figure 3 This is a flowchart illustrating the steps involved in implementing pairwise comparison operations in this invention. Figure 4 This is a flowchart of the steps for measuring the accumulated delay value according to the present invention; Figure 5 This is a flowchart of the steps for achieving independent measurement using time gating in this invention. Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0018] Reference Figure 1 As shown, this invention proposes a dynamic monitoring method for inter-die clock skew in a system-in-package (SoC). First, delay chain sensors are deployed at the clock inputs of at least three dies within the SoC. These sensors simultaneously capture the actual arrival times of the same source clock signal at each die's clock input and record the time difference between each arrival time and a reference clock edge, thus forming an original sequence containing at least three time differences. The core of this step lies in simultaneous capture and multi-node deployment, which ensures that the time differences between dies can be compared under a unified time reference system, avoiding additional errors introduced by asynchronous measurement times, and providing a complete data foundation for subsequent multi-path comparisons and positioning.

[0019] Based on this, pairwise comparisons are performed on each time difference value in the original sequence to obtain multiple extreme time difference values. The maximum value is then compared with the width of the physical time window corresponding to the system synchronization tolerance. If the maximum value exceeds the width of the physical time window, a clock skew event is determined to exist. Pairwise comparisons are used here instead of simply subtracting the maximum and minimum values ​​because in multi-die systems, the severity of skew may not only be reflected in the global maximum difference; skew between two non-extreme dies may also trigger synchronization problems. Pairwise comparisons can comprehensively capture the skew status of all path pairs.

[0020] After determining the existence of a skew event, the die corresponding to the largest time difference in the original sequence is further identified as the latest arriving die, and the die corresponding to the smallest time difference is identified as the earliest arriving die. This allows for precise localization of the skew source to the signal transmission path between the two dies. This localization function is the core difference from existing technologies: existing technologies can only indicate the magnitude of the skew, while this method can indicate which two dies and on which segment of the path the skew occurred. This has substantial guiding significance for multi-die systems, because only by knowing the source of the skew can subsequent calibrations (such as clock tree adjustment and local delay compensation) be carried out effectively.

[0021] After locating the source of the skew, a simulated high-frequency switching signal is independently applied to the located signal transmission path. By measuring the accumulated switching delay of the buffer chain connected in series along the path, the equivalent delay increment of the path under high-frequency operating conditions is calculated. This measurement process is independent of the system's normal clock operation. This step overcomes the limitation of existing technologies that can only detect skew at the current operating frequency. The principle is that the delay of the clock signal on the path is not only related to the physical length and material properties of the path itself, but also closely related to the signal switching frequency—higher frequencies mean shorter signal rise / fall times, making non-ideal effects such as parasitic capacitance, crosstalk, and power supply voltage drop on the path more significant, leading to an increase in actual delay. By independently applying a simulated high-frequency signal (whose frequency can be set to an upper limit higher than the system's normal operating frequency), the delay margin of the path under extreme conditions can be assessed in advance, which is equivalent to performing a stress test on the path, thereby obtaining more comprehensive delay characteristic information than the current skew amount.

[0022] Finally, the measured equivalent delay increment is compared with the physical time window width. If the equivalent delay increment is greater than the physical time window width, the identifiers of the latest arriving wafer and the earliest arriving wafer, along with the value of the equivalent delay increment, are output as dynamic monitoring results. This output not only includes the specific value of the skew amount but also clearly indicates the location of the skew source (which two wafers), enabling system designers or upper-level calibration modules to directly perform targeted processing based on this result.

[0023] In summary, the dynamic monitoring method proposed in this application systematically solves a series of technical problems in multi-die system-in-package, such as the difficulty in locating the source of clock skew, the inability to evaluate delay characteristics under high-frequency conditions, and the insufficiency of existing technology output information to guide calibration, through synchronous acquisition of multi-node delay chain sensors, pairwise comparison of skew determination, die positioning corresponding to the maximum / minimum difference, active measurement of independent high-frequency signals, and result output including position identification.

[0024] Compared with existing technologies, this method can accurately identify and locate the most severely skewed transmission path in a complex packaging environment with at least three dies, and evaluate the delay margin of the path under high-frequency extreme conditions independently of the system operating frequency. Finally, the monitoring results containing location identifiers and quantization values ​​are output, providing a clear and operable technical basis for subsequent skew calibration or clock tree optimization.

[0025] In system-in-package (SoC) architectures, accurate monitoring of clock skew between dies requires precisely capturing the actual arrival time of the source clock signal at each die's clock input. However, in practical implementation, designing a delay chain sensor that provides high-precision time measurement while effectively resisting noise and process variations is crucial for ensuring the reliability of the monitoring system. Traditional delay measurement structures may suffer from insufficient accuracy, high power consumption, or sensitivity to clock signal characteristics, making it difficult to meet the high-precision, low-power dynamic clock skew monitoring requirements of SoCs.

[0026] To address this, this application further proposes an optimized implementation of a delay chain sensor. Specifically, the delay chain sensor consists of multiple inverters connected in series. These inverter units are carefully designed to ensure stable and predictable delay characteristics. When a source clock signal enters the delay chain sensor, it passes through these inverters sequentially, generating a signal copy with a specific delay at the output of each inverter. The number of inverter stages can be adjusted according to the required measurement resolution and clock frequency to cover the expected clock cycle range. For example, standard inverter units from CMOS processes can be used, and their delay characteristics can be fine-tuned by adjusting their size or bias voltage to meet different accuracy requirements.

[0027] To accurately capture the propagation position of the source clock signal in the delay chain, the output of each inverter is connected to the data input of a flip-flop. These flip-flops are arranged in parallel to form a sampling array. The clock input of all these flip-flops is connected to the source clock signal under test. This connection method ensures that all flip-flops synchronously capture the level state of their respective data inputs when the same valid edge (e.g., rising edge) of the source clock signal arrives. As the source clock signal propagates along the inverter chain, it exhibits different delay states at the outputs of different inverters. The flip-flops "freeze" and store these instantaneous states when the valid edge of the source clock signal arrives. This synchronous sampling mechanism avoids the complexity and potential clock skew introduced by additional clock distribution networks, ensuring the consistency of the measurement reference.

[0028] By reading the output states of each flip-flop, the actual arrival time of the source clock signal propagating along the inverter chain can be determined. For example, if the source clock signal is triggered by a rising edge, and at a certain sampling moment, the outputs of the first N flip-flops are high, while the output of the (N+1)th flip-flop is low, it indicates that the rising edge of the source clock signal has propagated past the Nth inverter, but has not yet reached the (N+1)th inverter. In this way, based on the position of the high-low level transition and the known delay of each inverter unit, the actual time for the source clock signal to arrive at the clock input of the die can be accurately calculated.

[0029] If the specific source and definition of the reference clock edge are not clearly defined when calculating the time difference, the calculation of the time difference may lack a unified benchmark, thus affecting the accuracy and consistency of skew monitoring and making subsequent skew determination and positioning processes unreliable. Figure 2 As shown, this application further proposes that the reference clock edge is the rising edge of the source clock signal at the reference die, and the time difference is obtained by subtracting the actual arrival time of the delay chain sensor output at each die from the arrival time of the reference clock edge.

[0030] Specifically, a reference die refers to a pre-designated or selected die among multiple dies within a system-in-package (SoC). This die typically has stable clock reception characteristics or is centrally located in the physical layout to serve as a reference point for clock signal propagation. The rising edge, the point at which a digital signal transitions from low to high, is usually chosen as the effective trigger edge of the clock signal because it has good noise immunity and a well-defined purpose. Using the rising edge of the source clock signal at the reference die as the reference clock edge aims to provide a uniform and clear time reference for all dies, eliminating uncertainties in the measurement process.

[0031] The actual arrival time of the delay chain sensor output at each die refers to the specific moment when the source clock signal, captured by the delay chain sensor on each die, arrives at its clock input terminal, according to the method described above. The reference clock edge arrival time refers to the actual moment when the rising edge of the source clock signal arrives at the clock input terminal of the reference die, which is also captured by the delay chain sensor on the reference die. The subtraction operation involves subtracting the actual arrival time of each die from the actual arrival time of the reference die, which can be performed by an on-chip subtractor circuit. This operation can directly quantify the time delay or lead of each die relative to the reference die, thereby accurately obtaining the relative clock skew between each die and the reference die. In this way, the influence of the absolute propagation delay of the source clock signal itself on the time difference calculation can be eliminated, so that the obtained time difference can truly reflect the relative timing differences between dies.

[0032] In some of the embodiments described above in this application, it is necessary to perform pairwise comparisons on each time difference value in the original sequence to obtain multiple time difference extreme values. However, in actual implementation, if all pairwise combinations are compared exhaustively, it may lead to excessive computation, especially when the number of bare dies increases, the hardware resource consumption and processing time will increase significantly, thereby affecting the efficiency and real-time performance of clock skew monitoring.

[0033] Reference Figure 3As shown, this application further proposes a specific implementation of pairwise comparison operations, which is accomplished by sequentially inputting each time difference value in the original sequence into a comparator circuit. Specifically, the first input terminal of the comparator circuit is configured to receive the currently processed time difference value, while its second input terminal receives the stored extreme values, i.e., the maximum or minimum value determined previously. The comparator circuit compares these two input values ​​and, based on the comparison result, updates the storage in the register with the larger or smaller value indicated by its output terminal. This "sequential input" method means that the time differences are not processed all at once, but are fed into the processing unit one by one in a preset order (e.g., from first to last). This sequential input method simplifies hardware design and allows for the reuse of comparator circuits, rather than setting up a separate comparator for each possible comparison pair. In implementation, a shift register or a counter can be used to control the data flow, reading the original sequence data stored in memory (such as RAM or FIFO) one by one and feeding it into the comparator. The comparator circuit itself can be implemented by basic logic gates or a dedicated comparator chip, and its output indicates the magnitude relationship between the two input values. "Updating to registers" refers to the comparator circuit's output (e.g., indicating which input value is larger or smaller) controlling whether to update the extreme values ​​in the register. If the current time difference is larger than the maximum value stored in the register, the register is updated to the current time difference; if the current time difference is smaller than the minimum value stored in the register, the register is updated to the current time difference. A register is a high-speed storage unit used to temporarily store data, ensuring that the currently known maximum and minimum values ​​are always maintained throughout the traversal. Two independent registers can be set up, one to store the maximum value and the other to store the minimum value. This process continues until all elements in the original sequence have been traversed. When all elements have been processed, the final values ​​stored in the registers are the maximum and minimum time differences in the original sequence, that is, the maximum and minimum values ​​among multiple time difference extremes. This successive comparison and update mechanism effectively avoids complex parallel comparison logic and simplifies hardware implementation.

[0034] In the dynamic monitoring of inter-die clock skew within a system-in-package (SISP), it is crucial to accurately determine the presence of clock skew events. This relies on comparing the detected extreme time difference with the physical time window width corresponding to the system synchronization tolerance. However, if the determination of this physical time window width is not precise enough or lacks clear quantitative standards, it may lead to misjudgment or missed detection of clock skew events, thereby affecting the accuracy and reliability of monitoring.

[0035] In response, this application further proposes that the physical time window width corresponding to the system synchronization tolerance is jointly determined by the system operating frequency and the signal setup and hold time requirements, specifically expressed as: W= Tcycle·K, where W is the width of the physical time window, T cycle The system clock cycle is K, which is a preset tolerance coefficient. The value of K ranges from 0.05 to 0.2.

[0036] Specifically, the physical time window width W corresponding to the system synchronization tolerance is a key threshold for determining whether a clock skew event exists. It represents the maximum clock arrival time difference that the system can tolerate under normal operating conditions. If the actual measured clock skew exceeds this width, the system synchronization is considered threatened. The system operating frequency refers to the clock frequency used by each die within the system-in-package during normal operation, and this frequency determines the system clock period T. cycle These are the foundation of the overall system timing. Signal setup and hold times are two key timing parameters that must be met for sequential elements (such as flip-flops) in digital circuits to function properly. They together define the effective window of data near the clock edge and are an inherent constraint on the system's synchronization tolerance. The preset tolerance coefficient K is a dimensionless coefficient between 0.05 and 0.2, used to adjust the system clock period T. cycle Weighting is applied to obtain the final physical time window width W. The introduction of this coefficient allows designers to flexibly adjust the clock skew tolerance based on factors such as specific system design margins, process variations, temperature drift, and sensitivity to clock skew. For example, for systems with extremely stringent timing requirements, a smaller K value can be used to improve detection sensitivity; for systems with higher fault tolerance, the K value can be appropriately increased to avoid oversensitivity. W=T cycle The formula for K clarifies the method for calculating the physical time window width W. This is achieved by calculating the system clock period T. cycle Multiplying this by a preset tolerance factor K yields a quantified clock skew tolerance threshold that is closely related to the actual operating conditions of the system. This calculation method ensures that the judgment criterion for clock skew is based on the system's own timing characteristics and design requirements, rather than a fixed, universally applicable value.

[0037] The value of K ranges from 0.05 to 0.2. A minimum value of 0.05 for K corresponds to high-performance, high-frequency systems with tight timing margins. Typical applications include server CPUs, GPU internal clock networks, high-speed SerDes interfaces (≥25Gbps), and high-frequency DDR5 / DDR6 memory interfaces. In these scenarios, the system clock cycle itself is very small (e.g., 1GHz corresponds to Tcycle=1ns). Any significant skew will lead to timing violations. Furthermore, due to limitations in routing resources and power consumption, skew cannot be improved by adding buffers or extending routing. Therefore, strict skew control must be implemented during system design. For example, at a system frequency of 2.5GHz, Tcycle=400ps, and K=0.05 corresponds to W=20ps. This width, under typical process technology, is approximately equal to the cumulative delay of 4 to 6 stages of inverters. This is the skew control level achievable for high-performance chip clock networks.

[0038] The scenario where K is set to its maximum value of 0.2 corresponds to low-power, low-frequency systems with ample timing margins. Typical applications include IoT sensor nodes (MHz-level clocks), battery-powered wearable devices, and MCUs in cost-sensitive consumer electronics. In these scenarios, the clock frequency is low (e.g., 10–100MHz) and the clock period is long (10–100ns). Even with K=0.2, the absolute skew W can still reach 2–20ns, corresponding to signal transmission distances of tens of centimeters (based on a signal propagation speed of approximately 15cm / ns in the package material), far exceeding the typical difference in physical path length between dies within a package (usually in the millimeter range). Therefore, taking a larger K value will not cause timing violations; on the contrary, it can reduce the requirements for clock network routing, reduce the number of buffers, and decrease power consumption.

[0039] Scenarios where K takes a range of values ​​(i.e., 0.05 < K < 0.2) correspond to balanced designs, requiring a balance between performance, power consumption, cost, and reliability. Typical applications include smartphone application processors, automotive electronic control units, and industrial control FPGAs. In such scenarios, the specific determination of the K value needs to comprehensively consider the following factors: K takes a smaller value when the operating frequency increases; K takes a larger value when the chip area increases; K takes a larger value when the temperature variation range is wide; K takes a larger value when the voltage fluctuation is large; K takes a larger value when the yield requirement is high; and K takes a smaller value when the power consumption constraint is strict.

[0040] In some embodiments described above in this application, a simulated high-frequency switching signal is independently applied to the located signal transmission path to measure its equivalent delay increment under high-frequency operating conditions. However, in the implementation process, how to efficiently and reliably generate the required simulated high-frequency switching signal within the system-in-package, and ensure that its oscillation frequency meets the high-frequency testing requirements while avoiding interference with the normal clock operation of the system, is a technical problem that needs to be solved.

[0041] In this regard, this application further proposes that the analog high-frequency switching signal is generated by an on-chip ring oscillator, which includes a closed loop consisting of an odd number of inverters connected in series. Its oscillation frequency is higher than the normal operating frequency of the system, and the output of the ring oscillator is connected to the input of the located signal transmission path through a selection switch.

[0042] Specifically, an on-chip ring oscillator is a self-excited oscillation circuit integrated within a system-in-package (SoC). Its core structure consists of an odd number of inverters connected end-to-end to form a closed loop. This design utilizes the inherent signal delay and inversion characteristics of inverters, allowing the signal to propagate continuously and flip levels within the loop, thereby generating a periodic analog high-frequency switching signal. The advantages of a ring oscillator lie in its simple structure, ease of on-chip integration, and ability to avoid introducing external signal sources, thus reducing the number of pins in the SoC, lowering the overall system complexity, and effectively suppressing the influence of external noise on the measurement signal. To ensure that the analog high-frequency switching signal fully simulates the real-world operation of the system at high frequencies, the ring oscillator is designed with an oscillation frequency higher than the system's normal operating frequency. This means that the monitoring method can perform more rigorous testing on the signal transmission path, thereby detecting and diagnosing clock skew problems that may be insignificant at normal operating frequencies but are exacerbated under high-frequency conditions earlier. Furthermore, to achieve independent measurement of the identified signal transmission path, the output of the ring oscillator is connected to the input of that path via a selection switch. This selector switch, acting as a control unit, can precisely route the analog high-frequency switching signal generated by the ring oscillator to the target signal transmission path when high-frequency delay measurement is required, while disconnecting during non-measurement periods. This ensures the independence of the measurement process and avoids mutual interference between the measurement signal and the normal clock operation of the system.

[0043] Furthermore, after applying a simulated high-frequency switching signal, a key technical problem to solve is how to accurately obtain the accumulated switching delay value during the actual measurement process, and how to effectively isolate and quantify the additional delay caused by packaging unevenness factors within the system-in-package. (Refer to...) Figure 4 As shown, this application further proposes a specific method for measuring the accumulated switching delay value of a series of buffer chains on a signal transmission path. The method includes simultaneously inputting an analog high-frequency switching signal to both the signal transmission path and a reference path. The reference path consists of buffers of the same order as the signal transmission path but unaffected by packaging unevenness. The accumulated switching delay value is obtained by measuring the phase difference between the output terminals of the signal transmission path and the reference path, and converting this phase difference into a time quantity.

[0044] Specifically, when measuring the located signal transmission path, an analog high-frequency switching signal is first applied simultaneously to the input of the signal transmission path and the input of a pre-designed reference path. The analog high-frequency switching signal can be generated by an on-chip ring oscillator with an oscillation frequency higher than the system's normal operating frequency to ensure measurements are performed at frequencies close to actual operating conditions. The design of the reference path is crucial; it consists of the same number and type of buffers as the buffer chains connected in series in the signal transmission path, but its physical layout and environment should ensure it is unaffected or minimally affected by packaging non-uniformities within the system-in-package. For example, the reference path can be placed in a stable region within the die or in a known uniform region within the package. In this way, the reference path provides a baseline delay, representing the fundamental delay under ideal or uniform packaging conditions.

[0045] Subsequently, this application measures the phase difference between the output signal of the signal transmission path and the output signal of the reference path. This phase difference directly reflects the time delay difference between the two paths. Since the analog high-frequency switching signals are input simultaneously, and the reference path excludes the influence of packaging non-uniformity, the measured phase difference can accurately characterize the additional delay introduced by packaging non-uniformity in the signal transmission path. To convert this phase difference into a quantifiable time value, it needs to be converted according to the known frequency or period of the analog high-frequency switching signal. For example, if the period of the analog high-frequency switching signal is T, then the time quantity corresponding to the phase difference Δφ (in radians) is Δt = Δφ / (2π)·T. Through this conversion, the cumulative switching delay of the buffer chain connected in series on the signal transmission path can be obtained.

[0046] In this embodiment, the phase difference is measured by a time-to-digital converter circuit. This time-to-digital converter circuit includes a delay chain composed of multiple delay units and a thermometer code encoder. Specifically, the input of the delay chain receives the output signal of the signal transmission path, the output of each delay unit in the delay chain is connected to the data input of a set of flip-flops, the clock input of the flip-flops receives the output signal of the reference path, and the delay time corresponding to the phase difference is determined based on the high / low level transition position in the flip-flop output state.

[0047] A time-to-digital converter (TD-SCDMA) is a circuit that converts time intervals or phase differences into digital outputs. Its core function is to quantify the time difference between two events with high precision. In system-in-package (SISP) architectures, clock skew can manifest as minute time differences on the order of nanoseconds or even picoseconds. TD-SCDMA circuits can provide sufficient measurement resolution and accuracy to meet the needs of dynamic monitoring. This circuit typically consists of one or more delay chains, flip-flop arrays, and encoding logic, enabling it to convert analog time information into easily processed and analyzed digital information.

[0048] To achieve accurate phase difference measurement, this time-to-digital converter utilizes a delay chain composed of multiple delay units. The input of this delay chain receives the output signal from the signal transmission path, which propagates sequentially through the chain, forming a time tap with a different delay at the output of each delay unit. The output of each delay unit in these delay chains is connected to the data input of a set of flip-flops. Simultaneously, the clock input of the flip-flops receives the output signal from the reference path, which serves as the sampling clock, latching the data input states of all flip-flops at specific moments. Through this parallel sampling mechanism, the output states of the flip-flop array form a thermometer code reflecting the relative arrival time of the output signal from the signal transmission path with respect to the output signal from the reference path.

[0049] Subsequently, the thermometer code encoder in this time-to-digital converter circuit is responsible for parsing the output state of the trigger array. The thermometer code encoder can identify the high-low level transition positions in the trigger output state. These transition positions precisely indicate the depth of the output signal propagation in the delay chain, thus directly corresponding to the phase difference between the two signals. By converting this transition position into a digital quantity, the delay time corresponding to the phase difference can be determined.

[0050] In system-in-package (SiP), to accurately assess the equivalent delay increment of inter-die signal transmission paths under high-frequency operating conditions, it is necessary to independently apply an analog high-frequency switching signal to the path for measurement. However, if such measurements are performed directly during normal system clock operation, the system clock signal may interfere with the analog high-frequency switching signal, leading to inaccurate measurement results and potentially affecting the normal functioning of the system. Therefore, effectively isolating the measurement process from normal system clock operation is a key issue in ensuring measurement accuracy and system stability.

[0051] Reference Figure 5 As shown, this application further proposes a specific implementation method for measuring independently of the system's normal clock operation: during the application of an analog high-frequency switching signal, the input of the system's normal clock to the located signal transmission path is suspended, the connection between the system clock and the signal transmission path is cut off through a clock gating circuit, and the connection is restored after the measurement is completed.

[0052] Specifically, during the application of the analog high-frequency switching signal, the input of the system's normal clock to the located signal transmission path is paused to eliminate interference from the system's normal clock on the measurement process. By temporarily stopping the input of the system's normal clock to a specific signal transmission path, it can be ensured that no other clock signals compete with or superimpose on it when the analog high-frequency switching signal is applied to that path, thereby guaranteeing the purity and accuracy of the measurement results. This pause can be achieved through control logic gates, multiplexers, or clock enable signals.

[0053] Simultaneously, a clock gating circuit disconnects the system clock from the signal transmission path. Clock gating is a common digital circuit design technique used to control the transmission of clock signals. In this context, the clock gating circuit is configured to physically disconnect the system clock from the transmission path of the signal under test during measurement. This prevents the system clock signal from leaking into the path under test, even if the system clock itself is still running in other parts. Clock gating circuits are typically composed of AND gates, OR gates, or more complex combinational logic, whose control input receives an enable signal; when the enable signal is invalid, the clock signal is blocked from passing through.

[0054] After the measurement is completed, the connection must be restored. This means that once the measurement is finished, the connection between the system clock and the signal transmission path needs to be restored to its normal operating state to ensure the system can continue to function normally. This is typically achieved by reversing the control signal of the clock gating circuit, allowing the system clock signal to pass through again. The connection restoration action should be coordinated with the pause and disconnect operations to avoid any transient errors or system instability.

[0055] By suspending the input of the system's normal clock to the located signal transmission path during the application of an analog high-frequency switching signal, and by using a clock gating circuit to disconnect the connection between the system clock and the signal transmission path, this application effectively isolates the measurement process from the operation of the system's normal clock. This isolation mechanism avoids mutual interference between the system's normal clock signal and the analog high-frequency switching signal, thereby ensuring the accuracy and reliability of the equivalent delay increment measurement of the signal transmission path under high-frequency operating conditions. Furthermore, since the connection can be restored promptly after the measurement is completed, this scheme minimizes interference with the normal operation of the system while ensuring measurement accuracy, thus improving the practicality and efficiency of the dynamic monitoring method.

[0056] In practical applications, this application provides an efficient and standardized way to output the dynamic monitoring results of clock skew between dies in a system-in-package, specifically including: writing the die numbers corresponding to the latest and earliest arriving dies into the first and second fields of the output register, writing the binary code of the equivalent delay increment into the third field of the output register, and outputting the output register to the outside through the test access port or dedicated output pin of the system-in-package.

[0057] Specifically, the die numbers corresponding to the latest and earliest arriving dies are written into the first and second fields of the output register. This aims to standardize the storage of the identity information of the latest and earliest arriving dies identified by the dynamic monitoring method. The die number is a unique identifier for each die in the system-level package, typically a pre-assigned numeric or alphanumeric code. By writing these numbers into different fields of the output register, clear distinction and structured storage of information can be ensured, facilitating subsequent reading and parsing. For example, the first field can be specifically used to store the number of the latest arriving die, and the second field can be used to store the number of the earliest arriving die, thus forming a clear pair of skew source location information.

[0058] The binary code of the equivalent delay increment is written to the third field of the output register to store the calculated equivalent delay increment in a standardized digital form. The equivalent delay increment is a quantified value that reflects the actual delay of the signal transmission path under high-frequency operating conditions. Converting it to binary code and writing it to the third field of the output register ensures the accuracy and readability of the numerical information. This encoding method facilitates processing and transmission by digital circuits and allows external systems to directly read and perform quantitative analysis, for example, to assess the severity of skew or to make compensation adjustments.

[0059] The output register outputs data via a system-in-package (SiP) test access port or a dedicated output pin, defining the output path for dynamic monitoring results. The output register is a hardware unit used for temporary data storage, containing information such as die identifier and equivalent delay increment. The SiP test access port (such as the JTAG interface) is a standardized debugging and testing interface that allows external devices to access the chip's internal registers and signals. Dedicated output pins are physical pins reserved for specific functions, allowing direct output of data from registers in parallel or serial mode.

[0060] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for dynamically monitoring clock skew between dies in a system-in-package, characterized in that, Includes the following steps: Delay chain sensors are deployed at the clock inputs of at least three dies within the system-in-package. Each delay chain sensor simultaneously captures the actual arrival time of the same source clock signal at each die clock input and records the time difference between each actual arrival time and the reference clock edge, forming an original sequence containing at least three time differences. The time difference values ​​in the original sequence are compared pairwise to obtain multiple time difference extreme values. If the maximum value among the multiple time difference extreme values ​​exceeds the width of the physical time window corresponding to the system synchronization tolerance, it is determined that there is a clock skew event. When a clock skew event is determined, the die corresponding to the largest time difference in the original sequence is identified as the die with the latest clock signal arrival, the die corresponding to the smallest time difference is identified as the die with the earliest clock signal arrival, and the source of the skew is located as the signal transmission path between the latest and earliest arriving dies. A simulated high-frequency switching signal is independently applied to the located signal transmission path. The equivalent delay increment of the signal transmission path under high-frequency operating conditions is calculated by measuring the cumulative value of the switching delay of the buffer chain connected in series on the signal transmission path. The measurement is independent of the normal clock of the system. The equivalent delay increment is compared with the physical time window width. If the equivalent delay increment is greater than the physical time window width, the identifier of the latest arriving slice, the identifier of the earliest arriving slice, and the value of the equivalent delay increment are output as dynamic monitoring results.

2. The dynamic monitoring method for inter-die clock skew in system-in-package according to claim 1, characterized in that: The delay chain sensor consists of multiple inverters connected in series. The output of each inverter is connected to the data input of a flip-flop, and the clock input of the flip-flop is connected to the source clock signal. The actual arrival time of the source clock signal propagating along the inverter chain is determined by reading the output state of each flip-flop.

3. The dynamic monitoring method for inter-die clock skew in system-in-package according to claim 1, characterized in that: The reference clock edge is the rising edge of the source clock signal at the reference die. The time difference is obtained by subtracting the actual arrival time of the delay chain sensor output at each die from the arrival time of the reference clock edge.

4. The dynamic monitoring method for inter-die clock skew in system-in-package according to claim 1, characterized in that: The pairwise comparison operation is implemented as follows: the time difference values ​​in the original sequence are input into the comparator circuit in sequence. The first input terminal of the comparator circuit receives the current time difference value, the second input terminal receives the stored extreme value, and the output terminal updates the larger or smaller value stored in the register. After traversing all elements of the original sequence, the maximum and minimum values ​​stored in the register are the maximum and minimum values ​​among the multiple time difference extreme values.

5. The dynamic monitoring method for inter-die clock skew in a system-in-package according to claim 1, characterized in that: The physical time window width corresponding to the system synchronization tolerance is jointly determined by the system operating frequency and the signal setup and hold time requirements, specifically expressed as: W=T cycle ·K, where W is the width of the physical time window, T cycle The system clock cycle is K, which is a preset tolerance coefficient. The value of K ranges from 0.05 to 0.

2.

6. The dynamic monitoring method for inter-die clock skew in a system-in-package according to claim 1, characterized in that: The analog high-frequency switching signal is generated by an on-chip ring oscillator, which consists of a closed loop formed by an odd number of inverters connected in series. Its oscillation frequency is higher than the normal operating frequency of the system. The output of the ring oscillator is connected to the input of the signal transmission path to be located via a selection switch.

7. The dynamic monitoring method for inter-die clock skew in a system-in-package according to claim 1, characterized in that: The specific method for measuring the cumulative switching delay of the buffer chain connected in series on the signal transmission path is as follows: Simultaneously input the analog high-frequency switching signal to the signal transmission path and the reference path. The reference path is composed of buffers of the same level as the signal transmission path but not affected by the factor of uneven packaging. By measuring the phase difference between the output end of the signal transmission path and the output end of the reference path, the phase difference is converted into a time quantity to obtain the cumulative switching delay value.

8. The dynamic monitoring method for inter-die clock skew in a system-in-package according to claim 7, characterized in that: The phase difference is measured by a time-to-digital converter circuit, which includes a delay chain composed of multiple delay units and a thermometer code encoder. The input of the delay chain receives the output signal of the signal transmission path. The output of each delay unit in the delay chain is connected to the data input of a set of flip-flops. The clock of the flip-flops receives the output signal of the reference path. The delay time corresponding to the phase difference is determined according to the high and low level transition position in the output state of the flip-flops.

9. The dynamic monitoring method for inter-die clock skew in a system-in-package according to claim 1, characterized in that: The specific implementation method for measuring independently of the system's normal clock is as follows: during the application of an analog high-frequency switching signal, the input of the system's normal clock to the located signal transmission path is paused, and the connection between the system clock and the signal transmission path is cut off through a clock gating circuit. The connection is restored after the measurement is completed.

10. The dynamic monitoring method for inter-die clock skew in a system-in-package according to claim 1, characterized in that: The identifiers of the latest arriving chip, the identifiers of the earliest arriving chip, and the value of the equivalent delay increment are output in the following way: the die numbers corresponding to the latest and earliest arriving chips are written into the first and second fields of the output register, the binary code of the equivalent delay increment is written into the third field of the output register, and the output register is output to the outside through the system-in-package test access port or dedicated output pin.

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