Batch testing method and device for chips, chip testing system

Abstract

The application relates to the chip testing technical field and discloses a batch testing method and device for a chip and a chip testing system. The method is applied to an upper computer of the chip testing system, and the method comprises the following steps: a single test firmware containing multiple test task modules is written into a to-be-tested chip through a CAN bus; a target test task required by the to-be-tested chip is determined from the single test firmware according to a target IO pin state of the to-be-tested chip; a test starting instruction is issued to the to-be-tested chip through the CAN bus, the to-be-tested chip executes the corresponding target test task, and running state information of the to-be-tested chip is acquired in the process of executing the target test task; and a test report of the to-be-tested chip is generated according to the running state information after the target test task is executed. The application can improve the batch testing efficiency and testing accuracy of the chip.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, such as a method and apparatus for batch testing of chips, and a chip testing system. Background Technology

[0002] Chips with high reliability and high safety requirements (such as automotive grade chips) operate in complex environments involving alternating high and low temperatures, vibration and shock, and electromagnetic interference. To ensure the long-term reliable operation of these chips, they must undergo rigorous reliability testing and certification before leaving the factory.

[0003] In related technologies, batch reliability testing of such chips is usually carried out in the following way: multiple chips under test are mounted on a test array board and placed in environmental equipment such as high and low temperature chambers. Testers manually complete the loading of test programs, setting of environmental parameters, monitoring of the test process, and extraction and analysis of test data.

[0004] In the process of implementing the embodiments of this disclosure, it was found that the related technology has at least the following problems: Different test tasks (such as FLASH testing, HTOL, HAST, etc.) correspond to different test logic and parameter configurations. Testers need to compile a separate Hex project file for each test task. For the same chip, completing all test tasks often results in dozens of different Hex files. When test parameters are slightly adjusted, a new Hex version needs to be recompiled, leading to version management chaos and increasing the risk of programming errors in practice, thus hindering testing efficiency and accuracy. Therefore, improving the batch testing efficiency and accuracy of automotive-grade chips has become an urgent technical problem to be solved.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This disclosure provides a method and apparatus for batch testing of chips, as well as a chip testing system. These methods can improve the efficiency and accuracy of batch chip testing.

[0008] In some embodiments, the batch testing method for chips is applied to a host computer of a chip testing system. The testing system further includes a test array board with multiple chip test positions. The host computer communicates with the chip under test (DUT) at the chip test positions via a CAN bus. The batch testing method includes: writing a single test firmware containing multiple test task modules into the DUT via a CAN bus; determining the target test task to be executed by the DUT from the single test firmware based on the target IO pin status of the DUT; issuing a test start command to the DUT via the CAN bus; the DUT executing the corresponding target test task; acquiring the operating status information of the DUT during the execution of the target test task; and generating a test report for the DUT based on the operating status information after the target test task is completed.

[0009] Optionally, based on the target I / O pin state of the chip under test, the target test task to be performed by the chip under test is determined from a single test firmware, including: when the target I / O pin state is low, reading the level combination of the hardware configuration I / O pin group, and indexing the corresponding test task from the single test firmware according to the level combination, as the target test task; when the target I / O pin state is high, reading the software configuration parameters in the internal storage area, and indexing the corresponding test task from the single test firmware according to the software configuration parameters, as the target test task.

[0010] Optionally, a test start command is sent to the chip under test via the CAN bus, including: receiving attribute information reported by the chip under test via the CAN bus after power-on initialization; determining the ready state of the chip under test based on the attribute information; and sending a test start command to the chip under test via the CAN bus when all chips under test are in the ready state.

[0011] Optionally, after determining the readiness status of the chip under test based on the attribute information, the batch testing method further includes: displaying the readiness status of the chip under test on the display interface of the host computer.

[0012] Optionally, a single test firmware includes test task modules such as: a reliability test module, a high-temperature operating life test module, a high-acceleration temperature and humidity stress test module, a latch-up effect test module, an electromagnetic interference test module, and a power temperature cycle test module; wherein, the reliability test module includes: idle mode, durability test mode, data retention-checkerboard mode, data retention-anti-checkerboard mode, data retention-ECC all-zero mode, online life test-checkerboard mode, online life test-checkerboard mode, online life test-anti-checkerboard mode, erase interference test mode, and write interference test mode.

[0013] Optionally, the chip testing system also includes a programmable power supply for powering the chip under test; before sending a test start command to the chip under test via the CAN bus, the batch testing method further includes: acquiring the actual output voltage value and the actual output current value of the programmable power supply; and controlling the programmable power supply based on the voltage difference between the actual output voltage value and the voltage setting value, and the current difference between the actual output current value and the current setting value.

[0014] Optionally, the batch testing method further includes: upon receiving the upgrade firmware data packet, simultaneously sending the upgrade firmware data packet to all chips under test via the CAN bus in the form of a broadcast frame; so that the chips under test can receive the upgrade firmware data packet and complete the firmware update through the preset BootLoader.

[0015] In some embodiments, the batch testing device for chips is applied to the host computer of a chip testing system. The testing system further includes a test array board with multiple chip test positions. The host computer communicates with the chip under test (DUT) at the chip test positions via a CAN bus. The batch testing device includes: a firmware writing module for writing a single test firmware containing multiple test task modules into the DUT via the CAN bus; a task determination module for determining the target test task to be executed by the DUT from the single test firmware based on the target IO pin status of the DUT; an instruction sending module for sending a test start instruction to the DUT via the CAN bus, and the DUT executes the corresponding target test task. During the execution of the target test task, the operating status information of the DUT is obtained; and a report generation module for generating a test report for the DUT based on the operating status information after the target test task is completed.

[0016] In some embodiments, a batch testing apparatus for chips includes a processor and a memory storing program instructions, the processor being configured to execute the batch testing method for chips as described above when running the program instructions.

[0017] In some embodiments, a chip testing system includes: a host computer; a test array board having multiple chip test positions, the host computer communicating with the chip under test at the chip test positions via a CAN bus; and a batch testing device for chips as described above, integrated into the host computer.

[0018] The batch testing method and apparatus for chips, and the chip testing system provided in this disclosure can achieve the following technical effects: In this embodiment, multiple test task modules are pre-compiled into a single test firmware. When testing the chip, this single test firmware is first written to the chip under test (DUT) via the CAN bus. Based on the target I / O pin status of the DUT, the target test task to be executed by the DUT is determined from this single test firmware. Compared to the related technologies where each test task has its own Hex file, this eliminates the need to recompile and burn multiple different versions of Hex files when switching between different test tasks, thus avoiding firmware version management chaos and Hex file burning errors. After determining the target test task to be executed by the DUT, a test start command is sent to the DUT via the CAN bus, causing the DUT to execute the corresponding target test task. During the execution of the target test task, the operating status information of the DUT is acquired. In this way, the host computer can batch-start the test tasks of all DUTs via commands and continuously collect the operating status of each DUT during the test. Compared to the related technologies that rely on manual operation and periodic inspection of each chip, this reduces human intervention and improves test accuracy. After the target test task is completed, a test report for the chip under test is generated based on the running status information. This reduces the time required to process test results compared to the cumbersome process in related technologies, which requires disassembling each chip under test, reading logs via serial port, and then manually organizing the data. Therefore, the embodiments of this disclosure can improve the efficiency and accuracy of batch chip testing.

[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of a chip testing system provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of a batch testing method for chips provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of another batch testing method for chips provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of another batch testing method for chips provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of another batch testing method for chips provided in an embodiment of this disclosure; Figure 6This is a schematic diagram of a batch testing apparatus for chips provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of another batch testing apparatus for chips provided in an embodiment of this disclosure. Detailed Implementation

[0021] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0022] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0023] Unless otherwise stated, the term "multiple" means two or more.

[0024] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0025] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0026] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0028] Combination Figure 1 As shown, this embodiment of the present disclosure provides a chip testing system 100, including: a host computer 110, a test array board 120, and a batch testing device 600 (700) for chips. The test array board 120 is provided with multiple chip test positions, and the host computer 110 is communicatively connected to the chips under test at the chip test positions via a CAN bus. The batch testing device 600 (700) for chips is integrated into the host computer 110.

[0029] Optionally, the batch testing device 600 (700) for chips is integrated into the host computer 110 and can be a fixed hardware part of the host computer 110.

[0030] Optionally, the chip testing system also includes a programmable power supply 130 and a high / low temperature chamber 140. The programmable power supply 130 is used to power the chip under test. The test array board 120 is disposed inside the high / low temperature chamber 140.

[0031] Based on the chip testing system described above, this disclosure provides a batch testing method for chips, wherein the executing entity of this batch testing method can be the aforementioned host computer. Figure 2 As shown, this batch testing method includes: S201, the host computer writes a single test firmware containing multiple test task modules into the chip under test via the CAN bus.

[0032] Optionally, a single test firmware may include test task modules such as: reliability test module (FLASH), high temperature operating life test module (HTOL), high accelerated temperature and humidity stress test module (HAST), latch-up test module (LatchUp), electromagnetic interference test module (EMI), and power temperature cycling test module (PTC). The reliability testing module includes: Idle mode, Endurance test mode, Data retention - checkerboard mode (DR_CKBD), Data retention - reverse checkerboard mode (DR_ICKBD), Data retention - ECC all zero mode (DR_ECC_ZERO), Online life test - checkerboard mode (DR_ECC_FF), Online life test - checkerboard mode (OLT_ICKBD), Online life test - reverse checkerboard mode (OLT_ICKBD), Disturb_Erase test mode, and Disturb_Write test mode.

[0033] Specifically, by building multiple test task modules into a single test firmware, the testing capabilities of all test tasks can be pre-installed in the chip under test through a single write operation. This eliminates the need to re-flash the firmware when switching between subsequent test tasks, avoiding the management issues of multiple firmware versions and reducing the risk of human error.

[0034] Specifically, by writing a single test firmware to the chip under test via the CAN bus, compared to the current related technologies that use debugging interfaces such as JTAG / SWD to program the firmware one chip at a time, multiple chips under test can be programmed and written with a single test firmware at once, thus improving the efficiency of writing firmware to the chip under test.

[0035] Specifically, upon receiving a write command, the host computer responds by writing a single test firmware containing multiple test task modules into the chip under test via the CAN bus.

[0036] S202, the host computer determines the target test task that the chip under test needs to perform from a single test firmware based on the target IO pin status of the chip under test.

[0037] Specifically, after writing a single test firmware into the chip under test (DUT), the DUT has the ability to perform multiple test tasks, but it is not yet clear which specific test task each DUT needs to perform. Therefore, it is necessary to first determine the target test task to be performed by the DUT based on the target I / O pin status.

[0038] Specifically, the target pin is the mode selection pin in the chip under test, typically IO12.

[0039] Specifically, based on the target I / O pin status, it can be determined which test tasks the chip under test (DUT) has been selected to perform. Therefore, the host computer determines the target test tasks that the DUT needs to perform from a single test firmware based on the target I / O pin status of the DUT.

[0040] Optionally, based on the target I / O pin state of the chip under test, the target test task to be performed by the chip under test is determined from a single test firmware, including: when the target I / O pin state is low, reading the level combination of the hardware configuration I / O pin group, and indexing the corresponding test task from the single test firmware according to the level combination, as the target test task; when the target I / O pin state is high, reading the software configuration parameters in the internal storage area, and indexing the corresponding test task from the single test firmware according to the software configuration parameters, as the target test task.

[0041] Specifically, if the target I / O pin is low, it indicates that the chip under test (DUT) is in hardware configuration mode. In this mode, the DUT's firmware reads the current level of the hardware configuration I / O pin group (IO8 to IO11) and treats it as a 4-bit binary code, with each code value corresponding to a side-accident task. Therefore, by reading the level combination of the hardware configuration I / O pin group, the corresponding test task can be indexed from a single test firmware as the target assessment task.

[0042] Specifically, IO8 to IO11 are pre-set to high or low levels via external circuitry, forming seven valid code combinations from 0000 to 0111 (i.e., 0 to 6), which are mapped to test tasks such as idle mode, reliability testing, power temperature cycling testing, high-acceleration temperature and humidity stress testing, electromagnetic interference testing, high-temperature operating life testing, and latch-up effect testing. The level settings of these four IO pins can be independently configured on each chip test bit of the test array board using simple hardware means such as jumpers, DIP switches, or pull-up / pull-down resistors. This allows operators to specify the test task for each chip under test (DUT) based on the test plan for each chip test bit, without any software intervention, simply by using physical jumpers when the DUT is mounted on the array board. After the DUT is powered on, the firmware immediately reads the level states of IO8 to IO11 during the initialization phase and quickly indexes the corresponding test task.

[0043] Specifically, if the target I / O pin is high, it indicates that the chip under test (DUT) is in software configuration mode. In this mode, the firmware of the DUT no longer relies on the level combination of hardware I / O pins to determine the test task. Instead, it reads the software configuration parameters pre-written in the internal storage area of ​​the DUT (usually a specific configuration area in the FLASH memory) and indexes the corresponding target assessment task from a single test firmware according to the value of the software configuration parameters.

[0044] Specifically, there is a one-to-one logical mapping relationship between software configuration parameters and hardware I / O level combinations. That is, when the parameter value is 0, it corresponds to IDLE mode, and when the parameter value is 1, it corresponds to FLASH assessment.

[0045] Specifically, the target test task is determined based on the level combination of the hardware configuration I / O pin group or the software configuration parameters in the chip's internal memory area, according to the target I / O pin state. This ensures that the target test task can still be clearly defined even if problems occur in the hardware or software mode.

[0046] S203: The host computer sends a test start command to the chip under test via the CAN bus. The chip under test executes the corresponding target test task. During the execution of the target assessment task, the host computer obtains the operating status information of the chip under test.

[0047] Specifically, after clarifying the target test tasks that the chip under test needs to perform, a test start command is sent to the chip under test via the CAN bus, ensuring that all chips under test can start the test at the same time, avoiding the time deviation and operational burden caused by starting each chip under test one by one.

[0048] Specifically, during the execution of the target test task by the chip under test (DUT), the host computer continuously acquires the DUT's operational status information via the CAN bus. Compared to related technologies where testers obtain test log data through cumbersome operations such as disassembling the chip and connecting a serial port after the test, this method allows for the acquisition of real-time operational details within the DUT, enabling testers to remotely monitor the entire DUT's real-time status without entering the test site.

[0049] S204: After the target test task is completed, the host computer generates a test report for the chip under test based on the running status information.

[0050] Specifically, after the target test task is completed, all operational status information of the chip under test is electronically summarized in the host computer. Compared with related technologies, no physical disassembly or secondary reading is required to obtain test data. After obtaining this data, a test report for the chip under test can be quickly generated according to a preset summary template. The test report can cover the entire operational trajectory of the chip under test throughout the entire assessment cycle, including but not limited to test results at each stage, key parameter change curves, timestamp records of abnormal events, and pass / fail judgment conclusions.

[0051] In this embodiment, multiple test task modules are pre-compiled into a single test firmware. When testing the chip, this single test firmware is first written to the chip under test (DUT) via the CAN bus. Based on the target I / O pin status of the DUT, the target test task to be executed by the DUT is determined from this single test firmware. Compared to the related technologies where each test task has its own Hex file, this eliminates the need to recompile and burn multiple different versions of Hex files when switching between different test tasks, thus avoiding firmware version management chaos and Hex file burning errors. After determining the target test task to be executed by the DUT, a test start command is sent to the DUT via the CAN bus, causing the DUT to execute the corresponding target test task. During the execution of the target test task, the operating status information of the DUT is acquired. In this way, the host computer can batch-start the test tasks of all DUTs via commands and continuously collect the operating status of each DUT during the test. Compared to the related technologies that rely on manual operation and periodic inspection of each chip, this reduces human intervention and improves test accuracy. After the target test task is completed, a test report for the chip under test is generated based on the running status information. This reduces the time required to process test results compared to the cumbersome process in related technologies, which requires disassembling each chip under test, reading logs via serial port, and then manually organizing the data. Therefore, the embodiments of this disclosure can improve the efficiency and accuracy of batch chip testing.

[0052] This disclosure provides another method for batch testing of chips, combined with... Figure 3 As shown, this batch testing method includes: S301: The host computer writes a single test firmware containing multiple test task modules into the chip under test via the CAN bus.

[0053] S302: The host computer determines the target test task that the chip under test needs to perform from a single test firmware based on the target IO pin status of the chip under test.

[0054] S303: The host computer receives the attribute information reported by the chip under test via the CAN bus after power-on initialization.

[0055] The attribute information includes at least one of the following: chip frequency, chip lifespan, chip serial number, chip version, chip three-channel voltage and current values, firmware version, IO pin status, and the name of the currently selected test task.

[0056] Specifically, after power-on, the chip under test (DUT) first executes the initialization program in its firmware, including a series of basic settings such as system clock configuration, I / O port initialization, CAN communication controller initialization, and FLASH configuration parameter reading. It accurately reads its own attribute information and reports this information to the host computer. Therefore, the host computer can receive the attribute information reported by the DUT via the CAN bus after power-on initialization.

[0057] Optionally, the three voltage and current values ​​of the chip correspond to the real-time voltage and current sampling values ​​of the three power supply rails: VDD (core power), VEXT (external interface power), and VDDP3 (IO power). This data can reflect whether the electrical connection of the chip under test is normal at the initial power-on stage. Therefore, the chip under test needs to report the three voltage and current values ​​of the chip.

[0058] S304, the host computer determines the ready state of the chip under test based on the attribute information.

[0059] Specifically, if all parameter values ​​in the attribute information are within a preset reasonable range, it can be determined that the chip under test is in a ready state.

[0060] S305: When all chips under test are in a ready state, the host computer sends a test start command to the chips under test via the CAN bus, so that the chips under test can execute the corresponding target test tasks and obtain the operating status information of the chips under test during the execution of the target test tasks.

[0061] Optionally, test start commands can be sent only to the chip under test that is in a ready state via the CAN bus.

[0062] S306: After the target test task is completed, the host computer generates a test report for the chip under test based on the running status information.

[0063] In this embodiment, before issuing a test start command to the chip under test (DUT), the system determines whether the DUT is in a ready state based on the attribute information reported by the DUT. Only when all DUTs are in a ready state will the step of issuing the test start command to the DUT be executed. This effectively avoids invalid tests and data deviations caused by blindly starting the test when the DUT is not fully ready.

[0064] In some embodiments, after determining the ready state of the chip under test based on attribute information, the batch testing method further includes: displaying the ready state of the chip under test on the display interface of the host computer.

[0065] In this embodiment, after determining the readiness status of the chip under test (DUT), the DUT's readiness status is also displayed on the host computer's screen. This allows testers to intuitively, quickly, and accurately interpret the readiness status of each DUT.

[0066] In some embodiments, each chip test bit on the test array board is equipped with an indicator light; after acquiring the operating status information of the chip under test, the batch testing method further includes: controlling the indicator light to present a corresponding state according to the operating status information of the chip under test; wherein, when the operating status information indicates a chip error, the indicator light is controlled to remain on red; when the operating status information indicates that the chip test is working normally, the indicator light is controlled to flash green; and when the operating status information indicates that the chip test is completed, the indicator light is controlled to remain on yellow.

[0067] In this embodiment, each chip test position on the test array board is equipped with an indicator light. After obtaining the operating status information of the chip under test, the indicator light is controlled to display the status corresponding to the operating status information of the chip under test, which allows the tester to intuitively judge the real-time status of the chip under test in performing the test task.

[0068] In some embodiments, the chip testing system further includes a programmable power supply for powering the chip under test. This disclosure provides another method for batch testing of chips, combined with… Figure 4 As shown, this batch testing method includes: S401: The host computer writes a single test firmware containing multiple test task modules into the chip under test via the CAN bus.

[0069] S402: The host computer determines the target test task that the chip under test needs to perform from a single test firmware based on the target IO pin status of the chip under test.

[0070] S403 allows the host computer to obtain the actual output voltage and current values ​​of the programmable power supply.

[0071] S404: The host computer controls the programmable power supply based on the voltage difference between the actual output voltage and the voltage setting, and the current difference between the actual output current and the current setting.

[0072] S405: The host computer sends a test start command to the chip under test (DUT) via the CAN bus. The DUT executes the corresponding target test task. During the execution of the target test task, the host computer obtains the operating status information of the DUT.

[0073] S406: After the target test task is completed, the host computer generates a test report for the chip under test based on the running status information.

[0074] In this embodiment, before sending the test start command to the chip under test (DUT) via the CAN bus, the actual output voltage and current values ​​of the programmable power supply are acquired. Based on the voltage difference between the actual output voltage and the set voltage value, and the current difference between the actual output current and the set current value, the programmable power supply is controlled. This ensures that the voltage and current conditions of the DUT during the assessment task meet the set standards, guaranteeing the accuracy of the test results.

[0075] In some embodiments, the chip testing system further includes a high-low temperature chamber, and the test array board is disposed inside the high-low temperature chamber. This disclosure provides another method for batch testing of chips, combined with... Figure 5 As shown, this batch testing method includes: The S501, the host computer writes a single test firmware containing multiple test task modules into the chip under test via the CAN bus.

[0076] S502: The host computer determines the target test task that the chip under test needs to perform from a single test firmware based on the target IO pin status of the chip under test.

[0077] S503, the host computer obtains the actual temperature and humidity values ​​inside the high and low temperature chamber.

[0078] S504, the host computer controls the high and low temperature chamber based on the temperature difference between the actual temperature value and the temperature setting value, and the humidity difference between the actual humidity value and the humidity setting value.

[0079] The S505, the host computer sends a test start command to the chip under test via the CAN bus, the chip under test executes the corresponding target test task, and obtains the operating status information of the chip under test during the execution of the target assessment task.

[0080] S506: After the target test task is completed, the host computer generates a test report for the chip under test based on the running status information.

[0081] In this embodiment, before sending the test start command to the chip under test (DUT) via the CAN bus, the actual temperature and humidity values ​​inside the high and low temperature chamber are acquired. The chamber is then controlled based on the temperature difference between the actual temperature and the set temperature, and the humidity difference between the actual humidity and the set humidity. This ensures that the environmental conditions during the DUT's test meet the set standards, guaranteeing the accuracy of the test results.

[0082] In some embodiments, the batch testing method further includes: upon receiving an upgrade firmware data packet, simultaneously sending the upgrade firmware data packet to all chips under test via a CAN bus in the form of a broadcast frame; so that the chips under test receive the upgrade firmware data packet and complete the firmware update through a preset BootLoader.

[0083] In this embodiment, by broadcasting upgrade firmware data packets via the host computer's CAN bus and receiving them through the bootloader of the chip under test, parallel online firmware upgrades for the entire array of chips are achieved in a batch chip testing scenario. Compared to related technologies that require disassembling each chip individually and connecting a programmer for serial programming, with each round taking 0.5 to 1 hour, this method can reduce the batch firmware upgrade time to within minutes, significantly improving the efficiency of firmware upgrades for the chips under test.

[0084] Combination Figure 6 As shown, this disclosure provides a batch testing device 600 for chips, applied to a host computer in a chip testing system. The testing system also includes a test array board with multiple chip test positions. The host computer communicates with the chip under test (DUT) at the chip test positions via a CAN bus. The batch testing device 600 includes: a firmware writing module 601, a task determination module 602, an instruction sending module 603, and a report generation module 604. The firmware writing module 601 writes a single test firmware containing multiple test task modules into the DUT via the CAN bus. The task determination module 602 determines the target test task to be executed by the DUT from the single test firmware based on the target I / O pin status of the DUT. The instruction sending module 603 sends a test start instruction to the DUT via the CAN bus. The DUT executes the corresponding target test task, and during the execution of the target test task, it acquires the DUT's operating status information. The report generation module 604 generates a test report for the DUT based on the operating status information after the target test task is completed.

[0085] Combination Figure 7As shown, this disclosure provides a batch testing apparatus 700 for chips, including a processor 701 and a memory 702. Optionally, the apparatus may further include a communication interface 703 and a bus 704. The processor 701, communication interface 703, and memory 702 can communicate with each other via the bus 704. The communication interface 703 can be used for information transmission. The processor 701 can call logical instructions in the memory 702 to execute the batch testing method for chips described in the above embodiment.

[0086] Furthermore, the logic instructions in the aforementioned memory 702 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0087] The memory 702, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 701 executes functional applications and data processing by running the program instructions / modules stored in the memory 702, thereby implementing the batch testing method for chips described in the above embodiments.

[0088] The memory 702 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 702 may include high-speed random access memory and may also include non-volatile memory.

[0089] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the above-described batch testing method for chips.

[0090] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., and other media capable of storing program code.

[0091] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0092] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A method for batch testing of chips, characterized in that, The host computer is used in the chip testing system. The testing system also includes a test array board with multiple chip test positions. The host computer communicates with the chip under test at the chip test positions via a CAN bus. Batch testing methods include: A single test firmware containing multiple test task modules is written into the chip under test via the CAN bus; Based on the target I / O pin status of the chip under test, determine the target test task that the chip under test needs to perform from a single test firmware; The test start command is sent to the chip under test via the CAN bus. The chip under test executes the corresponding target test task. During the execution of the target assessment task, the operating status information of the chip under test is obtained. After the target test task is completed, a test report for the chip under test is generated based on the running status information.

2. The batch testing method according to claim 1, characterized in that, Based on the target I / O pin states of the chip under test, determine the target test tasks that the chip under test needs to perform from a single test firmware, including: When the target IO pin is in a low state, read the level combination of the hardware configuration IO pin group, and index the corresponding test task from a single test firmware according to the level combination, as the target test task; When the target IO pin is at a high level, read the software configuration parameters in the internal storage area, and index the corresponding test task from a single test firmware according to the software configuration parameters, and use it as the target test task.

3. The batch testing method according to claim 1, characterized in that, Send a test start command to the chip under test via the CAN bus, including: Receive the attribute information reported by the chip under test via the CAN bus after power-on initialization; Determine the ready state of the chip under test based on the attribute information; With all chips under test in a ready state, a test start command is sent to the chip under test via the CAN bus.

4. The batch testing method according to claim 3, characterized in that, After determining the readiness status of the chip under test based on its attribute information, the batch testing method also includes: The readiness status of the chip under test is displayed on the host computer's display interface.

5. The batch testing method according to any one of claims 1 to 4, characterized in that, A single test firmware contains test task modules, including: reliability test module, high temperature operating life test module, high accelerated temperature and humidity stress test module, latch-up effect test module, electromagnetic interference test module, and power temperature cycle test module; The reliability testing module includes: idle mode, durability test mode, data retention - checkerboard mode, data retention - anti-checkerboard mode, data retention - ECC all zero mode, online life test - checkerboard mode, online life test - checkerboard mode, online life test - anti-checkerboard mode, erase interference test mode, and write interference test mode.

6. The batch testing method according to any one of claims 1 to 4, characterized in that, The chip testing system also includes a programmable power supply for powering the chip under test; Before sending the test start command to the chip under test via the CAN bus, the batch testing method also includes: Obtain the actual output voltage and actual output current values ​​of the programmable power supply; The programmable power supply is controlled based on the voltage difference between the actual output voltage and the voltage setting, and the current difference between the actual output current and the current setting.

7. The batch testing method according to any one of claims 1 to 4, characterized in that, Also includes: Upon receiving the firmware upgrade data packet, the firmware upgrade data packet is simultaneously sent to all chips under test via the CAN bus in the form of a broadcast frame. This allows the chip under test to receive the firmware upgrade data package and complete the firmware update via the pre-installed BootLoader.

8. A batch testing apparatus for chips, characterized in that, A host computer is used in the chip testing system. The testing system also includes a test array board with multiple chip test positions. The host computer communicates with the chip under test at the chip test positions via a CAN bus. The batch testing device includes: The firmware writing module is used to write a single test firmware containing multiple test task modules into the chip under test via the CAN bus. The task determination module is used to determine the target test task that the chip under test needs to perform from a single test firmware based on the target IO pin status of the chip under test. The instruction sending module is used to send test start instructions to the chip under test via the CAN bus. The chip under test executes the corresponding target test task. During the execution of the target assessment task, the module obtains the operating status information of the chip under test. The report generation module is used to generate a test report for the chip under test based on the running status information after the target test task is completed.

9. A batch testing apparatus for chips, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to perform a batch testing method for a chip as described in any one of claims 1 to 7 when executing the program instructions.

10. A chip testing system, characterized in that, include: Host computer; The test array board has multiple chip test positions, and the host computer communicates with the chip under test on the chip test positions via a CAN bus. The batch testing device for chips as described in claim 8 or 9 is integrated into a host computer.

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