A method for detecting the connection state of a motherboard of a memory chip FT testing machine

Abstract

The application relates to the technical field of chip testing, and discloses a motherboard connection state detection method for an FT test machine table of a storage chip, which comprises the following steps: when a connectivity fault is detected at a DSA end, a cable is disassembled, and the motherboard is separated from the DSA end of a storage test machine; a test resource board card is connected with an upper computer, the motherboard is connected with a motherboard test board, and a loop of the test resource board card-motherboard-motherboard test board is formed; a test program is run through the upper computer; whether a problem of the motherboard itself or a connection problem between the test resource board card and the motherboard can be checked out, and it is avoided that the motherboard is difficult to check out due to hardware failure or that the motherboard has stains to affect connectivity. For each motherboard, whether the motherboard has a connectivity problem can be quickly analyzed through test data and test results, such as a connectivity test failure, and the failure type and failure channel can also be quickly confirmed, which is particularly important for improving the quality and stability of the motherboard.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and more specifically to a method for detecting the motherboard connection status of a memory chip FT test machine. Background Technology

[0002] In the field of final test (FT) testing for memory chips, the motherboard, as the core hub connecting the test equipment and the chip under test, plays a crucial role in signal transmission, power distribution, and data interaction. The stability and reliability of its connection directly determine the integrity of the test signals, the continuity of the test process, and the accuracy of the test results, making it a key link in ensuring the efficiency and yield of mass production testing for memory chips.

[0003] As the core interface between the board and the chip under test (DUT), the motherboard's connection status (such as loose connectors, poor wiring harness contact, open / short circuits in signal paths, etc.) is a significant factor contributing to channel timing differences. However, current detection solutions generally focus on open / short circuit detection at the socket end. Since the connection from the test resource board to the socket end involves the motherboard, cables, and DSA hardware structures, detecting open / short circuits only at the socket end makes it difficult to pinpoint the location of open / short circuits when connectivity issues arise. The lack of a systematic detection method for the motherboard's connection status makes it difficult to quickly locate signal deviations caused by connection problems. Often, after abnormal test results appear, manual troubleshooting is required to trace back to the motherboard connection fault, which not only prolongs the troubleshooting cycle but also fails to prevent test errors caused by abnormal connection status at the source, severely restricting test accuracy and efficiency. This is especially true for mass-produced equipment, directly impacting the device's OEE and increasing testing costs.

[0004] Based on this, the present invention provides a motherboard connection status detection method for a storage chip FT test machine that can quickly check whether a connection failure between the test resource board and the motherboard is detected when a connectivity failure is detected at the DSA end. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by providing a motherboard connection status detection method for a memory chip FT test machine, thereby solving the technical problem of not being able to quickly locate the location of an open or short circuit when a connectivity fault is detected at the DSA end.

[0006] The objective of this invention can be achieved through the following technical solutions: A method for detecting the motherboard connection status of a memory chip FT test instrument includes the following steps: Step S1: Calibrate the test resource boards and select the test resource boards that have passed the calibration; Step S2: Connect the test resource board to the motherboard, and at the same time connect the motherboard to the DSA terminal of the chip under test via a cable for testing; Step S3: When a connectivity fault is detected at the DSA end, disconnect the cable and separate the motherboard from the DSA end of the storage tester; Step S4: Connect the test resource board to the host computer, and connect the motherboard to the motherboard test board to form a loop: test resource board → motherboard → motherboard test board. Step S5: Run the test program via the host computer; Step S6: Collect the test results output by the host computer and determine the connection status of each channel on the motherboard based on these test results.

[0007] As a further aspect of the present invention: the calibration of the test resource board in step S1 specifically includes the following steps: Step S11: Connect the test resource board to the host computer; Step S12: Run the calibration program via the host computer; Step S13: If the host computer displays PASS, it is determined that the test resource board calibration has passed and its function is normal; otherwise, it is determined that the test resource board calibration has failed and its function is abnormal.

[0008] As a further aspect of the present invention: in step S4, a connector is provided on the motherboard test board, and the connector on the motherboard test board is connected to the connector on the motherboard.

[0009] As a further aspect of the present invention, step S5 specifically includes the following steps: Step S51: Apply voltage to the test resource board via the host computer, and there are configuration resistors on the motherboard test board; Step S52: Measure the current value of the test resource board through the host computer.

[0010] As a further aspect of the present invention: each channel on the motherboard test board is equipped with a resistor, and when the motherboard test board is placed on top of the motherboard, a complete circuit is formed: test resource board → motherboard → motherboard test board.

[0011] As a further aspect of the present invention: when the measured current value is higher than the maximum value of the threshold range, it is determined that the motherboard has an open circuit fault; when the measured current value is lower than the minimum value of the threshold range, it is determined that the motherboard has a short circuit fault; when the measured current value is within the threshold range, it is determined that the connection status of the motherboard is normal.

[0012] As a further aspect of the present invention: each digital channel on the motherboard test board is equipped with a 1.6 Kohm resistor, and each power channel on the motherboard test board is equipped with a 10 ohm resistor.

[0013] As a further aspect of the present invention: when the host computer runs the calibration program, a test excitation voltage is applied through the test resource board, a voltage of 1.6V is applied to the digital channel and a voltage of 1V is applied to the power channel, the threshold range of the measured current value is set to 0.95mA to 1.05mA for the digital channel, and the threshold range of the measured current value is set to 95mA to 105mA for the power channel.

[0014] As a further aspect of the present invention: the method is applied to a motherboard connection status detection system for a memory chip FT test machine, the system comprising: The test resource board is used to provide stimulus signals to the resource under test and to provide specific stimulus signals according to different test requirements during the test process. The motherboard has connectors for rewiring channels from the test resource board, making it easy to route the specified test channels to the corresponding test points and configure trace lines of equal length for specific signals. The motherboard test board has connectors that connect to the motherboard's connectors. Each pin of the motherboard test board is equipped with a resistor to detect the connection status of each channel on the motherboard. Cables are used to connect the motherboard to the DSA terminal of the chip under test during initial testing. The host computer is connected to the test resource board and applies the test excitation voltage through the test resource board.

[0015] The beneficial effects of this invention are: (1) In this invention, considering that when a connectivity fault is detected at the DSA end, the fault may occur at any location between the test resource board → motherboard → cable → DSA end, the connectivity between the test resource board and the motherboard can be checked by using the motherboard test board to check whether the problem is with the motherboard itself or the connection between the test resource board and the motherboard. This avoids the difficulty in detecting the fault due to hardware failure or contamination of the motherboard affecting connectivity, and is a supplement to the connectivity check at the DSA end. For each motherboard, the test data and test results can be used to quickly analyze whether there is a connectivity problem, such as a connectivity test failure, and can also quickly confirm the failure type and failure channel, which is particularly important for improving the quality and stability of the motherboard. Especially in the mass production stage, when repairing closed points, this solution can be used to quickly confirm whether the closed points are caused by a connectivity fault in the motherboard. (2) In this invention, the test resource board is checked in advance. Therefore, after selecting the calibrated test resource board, the connection fault detected in the subsequent testing process is either a problem with the motherboard itself or a connection problem between the test resource board and the motherboard. This allows for a more intuitive and faster detection of whether the connection problem occurs between the motherboard and the test resource board. (3) In this invention, some test points may be shut down due to poor connection status during mass production, resulting in low yield. Through the re-testing process of this embodiment, it can be quickly confirmed whether the poor connection status of the shut-down point is caused by a connection failure between the test resource board and the motherboard. Attached Figure Description

[0016] The invention will now be further described with reference to the accompanying drawings.

[0017] Figure 1 This is a schematic diagram of the detection state in this invention; Figure 2 This is a schematic diagram of the connection state in this invention; Figure 3 This is a circuit diagram of the present invention; Figure 4 This is a schematic diagram of the overall technical solution architecture in this invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figures 1-4 As shown, the present invention is a method for detecting the motherboard connection status of a memory chip FT test instrument, comprising the following steps: Step S1: Calibrate the test resource boards and select the test resource boards that have passed the calibration; Step S2: Connect the test resource board to the motherboard, and at the same time connect the motherboard to the DSA terminal of the chip under test via a cable for testing; Step S3: When a connectivity fault is detected at the DSA end, disconnect the cable and separate the motherboard from the DSA end of the storage tester; Step S4: Connect the test resource board to the host computer, and connect the motherboard to the motherboard test board to form a loop: test resource board → motherboard → motherboard test board. Step S5: Run the test program via the host computer; Step S6: Collect the test results output by the host computer, and determine the connection status of each channel on the motherboard based on these test results. In practical applications, this embodiment considers that when a connectivity fault is detected at the DSA end, the fault may occur anywhere between the test resource board → motherboard → cable → DSA end. By using a motherboard test board to detect the connectivity between the test resource board and the motherboard, it is possible to check whether the problem lies with the motherboard itself or the connection between the test resource board and the motherboard. This avoids the difficulty in detecting the fault due to hardware failure or contamination of the motherboard affecting connectivity, thus supplementing the connectivity check at the DSA end. For each motherboard, the test data and results can be used to quickly analyze whether there is a connectivity problem, such as a connectivity test failure, and can also quickly identify the failure type and failure path. This is particularly important for improving the quality and stability of the motherboard. Especially in the mass production stage, when repairing closed points, this solution can be used to quickly confirm whether the closed points are caused by a connectivity fault on the motherboard.

[0020] It should be noted that after the initial detection of a connectivity fault, the DSA terminal and cable are removed. The fault inspection between the motherboard, cable, and DSA terminal is not within the scope of this application. The fault inspection of this route is confirmed through other methods, and this inspection method is existing technology. This application has not improved upon it. Therefore, it is not necessary to disclose its specific mechanical and circuit structures, and this does not affect the completeness of this application. Specifically, the fault inspection between the motherboard, cable, and DSA terminal can be carried out by segmented isolation and troubleshooting: First, eliminate the TBST, Socket, and DUT back-end components; then conduct a visual inspection of the connector pins, cables, and PCB appearance; conduct continuity and insulation resistance electrical measurements, combined with machine loopback diagnosis; then use the replacement method to replace the Loadboard, cable assembly, and DSA module respectively to locate the faulty component, and at the same time check the assembly and locking status to distinguish whether the fault belongs to the motherboard, cable assembly, or DSA terminal.

[0021] like Figures 1-4 As shown, in a preferred embodiment of the present invention, the calibration of the test resource board in step S1 specifically includes the following steps: Step S11: Connect the test resource board to the host computer; Step S12: Run the calibration program via the host computer; Step S13: If the host computer displays PASS, it is determined that the test resource board calibration has passed and its function is normal; otherwise, it is determined that the test resource board calibration has failed and its function is abnormal.

[0022] It should be noted that the calibration procedure of the host computer is existing technology, and this application has not improved it. Therefore, it is not necessary to disclose its specific mechanical structure and circuit structure, and this does not affect the integrity of this application.

[0023] In practical applications, the test resource boards in this embodiment are checked in advance. Therefore, after selecting the calibrated test resource boards, the connectivity faults detected in the subsequent testing process are either problems with the motherboard itself or connection problems between the test resource boards and the motherboard.

[0024] like Figures 1-4 As shown, in a preferred embodiment of the present invention, in step S4, a connector is provided on the motherboard test board, and the connector on the motherboard test board is connected to the connector on the motherboard.

[0025] In practical applications, the motherboard test board has its own connector, and the motherboard also has its own connector. The test board and the motherboard are connected through the connector.

[0026] like Figures 1-4 As shown, in a preferred embodiment of the present invention, step S5 specifically includes the following steps: Step S51: Apply voltage to the test resource board via the host computer, and there are configuration resistors on the motherboard test board; Step S52: Measure the current value of the test resource board through the host computer.

[0027] In practical applications, this embodiment involves three connection states between the motherboard and the test resource board: normal connection, short circuit, and open circuit. Both short circuit and open circuit represent connection abnormalities. When designing the motherboard test board, a resistor R is configured on each corresponding channel. When the motherboard test board is placed on top of the motherboard, a complete circuit is formed: test resource board → motherboard → motherboard test board. By running the host computer test program, a certain voltage U is applied to the test resource board. According to Ohm's law, the current measured on the test resource board is I = U / R. If an open circuit fault exists in a channel, the measured current is close to 0; if a short circuit fault exists, the measured current is very large.

[0028] like Figures 1-4 As shown, in a preferred embodiment of the present invention, each channel on the motherboard test board is equipped with a resistor. When the motherboard test board is placed on top of the motherboard, a complete circuit is formed: test resource board → motherboard → motherboard test board.

[0029] In practical applications, this embodiment does not limit the specific number of resistors. The specific number of resistors depends on the number of channels, thereby improving adaptability and flexibility.

[0030] like Figures 1-4As shown, in a preferred embodiment of the present invention, when the measured current value is higher than the maximum value of the threshold range, it is determined that the motherboard has an open circuit fault; when the measured current value is lower than the minimum value of the threshold range, it is determined that the motherboard has a short circuit fault; when the measured current value is within the threshold range, it is determined that the connection status of the motherboard is normal.

[0031] In practical applications, some test points may be shut down during mass production due to poor connection status, resulting in low yield. Through the re-testing process in this embodiment, it can be quickly confirmed whether the poor connection status of the shut-down point is caused by a connection failure between the test resource board and the motherboard.

[0032] like Figures 1-4 As shown, in a preferred embodiment of the present invention, each digital channel on the motherboard test board is equipped with a 1.6 Kohm resistor, and each power channel on the motherboard test board is equipped with a 10 ohm resistor.

[0033] like Figures 1-4 As shown, in a preferred embodiment of the present invention, when the host computer runs the calibration program, a test excitation voltage is applied through the test resource board, a voltage of 1.6V is applied to the digital channel and a voltage of 1V is applied to the power channel, the threshold range of the measured current value is set to 0.95mA to 1.05mA for the digital channel, and the threshold range of the measured current value is set to 95mA to 105mA for the power channel.

[0034] In practical application, this embodiment runs a pre-developed program on a host computer, applies a test stimulus U through a test resource board, and configures a resistor R on each corresponding channel. The test resource board reads the current value of each channel. According to Ohm's law, I=U / R, the current on the digital channel is I=1.6V / 1.6Kohm=1mA; the current on the power channel is I=1V / 10ohm=100mA. For the digital channel, a measured value below 0.95mA indicates a short circuit fault; a measured value above 1.05mA indicates an open circuit fault; and a measured value between 0.95mA and 1.05mA indicates a normal connection. For the power channel, a measured value below 95mA indicates a short circuit fault; a measured value above 105mA indicates an open circuit fault; and a measured value between 95mA and 105mA indicates a normal connection.

[0035] like Figures 1-4 As shown, in a preferred embodiment of the present invention, the method is applied to a motherboard connection status detection system for a memory chip FT test machine, the system comprising: The test resource board is used to provide stimulus signals to the resource under test and to provide specific stimulus signals according to different test requirements during the test process. The motherboard has connectors for rewiring channels from the test resource board, making it easy to route the specified test channels to the corresponding test points and configure trace lines of equal length for specific signals. The motherboard test board has connectors that connect to the motherboard's connectors. Each pin of the motherboard test board is equipped with a resistor to detect the connection status of each channel on the motherboard. Cables are used to connect the motherboard to the DSA terminal of the chip under test during initial testing. The host computer is connected to the test resource board and applies the test excitation voltage through the test resource board.

[0036] The working principle of this invention: The above embodiments of this invention provide a method for detecting the motherboard connection status of a memory chip FT test machine. Considering that when a connectivity fault is detected at the DSA end, the fault may occur at any point between the test resource board → motherboard → cable → DSA end, detecting the connectivity between the test resource board and the motherboard using a motherboard test board can determine whether the problem is with the motherboard itself or the connection between the test resource board and the motherboard. This avoids the difficulty in detecting connectivity issues caused by hardware failures or contamination on the motherboard, thus supplementing connectivity checks at the DSA end. For each motherboard, test data and results can quickly analyze whether a connectivity problem exists, such as a connectivity test failure, and can also quickly identify the failure type and failure path. This is particularly important for improving the quality and stability of the motherboard. Especially in mass production, when repairing closed points, this solution can be used to quickly confirm whether the closed points are caused by a connectivity fault on the motherboard.

[0037] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the claims of this invention should still fall within the patent coverage of this invention.

Claims

1. A method for detecting the motherboard connection status of a memory chip FT test instrument, comprising the following steps: Step S1: Calibrate the test resource boards and select the test resource boards that have passed the calibration; Step S2: Connect the test resource board to the motherboard, and at the same time connect the motherboard to the DSA terminal of the chip under test via a cable for testing; Step S3: When a connectivity fault is detected at the DSA end, disconnect the cable and separate the motherboard from the DSA end of the storage tester; Step S4: Connect the test resource board to the host computer, and connect the motherboard to the motherboard test board to form a loop: test resource board → motherboard → motherboard test board. Step S5: Run the test program via the host computer; Step S6: Collect the test results output by the host computer and determine the connection status of each channel on the motherboard based on these test results.

2. The method for detecting the motherboard connection status of a memory chip FT test machine according to claim 1, characterized in that, The calibration of the test resource board in step S1 specifically includes the following steps: Step S11: Connect the test resource board to the host computer; Step S12: Run the calibration program via the host computer; Step S13: If the host computer displays PASS, it is determined that the test resource board calibration has passed and its function is normal; otherwise, it is determined that the test resource board calibration has failed and its function is abnormal.

3. The method for detecting the motherboard connection status of a memory chip FT test machine according to claim 1, characterized in that, In step S4, a connector is provided on the motherboard test board, and the connector on the motherboard test board is connected to the connector on the motherboard.

4. The method for detecting the motherboard connection status of a memory chip FT test machine according to claim 1, characterized in that, Step S5 specifically includes the following steps: Step S51: Apply voltage to the test resource board via the host computer, and there are configuration resistors on the motherboard test board; Step S52: Measure the current value of the test resource board through the host computer.

5. The method for detecting the motherboard connection status of a memory chip FT test machine according to claim 4, characterized in that, Each channel on the motherboard test board is equipped with a resistor. When the motherboard test board is placed on top of the motherboard, a complete circuit is formed: test resource board → motherboard → motherboard test board.

6. The method for detecting the motherboard connection status of a memory chip FT test machine according to claim 5, characterized in that, When the measured current value is higher than the maximum value of the threshold range, the motherboard is determined to have an open circuit fault; when the measured current value is lower than the minimum value of the threshold range, the motherboard is determined to have a short circuit fault; when the measured current value is within the threshold range, the connection status of the motherboard is determined to be normal.

7. The method for detecting the motherboard connection status of a memory chip FT test machine according to claim 6, characterized in that, Each digital channel on the motherboard test board is equipped with a 1.6 Kohm resistor, and each power channel on the motherboard test board is equipped with a 10 ohm resistor.

8. The method for detecting the motherboard connection status of a memory chip FT test machine according to claim 7, characterized in that, When the host computer runs the calibration program, it applies test excitation voltage through the test resource board, applies 1.6V to the digital channel and 1V to the power channel, sets the threshold range of the measured current value for the digital channel to 0.95mA to 1.05mA, and sets the threshold range of the measured current value for the power channel to 95mA to 105mA.

9. The method for detecting the motherboard connection status of a memory chip FT test instrument according to claim 1, characterized in that, The method is applied to a motherboard connection status detection system for a memory chip FT test machine, the system comprising: The test resource board is used to provide stimulus signals to the resource under test and to provide specific stimulus signals according to different test requirements during the test process. The motherboard has connectors for rewiring channels from the test resource board, making it easy to route the specified test channels to the corresponding test points and configure trace lines of equal length for specific signals. The motherboard test board has connectors that connect to the motherboard's connectors. Each pin of the motherboard test board is equipped with a resistor to detect the connection status of each channel on the motherboard. Cables are used to connect the motherboard to the DSA terminal of the chip under test during initial testing. The host computer is connected to the test resource board and applies the test excitation voltage through the test resource board.

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