Laser radar zero position detection method and system based on pulse period ratio determination

Abstract

The present application relates to the field of laser radar and embedded signal processing technology, and particularly provides a laser radar zero position detection method and system based on pulse period ratio determination. The method comprises constructing a PA pulse signal preprocessing and double-edge detection link to improve the angle resolution through double detection of rising and falling edges; designing a ring buffer reference period storage module to automatically maintain and zero-delay read the reference period value of the same angle position of the previous cycle; using a pulse period ratio determination module to determine the zero position by the ratio relationship between the current period value and the reference period value; constructing a rotation speed adaptive light emitting frequency control module to dynamically adjust the number of light emissions per cycle according to the real-time PA period value; designing an LFSR pseudo-random START offset module, and outputting the final laser trigger signal through a START pulse generation module. The method realizes high-reliability zero position detection and supports wide-range rotation speed adaptation and constant angle resolution control.

Description

Technical Field

[0001] This invention relates to the fields of lidar and embedded signal processing technology, and in particular to a lidar zero-position detection method and system based on pulse period ratio determination. Background Technology

[0002] Mechanical lidar, as a core sensor in fields such as autonomous driving, industrial safety, and robot navigation, achieves 360-degree scanning and ranging by rotating an optical system driven by a motor. The core of angle synchronization is zero-position detection, which determines the starting position (0 degrees) of the rotational scan and controls the timing of laser emission accordingly. The accuracy and reliability of zero-position detection directly affect the quality of point cloud data and the reliability of ranging. Although lidar zero-position detection technology has a promising future, existing methods still face the following technical challenges in achieving efficient zero-position detection: The reliance on hardware zero-position sensors leads to high costs and low reliability. Existing mechanical lidar typically uses incremental code disks in conjunction with hardware zero-position sensors to achieve angle synchronization. This involves mounting magnets on the motor shaft, detecting zero-position pulses using Hall effect sensors, creating light-transmitting notches on the code disk, and using photoelectric pairs to generate the zero-position signal; an encoder with a Z-pulse channel is also used. However, these hardware solutions increase the bill of materials (BOM) cost by approximately 5-15 RMB per unit (sensor + signal conditioning circuit), and require precise alignment of the sensor with physical markings during assembly, with assembly tolerances within ±0.1mm. This process is complex, and yield is limited by assembly accuracy. The zero-position sensor is an independent hardware component; damage, broken signal lines, or poor contact can lead to permanent loss of the zero-position signal, which the system cannot automatically recover from. Statistics show that approximately 15% of lidar field failures are related to the zero-position sensor.

[0003] Phase-locked loop (PLL) solutions suffer from narrow speed adaptation range and long locking times. PLL solutions require several motor cycles (typically 50-200ms) to complete locking, making effective measurement impossible during startup; speed changes exceeding ±10% may lead to loss of lock, and they do not support a wide speed adaptation range of 10Hz~30Hz. Fixed-frequency division schemes exhibit unstable angular resolution. Under fixed-frequency division, motor speed fluctuations directly cause changes in angular resolution. For example, at a 20Hz design point, a speed fluctuation of ±5% results in an angular resolution deviation of ±10%, affecting the consistency of point cloud data. Fixed-phase interference exists when multiple devices operate in the same scene. Under fixed-frequency or PLL locking schemes, fixed phase relationships exist between multiple devices, causing mutual interference of laser signals and reducing ranging reliability. Current technologies generally assume that zero-position detection must rely on hardware sensors (photoelectric, Hall effect, Z-pulse), neglecting the possibility of software zero-position determination based on the ratio of encoder pulse periods. This technological bias leads to high cost and low reliability of zero-position detection systems. Summary of the Invention

[0004] In view of this, the present invention provides a lidar zero-position detection method and system based on pulse period ratio determination, which can achieve highly reliable zero-position detection without increasing hardware costs, and supports wide-range speed adaptation and constant angular resolution control.

[0005] In a first aspect, the present invention provides a lidar zero-position detection method based on pulse period ratio determination, the method comprising: Step 1: Construct a PA pulse signal preprocessing and dual-edge detection link, eliminate metastability through three-level register synchronization, and improve angular resolution through dual detection of rising and falling edges; Step 2: Design a ring-shaped buffer reference period storage module to automatically maintain and read the reference period value of the previous ring at the same angular position with zero latency; Step 3: Use the pulse period ratio determination module to determine the zero position by the ratio of the current period value to the reference period value; Step 4: Construct a rotation speed adaptive emission frequency control module to dynamically adjust the number of emission cycles per revolution based on the real-time PA cycle value in order to maintain a constant angular resolution; Step 5: Design the LFSR pseudo-random START offset module to suppress mutual interference when multiple devices are working in the same scene, and output the final laser trigger signal through the START pulse generation module.

[0006] Optionally, step 1 includes: Step 11, Data Acquisition and Interface Configuration: Acquire the power amplifier (PA) pulse signal generated by the code disk. The code disk is an incremental photoelectric encoder, installed on the motor shaft, which generates 28 PA pulse signals per revolution, corresponding to 28 optical windows; the signal level is LVCMOS33, and the highest frequency is 30Hz×28=840Hz. Step 12, Three-level register synchronization: The PA pulse signal is synchronized in three levels using a 100MHz system clock to eliminate metastability across clock domains; the synchronization links are, in sequence, PA input signal, first-level synchronization PA_d0, second-level synchronization PA_d1, and third-level synchronization PA_D; the total synchronization delay is 30ns, which is 300MHz clock cycles. Step 13, Cross-clock domain synchronization: Synchronize the PA_D signal in the 100MHz domain to the 10MHz processing clock domain, and obtain PA_VLD through the level 1 register synchronization; Step 14, Double Edge Detection: Detect the rising and falling edges of the PA signal in the 10MHz clock domain; each PA pulse generates two edge events, a rising edge and a falling edge, improving the angular resolution from 28 pulses / revolution to 56 edges / revolution. Step 15, Angular resolution calculation: Original resolution 360 degrees / 28 = 12.86 degrees / pulse; Resolution after double edge detection 360 degrees / 56 = 6.43 degrees / edge.

[0007] Optionally, step 2 includes: Step 21, Periodic Timer Design: A 20-bit counter driven by a 10MHz clock with an accuracy of 100ns is used. The timer is cleared and restarted on the rising edge, and retains the maximum value when overflowing. Step 22, Current Period Value Latch: Latch the previous count value on each rising edge as the current PA period value T_cur; Step 23, Circular Buffer Array Design: Maintain an array of 28 20-bit registers, cycle_cnt_arr[0:27], to store the historical values ​​of the most recent 28 PA cycles; when each rising edge arrives, the new value is stored in the 0th position of the array, the original data is shifted to the right in turn, and the furthest data automatically overflows; Step 24, Reference Period Value Reading: The 27th bit is always the reference period value at the same angle position of the previous revolution; Step 25: Correspondence between the buffer array and the number of code disk pulses: The buffer length of 28 elements corresponds one-to-one with the number of code disk pulses of 28 pulses / cycle. The Nth element stores the period value of the Nth PA pulse. The update frequency is once for each rising edge, and the data delay is 28 rising edges.

[0008] Optionally, step 3 includes: Step 31, Zero-position feature analysis: The code disk has a widened mark at the zero position, and the PA pulse interval at the zero position is equal to 1.5 times that at the normal position, that is, T_zero = 1.5 × T_normal; Step 32, Ratio Determination Algorithm: Calculate the ratio between the current cycle value and the reference cycle value; the determination condition formula is: T_cur=T_ref+T_ref[19:1], where T_ref[19:1] represents T_ref shifted one position to the right, that is, the integer part of T_ref / 2; Step 33, FPGA implementation: Calculate 1.5 times the reference period value T_ref as the comparison benchmark; first, shift T_ref one bit to the right to obtain the integer part half_ref of T_ref / 2; then calculate the sum of T_ref and half_ref, sum_ref, i.e., sum_ref = T_ref + T_ref / 2 = 1.5 × T_ref; finally, compare the current period value T_cur with sum_ref. If they are equal, determine that the current position is zero. The above determination is equivalent to T_cur ≈ 1.5 × T_ref, and the determination interval is [1.4 × T_ref, 1.6 × T_ref]. Step 34, Synchronization Determination: After power-on, synchronization is established first to determine zero position; the synchronization establishment process is as follows: on each rising edge of PA and when the synchronization flag syn is 0, the synchronization counter syn_cnt is incremented by 1; when syn_cnt accumulates to 255, it is determined that the motor speed has stabilized, and the synchronization flag syn is set to 1; thereafter, the system enters normal working state and performs zero position detection. The synchronization condition is that the motor speed is determined to be stable after accumulating 255 rising edges. Step 35, Zero Position Detection Output: The Sync counter resets to zero after detecting a zero position. Each PA edge increments Sync by 1, and the Sync value cycles between 0 and 57, directly corresponding to the scanning angle position. The rising and falling edges of the PA signal are detected simultaneously in the 10MHz clock domain. The rising edge detection logic is as follows: when PA_D is high and PA_VLD is low, it indicates that a rising edge has been detected. The falling edge detection logic is as follows: when PA_D is low and PA_VLD is high, it indicates that a falling edge has been detected.

[0009] Optionally, step 4 includes: Step 41, Speed ​​Threshold Table Design: Determine the motor speed based on the PA cycle value to determine the number of times the light is emitted per revolution; Step 42, Light emission count selection logic: Based on the comparison result between the current PA cycle value T_cur and the preset threshold, the number of light emission counts N per cycle is automatically determined; when T_cur is greater than 35714, N=60; when T_cur is greater than 23810, N=40; when T_cur is greater than 17857, N=30; otherwise, N=20; Step 43, Frequency division coefficient calculation: Calculate the frequency division coefficient D based on the current PA cycle value T_cur and the number of light emission times per cycle N; the frequency division coefficient D = T_cur / N, which means that a laser trigger is generated once every D 10MHz clock cycles; Step 44, START pulse generation: The frequency divider counter is cleared to zero on the rising edge or when measurement is disabled, and returns to zero when it counts to D-4 and outputs the START pulse; the pulse width is 6 x 100MHz clock cycles, i.e. 60ns; Step 45: Special handling for zero position: The PA cycle at the zero position is 1.5 times that at the normal position, and the number of light emission times is twice the normal value.

[0010] Optionally, step 5 includes: Step 51, LFSR Design: Use an 8-bit linear feedback shift register (LFSR) to generate a pseudo-random sequence; the feedback polynomial of the LFSR is x. 8 +x 6 +x 5 +x 4+1 corresponds to tap positions bit7, bit5, bit4, and bit3; the feedback logic is: new input bit0 = bit7 ⊕ bit5 ⊕ bit4 ⊕ bit3; each clock cycle, the register shifts right by one bit, and the feedback value is shifted into the most significant bit; the LFSR generates a pseudo-random sequence with a period of 255; Step 52, Seed value generation: The seed value is determined by the system status parameters to ensure that the random sequence of each device is different; the seed value is calculated by taking the sum of the high 8 bits and low 8 bits of the maximum echo intensity value max_intensity, where max_intensity is the maximum echo intensity value; Step 53, Random Delay Calculation: Take the lower 5 bits of the LFSR output as the original random value, ranging from 0 to 31, limit it to 0 to 24, and finally multiply it by 10 to obtain the delay value. The delay range is 0 to 240 ns, with a step of 10 ns. Step 54, Delay application method: Apply a random delay before the START pulse. When the trigger signal arrives, load the delay value into the delay counter; after the counter decrements to 0, output the START pulse. Step 55, Multi-device interference suppression principle: Interference suppression rate = (no offset interference rate - offset interference rate) / no offset interference rate × 100%, which is used to quantify the suppression effect of LFSR random offset on multi-device interference.

[0011] Secondly, the present invention provides a lidar zero-position detection system based on pulse period ratio determination. The system is used to implement the lidar zero-position detection method based on pulse period ratio determination in the first aspect or any possible implementation thereof. The system includes a signal preprocessing and dual-edge detection module, a ring buffer reference period storage module, a pulse period ratio determination module, a rotational speed adaptive emission frequency control module, and an LFSR pseudo-random START offset module. The signal preprocessing and dual-edge detection module is used to synchronously eliminate metastability through a three-level register and improve angular resolution through dual detection of rising and falling edges. The ring-shaped buffer reference period storage module is used for automatic maintenance and zero-latency reading of the reference period value at the same angular position in the previous revolution. The pulse period ratio determination module is used to determine the zero position by comparing the current period value with the reference period value. The rotation speed adaptive emission frequency control module is used to dynamically adjust the number of emission times per revolution based on the real-time PA cycle value in order to maintain a constant angular resolution; The LFSR pseudo-random START offset module is used to suppress mutual interference when multiple devices are working in the same scene, and outputs the final laser trigger signal through the START pulse generation module.

[0012] Thirdly, embodiments of the present invention provide a computer-readable storage medium, the computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the device where the computer-readable storage medium is located to execute the lidar zero-position detection method based on pulse period ratio determination in the first aspect or any possible implementation of the first aspect.

[0013] Fourthly, embodiments of the present invention provide an electronic device, including: one or more processors; a memory; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions that, when executed by the device, cause the device to perform the lidar zero-position detection method based on pulse period ratio determination in the first aspect or any possible implementation of the first aspect.

[0014] The technical solution provided by this invention includes a method that constructs a PA pulse signal preprocessing and dual-edge detection link, eliminates metastability through three-level register synchronization, and improves angular resolution through dual detection of rising and falling edges; designs a ring buffer reference period storage module to automatically maintain and read the reference period value of the previous angular position; employs a pulse period ratio determination module to determine the zero position based on the ratio of the current period value to the reference period value; constructs a rotation speed adaptive emission frequency control module to dynamically adjust the number of emission cycles per revolution based on the real-time PA period value to maintain constant angular resolution; and designs an LFSR pseudo-random START offset module to suppress mutual interference when multiple devices work in the same scene, and outputs the final laser trigger signal through a START pulse generation module. This method achieves highly reliable zero-position detection without increasing hardware costs and supports wide-range rotation speed adaptation and constant angular resolution control. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A flowchart of a lidar zero-position detection method based on pulse period ratio determination provided in an embodiment of the present invention; Figure 2 A flowchart of another lidar zero-position detection method based on pulse period ratio determination provided in an embodiment of the present invention; Figure 3 A schematic diagram illustrating the updating of a circular buffer array according to an embodiment of the present invention; Figure 4 A schematic diagram of the pulse period ratio determination timing provided in an embodiment of the present invention; Figure 5 The timing diagram of adaptive rotational speed frequency division and random offset of LFSR provided in the embodiment of the present invention; Figure 6 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” used in the embodiments of this invention are also intended to include the plural forms unless the context clearly indicates otherwise.

[0019] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0020] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0021] This invention provides a lidar zero-position detection method based on pulse period ratio determination, such as... Figures 1 to 5 As shown, the method includes: Step 1: Construct a PA pulse signal preprocessing and dual-edge detection link, eliminate metastability through three-level register synchronization, and improve angular resolution through dual detection of rising and falling edges; In this embodiment of the invention, step 1 includes: Step 11, Data Acquisition and Interface Configuration: Acquire the power amplifier (PA) pulse signal generated by the code disk. The code disk is an incremental photoelectric encoder, installed on the motor shaft, generating 28 PA pulse signals per revolution, corresponding to 28 optical windows; the signal level is LVCMOS33 (3.3V), and the highest frequency is 30Hz×28=840Hz (calculated by multiplying the maximum speed of 30Hz by 28 pulses / revolution). In this embodiment of the invention, ① the encoder provides three output signals: the A-phase output PA pulse is used for angle synchronization, and the B and Z phases serve as backup channels. ② Regarding the FPGA pin configuration, the PA signal is input through the FPGA's P1 pin, which is configured for LVCMOS33 level input mode. To ensure signal quality, a 4.7kΩ external pull-up resistor and a 100pF debouncing capacitor are used at the input, and the FPGA input impedance is greater than 1MΩ. ③ The signal conditioning circuit includes three levels of processing: input protection uses a TVS diode with a clamping voltage set to 3.6V to prevent overvoltage damage to the FPGA; filtering uses an RC low-pass filter with a 1kΩ resistor, a 100pF capacitor, and a cutoff frequency of 1.6MHz to filter out high-frequency noise; since both the encoder output level and the FPGA input level are LVCMOS33, no additional level conversion circuit is required.

[0022] Step 12, Three-level register synchronization: The PA pulse signal is synchronized in three levels using a 100MHz system clock to eliminate metastability across clock domains; the synchronization links are, in sequence, PA input signal, first-level synchronization PA_d0, second-level synchronization PA_d1, and third-level synchronization PA_D; the total synchronization delay is 30ns, which is 300MHz clock cycles. In this embodiment of the invention, ① the purpose of three-stage register synchronization is to eliminate metastability across clock domains. This method employs a three-stage D flip-flop cascade structure, sequentially sampling the PA input signal at the rising edge of the 100MHz system clock. The first-stage flip-flop samples the original PA signal to obtain PA_d0, the second-stage flip-flop samples PA_d0 to obtain PA_d1, and the third-stage flip-flop samples PA_d1 to obtain the stable output PA_D. The delay of each flip-flop stage is one clock cycle (10ns), and the total delay of the three stages is 30ns. The metastability probability of this structure is less than 10%. -15 It exhibits extremely high reliability. ② Regarding synchronization delay, the first-stage delay is 10ns (1 clock cycle), the second-stage delay is 10ns (1 clock cycle), and the third-stage delay is 10ns (1 clock cycle), for a total delay of 30ns. Since the PA signal period is greater than 1ms, the impact of this delay on system performance is negligible.

[0023] Step 13, Cross-clock domain synchronization: Synchronize the PA_D signal in the 100MHz domain to the 10MHz processing clock domain, and obtain PA_VLD through the level 1 register synchronization; In this embodiment of the invention, ① cross-clock domain synchronization is used to synchronize the PA_D signal from the 100MHz clock domain to the 10MHz processing clock domain. Specifically, the PA_D signal is sampled at the rising edge of the 10MHz clock to obtain the PA_VLD signal. The synchronization delay is one 10MHz clock cycle (100ns). Combined with the 30ns delay of the preceding three-stage register synchronization, the total synchronization delay is 130ns, which is negligible compared to the PA signal period (>1ms). ② In terms of delay analysis, the 100MHz domain delay is 30ns (three-stage register synchronization), and the 10MHz domain delay is 100ns (one-stage register synchronization), for a total delay of 130ns. Since the PA signal period is greater than 1ms, the impact of this delay on system performance is negligible.

[0024] Step 14, Double Edge Detection: Detect the rising and falling edges of the PA signal in the 10MHz clock domain; each PA pulse generates two edge events, a rising edge and a falling edge, improving the angular resolution from 28 pulses / revolution to 56 edges / revolution. In this embodiment of the invention, the principle of double-edge detection is as follows: the condition for rising edge detection is that the current value is 1 and the previous value is 0, and the condition for falling edge detection is that the current value is 0 and the previous value is 1. The detection method is to compare the values ​​of PA_D and PA_VLD.

[0025] The principle of the dual-edge detection code is as follows: It simultaneously detects the rising and falling edges of the PA signal in a 10MHz clock domain. The rising edge detection logic is: when PA_D is high and PA_VLD is low, a rising edge is detected. The falling edge detection logic is: when PA_D is low and PA_VLD is high, a falling edge is detected. Each PA pulse can generate both rising and falling edge events, improving the angular resolution from 28 pulses / revolution to 56 edges / revolution, a doubling of the resolution.

[0026] Regarding the accuracy of dual-edge detection, the clock frequency is 10MHz (100ns resolution), the detection delay is less than 100ns, and the detection accuracy is ±100ns. The benefits of dual-edge detection include: improving the angle resolution from 28 pulses / revolution to 56 edges / revolution, enhancing angle measurement accuracy, and providing more reference points for zero-position detection.

[0027] Step 15, Angular resolution calculation: Original resolution 360 degrees / 28 = 12.86 degrees / pulse; Resolution after double edge detection 360 degrees / 56 = 6.43 degrees / edge.

[0028] In this embodiment of the invention, a motor speed of 20Hz is used as an example for verification: the PA frequency is 20×28=560Hz, the double-edge frequency is 560×2=1120Hz, the time resolution is 1 / 1120≈0.893ms, and the angular resolution is 20×360×0.000893≈6.43°. In terms of application, obstacle detection requires an angular resolution <10°, and point cloud generation requires an angular resolution <1°. The 6.43° resolution of this invention can meet the basic obstacle detection requirements.

[0029] The above steps improve the angle resolution by 2 times, from 12.86° / pulse to 6.43° / edge, thereby improving the angle measurement accuracy and providing more reference points for zero-position detection. The three-level register synchronization eliminates metastability, and the double-edge detection improves the angle resolution from 28 pulses / revolution to 56 edges / revolution.

[0030] Step 2: Design a ring-shaped buffer reference period storage module to automatically maintain and read the reference period value of the previous ring at the same angular position with zero latency; In this embodiment of the invention, step 2 includes: Step 21, Periodic Timer Design: A 20-bit counter driven by a 10MHz clock is used, with an accuracy of 100ns (10MHz clock cycle). The timer is cleared and restarted on the rising edge, and retains the maximum value when overflowing. In this embodiment of the invention, ① the principle of the periodic timer design code implementation: a 20-bit counter driven by a 10MHz clock is used to measure the PA pulse period. The counter increments by 1 on each rising edge of the 10MHz clock, with an accuracy of 100ns. When a rising edge of the PA signal is detected, the counter is reset to zero and starts counting again. When the counter reaches its maximum value (2... 20 The value remains unchanged when -1=1048575 to prevent overflow and flipping. The maximum measurable time is 1048575×100ns=104.8575ms, covering the speed range above 10Hz. ② The timer is driven by a 10MHz clock, with a resolution of 100ns, a counter bit width of 20 bits, and a maximum count value of 2. 20 -1 = 1048575, the maximum measurement time is 1048575 × 100 ns = 104.8575 ms, which can cover the rotational speed range above 10 Hz (PA cycle < 100 ms). In terms of accuracy, the clock accuracy is 10 MHz ± 50 ppm (± 0.005%), the single measurement counting error is less than 100 ns, and the cumulative error of 10 revolutions is less than 1 μs.

[0031] Step 22, Current Period Value Latch: Latch the previous count value on each rising edge as the current PA period value T_cur; In this embodiment of the invention, at each rising edge of the PA signal, the current counter value `cycle_cnt` is latched into the register `T_cur`. At this time, `cycle_cnt` has counted the time of one complete PA cycle, and the latched value is the count value of the current PA cycle. The latch delay is less than 100ns (one clock cycle), and the total measurement error is less than 200ns.

[0032] Step 23, Circular Buffer Array Design: Maintain an array of 28 20-bit registers, cycle_cnt_arr[0:27], to store the historical values ​​of the most recent 28 PA cycles; when each rising edge arrives, the new value is stored in the 0th position of the array, the original data is shifted to the right in turn, and the furthest data automatically overflows; In this embodiment of the invention, ① a 20-bit counter driven by a 10MHz clock is used to measure the PA pulse period. The counter increments by 1 on each rising edge of the 10MHz clock, with an accuracy of 100ns. When a rising edge of the PA signal is detected, the counter is reset to zero and starts counting again. When the counter reaches its maximum value (2... 20 The value remains unchanged when -1=1048575 to prevent overflow and flipping. The maximum measurable time is 1048575×100ns=104.8575ms, covering the speed range above 10Hz. ② The parameters of the ring buffer array are as follows: the array length is 28 elements (corresponding to 28 PA pulses / revolution), the element bit width is 20 bits, the storage capacity is 28×20 bits=560 bits, the update frequency is once per rising edge, and the data delay is 28 rising edges (one revolution). The functions of the ring buffer array include: storing the historical values ​​of the most recent 28 PA cycles, used for zero-position detection (comparing the current cycle with the reference cycle), used for speed adaptation (determining the number of emission times based on the PA cycle), and used for fault detection (detecting PA cycle abnormalities).

[0033] Step 24, Reference Period Value Reading: The 27th bit is always the reference period value at the same angle position of the previous revolution; In this embodiment of the invention, the reference period value T_ref is read from the 27th bit of the circular buffer array. Since the buffer array is updated as described above, the 27th bit always stores the PA period value at the same angular position in the previous revolution. This reference value is used for zero-position detection (comparing the ratio with the current period value) and rotational speed adaptation (determining the number of emission cycles based on the reference period). The read delay is less than 100 ns.

[0034] Step 25: Correspondence between the buffer array and the number of code disk pulses: The buffer length of 28 elements corresponds one-to-one with the number of code disk pulses of 28 pulses / cycle. The Nth element stores the period value of the Nth PA pulse. The update frequency is once for each rising edge, and the data delay is 28 rising edges.

[0035] In this embodiment of the invention, ① the correspondence between the buffer array and the number of code disk pulses is as follows: the buffer length is 28 elements, and the number of code disk pulses is 28 pulses / revolution, with a one-to-one correspondence. The 0th element stores the period value of the 0th PA pulse, the 1st element stores the period value of the 1st PA pulse, and so on, with the 27th element storing the period value of the 27th PA pulse. ② The update mechanism is as follows: when each rising edge arrives, the new value is stored in the 0th bit, the original data is shifted to the next bit, and the oldest data (the 27th bit) automatically overflows. The update frequency is once per rising edge. ③ Regarding data latency, the storage latency is 28 rising edges (one revolution), the read latency is less than 100ns (one clock cycle), and the total latency is 28 rising edges plus 100ns. ④ The functions of the buffer array include: storing the historical values ​​of the most recent 28 PA cycles, used for zero-position detection (comparing the ratio of the current cycle to the reference cycle), used for speed adaptation (determining the number of light emission times based on the reference cycle), and used for fault detection (detecting abnormal PA cycles).

[0036] The above steps read the reference cycle value with zero delay, support real-time zero-position determination, and store the reference cycle value of the same angle position of the previous revolution for zero-position detection; the circular buffer array design has 28 elements that correspond one-to-one with the number of code disk pulses.

[0037] Step 3: Use the pulse period ratio determination module to determine the zero position by the ratio of the current period value to the reference period value; Traditional solutions rely on hardware zero-position sensors (photoelectric / Hall / Z-pulse) for zero-position detection, which is costly and prone to single-point failures. This invention determines the zero-position position purely in software by measuring the ratio of the current PA pulse period to the reference period of the previous rotation at the same angle (T_cur≈1.5×T_ref), eliminating the dependence on hardware zero-position sensors.

[0038] In this embodiment of the invention, step 3 includes: Step 31, Zero-position feature analysis: The code disk has a widened mark at the zero position (the optical window width is about 1.5 times that of the normal position), and the PA pulse interval at the zero position is equal to 1.5 times that of the normal position, that is, T_zero = 1.5 × T_normal; Step 32, Ratio Determination Algorithm: Calculate the ratio between the current cycle value and the reference cycle value; the determination condition formula is: T_cur=T_ref+T_ref[19:1], where T_ref[19:1] represents T_ref shifted one position to the right, that is, the integer part of T_ref / 2; Step 33, FPGA implementation: Calculate 1.5 times the reference period value T_ref as the comparison benchmark; first, shift T_ref one bit to the right to obtain the integer part half_ref of T_ref / 2; then calculate the sum of T_ref and half_ref, sum_ref, i.e., sum_ref = T_ref + T_ref / 2 = 1.5 × T_ref; finally, compare the current period value T_cur with sum_ref. If they are equal, determine that the current position is zero. The above determination is equivalent to T_cur ≈ 1.5 × T_ref, and the determination interval is [1.4 × T_ref, 1.6 × T_ref]. Step 34, Synchronization Determination: After power-on, synchronization is established first to determine zero position; the synchronization establishment process is as follows: on each rising edge of PA and when the synchronization flag syn is 0, the synchronization counter syn_cnt is incremented by 1; when syn_cnt accumulates to 255, it is determined that the motor speed has stabilized, and the synchronization flag syn is set to 1; thereafter, the system enters normal working state and performs zero position detection. The synchronization condition is that the motor speed is determined to be stable after accumulating 255 rising edges. Step 35, Zero Position Detection Output: The Sync counter resets to zero after detecting a zero position. Each PA edge increments Sync by 1, and the Sync value cycles between 0 and 57, directly corresponding to the scanning angle position. The rising and falling edges of the PA signal are simultaneously detected in the 10MHz clock domain. The rising edge detection logic is as follows: when PA_D is high and PA_VLD is low, a rising edge is detected. The falling edge detection logic is as follows: when PA_D is low and PA_VLD is high, a falling edge is detected. Each PA pulse can generate both rising and falling edge events, improving the angle resolution from 28 pulses / revolution to 56 edges / revolution, a doubling of the improvement.

[0039] The above steps reduce BOM costs by 5-15 yuan per unit, increase MTBF by about 10%, achieve 100% detection success rate, eliminate reliance on hardware zero-position sensors, reduce costs, and improve reliability; zero position is determined through ratio relationships.

[0040] Step 4: Construct a rotation speed adaptive emission frequency control module to dynamically adjust the number of emission cycles per revolution based on the real-time PA cycle value in order to maintain a constant angular resolution; Traditional fixed-frequency division schemes suffer from fluctuating angular resolution with rotational speed (approximately ±10%), while PLL schemes have a narrow rotational speed adaptation range (±10% results in loss of lock-up). This invention measures the PA cycle in real time, determines the number of emission cycles by looking up a table, and dynamically calculates the frequency division coefficient, maintaining a constant angular resolution (approximately 0.06°) over a wide rotational speed range of 10Hz to 30Hz, thus overcoming the bottlenecks of fixed-frequency division and PLL schemes.

[0041] In this embodiment of the invention, step 4 includes: Step 41, Speed ​​Threshold Table Design: Determine the motor speed based on the PA cycle value and determine the number of times the light is emitted per revolution, as shown in Table 1; Table 1 Speed ​​Threshold Table ; Step 42, Light Emission Count Selection Logic: Based on the comparison between the current PA cycle value T_cur and the preset threshold, the number of light emission times N per revolution is automatically determined; when T_cur is greater than 35714 (corresponding to 10Hz rotation speed), N=60; when T_cur is greater than 23810 (corresponding to 15Hz rotation speed), N=40; when T_cur is greater than 17857 (corresponding to 20Hz rotation speed), N=30; otherwise, N=20 (corresponding to 30Hz rotation speed); the mapping from rotation speed to the number of light emission times is realized by looking up a table, ensuring that the angular resolution remains constant at around 0.06° across a wide rotation speed range of 10Hz~30Hz.

[0042] Step 43, Frequency division coefficient calculation: Calculate the frequency division coefficient D based on the current PA period value T_cur and the number of emission times per revolution N; the frequency division coefficient D = T_cur / N, which means that a laser trigger is generated every D 10MHz clock cycles; by dynamically adjusting the frequency division coefficient, the number of laser emission times per revolution is kept constant under different rotation speeds, thereby maintaining stable angular resolution.

[0043] Step 44, START pulse generation: The frequency divider counter is cleared to zero on the rising edge or when measurement is disabled, and returns to zero when it counts to D-4 and outputs the START pulse; the pulse width is 6 x 100MHz clock cycles, i.e. 60ns; The frequency divider counter div_cnt starts counting from 0 and is reset to zero when the count value reaches the frequency division factor D minus 4, at which point a START pulse is output. The START pulse width is six 100MHz clock cycles (60ns) and is used to trigger laser emission. Through this frequency division mechanism, the 10MHz processing clock is divided into a laser trigger signal that matches the rotation speed.

[0044] Step 45: Special handling for zero position: The PA cycle at the zero position is 1.5 times that at the normal position, and the number of light emission times is twice the normal value.

[0045] The widened marking on the code disk at the zero position results in a PA cycle approximately 1.5 times that of the normal position. To maintain consistent angular resolution near the zero position, the number of light emission cycles is doubled at the zero position (code_angle = 0 or 27) (N_zero = 2 × N), while the number of light emission cycles at other positions remains unchanged at N.

[0046] Through the above steps, the angular resolution deviation is less than 1% (compared to ±10% for traditional solutions), supporting adaptive rotation speed over a wide range of 10Hz to 30Hz; maintaining constant angular resolution over a wide range of rotation speeds of 10Hz to 30Hz; measuring the PA cycle in real time and determining the number of emission times by looking up a table, and dynamically calculating the frequency division coefficient.

[0047] Step 5: Design the LFSR pseudo-random START offset module to suppress mutual interference when multiple devices are working in the same scene, and output the final laser trigger signal through the START pulse generation module.

[0048] In traditional fixed-frequency or PLL-locked schemes, multiple devices have a fixed phase relationship, leading to mutual interference of laser signals. This invention uses an 8-bit linear feedback shift register to apply a 0-240ns pseudo-random offset to each START pulse, breaking the fixed phase relationship between devices and reducing the interference rate of multiple devices in the same scene from 12%-41% to 0.8%-3.5%.

[0049] In this embodiment of the invention, step 5 includes: Step 51, LFSR Design: Use an 8-bit linear feedback shift register (LFSR) to generate a pseudo-random sequence; the feedback polynomial of the LFSR is x. 8 +x 6 +x 5 +x 4 +1 corresponds to tap positions bit7, bit5, bit4, and bit3; the feedback logic is: new input bit0 = bit7 ⊕ bit5 ⊕ bit4 ⊕ bit3; each clock cycle, the register shifts right by one bit, and the feedback value is shifted into the most significant bit; the LFSR generates a pseudo-random sequence with a period of 255; Step 52, Seed value generation: The seed value is determined by the system state parameters to ensure that the random sequence of each device is different; the seed value is calculated by taking the sum of the high 8 bits and low 8 bits of the maximum echo intensity value max_intensity, where max_intensity is the maximum echo intensity value; since the max_intensity values ​​of different devices are different, the seed values ​​are also different, thereby ensuring that the LFSR sequences of each device are uncorrelated.

[0050] Step 53, Random Delay Calculation: Take the lower 5 bits of the LFSR output as the original random value, ranging from 0 to 31, limit it to 0 to 24 (take the smaller of the original value and 24), and finally multiply it by 10 to obtain the delay value (unit: ns). The delay range is 0 to 240 ns, with a step of 10 ns. This random delay is used to break the fixed phase relationship between multiple devices and suppress mutual interference. Step 54, Delay application method: Apply a random delay before the START pulse. When the trigger signal arrives, load the delay value into the delay counter. After the counter decrements to 0, the START pulse is output. Through this mechanism, each laser trigger signal will be subject to a random offset of 0~240ns, so that the START pulses of multiple devices no longer have a fixed phase relationship, thereby reducing the probability of mutual interference.

[0051] Step 55, Multi-device Interference Suppression Principle: Without LFSR offset, the START pulses of multiple devices have a fixed phase relationship, resulting in a high probability of mutual interference (12%-41%). With LFSR offset, the START pulse of each device is randomly offset, reducing the interference probability to 0.8%-3.5%. Interference suppression rate = (Interference rate without offset - Interference rate with offset) / Interference rate without offset × 100%, which is used to quantify the suppression effect of random LFSR offset on multi-device interference.

[0052] Through the above steps, the interference rate is reduced from 12%-41% to 0.8%-3.5%, and the suppression rate reaches 91%-93%. This suppresses mutual interference when multiple devices work in the same scene. An 8-bit linear feedback shift register generates a pseudo-random sequence and applies a random offset of 0-240ns.

[0053] This invention provides a lidar zero-position detection system based on pulse period ratio determination. This system implements the aforementioned lidar zero-position detection method based on pulse period ratio determination. The system includes a signal preprocessing and dual-edge detection module, a ring buffer reference period storage module, a pulse period ratio determination module, a rotational speed adaptive emission frequency control module, and an LFSR pseudo-random START offset module. The signal preprocessing and dual-edge detection module eliminates metastability synchronously through a three-level register and improves angular resolution through dual detection of rising and falling edges. The ring-shaped buffer reference cycle storage module is used for automatic maintenance and zero-delay reading of the reference cycle value of the previous angular position; the pulse cycle ratio determination module is used to determine the zero position by the ratio of the current cycle value to the reference cycle value; the rotation speed adaptive emission frequency control module is used to dynamically adjust the number of emission times per revolution according to the real-time PA cycle value to maintain a constant angular resolution; the LFSR pseudo-random START offset module is used to suppress mutual interference when multiple devices work in the same scene, and outputs the final laser trigger signal through the START pulse generation module.

[0054] The purpose of this invention is to verify and demonstrate the performance of the method through experiments. All experiments were conducted on the WIL5025-7I platform of Crystal Semiconductor.

[0055] 1. Evaluation metrics: To comprehensively evaluate model performance, the following four evaluation metrics are used: Detection success rate: The proportion of successful zero-position detections out of the total number of tests; Angle error: The angular deviation (degrees) between the detected zero-position and the true zero-position; Response delay: The time (microseconds) from PA pulse input to zero-position determination output; Angular resolution: The angular interval (degrees) between two adjacent laser emissions.

[0056] 2. Zero-position detection accuracy test, as shown in Table 2; Table 2 Zero-position detection accuracy test ; 3. Adaptive emission frequency test, as shown in Table 3; Table 3 Adaptive Emission Frequency Test ; 4. FPGA resource consumption (WIL5025-7I), as shown in Table 4; Table 4 Resource Consumption ; 5. Multi-device interference suppression test, as shown in Table 5; Table 5 Multi-device interference suppression test ; 6. The present invention is compared with the prior art, as shown in Table 6; Table 6 Comparison of the present invention with the prior art ; Embodiment 1 of the present invention: Autonomous driving LiDAR scenario. Scenario description: In an autonomous vehicle, the LiDAR needs to perform 360-degree scanning and ranging to provide environmental perception data for the autonomous driving system. The LiDAR is mounted on the roof of the vehicle, rotates at 20Hz, and generates 28 PA pulse signals per revolution.

[0057] System configuration: FPGA platform: Crystal Semiconductor WIL5025-7I, code disk type: incremental photoelectric encoder, 28 pulses / revolution, signal level: LVCMOS33 (3.3V), system clock: 100MHz, processing clock: 10MHz.

[0058] Performance: Zero-position detection success rate: 100% (1000 tests), angle error: <0.06°, response latency: <100μs, angular resolution: 0.06° (constant), BOM cost reduction: 10 yuan / unit, MTBF improvement: approximately 10%.

[0059] The above-described Embodiment 1 is compared with the prior art, as shown in Table 7; Table 7 Comparison of Example 1 and Existing Technology ; Embodiment 2 of the present invention: Industrial security lidar scenario. Scenario description: In industrial area security monitoring, lidar is used to detect personnel intrusion and obstacles, requiring highly reliable zero-point detection. The lidar is installed in a fixed position, rotates at 15Hz, and multiple devices operate in the same scenario.

[0060] System configuration: FPGA platform: Crystal Semiconductor WIL5025-7I, code disk type: incremental photoelectric encoder, 28 pulses / revolution, signal level: LVCMOS33 (3.3V), system clock: 100MHz, processing clock: 10MHz, LFSR random offset: 0~240ns.

[0061] Performance: Zero-position detection success rate: 100% (500 tests), angle error: <0.05°, response delay: <100μs, angular resolution: 0.06° (constant), multi-device interference suppression rate: 93.5% (2 devices in the same scenario), BOM cost reduction: 12 yuan / unit.

[0062] The above-described Embodiment 2 is compared with the prior art, as shown in Table 8; Table 8 Comparison of Example 2 and Existing Technology ; Embodiment 3 of the present invention: Robot navigation LiDAR scenario. Scenario description: In robot navigation, LiDAR is used for SLAM mapping and obstacle avoidance, requiring stable angular resolution and fast zero-position detection. The LiDAR is mounted on the top of the robot, rotating at 25Hz, and needs to support rotation speed fluctuations of ±10%.

[0063] System configuration: FPGA platform: Crystal Semiconductor WIL5025-7I, code disk type: incremental photoelectric encoder, 28 pulses / revolution, signal level: LVCMOS33 (3.3V), system clock: 100MHz, processing clock: 10MHz.

[0064] Operating results: Zero-position detection success rate: 100% (800 tests, including sudden speed changes), angle error: <0.06°, response delay: <100μs, angular resolution: 0.048° (at 25Hz), speed adaptation range: 10Hz~30Hz, BOM cost reduction: 8 yuan / unit.

[0065] The above embodiment 3 is compared with the prior art, as shown in Table 9; Table 9 Comparison of Example 3 with Existing Technology ; The method of this invention reduces BOM cost by 5-15 yuan per unit, increases MTBF by about 10%, reduces angular resolution deviation by <1% (compared to ±10% for traditional solutions), and supports adaptive speed over a wide range of 10Hz to 30Hz.

[0066] Compared with the prior art, the present invention has the following advantages: 1. Pure software zero-position detection, eliminating hardware dependence: Through the pulse period ratio determination module, the period ratio characteristic caused by the widening mark of the zero position of the code disk (T_cur≈1.5×T_ref) is used to realize zero-position detection in pure software. There is no need for photoelectric sensors, Hall elements or encoder Z pulse channels. The BOM cost is reduced by 5~15 yuan / unit, the assembly process is simplified, and the risk of single point failure of zero-position sensor is eliminated.

[0067] 2. Rotation speed adaptive constant angular resolution: Through the rotation speed adaptive emission frequency control module, the PA period value is measured in real time and the emission frequency is determined by looking up the table. The frequency division coefficient D=T_cur / N is calculated to ensure that the angular resolution is constant (about 0.06 degrees) over a wide rotation speed range of 10Hz~30Hz. This overcomes the technical bottlenecks of narrow rotation speed adaptation range (±10% loss of lock) of PLL phase-locked loop scheme and angular resolution fluctuation (±10%) of fixed frequency division scheme with rotation speed.

[0068] 3. Multi-device interference suppression: By using the LFSR pseudo-random START offset module, an 8-bit linear feedback shift register is used to generate a pseudo-random sequence. A random delay of 0~240ns is applied to each START pulse, breaking the fixed phase relationship between multiple devices. The interference rate is reduced from 12%~41% to 0.8%~3.5%, and the suppression rate reaches 91%~93%.

[0069] 4. Extremely low resource consumption: The entire system consumes only 326 LUTs (1.4%) and 285 Registers (1.2%) on the WIL5025-7I FPGA, without occupying EBR and DSP resources, making it suitable for resource-constrained embedded application scenarios.

[0070] The technical solution provided by this invention includes a method that constructs a PA pulse signal preprocessing and dual-edge detection link, eliminates metastability through three-level register synchronization, and improves angular resolution through dual detection of rising and falling edges; designs a ring buffer reference period storage module to automatically maintain and read the reference period value of the previous angular position; employs a pulse period ratio determination module to determine the zero position based on the ratio of the current period value to the reference period value; constructs a rotation speed adaptive emission frequency control module to dynamically adjust the number of emission cycles per revolution based on the real-time PA period value to maintain constant angular resolution; and designs an LFSR pseudo-random START offset module to suppress mutual interference when multiple devices work in the same scene, and outputs the final laser trigger signal through a START pulse generation module. This method achieves highly reliable zero-position detection without increasing hardware costs and supports wide-range rotation speed adaptation and constant angular resolution control.

[0071] The various steps in the embodiments of the present invention can be performed by an electronic device. This electronic device includes, but is not limited to, tablet computers, portable PCs, and desktop computers.

[0072] This invention provides a computer-readable storage medium including a stored program, wherein, when the program is running, it controls the electronic device containing the computer-readable storage medium to execute the above-described embodiment of the lidar zero-position detection method based on pulse period ratio determination.

[0073] Figure 6 A schematic diagram of an electronic device provided in an embodiment of the present invention, such as... Figure 6 As shown, the electronic device 21 includes a processor 211, a memory 212, and a computer program 213 stored in the memory 212 and executable on the processor 211. When the computer program 213 is executed by the processor 211, it implements the lidar zero-position detection method based on pulse period ratio determination in the embodiment. To avoid repetition, it will not be described in detail here.

[0074] Electronic device 21 includes, but is not limited to, processor 211 and memory 212. Those skilled in the art will understand that... Figure 6 This is merely an example of electronic device 21 and does not constitute a limitation on electronic device 21. It may include more or fewer components than shown, or combine certain components, or different components. For example, electronic device may also include input / output devices, network access devices, buses, etc.

[0075] The processor 211 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0076] The memory 212 can be an internal storage unit of the electronic device 21, such as a hard disk or RAM of the electronic device 21. The memory 212 can also be an external storage device of the electronic device 21, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or FlashCard equipped on the electronic device 21. Furthermore, the memory 212 can include both internal and external storage units of the electronic device 21. The memory 212 is used to store computer programs and other programs and data required by network devices. The memory 212 can also be used to temporarily store data that has been output or will be output.

[0077] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0078] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A lidar zero-position detection method based on pulse period ratio determination, characterized in that, The method includes: Step 1: Construct a PA pulse signal preprocessing and dual-edge detection link, eliminate metastability through three-level register synchronization, and improve angular resolution through dual detection of rising and falling edges; Step 2: Design a ring-shaped buffer reference period storage module to automatically maintain and read the reference period value of the previous ring at the same angular position with zero latency; Step 3: Use the pulse period ratio determination module to determine the zero position by the ratio of the current period value to the reference period value; Step 4: Construct a rotation speed adaptive emission frequency control module to dynamically adjust the number of emission cycles per revolution based on the real-time PA cycle value in order to maintain a constant angular resolution; Step 5: Design the LFSR pseudo-random START offset module to suppress mutual interference when multiple devices are working in the same scene, and output the final laser trigger signal through the START pulse generation module.

2. The method according to claim 1, characterized in that, Step 1 includes: Step 11, Data Acquisition and Interface Configuration: Acquire the power amplifier (PA) pulse signal generated by the code disk. The code disk is an incremental photoelectric encoder, installed on the motor shaft, which generates 28 PA pulse signals per revolution, corresponding to 28 optical windows; the signal level is LVCMOS33, and the highest frequency is 30Hz×28=840Hz. Step 12, Three-level register synchronization: The PA pulse signal is synchronized in three levels using a 100MHz system clock to eliminate metastability across clock domains; the synchronization links are, in sequence, PA input signal, first-level synchronization PA_d0, second-level synchronization PA_d1, and third-level synchronization PA_D; the total synchronization delay is 30ns, which is 300MHz clock cycles. Step 13, Cross-clock domain synchronization: Synchronize the PA_D signal in the 100MHz domain to the 10MHz processing clock domain, and obtain PA_VLD through the level 1 register synchronization; Step 14, Double Edge Detection: Detect the rising and falling edges of the PA signal in the 10MHz clock domain; each PA pulse generates two edge events, a rising edge and a falling edge, improving the angular resolution from 28 pulses / revolution to 56 edges / revolution. Step 15, Angular resolution calculation: Original resolution 360 degrees / 28 = 12.86 degrees / pulse; Resolution after double edge detection 360 degrees / 56 = 6.43 degrees / edge.

3. The method according to claim 2, characterized in that, Step 2 includes: Step 21, Periodic Timer Design: A 20-bit counter driven by a 10MHz clock with an accuracy of 100ns is used. The timer is cleared and restarted on the rising edge, and retains the maximum value when overflowing. Step 22, Current Period Value Latch: Latch the previous count value on each rising edge as the current PA period value T_cur; Step 23, Circular Buffer Array Design: Maintain an array of 28 20-bit registers, cycle_cnt_arr[0:27], to store the historical values ​​of the most recent 28 PA cycles; when each rising edge arrives, the new value is stored in the 0th position of the array, the original data is shifted to the right in turn, and the furthest data automatically overflows; Step 24, Reference Period Value Reading: The 27th bit is always the reference period value at the same angle position of the previous revolution; Step 25: Correspondence between the buffer array and the number of code disk pulses: The buffer length of 28 elements corresponds one-to-one with the number of code disk pulses of 28 pulses / cycle. The Nth element stores the period value of the Nth PA pulse. The update frequency is once for each rising edge, and the data delay is 28 rising edges.

4. The method according to claim 3, characterized in that, Step 3 includes: Step 31, Zero-position feature analysis: The code disk has a widened mark at the zero position, and the PA pulse interval at the zero position is equal to 1.5 times that at the normal position, that is, T_zero = 1.5 × T_normal; Step 32, Ratio Determination Algorithm: Calculate the ratio between the current cycle value and the reference cycle value; the determination condition formula is: T_cur=T_ref+T_ref[19:1], where T_ref[19:1] represents T_ref shifted one position to the right, that is, the integer part of T_ref / 2; Step 33, FPGA implementation: Calculate 1.5 times the reference period value T_ref as the comparison benchmark; first, shift T_ref one bit to the right to obtain the integer part half_ref of T_ref / 2; then calculate the sum of T_ref and half_ref, sum_ref, i.e., sum_ref = T_ref + T_ref / 2 = 1.5 × T_ref; finally, compare the current period value T_cur with sum_ref. If they are equal, determine that the current position is zero. The above determination is equivalent to T_cur ≈ 1.5 × T_ref, and the determination interval is [1.4 × T_ref, 1.6 × T_ref]. Step 34, Synchronization Determination: After power-on, synchronization is established first to determine zero position; the synchronization establishment process is as follows: on each rising edge of PA and when the synchronization flag syn is 0, the synchronization counter syn_cnt is incremented by 1; when syn_cnt accumulates to 255, it is determined that the motor speed has stabilized, and the synchronization flag syn is set to 1; thereafter, the system enters normal working state and performs zero position detection. The synchronization condition is that the motor speed is determined to be stable after accumulating 255 rising edges. Step 35, Zero Position Detection Output: The Sync counter resets to zero after detecting a zero position. Each PA edge increments Sync by 1, and the Sync value cycles between 0 and 57, directly corresponding to the scanning angle position. The rising and falling edges of the PA signal are detected simultaneously in the 10MHz clock domain. The rising edge detection logic is as follows: when PA_D is high and PA_VLD is low, it indicates that a rising edge has been detected. The falling edge detection logic is as follows: when PA_D is low and PA_VLD is high, it indicates that a falling edge has been detected.

5. The method according to claim 4, characterized in that, Step 4 includes: Step 41, Speed ​​Threshold Table Design: Determine the motor speed based on the PA cycle value to determine the number of times the light is emitted per revolution; Step 42, Light emission count selection logic: Based on the comparison result between the current PA cycle value T_cur and the preset threshold, the number of light emission counts N per cycle is automatically determined; when T_cur is greater than 35714, N=60; when T_cur is greater than 23810, N=40; when T_cur is greater than 17857, N=30; otherwise, N=20; Step 43, Frequency division coefficient calculation: Calculate the frequency division coefficient D based on the current PA cycle value T_cur and the number of light emission times per cycle N; the frequency division coefficient D = T_cur / N, which means that a laser trigger is generated once every D 10MHz clock cycles; Step 44, START pulse generation: The frequency divider counter is cleared to zero on the rising edge or when measurement is disabled, and returns to zero when it counts to D-4 and outputs the START pulse; the pulse width is 6 x 100MHz clock cycles, i.e. 60ns; Step 45, Special handling for zero position: The PA cycle at the zero position is 1.5 times that at the normal position, and the number of light emission times is twice the normal value.

6. The method according to claim 5, characterized in that, Step 5 includes: Step 51, LFSR Design: Use an 8-bit linear feedback shift register (LFSR) to generate a pseudo-random sequence; the feedback polynomial of the LFSR is x. 8 +x 6 +x 5 +x 4 +1 corresponds to tap positions bit7, bit5, bit4, and bit3; the feedback logic is: new input bit0 = bit7 ⊕ bit5 ⊕ bit4 ⊕ bit3; each clock cycle, the register shifts right by one bit, and the feedback value is shifted into the most significant bit; the LFSR generates a pseudo-random sequence with a period of 255; Step 52, Seed value generation: The seed value is determined by the system status parameters to ensure that the random sequence of each device is different; the seed value is calculated by taking the sum of the high 8 bits and low 8 bits of the maximum echo intensity value max_intensity, where max_intensity is the maximum echo intensity value; Step 53, Random Delay Calculation: Take the lower 5 bits of the LFSR output as the original random value, ranging from 0 to 31, limit it to 0 to 24, and finally multiply it by 10 to obtain the delay value. The delay range is 0 to 240 ns, with a step of 10 ns. Step 54, Delay application method: Apply a random delay before the START pulse. When the trigger signal arrives, load the delay value into the delay counter; after the counter decrements to 0, output the START pulse. Step 55, Multi-device interference suppression principle: Interference suppression rate = (no offset interference rate - offset interference rate) / no offset interference rate × 100%, which is used to quantify the suppression effect of LFSR random offset on multi-device interference.

7. A lidar zero-position detection system based on pulse period ratio determination, characterized in that, The system is used to implement the lidar zero-position detection method based on pulse period ratio determination as described in claim 1; the system includes a signal preprocessing and double edge detection module, a ring buffer reference period storage module, a pulse period ratio determination module, a rotation speed adaptive emission frequency control module, and an LFSR pseudo-random START offset module; the signal preprocessing and double edge detection module is used to eliminate metastability synchronously through a three-level register and improve angular resolution through dual detection of rising and falling edges; The ring-shaped buffer reference period storage module is used for automatic maintenance and zero-latency reading of the reference period value at the same angular position in the previous revolution. The pulse period ratio determination module is used to determine the zero position by comparing the current period value with the reference period value. The rotation speed adaptive emission frequency control module is used to dynamically adjust the number of emission times per revolution based on the real-time PA cycle value in order to maintain a constant angular resolution; The LFSR pseudo-random START offset module is used to suppress mutual interference when multiple devices are working in the same scene, and outputs the final laser trigger signal through the START pulse generation module.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein, when the program is executed, it controls the device containing the computer-readable storage medium to perform the lidar zero-position detection method based on pulse period ratio determination as described in any one of claims 1 to 6.

9. An electronic device, characterized in that, include: One or more processors; Memory; And one or more computer programs, wherein the one or more computer programs are stored in the memory, the one or more computer programs including instructions that, when executed by the device, cause the device to perform the lidar zero-position detection method based on pulse period ratio determination as described in any one of claims 1 to 6.

Images