An on-chip integrated topological photonic chip and method based on prime spectrum manifold critical line isomorphism

Abstract

The application discloses a kind of based on prime spectrum manifold critical line isomorphism on-chip integrated topological photonic chip and method, belong to topological photonics and integrated optoelectronic technology field.The application is mapped to standard CMOS photonic integration technology on the critical line isomorphism on prime spectrum manifold, integrates topological protection optical waveguide, topological optical beam splitter, topological optical modulator and topological detector array on chip, realizes with topological protection optical signal transmission, control and detection function.The application is robust to process error, temperature and wavelength drift, waveguide transmission loss is reduced by more than 50% compared with conventional SOI waveguide, modulator power consumption is reduced by about 40%, applicable to optical communication transceiver chip, optical quantum computing chip, on-chip optical interconnection, laser radar chip and the like scene.

Description

Technical Field

[0001] This invention belongs to the field of topological photonics and integrated optoelectronics technology, and is particularly applicable to topological protection of optical transmission and optical manipulation in scenarios such as optical communication transceiver chips, optical quantum computing chips, on-chip optical interconnects, optical sensing arrays, and LiDAR chips. Specifically, it relates to an integrated topological photonic chip and method that combines the isomorphism criterion of the critical line of the prime spectrum manifold with standard CMOS photonic integration technology to realize on-chip topological protection of optical waveguides, optical beam splitting, optical modulation, and optical detection functions. Background Technology

[0002] Silicon-based optoelectronics technology has become the mainstream platform in fields such as optical communication, optical interconnection, and optical computing, but existing on-chip photonic devices have the following inherent limitations: Optical waveguide transmission loss is sensitive to process errors: the transmission loss of standard SOI (silicon-on-insulator) waveguides is significantly affected by sidewall roughness. Scattering loss caused by process deviations can be as high as 2-3 dB / cm, which limits the performance of long-distance on-chip optical interconnects. The performance of devices such as beam splitters and modulators is greatly affected by wavelength and temperature: the beam splitting ratio and operating point of traditional Mach-Zehnder interferometers (MZI) and other devices are sensitive to changes in wavelength and temperature, requiring additional thermo-optical tuning structures to be added to the chip, which increases power consumption and control complexity. On-chip topological photonic structures mainly rely on magnetic materials or complex etching: the realization of existing topological photonic devices on chips often requires the introduction of magnetic materials (such as Ce:YIG) or complex nano-etching processes, which are incompatible with standard CMOS processes. Existing on-chip topology optical transmission lacks a unified design method based on critical line isomorphism: The parent design of this invention (RH00300) has proposed a critical line isomorphism design framework, but has not yet formed a chip architecture and layout design scheme that can be fabricated in standard photonics integration foundries (such as IMEC, Tower Semiconductor, etc.). Lack of topological optical receiving schemes integrated with detector arrays: Existing topological photonic devices mainly focus on optical transmission and optical modulation, and have not yet incorporated integration schemes with on-chip detector arrays into a unified topological protection framework. This invention proposes an on-chip integrated topological photonic chip based on the isomorphism of the critical line of a prime spectrum manifold. It combines the critical line isomorphism criterion with standard CMOS photonic integration technology, and realizes optical signal transmission, manipulation and detection functions with topological protection through the integration of on-chip topological waveguides, topological beam splitters, topological modulators and topological detector arrays. Summary of the Invention

[0003] Purpose of the invention This invention aims to provide an on-chip integrated topological photonic chip and method based on the isomorphism of the critical line of the prime spectrum manifold. By mapping the critical line isomorphism criterion to the design rules of standard CMOS photonic integration process, the chip realizes topologically protected on-chip optical waveguide, optical beam splitter, optical modulation and optical detection functions, improves the robustness of the optical chip to process errors, temperature and wavelength drift, reduces power consumption, and is compatible with standard foundry processes. Technical solution This invention is based on the mathematical principle established in RH00300: in the prime number spectrum manifold Above, all non-trivial zeros fall precisely on the critical line. The geometric conclusion is isomorphically mapped to the design rules of on-chip photonic devices, ensuring that the width, refractive index distribution, and unit cell period of the on-chip optical waveguide satisfy the critical line phase distribution equation. This chip comprises six core components: On-chip light source coupling module: Configured to couple external input light (fiber or on-chip laser) into the chip's topological waveguide. The coupling structure uses a grating coupler or end-face coupler, and its coupling condition satisfies the critical line phase matching equation to ensure that the incident light mode and the topological waveguide mode are phase matched, reducing coupling loss. Topology-protected optical waveguide network: Configured to form a topology optical waveguide connecting various functional units on the chip. The waveguide's geometric parameters (width, height, sidewall angle) and the periodic structure of the dielectric pillars satisfy the critical line isomorphism condition, thus protecting the optical field during transmission. The waveguide's propagation loss is robust to environmental disturbances (temperature changes, stress) and process errors. Topological beam splitting and modulation module: Configured as a topological beam splitter structure based on critical line isomorphism, it distributes the input light to multiple output ports according to a preset ratio. The splitting ratio is determined by the topological charge conservation condition and is insensitive to wavelength changes. At the same time, high-speed optical modulation is achieved by locally perturbing the critical line condition through electro-optic or thermo-optic effects. On-chip topological detector array: This configuration integrates a germanium or silicon-germanium photodetector array at the chip's output to convert optical signals into electrical signals. The detector unit arrangement satisfies the critical line isomorphism condition, minimizing the impact of process variations on the detector array's response consistency. On-chip control and tuning circuitry: Configured to provide bias voltage or tuning current to the topology modulator, performing closed-loop control of the chip's operating point. The circuit dynamically adjusts the modulator bias by monitoring the detector array output, ensuring the optical path always operates under critical line conditions. Standard I / O interfaces: configured to support high-speed electrical signal input and output, including RF signal interfaces (for modulator driving), detector transimpedance amplifier (TIA) output interfaces, and digital control interfaces (I²C or SPI). Overall process: External light source input → On-chip coupling → Topology waveguide transmission → Topology beam splitting → Topology modulation → Topology waveguide transmission → Detector array → Electrical signal output Chip specifications: - Operating wavelength: O-band (1310 nm) or C-band (1550 nm) - Waveguide transmission loss: < 1 dB / cm (topology protection) - Modulation bandwidth: > 25 GHz - Detector responsivity: > 0.8 A / W (1550 nm) - Chip size: < 5 mm × 5 mm Beneficial effects The critical line isomorphic topological waveguide is insensitive to sidewall roughness and manufacturing errors, and its waveguide transmission loss is reduced by more than 50% compared to traditional SOI waveguides. The beam splitting ratio of a topological beam splitter is determined by the conservation of topological charge, and its sensitivity to wavelength and temperature drift is much lower than that of a traditional MZI beam splitter. The topology modulator eliminates the need for an additional thermo-optical tuning structure, reducing power consumption by approximately 40%. The response consistency of the detector array is guaranteed by topological constraints, eliminating the need for pixel-by-pixel calibration; Compatible with standard CMOS photonic integration processes, it can be fabricated in commercial foundries. Detailed Implementation

[0004] Example 1: Topology-protected waveguide chip on silicon photonics platform (1310 nm) Step P1, Chip Layout Design: Calculate the width, dielectric pillar period, and phase distribution of the topological waveguide based on the critical line isomorphism criterion to generate a complete chip layout (GDSII format). The layout includes the input grating coupler, the topological waveguide network, and the output grating coupler. Step P2, Standard SOI process fabrication: Using a 220 nm SOI platform, waveguide patterns are defined by electron beam lithography or deep ultraviolet lithography, waveguide structures are formed by ICP etching, and SiO2 cladding is deposited. Step P3, Chip Testing: Use a tunable laser (1310 nm band) and an optical power meter to test the transmission loss of the waveguide. Compare the loss differences between the topological waveguide and the straight waveguide. Step P4, Performance Verification: Measure the loss change of the topological waveguide at different temperatures (20-80°C) to verify the robustness of the topology protection against temperature drift. Example 2: Integrated Topological Beam Splitter and Mach-Zehnder Modulator Step M1, Device Design: Integrate a topological beamsplitter with a 50:50 splitting ratio and a push-pull Mach-Zehnder modulator into a topological waveguide network. The beamsplitter is implemented using a Y-branch structure determined by the critical line phase distribution, and the splitting ratio is locked by topological charge conservation, independent of process variations. Step M2, Layout: The modulator electrode adopts a traveling wave electrode design with a modulation length of 2 mm. The distance between the signal electrode and the ground electrode meets the impedance matching requirements of the high-frequency transmission line. Step M3, tape-out and packaging: After tape-out on the SOI platform, the chip is mounted on a high-frequency test PCB and RF drive signals are input through the GSG probe. Step M4, Modulation Performance Testing: Test the modulator's extinction ratio, insertion loss, and bandwidth. Compared to traditional MZI modulators, the topology beamsplitter eliminates the sensitivity of the beam splitting ratio to process deviations, thereby improving the yield. Example 3: Topological optical receiver chip with on-chip integrated germanium detector array Step R1, Detector integration design: Integrate a 1×8 germanium detector array at the output end of the topological waveguide with a detector spacing of 100 μm. The positions of the detector elements satisfy the critical line isomorphism condition to ensure the response consistency of each channel. Step R2, Device fabrication: First, a topological waveguide and germanium epitaxial region are fabricated on the SOI wafer to form a lateral PIN structure detector, and then metal electrodes are deposited. Step R3, Array Testing: Using 8 channels of optical signals input simultaneously, measure the responsivity, dark current, and bandwidth of each detector to verify whether the channel consistency of the detector array is superior to that of traditional independent designs due to topological constraints. Step R4, System Application: Apply the chip to a wavelength division multiplexing (WDM) receiver to verify its uniform response performance under different wavelength channels. Terminology Explanation

[0005] Terminology Meaning On-chip integrated topological photonic chip: An integrated device that combines topological photonic structures with CMOS photonic integration technology to realize topologically protected optical transmission, manipulation and detection functions on a single chip. Critical line isomorphism condition: The design constraint that makes the geometric parameters of the on-chip photonic device satisfy the critical line equation of the prime spectral manifold, and the optical field mode has topological protection characteristics when propagating in the device. Topologically protected optical waveguides: The transverse mode field distribution of the waveguide is determined by the critical line isomorphism condition, and the waveguide structure is topologically robust to sidewall roughness, temperature and wavelength drift. Attached Figure Description

[0006] Figure 1 This is a block diagram of the overall architecture of this chip; Figure 2 This is a schematic diagram of the cross section and mode field distribution of the topology-protected waveguide; Figure 3 This is a schematic diagram of the integrated structure of the topology beam splitter and modulator; Figure 4 This is a schematic diagram of the detector array and the electrical output interface.

Claims

1. An on-chip integrated topological photonic chip based on the isomorphism of the critical line of a prime spectrum manifold, characterized in that, include: The on-chip light source coupling module is configured to couple external input light into the chip's topological waveguide, with coupling conditions satisfying the critical line phase matching equation; the topological protection waveguide network, whose geometric parameters satisfy the critical line isomorphism condition, is configured to connect the functional units on the chip and perform topological protection for optical transmission; the topological beam splitter and modulation module is configured to distribute the input light to multiple output ports according to a preset ratio based on a critical line isomorphism topological beam splitter structure, and achieve optical modulation by locally perturbing the critical line condition through electro-optic or thermo-optic effects; An on-chip topological detector array is configured to convert optical signals into electrical signals, and the detector units are arranged to satisfy the critical line isomorphism condition; an on-chip control and tuning circuit is configured to provide bias voltage or tuning current to the topological beam splitter and modulation module, and dynamically adjust the operating point by monitoring the output of the detector array. Standard I / O interface, configured to support high-speed electrical signal input and output.

2. The chip according to claim 1, characterized in that, The geometric parameters of the topology-protected optical waveguide network include waveguide width, height, sidewall angle, and dielectric pillar period. These geometric parameters satisfy the critical line equation on a prime spectral manifold. .

3. The chip according to claim 1, characterized in that, The on-chip light source coupling module is a grating coupler or an end-face coupler, and the grating period and etching depth of the grating coupler or end-face coupler are determined by the critical line phase matching equation.

4. The chip according to claim 1, characterized in that, The beam splitting ratio between the topological beam splitter and the topological beam splitter in the modulation module is determined by the topological charge conservation condition and is insensitive to wavelength and temperature changes.

5. The chip according to claim 1, characterized in that, The on-chip topological detector array is a germanium detector array or a silicon-germanium detector array, and the response consistency of the detector array is guaranteed by the critical line isomorphism condition.

6. The chip according to claim 1, characterized in that, The chip is implemented using a standard SOI photonic integration platform and operates at wavelengths of 1310 nm or 1550 nm.

7. The chip according to claim 1, characterized in that, The on-chip control and tuning circuit includes PID control logic. The PID control logic automatically calculates and applies bias adjustment based on the amplitude deviation of the detector array output signal, so that the modulator operating point returns to the optimal state of the critical line.

8. The chip according to claim 1, characterized in that, The standard I / O interface includes an RF signal interface, a detector transimpedance amplifier output interface, and a digital control interface (I²C or SPI).

9. A method for designing an on-chip integrated topological photonic chip based on the isomorphism of the critical line of a prime spectrum manifold, characterized in that... Includes the following steps: S1. Calculate the waveguide geometric parameters corresponding to the critical line isomorphism condition based on the target operating wavelength and chip functional requirements; S2. Generate the layout of the topological waveguide, beam splitter, modulator, and detector array based on the waveguide geometric parameters; S3. Fabricate the chip on a standard SOI photonic integration platform; S4. Test the chip's optical transmission loss, beam splitting ratio, modulation bandwidth, and detector responsivity; S5. Based on the test results, dynamically tune the operating point through the on-chip control circuit to make the chip operate under the optimal critical line condition.

10. The method according to claim 9, characterized in that, The transmission loss of the topological waveguide in the method is reduced by more than 50% compared with the traditional SOI waveguide, the beam splitting ratio deviation of the beam splitter is less than ±2%, and the statistical distribution of the deviation does not shift significantly with changes in process batches.

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