AWG chip preparation method with self-compensation of process error sub-wavelength structure

Abstract

The application relates to an AWG chip preparation method of a self-compensation sub-wavelength structure with process errors, which comprises the following steps: cleaning a wafer, and performing core layer deposition treatment on the cleaned wafer; modifying the line width parameters of sub-wavelength structure units in the input slab area, the array waveguide area and the output slab area of the wafer, so that the sub-wavelength structure units present continuous line width gradient along the light transmission direction; performing photoetching treatment on the wafer, and performing etching treatment on the wafer; performing upper cladding layer deposition and annealing treatment on the etched wafer; cutting the wafer to obtain an AWG chip; performing polishing treatment on the AWG chip; and performing performance test on the polished AWG chip, and determining the AWG chip passing the performance test as a target AWG chip. In the application, the line width error tolerance range of the sub-wavelength design is improved, the photoetching process fluctuation of different batches of wafers in the mass production process can be adapted, and the mass production yield is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating an AWG chip with a self-compensating subwavelength structure for process errors. Background Technology

[0002] With the rapid development of silicon-based optoelectronic integration technology, arrayed waveguide grating (AWG) chips based on high refractive index difference waveguide structures have become core devices for achieving high-density wavelength division multiplexing in data centers, AI computing power interconnection, and 5G-A transmission systems. Among these, introducing subwavelength structures into AWG chips is currently the mainstream technology used in the industry to suppress channel crosstalk and reduce phase errors in AWG chips.

[0003] However, existing subwavelength structure designs are mostly static parameter designs for fixed refractive index differences, only disclosing fixed duty cycle correction schemes for different refractive index difference gradients. These cannot adapt to the lithography process fluctuations of different batches of wafers during mass production. When there is a slight drift in lithography accuracy, it will cause the equivalent refractive index of the subwavelength structure to shift, ultimately leading to an increase in channel crosstalk of 5 to 10 dB, which will significantly reduce the mass production yield.

[0004] In summary, existing technologies suffer from performance instability in high refractive index difference AWG chips during mass production due to variations in subwavelength structure caused by batch-to-batch process variations. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an AWG chip fabrication method with a subwavelength structure that has self-compensation for process error, in order to overcome the shortcomings of the prior art.

[0006] The technical solution of the present invention to solve the above-mentioned technical problems is as follows:

[0007] A method for fabricating an AWG chip with a self-compensating subwavelength structure for process errors includes:

[0008] The wafer is cleaned, and the cleaned wafer is then subjected to core layer deposition.

[0009] Modify the linewidth parameters of the subwavelength structural units in the input plate region, array waveguide region, and output plate region of the wafer so that the subwavelength structural units have a continuous linewidth gradient along the optical transmission direction.

[0010] The wafer is subjected to photolithography and etching.

[0011] The etched wafer is then subjected to cladding deposition and annealing.

[0012] The wafer is diced to obtain AWG chips;

[0013] The AWG chip is polished.

[0014] The polished AWG chips are subjected to performance testing, and the AWG chips that pass the performance test are identified as the target AWG chips.

[0015] Optionally, the core layer deposition process on the cleaned wafer includes:

[0016] The wafer is placed in an atomic layer deposition apparatus, and trimethylsilane and oxygen are introduced into the atomic layer deposition apparatus to perform a deposition operation on the wafer, depositing a silicon dioxide buffer layer on the wafer;

[0017] The wafer is placed in a plasma-enhanced chemical vapor deposition (PECVD) apparatus, and a mixed gas including silane, oxygen, and nitrogen is introduced into the PECVD apparatus to perform a deposition operation on the wafer, depositing a silicon dioxide undercoat on the wafer.

[0018] The wafer is placed in the PECVD equipment, and a mixed gas including silane, germanane, oxygen, and nitrogen is introduced into the PECVD equipment to perform a deposition operation on the wafer, depositing a germanium-doped silicon dioxide core layer on the wafer.

[0019] Optionally, modifying the linewidth parameters of the subwavelength structural units in the input planar region, arrayed waveguide region, and output planar region of the wafer includes:

[0020] The linewidth of the subwavelength structural unit at the beginning of the input plate region, array waveguide region, and output plate region of the wafer is set to 300 nm, the linewidth at the end is set to 340 nm, and the gradient slope is set to 0.1 nm / μm.

[0021] The starting end is the end of the subwavelength structure unit that is close to the light incident side in the light transmission direction, and the ending end is the end of the subwavelength structure unit that is close to the light emitting side in the light transmission direction.

[0022] Optionally, the photolithography process on the wafer includes:

[0023] Photoresist spin coating is performed on the wafer;

[0024] The spin-coated wafers are then subjected to soft baking and deep ultraviolet exposure;

[0025] The exposed wafer is developed, and the developed wafer is inspected to obtain the development result.

[0026] Optionally, the etching process on the wafer includes:

[0027] The wafer that has been successfully developed is placed into an inductively coupled plasma (ICP) dry etching apparatus. A mixed gas including sulfur hexafluoride and octafluorocyclobutane is introduced into the ICP dry etching apparatus to perform etching on the wafer.

[0028] After etching, the wafer is cleaned to remove the resist.

[0029] Optionally, the process of depositing an upper cladding layer and annealing the etched wafer includes:

[0030] The etched wafer is placed into a PECVD equipment, and a mixed gas including silane, diborane, phosphorus oxychloride, oxygen and nitrogen is introduced into the PECVD equipment to perform a deposition operation on the wafer, depositing a boron phosphorus-doped silicon dioxide overcoat on the wafer.

[0031] The wafer with the top cladding deposited is placed in a high-temperature annealing furnace for high-temperature annealing.

[0032] Optionally, the step of dicing the wafer to obtain AWG chips includes:

[0033] The wafer is placed into a laser marking machine, and the laser marking machine performs laser positioning and marking at the scribe line position of the wafer;

[0034] The positioned wafer is placed into a dicing machine, which cuts the wafer according to the dicing lines to obtain AWG chips.

[0035] Optionally, the polishing process of the AWG chip includes:

[0036] The AWG chip is fixed using a polishing fixture;

[0037] The AWG chip was rough polished using a coarse polishing slurry.

[0038] The AWG chip after coarse polishing was finely polished using a fine polishing slurry.

[0039] AWG chips after cleaning and polishing.

[0040] Optionally, the step of performing performance testing on the polished AWG chip and determining the AWG chip that passes the performance test as the target AWG chip includes:

[0041] Place the AWG chip onto the test bench;

[0042] Align the input optical fiber with the input end face of the AWG chip, align the output optical fiber with the output end face of the AWG chip, and adjust the coupling position of the AWG chip.

[0043] Input test wavelength signals within a preset range in sequence to test the insertion loss, channel crosstalk, and polarization loss of each channel in the AWG chip;

[0044] Based on the insertion loss, the channel crosstalk, and the polarization loss, performance test results are generated.

[0045] The performance test results characterize the AWG chips that pass the test and identify them as the target AWG chips.

[0046] Optionally, generating performance test results based on the insertion loss, the channel crosstalk, and the polarization loss includes:

[0047] Under the condition that the insertion loss is less than or equal to 2.5dB, the channel crosstalk is less than or equal to -25dB, and the polarization loss is less than or equal to 0.2dB, a performance test result is generated to characterize the test as passed.

[0048] If the insertion loss is greater than 2.5dB, the channel crosstalk is greater than -25dB, or the polarization loss is greater than 0.2dB, a performance test result indicating that the characterization test failed is generated.

[0049] The beneficial effects of this invention are:

[0050] In this application, by modifying the linewidth parameters of the subwavelength structural units in the input plate area, arrayed waveguide area, and output plate area of ​​the wafer, the subwavelength structural units are made to have a continuous linewidth gradient along the light transmission direction. This allows the equivalent refractive index deviation caused by the linewidth offset to be self-cancelled within the unit, thereby improving the linewidth error tolerance range of the subwavelength design. This can adapt to the lithography process fluctuations of different batches of wafers during mass production, thereby improving the mass production yield. Attached Figure Description

[0051] Figure 1 This is a schematic flowchart illustrating the fabrication method of an AWG chip with a self-compensating subwavelength structure for process errors provided by the present invention. Detailed Implementation

[0052] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0053] like Figure 1 As shown, this application provides a method for fabricating an AWG chip with a self-compensating subwavelength structure for process errors, comprising:

[0054] Step 110 involves cleaning the wafer and performing core layer deposition on the cleaned wafer.

[0055] Step 120: Modify the linewidth parameters of the subwavelength structural units in the input plate region, arrayed waveguide region, and output plate region of the wafer so that the subwavelength structural units have a continuous linewidth gradient along the optical transmission direction.

[0056] Step 130: Perform photolithography on the wafer and etch the wafer.

[0057] Step 140: Perform cladding deposition and annealing on the etched wafer.

[0058] Step 150: The wafer is cut to obtain an AWG chip.

[0059] Step 160: Polish the AWG chip.

[0060] Step 170: Perform performance testing on the polished AWG chip, and identify the AWG chip that passes the performance test as the target AWG chip.

[0061] To facilitate understanding of the technical solution, this application uses the fabrication of an 8-inch, SOI substrate, 16-channel, high refractive index difference AWG chip with a refractive index difference of 2.0% as an example for illustrative purposes. It should be understood that the AWG chip fabrication method with a self-compensating subwavelength structure for process errors provided in this application can also be applied to the fabrication of AWG chips of other specifications.

[0062] In this embodiment, the wafer can be an 8-inch N-type wafer. <100> The crystal-oriented SOI silicon wafer has a substrate top silicon thickness deviation of 220nm±5nm, an oxide layer thickness of 2μm, and no surface defects such as scratches, particles, or edge chipping.

[0063] The wafer is first cleaned, and the specific process includes:

[0064] Step 1 SC-1 cleaning: Place the wafer in a quartz carrier boat and immerse it in the pre-prepared SC-1 cleaning solution (where the volume ratio of ammonia water: hydrogen peroxide: deionized water in the SC-1 cleaning solution is 1:1:5). Heat to 75℃ and soak for 10 minutes. Then turn on the 40KHz ultrasonic power for ultrasonic cleaning to thoroughly remove surface particles and organic impurities.

[0065] After removal, rinse with ultrapure water at a pressure of 0.2 MPa for 5 minutes to remove any residual cleaning solution.

[0066] Step 2: SC-2 cleaning: Transfer the wafer into SC-2 cleaning solution (where the volume ratio of hydrochloric acid: hydrogen peroxide: deionized water in SC-2 cleaning solution is 1:1:6), continue heating to 75℃ and soak for 10 minutes to remove residual metal ion impurities on the surface.

[0067] Rinse again with ultrapure water overflow for 8 minutes, and finally dry the wafer surface with nitrogen at a pressure of 0.15 MPa, ensuring no residual water stains throughout the process.

[0068] Drying and removing moisture: The cleaned wafers are placed in a 120℃ hot air circulating oven for 30 minutes. After baking, they are allowed to cool naturally to 40℃ and then placed in a nitrogen-protected wafer storage box.

[0069] After cleaning, the wafer undergoes core layer deposition, depositing a silicon dioxide buffer layer, a silicon dioxide lower cladding layer, and a germanium-doped silicon dioxide core layer on the wafer.

[0070] The wafer after core layer deposition is mechanically polished. Specifically:

[0071] The wafer is placed in a chemical mechanical polishing machine, first using a 50nm particle size... Use polishing fluid, set the polishing pressure to 3 psi, the polishing disc speed to 60 rpm, the polishing head speed to 55 rpm, and polish continuously for 15 minutes.

[0072] After polishing, rinse the wafer surface with deionized water to remove polishing residue, blow dry, and then test the surface flatness with a white light interferometer. The flatness should be controlled within the range of ≤0.3μm.

[0073] If the flatness does not meet the requirements, repeat polishing until the requirements are met. After completion, place it in the cleaning tank for a second cleaning to completely remove polishing residue particles.

[0074] The layout of the mechanically polished wafer is designed, and the linewidth parameters of the subwavelength structural units in the input plate area, array waveguide area, and output plate area of ​​the wafer are modified so that the subwavelength structural units have a continuous linewidth gradient along the optical transmission direction.

[0075] The wafer undergoes photolithography and etching. The etched wafer is then subjected to cladding deposition and annealing. The wafer is diced to obtain AWG chips. The AWG chips are then polished. The polished AWG chips are subjected to performance testing, and those that pass the performance test are identified as the target AWG chips. For detailed implementation methods, please refer to subsequent embodiments.

[0076] In this embodiment, by modifying the linewidth parameters of the subwavelength structural units in the input plate area, array waveguide area, and output plate area of ​​the wafer, the subwavelength structural units are made to have a continuous linewidth gradient along the light transmission direction. This allows the equivalent refractive index deviation caused by the linewidth offset to be self-cancelled within the unit, thereby improving the linewidth error tolerance range of the subwavelength design. This can adapt to the lithography process fluctuations of different batches of wafers during mass production, thereby improving the mass production yield.

[0077] Optionally, the core layer deposition process on the cleaned wafer includes:

[0078] The wafer is placed in an atomic layer deposition apparatus, and trimethylsilane and oxygen are introduced into the atomic layer deposition apparatus to perform a deposition operation on the wafer, depositing a silicon dioxide buffer layer on the wafer;

[0079] The wafer is placed in a plasma-enhanced chemical vapor deposition (PECVD) apparatus, and a mixed gas including silane, oxygen, and nitrogen is introduced into the PECVD apparatus to perform a deposition operation on the wafer, depositing a silicon dioxide undercoat on the wafer.

[0080] The wafer is placed in the PECVD equipment, and a mixed gas including silane, germanane, oxygen, and nitrogen is introduced into the PECVD equipment to perform a deposition operation on the wafer, depositing a germanium-doped silicon dioxide core layer on the wafer.

[0081] In this embodiment, the wafer is placed into the cavity of the atomic layer deposition equipment, and the atomic layer deposition equipment is evacuated until the base vacuum level of the cavity reaches a certain level. The deposition temperature was stabilized at 300℃, and trimethylsilane and oxygen were used as precursors. After 100 cycles of cyclic deposition, a dense deposit with a thickness of 10 nm ± 0.5 nm was obtained. Buffer layer. After deposition, the chamber is filled with nitrogen to atmospheric pressure, and the wafer is removed.

[0082] In this embodiment, the wafer is fed into the PECVD equipment, and the PECVD equipment is evacuated until the cavity vacuum level stabilizes. , access , , Mixed gas, each gas flow rate is set separately. 100 sccm 200 sccm With a deposition depth of 500 sccm, an RF power of 300 W, and a deposition temperature of 350 °C, continuous deposition was performed for 15 hours to obtain a low refractive index deposition thickness of 15 μm. Lower cladding. After deposition, the refractive index is tested and calibrated using an ellipsometer, and the refractive index is controlled to be 1.444±0.0005. Once the requirement is met, the wafer is removed.

[0083] In this embodiment, the wafer with the lower cladding layer deposited is sent back into the PECVD equipment cavity, and the PECVD equipment is evacuated to the required cavity vacuum level. , access , (in, For a concentration of 10%, the following method was adopted: dilution), , Mixed gas, each gas has a flow rate of... 95 sccm 20 sccm 200 sccm With a deposition depth of 500 sccm, an RF power of 350 W, and a deposition temperature of 350 °C, continuous deposition was performed for 4.5 hours to obtain a germanium-doped layer with a thickness of approximately 4 μm. Core layer. The refractive index of the core layer is controlled at 1.459±0.0005, corresponding to a refractive index difference Δn=2.0%. After meeting the design requirements, it is removed.

[0084] Optionally, modifying the linewidth parameters of the subwavelength structural units in the input planar region, arrayed waveguide region, and output planar region of the wafer includes:

[0085] The linewidth of the subwavelength structural unit at the beginning of the input plate region, array waveguide region, and output plate region of the wafer is set to 300 nm, the linewidth at the end is set to 340 nm, and the gradient slope is set to 0.1 nm / μm.

[0086] The starting end is the end of the subwavelength structure unit that is close to the light incident side in the light transmission direction, and the ending end is the end of the subwavelength structure unit that is close to the light emitting side in the light transmission direction.

[0087] In this embodiment, the overall design parameters of the original AWG chip are kept unchanged. That is, the core parameters such as the array waveguide length difference, Rowland circle radius, and input-output waveguide spacing are kept consistent with the original design. The linewidth parameters of the subwavelength structural units in the three functional areas of the input planar area, array waveguide area, and output planar area are modified.

[0088] Optionally, all subwavelength structural units have a continuously gradient linewidth along the light transmission direction. In this embodiment, the unit period is fixed at 400 nm, the linewidth at the beginning of the subwavelength structural unit is set to 300 nm, and the linewidth at the end of the subwavelength structural unit linearly gradients to 340 nm, with a gradient slope of 0.1 nm / μm. The beginning end is the end of the subwavelength structural unit closest to the light incident side in the light transmission direction, and the end end is the end of the subwavelength structural unit closest to the light emitting side in the light transmission direction.

[0089] In other alternative implementation methods, the gradient slope can be flexibly adjusted for different process fluctuation ranges. For example, to adapt to ±3% linewidth, the corresponding slope is 0.06 nm / μm; to adapt to ±7% linewidth, the corresponding slope is 0.14 nm / μm. This embodiment adapts to the ±5% linewidth fluctuation common in mass production, so a slope of 0.1 nm / μm is used.

[0090] All gradient units are uniformly arranged along the light transmission direction, without any reverse or misalignment, ensuring that the equivalent refractive index deviation gradually accumulates and cancels out along the transmission direction, achieving a self-compensation effect.

[0091] The gradient design logic provided in this embodiment is not bound to a specific refractive index difference parameter. It can be adapted to all specifications of high refractive index difference AWG products in the range of Δn from 0.75% to 2.5% by adjusting the gradient slope, thus filling the design gap of the prior art that only covers a single fixed refractive index difference.

[0092] Furthermore, this embodiment only modifies the structural design of the photomask layout, without requiring additional photolithography, etching, or deposition steps. It is compatible with existing 8-inch and 12-inch AWG chip mass production lines and will not increase manufacturing costs or production cycles.

[0093] Optionally, the photolithography process on the wafer includes:

[0094] Photoresist spin coating is performed on the wafer;

[0095] The spin-coated wafers are then subjected to soft baking and deep ultraviolet exposure;

[0096] The exposed wafer is developed, and the developed wafer is inspected to obtain the development result.

[0097] In this embodiment, the wafer is placed on the spin coater of a photolithography machine, and positive photoresist is added to the wafer for spin coating. Specifically, the photoresist is first spin-coated at a low speed of 500 rpm for 10 seconds to allow it to spread evenly, and then spin-coated at a high speed of 3000 rpm for 30 seconds to obtain a uniform photoresist layer with a thickness of 2 μm ± 0.1 μm.

[0098] After spin coating, the wafer is placed in a 100°C hot plate for 90 seconds to remove residual solvent from the photoresist and prevent the photoresist from sticking to the photomask.

[0099] The spin-coated wafer is then fed into a deep ultraviolet lithography machine for step-by-step projection exposure according to the design layout. Optionally, the exposure dose is set to 18 mJ / cm², and the exposure accuracy is controlled within ±10 nm to complete the exposure of all AWG chips on the entire wafer.

[0100] After exposure, the wafer is immersed in a 2.38% tetramethylammonium hydroxide (TMAH) developer for 60 seconds at room temperature, then immersed in deionized water for 30 seconds for fixing. After removal, it is dried with nitrogen gas and the photoresist pattern is inspected with an optical microscope. The developed wafer is inspected, and wafers without missing photoresist, ghosting, or pinhole defects are identified as qualified products. The development result is qualified.

[0101] Optionally, the etching process on the wafer includes:

[0102] The wafer that has been successfully developed is placed into an inductively coupled plasma (ICP) dry etching apparatus. A mixed gas including sulfur hexafluoride and octafluorocyclobutane is introduced into the ICP dry etching apparatus to perform etching on the wafer.

[0103] After etching, the wafer is cleaned to remove the resist.

[0104] The developed wafers are then fed into the ICP dry etching equipment, which is then evacuated to a minimum vacuum level. , access and Mixed etching gases, with flow rates of respectively 30 is sccm, The etching rate is 80 sccm, the ICP power is set to 600W, the RF bias power is 100W, the etching rate is about 0.2μm / min, and the total etching depth is controlled to 3μm±0.05μm to ensure complete etching through the core layer and reaching the surface of the lower cladding layer.

[0105] After etching, the wafer is immersed in acetone solution and heated in a 60°C water bath for 30 minutes to remove residual photoresist. Then, it is ultrasonically cleaned with isopropanol for 10 minutes to remove acetone residue. Finally, it is rinsed with ultrapure water for 5 minutes, dried with nitrogen, and examined with an optical microscope to confirm that there is no photoresist residue.

[0106] Optionally, the process of depositing an upper cladding layer and annealing the etched wafer includes:

[0107] The etched wafer is placed into a PECVD equipment, and a mixed gas including silane, diborane, phosphorus oxychloride, oxygen and nitrogen is introduced into the PECVD equipment to perform a deposition operation on the wafer, depositing a boron phosphorus-doped silicon dioxide overcoat on the wafer.

[0108] The wafer with the top cladding deposited is placed in a high-temperature annealing furnace for high-temperature annealing.

[0109] In this embodiment, the etched and cleaned wafer is fed into the PECVD equipment cavity, and the PECVD equipment is evacuated to the required cavity vacuum level. , access , , , , Mixed gases, with flow rates of respectively 100 sccm 2sccm 1.5 sccm 200 sccm With a deposition rate of 500 sccm, an RF power of 300 W, a deposition temperature of 350 °C, and continuous deposition for 20 hours, a boron-phosphorus doped layer with a thickness of approximately 20 μm was obtained. The upper cladding layer, with a refractive index controlled at 1.444±0.0005, completely covers the etched core structure.

[0110] The deposited wafer is placed in a high-temperature annealing furnace, first heated to 1050°C at a rate of 5°C / min, and then annealed for 3 hours under a nitrogen atmosphere with a nitrogen flow rate controlled at 200 sccm. It is then cooled to 200°C at a rate of 3°C / min, and finally allowed to cool naturally to room temperature. The annealing process densifies the upper cladding layer, reducing porosity defects, and releases internal stress between the core and cladding layers, stabilizing the core's refractive index.

[0111] Optionally, the step of dicing the wafer to obtain AWG chips includes:

[0112] The wafer is placed into a laser marking machine, and the laser marking machine performs laser positioning and marking at the scribe line position of the wafer;

[0113] The positioned wafer is placed into a dicing machine, which cuts the wafer according to the dicing lines to obtain AWG chips.

[0114] In this embodiment, the annealed wafer is taken out and sent to a laser marking machine. Laser positioning lines are drawn on the wafer dicing track to mark the dicing position of each AWG chip. The positioning accuracy is controlled within ±5μm.

[0115] The positioned wafer is fed into a diamond dicing machine and cut according to the diced lines. The cutting depth is controlled to 2 / 3 of the entire wafer thickness, and the cutting speed is set to 10mm / s. After cutting, the wafer is gently pried open to obtain a single independent AWG chip.

[0116] Optionally, the polishing process of the AWG chip includes:

[0117] The AWG chip is fixed using a polishing fixture;

[0118] The AWG chip was rough polished using a coarse polishing slurry.

[0119] The AWG chip after coarse polishing was finely polished using a fine polishing slurry.

[0120] AWG chips after cleaning and polishing.

[0121] In this embodiment, a single AWG chip is placed and fixed in a dedicated polishing fixture. First, a W14 diamond polishing slurry is used to coarsely polish the AWG chip, removing any chipped edges left from cutting. The polishing pressure is 0.1 MPa, and the polishing time is 5 minutes. Then, a W7 diamond polishing slurry is used for fine polishing of the AWG chip, with a polishing time of 10 minutes. Finally, a cloth polishing pad is used for mirror polishing, resulting in an end-face roughness Ra ≤ 0.05 μm, ensuring a smooth, scratch-free coupling end face.

[0122] Furthermore, after polishing, the chip is placed in anhydrous ethanol for ultrasonic cleaning for 5 minutes to remove residual polishing abrasive. After removal, it is dried with nitrogen gas.

[0123] Optionally, the step of performing performance testing on the polished AWG chip and determining the AWG chip that passes the performance test as the target AWG chip includes:

[0124] Place the AWG chip onto the test bench;

[0125] Align the input optical fiber with the input end face of the AWG chip, align the output optical fiber with the output end face of the AWG chip, and adjust the coupling position of the AWG chip.

[0126] Input test wavelength signals within a preset range in sequence to test the insertion loss, channel crosstalk, and polarization loss of each channel in the AWG chip;

[0127] Based on the insertion loss, the channel crosstalk, and the polarization loss, performance test results are generated.

[0128] The performance test results characterize the AWG chips that pass the test and identify them as the target AWG chips.

[0129] In this embodiment, the polished AWG chip is placed in an automatic coupling test bench, the input optical fiber is aligned with the input end face of the AWG chip, the output optical fiber is aligned with the output end face of the AWG chip, and the coupling position of the AWG chip is adjusted to minimize insertion loss before being fixed.

[0130] Input test wavelength signals within the design range sequentially, and test the insertion loss, channel crosstalk, and polarization-dependent loss of each channel one by one.

[0131] Then, based on insertion loss, channel crosstalk, and polarization loss, performance test results are generated.

[0132] The AWG chips that pass the performance test are identified as the target AWG chips.

[0133] Optionally, generating performance test results based on the insertion loss, the channel crosstalk, and the polarization loss includes:

[0134] Under the condition that the insertion loss is less than or equal to 2.5dB, the channel crosstalk is less than or equal to -25dB, and the polarization loss is less than or equal to 0.2dB, a performance test result is generated to characterize the test as passed.

[0135] If the insertion loss is greater than 2.5dB, the channel crosstalk is greater than -25dB, or the polarization loss is greater than 0.2dB, a performance test result indicating that the characterization test failed is generated.

[0136] In this embodiment, AWG chips with an insertion loss of less than or equal to 2.5dB, a channel crosstalk of less than or equal to -25dB, and a polarization loss of less than or equal to 0.2dB are determined to be qualified products.

[0137] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating an AWG chip with a self-compensating subwavelength structure for process errors, characterized in that, include: The wafer is cleaned, and the cleaned wafer is then subjected to core layer deposition. Modify the linewidth parameters of the subwavelength structural units in the input plate region, array waveguide region, and output plate region of the wafer so that the subwavelength structural units have a continuous linewidth gradient along the optical transmission direction. The wafer is subjected to photolithography and etching. The etched wafer is then subjected to cladding deposition and annealing. The wafer is diced to obtain AWG chips; The AWG chip is polished. The polished AWG chips are subjected to performance testing, and the AWG chips that pass the performance test are identified as the target AWG chips.

2. The method according to claim 1, characterized in that, The core layer deposition process on the cleaned wafer includes: The wafer is placed in an atomic layer deposition apparatus, and trimethylsilane and oxygen are introduced into the atomic layer deposition apparatus to perform a deposition operation on the wafer, depositing a silicon dioxide buffer layer on the wafer; The wafer is placed in a plasma-enhanced chemical vapor deposition (PECVD) apparatus, and a mixed gas including silane, oxygen, and nitrogen is introduced into the PECVD apparatus to perform a deposition operation on the wafer, depositing a silicon dioxide undercoat on the wafer. The wafer is placed in the PECVD equipment, and a mixed gas including silane, germanane, oxygen, and nitrogen is introduced into the PECVD equipment to perform a deposition operation on the wafer, depositing a germanium-doped silicon dioxide core layer on the wafer.

3. The method according to claim 1, characterized in that, Modifying the linewidth parameters of the subwavelength structural units in the input planar region, arrayed waveguide region, and output planar region of the wafer includes: The linewidth of the subwavelength structural unit at the beginning of the input plate region, array waveguide region, and output plate region of the wafer is set to 300 nm, the linewidth at the end is set to 340 nm, and the gradient slope is set to 0.1 nm / μm. The starting end is the end of the subwavelength structure unit that is close to the light incident side in the light transmission direction, and the ending end is the end of the subwavelength structure unit that is close to the light emitting side in the light transmission direction.

4. The method according to claim 1, characterized in that, The photolithography process on the wafer includes: Photoresist spin coating is performed on the wafer; The spin-coated wafers are then subjected to soft baking and deep ultraviolet exposure; The exposed wafer is developed, and the developed wafer is inspected to obtain the development result.

5. The method according to claim 4, characterized in that, The etching process on the wafer includes: The wafer that has been successfully developed is placed into an inductively coupled plasma (ICP) dry etching apparatus. A mixed gas including sulfur hexafluoride and octafluorocyclobutane is introduced into the ICP dry etching apparatus to perform etching on the wafer. After etching, the wafer is cleaned to remove the resist.

6. The method according to claim 1, characterized in that, The process of depositing an upper cladding layer and annealing the etched wafer includes: The etched wafer is placed into a PECVD equipment, and a mixed gas including silane, diborane, phosphorus oxychloride, oxygen and nitrogen is introduced into the PECVD equipment to perform a deposition operation on the wafer, depositing a boron phosphorus-doped silicon dioxide overcoat on the wafer. The wafer with the top cladding deposited is placed in a high-temperature annealing furnace for high-temperature annealing.

7. The method according to claim 1, characterized in that, The process of dicing the wafer to obtain AWG chips includes: The wafer is placed into a laser marking machine, and the laser marking machine performs laser positioning and marking at the scribe line position of the wafer; The positioned wafer is placed into a dicing machine, which cuts the wafer according to the dicing lines to obtain AWG chips.

8. The method according to claim 1, characterized in that, The polishing process of the AWG chip includes: The AWG chip is fixed using a polishing fixture; The AWG chip was rough polished using a coarse polishing slurry. The AWG chip after coarse polishing was finely polished using a fine polishing slurry. AWG chips after cleaning and polishing.

9. The method according to claim 1, characterized in that, The process of performing performance testing on the polished AWG chips and identifying the AWG chips that pass the performance test as the target AWG chips includes: Place the AWG chip onto the test bench; Align the input optical fiber with the input end face of the AWG chip, align the output optical fiber with the output end face of the AWG chip, and adjust the coupling position of the AWG chip. Input test wavelength signals within a preset range in sequence to test the insertion loss, channel crosstalk, and polarization loss of each channel in the AWG chip; Based on the insertion loss, the channel crosstalk, and the polarization loss, performance test results are generated. The performance test results characterize the AWG chips that pass the test and identify them as the target AWG chips.

10. The method according to claim 9, characterized in that, The generation of performance test results based on the insertion loss, the channel crosstalk, and the polarization loss includes: Under the condition that the insertion loss is less than or equal to 2.5dB, the channel crosstalk is less than or equal to -25dB, and the polarization loss is less than or equal to 0.2dB, a performance test result is generated to characterize the test as passed. If the insertion loss is greater than 2.5dB, the channel crosstalk is greater than -25dB, or the polarization loss is greater than 0.2dB, a performance test result indicating that the characterization test failed is generated.

Images