A method for preparing a silicon-based inverted-pyramid positioning via integrated MPO ferrule

Abstract

The application discloses a preparation method of a silicon-based inverted-pyramid positioning through-hole integrated MPO ferrule, and comprises the following steps: S1, substrate processing; S2, front surface photoetching and etching: photoetching is performed on the front surface of a silicon wafer to form a fiber positioning window and a positioning mark Mark pattern, and a SiN film layer is etched to expose a silicon substrate; S3, inverted-pyramid etching: wet etching is performed on the silicon substrate by using an etching solution to form an arrayed inverted-pyramid type fiber positioning pit, and a positioning mark is reserved; S4, back surface medium layer preparation: a silicon dioxide film layer is deposited on the back surface of the silicon wafer by using a PECVD process; S5, groove surface protective layer preparation; S6, back surface positioning photoetching; S7, back surface deep silicon etching; S8, post-processing: residual masks and protective layers are removed, and a silicon-based MPO / MT ferrule is obtained; the application has high positioning precision, high integration density, effectively protects the groove surface appearance, and avoids damage and drilling corrosion.

Description

Technical Field

[0001] This invention belongs to the field of optical fiber communication connector technology, and relates to a method for preparing a silicon-based inverted pyramid positioning through-hole integrated MPO ferrule. Background Technology

[0002] MPO / MT multi-core fiber optic connectors are core connection devices for high-speed optical modules, data center optical interconnects, and CPO co-packaged optical systems, with the MT ferrule being the core component.

[0003] Currently, commercially available MT ferrules are mainly made of zirconia ceramic or engineering plastics, and are manufactured through mechanical drilling, grinding, V-groove forming, etc., which has the following shortcomings: 1. The machining precision of ceramic ferrules is limited, the consistency of high-density arrays is poor, and the positioning accuracy is difficult to meet the requirements of ultra-high-speed optical modules; 2. Plastic cores have poor high temperature resistance and aging resistance, and are prone to thermal deformation and end face ablation in high power transmission scenarios; 3. Traditional silicon-based fiber arrays mostly adopt a long strip V-groove structure without a through hole on the back, and cannot be used directly as an MPO ferrule; 4. Conventional through-silicon via (TSV) technology only achieves vertical through-holes, lacks a front-end fiber self-alignment structure, and has low assembly coaxiality and high coupling loss. 5. During the deep silicon etching process on the back side, etching damage and drilling can easily occur on the inverted pyramid groove surface on the front side, affecting the positioning accuracy. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for preparing a silicon-based inverted pyramid positioning through-hole integrated MPO ferrule.

[0005] The technical solution adopted in this invention is: a method for preparing a silicon-based inverted pyramid positioning through-hole integrated MPO ferrule, comprising the following steps: S1, Substrate Treatment: Select <100> Using crystal-oriented monocrystalline silicon wafers as substrates, SiN films are deposited on both sides of the silicon wafers through LPCVD process, serving as hard masks for wet etching. S2. Front-side photolithography and etching: Photolithography is performed on the front side of the silicon wafer to form fiber positioning windows and alignment mark patterns, and the SiN film layer is etched to expose the silicon substrate. S3, Inverted Pyramid Etching: Wet etching of silicon substrate is performed using an etching solution to form an array of inverted pyramid-shaped fiber positioning pits, while retaining alignment marks; S4. Backside dielectric layer preparation: A silicon dioxide film is deposited on the backside of the silicon wafer using PECVD process, which serves as a backside deep silicon etching mask; S5. Preparation of the trench surface protective layer: In the inverted pyramid trench surface area, a multi-layer composite protective layer is deposited by magnetron sputtering to protect the trench surface from damage and drilling during subsequent deep silicon etching. S6. Backside alignment photolithography: Using the Mark retained on the front side as a reference, double-sided precise alignment photolithography is performed to etch silicon dioxide on the back side to form through-hole patterns. S7. Backside deep silicon etching: Deep silicon etching is performed on the backside of the silicon wafer to form a vertical fiber optic via that is precisely connected to the bottom of the inverted pyramid on the front side, and MPO standard positioning pinholes are formed simultaneously. S8. Post-processing: Remove residual mask and protective layer to obtain silicon-based MPO / MT ferrules.

[0006] Preferably, in step S1, the SiN film thickness is 100–300 nm.

[0007] Preferably, in step S5: the multilayer composite protective layer is an etching protection layer, used to prevent deep silicon etching from causing damage and erosion to the inverted pyramid groove surface.

[0008] Preferably, in step S7: deep silicon etching is DRIE (Deep Reactive Ion Etching) with an etching depth ≥ 500 μm.

[0009] Preferably, in step S2: the alignment mark is a combined structure, which includes a cross mark, a square mark, and a ruler, with a size of 10–200 μm.

[0010] Preferably, in step S3: the etching solution is a KOH or TMAH alkaline anisotropic etching solution.

[0011] Preferably, in step S8, after removing the residual mask and protective layer, the processes of dicing, thinning, end face grinding, and cleaning are performed sequentially.

[0012] Preferably, in step S1, the <100> The thickness of the crystal-oriented single-crystal silicon wafer is 300–1500 μm, and it is n-type. <100> silicon wafers or p-type <100> Silicon wafers.

[0013] Compared with the prior art, the silicon-based inverted pyramid positioning through-hole integrated MPO ferrule manufacturing method provided by the present invention achieves at least the following beneficial effects: 1. Extremely high positioning accuracy: The positioning structure is defined by photolithography, and the hole positioning accuracy can reach ±0.5μm, which is far superior to traditional ceramic and mechanical processing solutions; 2. Extremely high integration density: Currently, it is possible to mass-produce 424-core ultra-high-density MPO ferrules, and the integration density can be further improved through layout design; 3. Reliable trench surface protection: The inverted pyramid trench surface is equipped with a composite protective layer, which effectively protects the trench surface morphology during deep silicon etching on the back side, avoids damage and drilling, and ensures high-precision positioning; 4. Double-sided precise alignment: High-precision alignment is achieved by relying on the front Mark, the through hole and the inverted pyramid have high coaxiality, the fiber optic assembly is convenient and the coupling loss is low. 5. Excellent stability of silicon substrate: Monocrystalline silicon has good dimensional stability and high processing consistency, making it suitable for 800G / 1.6T and CPO high-speed optical module scenarios; 6. Mass production capability: Compatible with standard MEMS micro-nano fabrication production lines, with high yield and good consistency, enabling large-scale manufacturing. Attached Figure Description

[0014] Figure 1 This is a schematic cross-sectional view of the process flow for the fabrication method of an integrated MPO ferrule with a silicon-based inverted pyramid positioning through-hole according to the present invention. Detailed Implementation

[0015] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0016] A method for fabricating a silicon-based inverted pyramid positioning through-hole integrated MPO ferrule includes the following steps: S1, Substrate Treatment: Select <100> Using crystal-oriented monocrystalline silicon wafers as substrates, SiN films are deposited on both sides of the silicon wafers through LPCVD process, serving as hard masks for wet etching. S2. Front-side photolithography and etching: Photolithography is performed on the front side of the silicon wafer to form fiber positioning windows and alignment mark patterns, and the SiN film layer is etched to expose the silicon substrate. S3, Inverted Pyramid Etching: Wet etching of silicon substrate is performed using an etching solution to form an array of inverted pyramid-shaped fiber positioning pits, while retaining alignment marks; S4. Backside dielectric layer preparation: A silicon dioxide film is deposited on the backside of the silicon wafer using PECVD process, which serves as a backside deep silicon etching mask; S5. Preparation of the trench surface protective layer: In the inverted pyramid trench surface area, a multi-layer composite protective layer is deposited by magnetron sputtering to protect the trench surface from damage and drilling during subsequent deep silicon etching. S6. Backside alignment photolithography: Using the Mark retained on the front side as a reference, double-sided precise alignment photolithography is performed to etch silicon dioxide on the back side to form through-hole patterns. S7. Backside deep silicon etching: Deep silicon etching is performed on the backside of the silicon wafer to form a vertical fiber optic via that is precisely connected to the bottom of the inverted pyramid on the front side, and MPO standard positioning pinholes are formed simultaneously. S8. Post-processing: Remove residual mask and protective layer to obtain silicon-based MPO / MT ferrules.

[0017] In step S1: the SiN film thickness is 100–300 nm; in step S5: the multilayer composite protective layer is an etching protection layer, used to prevent deep silicon etching from damaging and eroding the inverted pyramid groove surface; in step S7: the deep silicon etching is DRIE deep reactive ion etching with an etching depth ≥ 500 μm.

[0018] In step S2: the alignment mark is a combined structure, which includes a cross mark, a square mark, and a scale, with dimensions of 10–200 μm; In step S3: the etching solution is a KOH or TMAH alkaline anisotropic etching solution, suitable for large-area uniform etching; In step S8, after removing the residual mask and protective layer, the etching, thinning, end-face grinding, and cleaning are performed sequentially, improving the overall yield and process compatibility; In step S1, <100> The thickness of the crystal-oriented single-crystal silicon wafer is 300–1500 μm, and it is n-type. <100> silicon wafers or p-type <100> Silicon wafers are suitable for both wet etching and dry etching, facilitating micro- and nano-fabrication.

[0019] See Figure 1 The specific steps for implementation are as follows: Step 1, Select <100> Crystal-oriented single-crystal silicon wafers; Step 2: Deposit SiN hard mask on both sides using LPCVD; Step 3: Form the pattern on the front side using photolithography; Step 4: Etch the front-side SiN; Step 5: Form an array of inverted pyramid positioning pits by alkaline wet etching, preserving alignment marks; Step 6: Remove the SiN film; Step 7: Prepare a silicon dioxide mask on the back side of the silicon wafer by PECVD, and deposit a multilayer composite metal protective layer on the pyramid face by magnetron sputtering. Step 8: Perform double-sided alignment photolithography on the back of the wafer using the front-side mark; Step 9: Etch the SiO2 layer on the back side; Step 10: Etch deep Si using deep reactive ion etching (DRIE) technology until it penetrates the front pyramid to form a via and an MPO positioning pinhole; Step 11: Wet cleaning and removal of the mask and protective layer; Step 12: Dicing and grinding to obtain silicon-based MPO / MT ferrules.

[0020] In summary, this invention provides a silicon-based inverted pyramid positioning through-hole integrated MPO ferrule fabrication method. It employs photolithography to define the positioning structure, achieving a hole positioning accuracy of ±0.5μm, far superior to traditional ceramic and mechanical processing methods, demonstrating extremely high positioning precision. Currently, it can mass-produce 424-core ultra-high-density MPO ferrules, and the integration density can be further improved through layout design, resulting in high integration density. A composite protective layer is set on the inverted pyramid groove surface, effectively protecting the groove morphology during deep silicon etching on the back side, avoiding damage and drilling, and ensuring high-precision positioning. High-precision alignment is achieved using the front-side marker, with high coaxiality between the through-hole and the inverted pyramid, facilitating fiber assembly and reducing coupling loss. The single-crystal silicon exhibits good dimensional stability and high processing consistency, making it suitable for 800G / 1.6T and CPO high-speed optical module scenarios, demonstrating excellent silicon substrate stability. It is compatible with standard MEMS micro / nano processing lines, achieving high yield and good consistency, and enabling large-scale manufacturing.

[0021] The above embodiments are not intended to limit the present invention, and the present invention is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of the technical solution of the present invention are also within the protection scope of the present invention.

Claims

1. A method for fabricating a silicon-based inverted pyramid positioning through-hole integrated MPO ferrule, characterized in that: Includes the following steps: S1, Substrate Treatment: Select <100> Using crystal-oriented monocrystalline silicon wafers as substrates, SiN films are deposited on both sides of the silicon wafers through LPCVD process, serving as hard masks for wet etching. S2. Front-side photolithography and etching: Photolithography is performed on the front side of the silicon wafer to form fiber positioning windows and alignment mark patterns, and the SiN film layer is etched to expose the silicon substrate. S3, Inverted Pyramid Etching: Wet etching of silicon substrate is performed using an etching solution to form an array of inverted pyramid-shaped fiber positioning pits, while retaining alignment marks; S4. Backside dielectric layer preparation: A silicon dioxide film is deposited on the backside of the silicon wafer using PECVD process, which serves as a backside deep silicon etching mask; S5. Preparation of the trench surface protective layer: In the inverted pyramid trench surface area, a multi-layer composite protective layer is deposited by magnetron sputtering to protect the trench surface from damage and drilling during subsequent deep silicon etching. S6. Backside alignment photolithography: Using the Mark retained on the front side as a reference, double-sided precise alignment photolithography is performed to etch silicon dioxide on the back side to form through-hole patterns. S7. Backside deep silicon etching: Deep silicon etching is performed on the backside of the silicon wafer to form a vertical fiber optic via that is precisely connected to the bottom of the inverted pyramid on the front side, and MPO standard positioning pinholes are formed simultaneously. S8. Post-processing: Remove residual mask and protective layer to obtain silicon-based MPO / MT ferrules.

2. The method according to claim 1, characterized in that: In step S1, the thickness of the SiN film is 100–300 nm.

3. The method according to claim 1, characterized in that: In step S5: the multi-layer composite protective layer is an etching protection layer, used to prevent deep silicon etching from causing damage and erosion to the inverted pyramid groove surface.

4. The method according to claim 1, characterized in that: In step S7, the deep silicon etching is DRIE (Deep Reactive Ion Etching) with an etching depth ≥ 500 μm.

5. The method according to claim 1, characterized in that: In step S2: the alignment mark is a combination structure, which includes a cross mark, a square mark, and a ruler, with a size of 10–200 μm.

6. The method according to claim 1, characterized in that: In step S3: the etching solution is KOH or TMAH alkaline anisotropic etching solution.

7. The method according to claim 1, characterized in that: In step S8, after removing the residual mask and protective layer, the processes of dicing, thinning, end face grinding and cleaning are performed in sequence.

8. The method according to any one of claims 1-7, characterized in that: In step S1, the <100> The thickness of the crystal-oriented single-crystal silicon wafer is 300–1500 μm, and it is n-type. <100> silicon wafers or p-type <100> Silicon wafers.

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