A bridge chip structure applied to photoelectric co-packaging

Abstract

The application discloses a bridge chip structure applied to photoelectric co-encapsulation. Small-size light spots in a silicon light waveguide on a silicon light chip are converted into large-size light spots matched with optical fibers through an on-chip light spot conversion structure by adopting a silicon-based silicon nitride or silicon oxy-nitride waveguide, and meanwhile, dense silicon light waveguide input and output arrays are expanded to standard pitches of optical fiber arrays. The bridge chip can be bonded to a silicon-based CPO adapter plate or substrate in a die-to-wafer or die-to-die mode, stable integration is realized, and long-term reliability problems of a glass bridge solution are avoided. Without the aid of external lens groups or independent fan-out components, the CPO optical coupling system architecture is greatly simplified, assembly complexity and material costs are reduced. The bonding interface thermal stress failure problem caused by CTE mismatch in the glass bridge solution is avoided, and the long-term reliability of the packaging structure is significantly improved. The coupling efficiency can remain stable, and the long-term reliability is significantly better than that of the existing solution.

Description

Technical Field

[0001] This invention relates to the field of optical communication, and more specifically, to a bridge chip structure applied to optoelectronic co-packaging. Background Technology

[0002] Co-Packaged Optics (CPO) technology, which integrates optical engines and switching chips, is a key solution for overcoming the "power consumption wall" and "bandwidth wall" in AI data centers. As data centers move towards the 800G / 1.6T / 3.2T era, CPO technology, with its significant advantages such as shortening electrical signal transmission distance, reducing power consumption, and increasing bandwidth density, has become a cutting-edge development direction in the field of optical communication.

[0003] In a CPO optical engine, the optical coupling between the fiber array (FA) and the silicon photonic chip is a core element determining system performance—the optical signal needs to enter the silicon photonic chip from the fiber array for processing, and then be coupled back to the fiber array for output to the system. The efficiency and quality of this optical coupling channel directly determine the insertion loss, transmission bandwidth, and long-term reliability of the entire optical engine. However, this coupling process faces serious technical bottlenecks, specifically including:

[0004] 1) Severe spot size mismatch and extremely high direct coupling loss. The spot size of silicon waveguides is only 1~10μm (typically 4μm), while the mode field diameter of standard single-mode fiber is 8~10μm or even larger. The mode field area of ​​the two differs by several times. When directly end-to-end is connected, the mode field mismatch loss can reach several dB, which cannot meet the performance requirements of CPO optical engines for low insertion loss.

[0005] 2) The coupling alignment tolerance is extremely stringent, resulting in low packaging yield. Because the spot size is on the micrometer scale, the coupling alignment tolerance between the silicon photonics chip and the fiber array is usually in the submicrometer level (1dB position tolerance is usually <±1μm). This places extremely stringent requirements on the precision of the packaging equipment, environmental vibration, and temperature stability, resulting in a long packaging process, low yield, and high cost, making it difficult to achieve mass production.

[0006] 3) Beam expander lens schemes are complex in structure and lack long-term reliability. Existing beam expander schemes require a series of discrete micro-optical components such as spherical lenses, aspherical lenses, and mirrors, resulting in complex optical path structures and multiple coupling links. Each interface introduces additional Fresnel reflection loss and assembly tolerance accumulation. Furthermore, even a small displacement (submicron level) after the fiber is thermally expanded or stretched by external forces can lead to significant coupling degradation, making it difficult to guarantee long-term reliability.

[0007] 4) Mismatched array spacing, making high-channel-count coupling difficult. The spacing between silicon photonic waveguide input and output arrays on silicon photonic chips is typically only 20~100μm, while the standard spacing of fiber arrays is 127μm or 250μm, a difference of 2.5 to 12.5 times. As the number of CPO channels evolves from 4 channels to 32 channels and even higher, silicon photonic chips have limited edge length and dense waveguide arrangement, while fiber arrays are limited by the fiber cladding diameter, resulting in a fixed spacing. The two spatial scales are severely mismatched, making direct one-to-one coupling of multiple channels impossible. Optical path conversion is necessary to achieve fan-in / fan-out.

[0008] 5) Poor compatibility between glass bridging solutions and silicon photonic chips. Glass bridge solutions use ion-exchange waveguides to prefabricate optical paths inside the glass. However, the CTE (coefficient of thermal expansion) of glass and silicon photonic chips differs significantly. During temperature cycling, thermal stress accumulation at the bonding interface can easily lead to cracking or desoldering. Furthermore, glass waveguides are difficult to integrate stably with silicon photonic chips using standard semiconductor bonding processes such as die-to-wafer (D2W) or die-to-die (D2D), increasing system complexity and failure risk. Summary of the Invention

[0009] To address the dual bottlenecks of spot mismatch and array spacing mismatch in CPO optical coupling, this invention proposes a bridging chip structure for optoelectronic co-packaging. This chip structure employs silicon-based silicon nitride or silicon oxynitride waveguides. Through an on-chip spot conversion structure, the small-sized spot in the silicon waveguide on the silicon photonic chip is converted into a large-sized spot that matches the optical fiber. Simultaneously, the dense silicon waveguide input / output array is extended to the standard spacing of an optical fiber array. This bridging chip can be bonded to a silicon-based CPO adapter board or substrate via die-to-wafer or die-to-die bonding, achieving robust integration and avoiding the long-term reliability issues of glass bridging solutions.

[0010] This invention is achieved in the following ways:

[0011] The beneficial effects of this invention are:

[0012] 1) This invention uses silicon-based silicon nitride or silicon oxynitride waveguide chips, integrating the spot conversion structure and waveguide array extension structure on the chip. It integrates the two major functions of spot conversion and spacing fan-out into a single chip, eliminating the need for external lens groups or independent fan-out components. This greatly simplifies the CPO optical path coupling system architecture and reduces assembly complexity and material costs.

[0013] 2) The bridging chip in this invention uses silicon as the substrate, silicon dioxide as the cladding, and silicon nitride or silicon oxynitride as the core layer. The material system is the same as that of silicon photonic chips. It can be stably integrated through standard semiconductor bonding processes such as die-to-wafer (D2W) or die-to-die (D2D). The coefficient of thermal expansion (CTE) is highly matched with that of silicon photonic chips, avoiding the thermal stress failure problem of the bonding interface caused by CTE mismatch in glass bridge solutions, and significantly improving the long-term reliability of the packaging structure.

[0014] 3) This invention uses an on-chip graded waveguide structure to gradually widen the small-sized light spot on the end face of the silicon photonic chip into a large-sized light spot that matches the fiber mode field, significantly widening the coupling tolerance between the bridging chip and the fiber array; at the same time, through the S-shaped bent waveguide and straight waveguide connection structure, the dense silicon photonic waveguide array (spacing 20~100μm) is gradually expanded to the standard spacing of the fiber array (127μm or 250μm or more compact spacing), realizing efficient fan-in / fan-out of the optical path under high channel number, effectively supporting the multi-channel parallel coupling requirements of 800G / 1.6T / 3.2T CPO optical engines.

[0015] 4) This invention adopts a monolithic integrated waveguide structure, which avoids the use of discrete micro-optical components such as spherical lenses, aspherical lenses, and mirrors in the beam expander lens scheme. It eliminates the accumulation of multi-interface Fresnel reflection loss and assembly tolerance. Moreover, the bridging chip structure is stable and has no moving parts. Even if the optical fiber is thermally expanded or subjected to external force and undergoes a small displacement after packaging, the coupling efficiency can still remain stable. The long-term reliability is significantly better than the existing scheme. Attached Figure Description

[0016] Figure 1 This is a side view of the co-packaging structure when the bridging chip proposed in this invention is applied to optoelectronic co-packaging (CPO).

[0017] Figure 2 A schematic diagram (side view) of the bridging chip film layer before co-packaging, i.e. before bonding to the CPO adapter board or substrate.

[0018] Figure 3 This is a schematic diagram (top view) of the waveguide connection of the bridging chip proposed in this invention.

[0019] Figure 4 The images show the light field distribution of 4μm and 10μm diameter light spots in the embodiments listed in this invention.

[0020] Among them, 1 is the bridging chip, 2 is the silicon photonics chip, 3 is the cladding layer, 4 is the CPO adapter board or substrate, 5 is the fiber array, 6 is the silicon substrate of the bridging chip, 7 is the lower cladding of the bridging chip, 8 is the waveguide core layer of the bridging chip, 9 is the upper cladding of the bridging chip, 21 is the silicon photonics waveguide input / output array, 111 is narrow straight waveguide a, 112 is narrow straight waveguide b, 113 is narrow straight waveguide c, 171 is narrow straight waveguide d, 172 is narrow straight waveguide e, 173 is narrow straight waveguide f, 121 is trapezoidal waveguide a on both sides, 122 is trapezoidal waveguide a in the middle, 123 is trapezoidal waveguide b on both sides, 161 is trapezoidal waveguide c on both sides, 162 is trapezoidal waveguide b in the middle, 163 is trapezoidal waveguide d on both sides, 13 is wide straight waveguide a, 14 is S-shaped curved waveguide, and 15 is wide straight waveguide b. Detailed Implementation

[0021] This invention proposes a bridging chip 1 structure for optoelectronic co-packaging, i.e., CPO. The chip has a spot conversion structure for converting a small spot into a large spot, and is bonded to a silicon-based CPO adapter board or substrate 4 via die-to-wafer D2W or die-to-die D2D. The spot conversion structure includes a bridging chip 1 waveguide array, which includes at least one bridging chip 1 waveguide array unit. Each bridging chip 1 waveguide array unit includes a waveguide group A that interfaces with the silicon photonic waveguide input / output array 21 in the silicon photonic chip 2, a waveguide group B that interfaces with the fiber array 5, and a bent waveguide group connecting the waveguide group A and the waveguide group B.

[0022] The waveguide assembly consists of optical waveguides, and each optical waveguide has the same film structure in the cross-section of the bridging chip 1, such as... Figure 2 As shown, the bridging chip includes, from bottom to top, a silicon substrate 6, a lower cladding layer 7, a waveguide core layer 8, and an upper cladding layer 9 covering the upper and side surfaces of the waveguide core layer 8. The silicon substrate 6 is silicon with a thickness of 50-400 μm. The waveguide core layer 8 is silicon nitride or silicon oxynitride with a thickness of 100 nm-500 nm. The upper cladding layer 9 and the lower cladding layer 7 are silicon dioxide with a thickness of 5-30 μm. The width of the waveguide core layer 8 is 50 nm-3000 nm.

[0023] Waveguide group A and waveguide group B both consist of an odd number of narrow straight waveguides with constant width and trapezoidal waveguides with varying width connected to them, which together support an optical mode. The middle trapezoidal waveguide widens and connects to the wide straight waveguide, while the trapezoidal waveguides on both sides become narrower and are no longer connected to other waveguides. However, in order to expand the light spot, the spacing between the narrow straight waveguides in waveguide group B is larger than that in waveguide group A.

[0024] The curved waveguide group includes two wide straight waveguides connected to the trapezoidal waveguides in the middle of waveguide group A and waveguide group B, respectively, and an S-shaped curved waveguide 14 connecting the two wide straight waveguides to realize the connection between the waveguide on the side docked with the silicon photonic chip 2 and the waveguide on the side docked with the fiber array 5. On the side docked with the silicon photonic chip 2, the waveguide size and spacing in each bridging chip 1 waveguide array unit are the same. On the side docked with the fiber array 5, the waveguide size and spacing in each bridging chip 1 waveguide array unit are also the same. The width w of the S-shaped curved waveguide 14 in each bridging chip 1 waveguide array unit along the array direction is different to realize the fan-out of the waveguide.

[0025] The spacing between waveguide groups A of each bridging chip 1 waveguide array unit corresponds to the spacing between silicon photonic waveguide input / output arrays 21, which is 20~100μm. The spacing between waveguide groups B of each bridging chip 1 waveguide array unit corresponds to the fiber spacing, which is 127μm, 250μm, or 60~90μm.

[0026] In waveguide group A and waveguide group B, the width of the narrow straight waveguide is 100nm~400nm. The trapezoidal waveguides on both sides gradually narrow from the narrow straight waveguide to 50nm~200nm, and the trapezoidal waveguide in the middle gradually widens from the narrow straight waveguide to 400nm~3μm. The spacing between the narrow straight waveguides is 0.5μm~3μm on the side that is connected to the silicon photonic chip 2, and 1μm~10μm on the side that is connected to the fiber array 5. The bending radius of the S-shaped waveguide is 100μm~1000μm.

[0027] Small-sized light spots, ranging from 1 to 10 μm, are generated by the silicon photonic waveguide input / output array 21. After passing through waveguide group A, the bent waveguide group, and the waveguide group B of the light spot conversion structure of bridging chip 1, large-sized light spots ranging from 5 to 30 μm are generated. In a classic sense, the small-sized light spot is 4 μm and the large-sized light spot is 10 μm.

[0028] The number of arrays in the silicon photonic waveguide input / output array 21, the bridging chip 1 waveguide array, and the fiber array 5 is the same, ranging from 8 to 300.

[0029] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: In this embodiment, the number of waveguide subgroups A and B, and the number of narrow straight waveguides are both odd numbers of 3.

[0030] The bridge chip 1 is applied to CPO in the form shown in the instruction manual. Figure 1As shown, bridging chip 1 and silicon photonic chip 2 are bonded together to CPO adapter board or substrate 4, achieving coupling between the silicon photonic waveguide on silicon photonic chip 2 and the optical waveguide on bridging chip 1. Both chips are covered by a capping layer 3. Removing the capping layer 3 from the side of bridging chip 1 opposite to silicon photonic chip 2 allows the fiber array 5 to be placed at the edge of bridging chip 1 and coupled with the waveguide on bridging chip 1. The beam conversion structure includes a bridging chip 1 waveguide array, comprising 16 bridging chip 1 waveguide array units. Each bridging chip 1 waveguide array unit includes waveguide group A, which interfaces with the silicon photonic waveguide input / output array 21 in silicon photonic chip 2; waveguide group B, which interfaces with the fiber array 5; and a curved waveguide group connecting waveguide group A and waveguide group B. The waveguide assembly consists of optical waveguides. Each optical waveguide in the bridging chip 1 has the same film structure in its cross-section, including, from bottom to top, the bridging chip silicon substrate 6, the bridging chip lower cladding 7, the bridging chip waveguide core layer 8, and the bridging chip upper cladding 9 covering the upper and side surfaces of the bridging chip waveguide core layer 8. The bridging chip waveguide core layer 8 on the bridging chip 1 is entirely composed of interconnected silicon nitride optical waveguides, and all optical waveguides are silicon nitride waveguides of the same thickness. In the commonly used communication band, i.e., a wavelength of 1310 nm, the refractive indices of silicon nitride and silicon dioxide are 1.9788 and 1.46, respectively. The silicon substrate thickness is 200 μm (for convenient subsequent bonding to the CPO adapter board or substrate 4), the silicon nitride waveguide thickness is 200 nm, and the silicon dioxide thickness of both the upper and lower cladding layers is 10 μm.

[0031] The spacing between waveguide groups A of each bridging chip 1 waveguide array unit corresponds to the spacing between silicon photonic waveguide input / output arrays 21, which is 50 μm. The spacing between waveguide groups B of each bridging chip 1 waveguide array unit corresponds to the fiber spacing, which is 127 μm.

[0032] Waveguide group A consists of three narrow, straight waveguides, each 220 nm wide and 0.8 μm apart, which together support one optical mode (as per the instruction manual). Figure 4 As shown in the left figure, the calculated mode width is 4μm, and the coupling efficiency with a 4μm diameter circular spot (assuming it is a silicon waveguide end face spot) is 0.94, which can very well realize the optical field coupling from the silicon waveguide to the bridging chip 1 waveguide.

[0033] Waveguide group B consists of three narrow, straight waveguides, each 220 nm wide and 2.6 μm apart, which together support one optical mode (as per the instruction manual). Figure 4 As shown in the right figure, the calculated mode width is 10μm, and the coupling efficiency with a 10μm diameter circular light spot (assuming it is an optical fiber spot) is 0.93, which can very well realize the optical field coupling from the waveguide of bridging chip 1 to the optical fiber.

[0034] In waveguide group A, there are three waveguide subgroups, each consisting of three trapezoidal waveguides connecting the three narrow straight waveguides. The middle waveguide gradually widens from 220nm to 800nm, while the two side waveguides gradually narrow to 150nm. Similarly, in waveguide group B, three trapezoidal waveguides also connect the three narrow straight waveguides, with the middle waveguide gradually widening from 220nm to 800nm ​​and the two side waveguides gradually narrowing to 150nm.

[0035] In the two sets of waveguide structures mentioned above, the widened waveguides are connected by an S-shaped curved waveguide 14 and wide straight waveguides on both sides connected to it. The width of each waveguide is 800 nm and the S-shaped bending radius is 400 μm.

[0036] like Figure 3 As shown, to illustrate how the waveguides are arranged, this figure also shows the relative positions of the waveguide array of the bridging chip 1 after optoelectronic co-packaging, the silicon photonics waveguide input / output array 21, and the fiber array 5.

[0037] Narrow straight waveguide a111 is connected to the two trapezoidal waveguides a121, narrow straight waveguide b112 is connected to the middle trapezoidal waveguide a122, and narrow straight waveguide c113 is connected to the two trapezoidal waveguides b123 respectively. Narrow straight waveguide d171 is connected to the two trapezoidal waveguides c161, narrow straight waveguide e172 is connected to the middle trapezoidal waveguide b162, and narrow straight waveguide f173 is connected to the two trapezoidal waveguides d163 respectively. The above two sets of structures are connected by a structure in which the middle trapezoidal waveguide a122, the wide straight waveguide a13, the S-shaped curved waveguide 14, the wide straight waveguide b15, and the middle trapezoidal waveguide b162 are connected in sequence. Among them, the middle trapezoidal waveguide gradually widens, while the two trapezoidal waveguides gradually narrow.

[0038] The curved waveguide group includes two wide straight waveguides connected to the trapezoidal waveguides in the middle of waveguide group A and waveguide group B, respectively, and an S-shaped curved waveguide 14 connecting the two wide straight waveguides, so as to realize the connection between the waveguide on the side docked with the silicon photonic chip 2 and the waveguide group on the side docked with the fiber array 5. On the side docked with the silicon photonic chip 2, the waveguide size and spacing in each bridging chip 1 waveguide array unit are the same. On the side docked with the fiber array 5, the waveguide size and spacing in each bridging chip 1 waveguide array unit are also the same. The width w of the S-shaped curved waveguide 14 in each bridging chip 1 waveguide array unit along the array direction is different, so as to realize the fan-out of the waveguide. Assuming the array size is 16, then w will be: 616μm, 539μm, 462μm, 385μm, 308μm, 231μm, 154μm, 77μm, 77μm, 154μm, 231μm, 308μm, 385μm, 462μm, 539μm, 616μm.

[0039] After the bridging chip 1 is fabricated, it can be bonded together with the silicon photonic chip 2 onto the CPO adapter board or substrate 4 and coupled. Both chips are covered by a cover layer 3 of silicon oxide or optical adhesive. After removing the cover layer 3 on the other side of the bridging chip 1 relative to the silicon photonic chip 2, the fiber array 5 can be placed at the edge of the bridging chip 1 and coupled with the waveguide array on the bridging chip 1. This achieves efficient and stable coupling between the optical fiber and the silicon photonic chip 2 through the bridging chip 1.

[0040] Simulation calculations show that, with the above settings, the efficiency of a 4-micrometer diameter light spot (assuming it is a silicon optical waveguide end face light spot) being transmitted through the light spot conversion chip and coupled to a 10-micrometer diameter light spot (assuming it is an optical fiber light spot) is 0.82, and the loss is 0.86dB, which is much smaller than the loss of direct coupling between optical fiber and the two end faces of silicon optical chip (>1.5dB) reported so far.

[0041] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention. Those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A bridge chip structure for use in optoelectronic co-packaging (CPO), characterized in that, The chip has a spot conversion structure for converting a small spot into a large spot, and is bonded to a silicon-based CPO adapter board or substrate via die-to-wafer (D2W) or die-to-die (D2D) bonding. The spot conversion structure includes a bridging chip waveguide array, which includes at least one bridging chip waveguide array unit. Each bridging chip waveguide array unit includes waveguide group A, which is connected to the silicon photonic waveguide input / output array in the silicon photonic chip, waveguide group B, which is connected to the fiber array, and a bent waveguide group connecting waveguide group A and waveguide group B.

2. The bridge chip structure for optoelectronic co-packaging according to claim 1, characterized in that, The waveguide assembly consists of optical waveguides, and each optical waveguide has the same film structure in the cross section of the bridging chip, including, from bottom to top, the bridging chip silicon substrate, the bridging chip lower cladding, the bridging chip waveguide core layer, and the bridging chip upper cladding covering the upper and side surfaces of the bridging chip waveguide core layer.

3. The bridge chip structure for optoelectronic co-packaging according to claim 2, characterized in that, The bridging chip has a silicon substrate with a thickness of 50-400 μm; the bridging chip waveguide core layer is made of silicon nitride or silicon oxynitride with a thickness of 100 nm-500 nm; the upper and lower cladding layers of the bridging chip are made of silicon dioxide with a thickness of 5-30 μm; and the width of the bridging chip waveguide core layer is 50 nm-3000 nm.

4. The bridge chip structure for optoelectronic co-packaging according to claim 1, 2, or 3, characterized in that, Both waveguide group A and waveguide group B consist of an odd number of narrow straight waveguides with constant width and trapezoidal waveguides with varying width connected to them, which together support an optical mode. The middle trapezoidal waveguide widens and connects to the wide straight waveguide, while the trapezoidal waveguides on both sides become narrower and are no longer connected to other waveguides. However, in order to expand the light spot, the spacing between the narrow straight waveguides in waveguide group B is larger than that in waveguide group A.

5. The bridge chip structure for optoelectronic co-packaging according to claim 4, characterized in that, The curved waveguide assembly includes two wide straight waveguides connected to the trapezoidal waveguides in the middle of waveguide assembly A and waveguide assembly B, respectively, and an S-shaped curved waveguide connecting the two wide straight waveguides to realize the connection between the waveguide on the side that interfaces with the silicon photonic chip and the waveguide on the side that interfaces with the fiber array. On the side that interfaces with the silicon photonic chip, the waveguide dimensions and spacing in each bridging chip waveguide array unit are the same. On the side that interfaces with the fiber array, the waveguide dimensions and spacing in each bridging chip waveguide array unit are also the same. The width w of the S-shaped curved waveguide in each bridging chip waveguide array unit along the array direction is different to realize the fan-out of the waveguide.

6. The bridge chip structure for optoelectronic co-packaging according to claim 5, characterized in that, The spacing between waveguide groups A of each bridging chip waveguide array unit corresponds to the spacing between silicon photonic waveguide input and output arrays, and is 20~100μm. The spacing between waveguide groups B of each bridging chip waveguide array unit corresponds to the fiber spacing, and is 127μm, 250μm, or 60~90μm.

7. The bridge chip structure for optoelectronic co-packaging according to claim 5 or 6, characterized in that, The width of the narrow straight waveguides in waveguide group A and waveguide group B is 100nm~400nm. The trapezoidal waveguides on both sides gradually narrow from narrow straight waveguides to 50nm~200nm, and the trapezoidal waveguide in the middle gradually widens from narrow straight waveguides to 400nm~3μm. The spacing between the narrow straight waveguides is 0.5μm~3μm on the side that interfaces with the silicon photonics chip and 1μm~10μm on the side that interfaces with the fiber array. The bending radius of the S-shaped waveguide is 100μm~1000μm.

8. The bridge chip structure for optoelectronic co-packaging according to claim 7, characterized in that, The small-sized light spot is generated by the silicon optical waveguide input-output array, with a size of 1~10μm. After passing through waveguide group A, curved waveguide group and waveguide group B of the bridging chip light spot conversion structure, a large-sized light spot with a size of 5~30μm is generated.

9. The bridge chip structure for optoelectronic co-packaging according to claim 8, characterized in that, The small-sized light spot has a size of 4μm; the large-sized light spot has a size of 10μm.

10. The bridge chip structure applied to optoelectronic co-packaging according to claim 1, 2, 3, 5, 6, 8, or 9, characterized in that, The silicon optical waveguide input / output array, the bridging chip waveguide array, and the fiber array all have the same array number, ranging from 8 to 300.

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