Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a first waveguide extending in a first direction; the first waveguide includes a first doped contact region and a heating target region; a heater extending in the first direction and on the heating target region of the first waveguide with respect to a second direction perpendicular to the first direction; a tower, including a first tower on the first doped contact region, that is electrically conductive; a wall, including a first wall on the first waveguide and between the first tower and the heater; and the first wall includes one or more first materials configured to protect the first tower against heat transfer from the heater.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry produces a wide variety of analog and digital devices to solve problems in many different fields. Advances in semiconductor process technology nodes have gradually reduced component size and reduced spacing, leading to a gradual increase in transistor density. ICs have become smaller. Summary of the Invention

[0003] In some embodiments, the semiconductor device includes: a first waveguide extending in a first direction; the first waveguide including a first doped contact region and a heating target region; a heater extending in the first direction and on the heating target region of the first waveguide relative to a second direction perpendicular to the first direction; a conductive tower including the first tower on the first doped contact region; a wall including the first wall on the first waveguide and between the first tower and the heater; and the first wall including one or more first materials configured to protect the first tower from heat transfer from the heater.

[0004] In some embodiments, a method of manufacturing a semiconductor device includes: forming a first waveguide extending in a first direction; the first waveguide including a first doped contact region and a heating target region; forming a heater extending in the first direction and on the heating target region of the first waveguide, relative to a second direction perpendicular to the first direction; forming a first dielectric structure on the heater and the first waveguide; etching a groove including a T-groove and a W-groove in the first dielectric structure, which correspondingly exposes the first waveguide or the heater; depositing material in the T-groove and the W-groove to correspondingly form a tower and a wall, the tower including a first tower on the first doped contact region, and the wall including a first wall on the first waveguide and between the first tower and the heater; and depositing the material including: depositing one or more first materials in one of the W-grooves corresponding to the first wall, the one or more first materials being configured to protect the first tower against heat transfer from the heater.

[0005] In some embodiments, the semiconductor device includes: a first waveguide extending in a first direction; the first waveguide including a first doped contact region and a heating target region; a heater extending in the first direction and on the heating target region of the first waveguide, relative to a second direction perpendicular to the first direction; a conductive tower including the first tower on the first doped contact region; and a wall including: a first wall on the first waveguide and between the first tower and the heater, and a second wall on the first waveguide and between the first tower and the heater; the first wall including one or more first materials configured to protect the first tower against heat transfer from the heater; and the second wall including one or more second materials configured to protect the first tower against heat transfer from the heater. Attached Figure Description

[0006] One or more embodiments are illustrated in the accompanying drawings by way of example rather than limitation, wherein elements having the same reference numerals denote similar elements throughout the drawings. Unless otherwise disclosed, the drawings are not drawn to scale.

[0007] Figure 1A This is a layout diagram according to some embodiments.

[0008] Figure 1B The waveform diagram is shown according to some embodiments.

[0009] Figure 1C This is a schematic circuit diagram according to some embodiments.

[0010] Figure 1D-1E This is a temperature distribution diagram based on some embodiments.

[0011] Figure 1F-1G The following are corresponding waveform diagrams according to some embodiments.

[0012] Figure 1H This is a cross-sectional view according to some embodiments.

[0013] Figure 2A-2B Correspondingly, layout diagrams and cross-sectional views are provided according to some embodiments.

[0014] Figure 2C-2D Correspondingly, layout diagrams and cross-sectional views are provided according to some embodiments.

[0015] Figure 2E-2F The following are corresponding waveform diagrams according to some embodiments.

[0016] Figure 2G-2H This is a corresponding three-quarter perspective view according to some embodiments.

[0017] Figure 2I This is a schematic circuit diagram according to some embodiments.

[0018] Figures 3A-3B This is a corresponding cross-sectional view according to some embodiments.

[0019] Figures 4A-4D This is a corresponding cross-sectional view according to some embodiments.

[0020] Figures 5A-5D This is a corresponding cross-sectional view according to some embodiments.

[0021] Figure 6 and Figure 7 The following is a flowchart of a corresponding method according to some embodiments.

[0022] Figure 8This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0023] Figure 9 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0024] The following disclosure reveals numerous different embodiments or examples for implementing various features of the subject matter. The following descriptions of elements, materials, values, steps, operations, configurations, or the like are examples to simplify the content of this disclosure. Of course, these are merely examples and are not intended to be limiting. Other elements, values, operations, materials, configurations, or the like are also considered. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0025] Furthermore, this document uses spatially relative terms, such as “beneath,” “lower,” “below,” “above,” “upper,” and similar terms, to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. In some embodiments, the term "standard cell structure" refers to a standardized building block included in various libraries of standard cell structures. In some embodiments, various standard cell structures are selected from their libraries and used as elements in layout diagrams representing circuits.

[0026] In some embodiments, the semiconductor device includes: a first waveguide extending along a first direction; the first waveguide including a first doped contact region and a heating target region; a heater extending along the first direction and located on the heating target region of the first waveguide relative to a second direction perpendicular to the first direction; a conductive tower including a first tower located on the first doped contact region; a wall including a first thermally-protective (TP) wall located on the first waveguide and between the first tower and the heater; and the first TP wall including one or more first materials and / or one or more first layers protecting the first tower from heat transfer from the heater. In some embodiments, the first TP wall exhibits a first thermal protection mode of low thermal conductivity (thermal insulation). In some embodiments, the first TP wall exhibits a first thermal protection mode of high reflectivity (IR reflection) relative to the infrared band of the electromagnetic spectrum. In some embodiments, the first TP wall exhibits a first thermal protection mode of a combination of thermal insulation and IR reflection; in some embodiments, this combination is referred to as 2-in-1 thermal protection. In some embodiments, the wall further includes a second TP wall located on the first waveguide and between the first tower and the heater, the second TP wall including one or more second materials and / or one or more second layers protecting the first tower from heat transfer from the heater. In some embodiments, the primary modes of protection of the first tower from heat transfer from the heater by the first TP wall and the second TP wall differ. In some embodiments, the first TP wall is thermally insulating. In some embodiments, the second TP wall is IR reflective. By including at least the first TP wall, the presented tower is protected from heat transfer from the heater that would otherwise cause a significant increase in the temperature of the presented tower and correspondingly an increase in the resistance of the presented tower, which would hinder the control of the presented PN junction, i.e., hinder the control of the presented diode, compared to another approach.

[0027] Figure 1A This is a layout diagram of a semiconductor device 100A according to some embodiments.

[0028] The structure in a semiconductor device is represented by a pattern (also called a shape) in a layout diagram. For the sake of simplicity, Figure 1A The elements in the layout diagrams and other layout diagrams disclosed herein will be referred to as structures rather than patterns. For example, Figure 1A The shape of the tower instance is referred to as the tower itself, not the tower shape.

[0029] The layout diagram is a top view. The shapes in the layout diagram are two-dimensional relative to, for example, the X and Y axes, while the represented device is three-dimensional. Therefore, the shapes in this layout diagram are described as having a width / length relative to the X-axis and a height relative to the Y-axis. Relative to the Z-axis, for example, the bottom / back side of the first element represented in the layout diagram is stacked on the top / front side of the second element represented in the layout diagram, or the top / front side of the first element is stacked, for example, below the bottom / back side of the second element.

[0030] Generally, layout diagrams assume a Cartesian coordinate system, where dimensions are shown parallel to the X or Y axis. Typically, semiconductor devices are organized as stacks of layers within a corresponding structure, with respect to the Z-axis. Each shape in the layout diagram more specifically represents an element in a corresponding layer of the corresponding device. Furthermore, layout diagrams typically represent the relative depth of a shape and its corresponding layer, i.e., its position along the Z-axis, by superimposing a second shape on a first shape such that the second shape at least partially overlaps the first shape. For illustrative purposes, some structures in a device having a first stacking order along the Z-axis are represented in the layout diagram using a second stacking order along the Z-axis, i.e., a different / twisted stacking order.

[0031] Layout diagrams vary in the amount of detail they represent. In some cases, selected layers of a layout diagram are combined / abstracted into a single layer, for example, for simplification. Alternatively, and / or additionally, in some cases, not all layers of the corresponding device are represented; that is, selected layers of the layout diagram are omitted, for example, for illustrative simplification. Alternatively, and / or additionally, in some cases, not all elements of a given depicted layer of the corresponding device are represented; that is, selected elements of a given depicted layer of the layout diagram are omitted, for example, for illustrative simplification. The layout diagrams disclosed herein are examples of layout diagrams in which selected layers and / or selected elements of a given depicted layer have been omitted.

[0032] According to the numbering convention of the corresponding process technology nodes for manufacturing the device, on the front side of the device, the first metallization layer is designated as metallization layer zero (MET0) or metallization layer one (MET1), and correspondingly, the first interconnect layer on the first metallization layer is designated as interconnect layer zero (VIA0) or interconnect layer one (VIA1). In this embodiment, again according to the numbering convention of the corresponding process technology nodes, on the back side of the device (not shown), the first buried metallization layer is designated as buried metallization layer zero (BMET0) or buried metallization layer one (BMET1), and correspondingly, the first buried interconnect layer under the first metallization layer is designated as interconnect layer zero (VIA0) or interconnect layer one (VIA1).

[0033] Generally, regarding the diagrams disclosed herein (unless otherwise stated), the following nomenclature for the front side of the device is adopted: the first metallization layer is assumed to be MET0; the first interconnect layer is assumed to be VIA0; the second metallization layer is assumed to be MET1; the second interconnect layer is assumed to be VIA1; and the third metallization layer is assumed to be MET2. The metallized section in layer MET0 is called the M0 section. The via structure in layer VIA0 is called the V0 structure. The metallized section in layer MET1 is called the M1 section. The via structure in layer VIA1 is called the V1 structure. The metallized section in layer MET2 is called the M2 section.

[0034] Generally, regarding the diagrams disclosed herein (unless otherwise stated) or similar cases, the following nomenclature for the back side of the device is adopted: the first embedded metallization layer is assumed to be BMET0; the first embedded interconnect layer is assumed to be BVIA0; the second embedded metallization layer is assumed to be BMET1; the second embedded interconnect layer is assumed to be BVIA1; and the third embedded metallization layer is assumed to be BMET2. The metallized sections in layer BMET0 are called embedded M0 (BM0) sections. The via structures in layer BVIA0 are called BV0 structures. The metallized sections in layer BMET1 are called embedded M1 (BM1) sections. The via structures in layer BVIA1 are called BV1 structures. The metallized sections in layer BMET2 are called embedded M2 (BM2) sections.

[0035] exist Figure 1A In the semiconductor device 100A, there are: waveguide 102; waveguide 104; heater 114; towers 116(1), 116(2), 116(3) and 116(4); and thermal protection wall 118.

[0036] exist Figure 1A In the middle, the offset profile line 1H-1H' corresponds to Figure 1H The cross-section, section line 3A-3A' corresponds to Figure 3A The cross-section, and the section line 3B-3B' corresponding to Figure 3B The cross-section. In some embodiments, heater 114 comprises a metallic material, such as a single metal or a combination of one or more metals, or another type of conductive material. In some embodiments, each of towers 116(1) to 116(4) comprises a metallic material, such as a single metal or a combination of one or more metals, or another type of conductive material. In some embodiments, at least one of towers 116(1) to 116(4) or other towers in this disclosure is a corresponding interconnect, and each interconnect comprises one or more conductive lines and one or more conductive vias.

[0037] Waveguide 102 is a bus waveguide that extends in a first direction, for example, parallel to the X-axis. In some embodiments, waveguide 102 is referred to as a straight waveguide. In some embodiments, light enters waveguide 102 at a first / left end and exits waveguide 102 at a second / right end opposite to the first / left end.

[0038] Waveguide 104 includes at least a first arc-shaped segment. Figure 1A In this context, waveguide 104 is assumed to be ring-shaped and is referred to as a ring waveguide. In some embodiments, waveguide 104 includes a first arcuate segment, but has a shape different from that of a ring.

[0039] The center of the ring waveguide 104 is offset from the centerline of the bus waveguide 102 in a second direction perpendicular to the first direction (e.g., parallel to the Y-axis). In some embodiments, the bus waveguide 102 and the ring waveguide 104 are described relative to each other in a Cartesian coordinate system with respect to a top view. The Cartesian coordinate system includes a third direction perpendicular to each of the first and second directions (e.g., parallel to the Z-axis).

[0040] In some embodiments, the ring waveguide 104 is also described in a spherical coordinate system relative to the top view. When applied to the ring waveguide 104, the spherical coordinate system has: an origin corresponding to the center of the ring waveguide 104; a fundamental plane corresponding to the plane defined by the X and Y axes; and a zenith axis extending from the origin and parallel to the Z-axis. In the spherical coordinate system, the ring waveguide 104 extends in the azimuth direction. In some embodiments where the waveguide 104 includes a first arcuate segment but has a shape different from a ring, in the spherical coordinate system, the first arcuate segment of the waveguide 104 extends in the azimuth direction.

[0041] In some embodiments, relative to a top view, heater 114 is described as having a shape resembling the uppercase letter omega in the Greek alphabet. The shape. In some embodiments, the heater 114 is described as having a shape similar to a badminton shuttlecock, relative to the top view. In some embodiments, the heater 114 is described as having a shape similar to an open cone, relative to the top view, including: an arcuate segment 115 (1) representing a nearly complete ring (ring portion); and substantially similar first and second pentagonal shapes (pentagonal portions, first portion 115 (2), second portion 115 (3)).

[0042] In some embodiments, relative to a top view, the ring portion 115 (1) is described as a split ring. The center of the ring portion 115 (1) is substantially coaxial with the center of the ring waveguide 104. Each of the pentagonal portions of the first portion 115 (2) and the second portion 115 (3) has a shape similar to a truncated right trapezoid (trapezoidal portion). For each trapezoidal portion 115 (2) and 115 (3), at corners that would otherwise have acute interior angles (acute angles), the acute angles are truncated to have an arcuate surface substantially concentric with the ring portion 115 (1). The trapezoidal portion 115 (2) is substantially mirror-symmetric with respect to a line of mirror symmetry corresponding to a radius extending from the center of the ring portion 115 (1). In some embodiments, the heater 114 has a different Figure 1A The shape of the heater 114 depicted in the image.

[0043] In some embodiments, heater 114 is also described in a spherical coordinate system relative to the top view. When applied to the ring 115(1), the spherical coordinate system has: an origin corresponding to the center of the ring 115(1); a basic plane corresponding to the plane defined by the X-axis and Y-axis; and a zenith axis extending from the origin and parallel to the Z-axis. In terms of the spherical coordinate system, the ring 115(1) extends in the azimuth direction. In some embodiments, the spherical coordinate system of heater 114 is substantially the same as that of ring waveguide 104.

[0044] The ring waveguide 104 further includes a heated target region 110; and an arc-shaped contact region 106 (see [link]). Figures 3A-3B ); PN junction area 107 (see Figures 3A-3B ); and the arc-shaped contact area 108 (see Figures 3A-3B In some embodiments, the target heating area 110 is described as having a shape similar to that of the heater 114. Figure 1A Assume that the target heating region 110 is substantially completely overlapped by the heater 114. In some embodiments, the degree to which the target heating region 110 is overlapped by the heater 114 is... Figure 1A The two are substantially different.

[0045] Figure 1A Assume that each of contact region 106, PN junction region 107, and contact region 108 is substantially concentric with the ring waveguide 104. In terms of a spherical coordinate system, each of contact region 106, PN junction region 107, and contact region 108 extends in the azimuth direction. Each of contact region 106, PN junction region 107, and contact region 108 does not overlap with the heating target region 110. Each of contact region 106, PN junction region 107, and contact region 108 is substantially not overlapped by the heater 114.

[0046] The PN junction region 107 lies between contact regions 106 and 108, relative to the radius extending from the center of the ring waveguide 104. Regarding the radius, and relative to each other, contact region 106 is closer to the center of the ring waveguide 104, while the PN junction region 107 is farther from the center of the ring waveguide 104. Regarding the radius, and relative to each other, the PN junction region 107 is closer to the center of the ring waveguide 104, while the contact region 108 is farther from the center of the ring waveguide 104. Regarding the radius, and relative to each other, contact region 106 is closer to the center of the ring waveguide 104, while the contact region 108 is farther from the center of the ring waveguide 104.

[0047] Relative to a second direction perpendicular to the first direction (e.g., parallel to the Y-axis), the ring waveguide 104 is close to but separate from the bus waveguide 102. A portion of the heated target region 110 and the corresponding region of the bus waveguide 102 together represent the near-field coupling region 112, in which light from the bus waveguide 102 is coupled into the ring waveguide 104 and / or light from the ring waveguide 104 is coupled into the bus waveguide 102. In some embodiments, the semiconductor device 100A is incorporated into a ring resonator. In some embodiments, the semiconductor device 100A is incorporated into a ring modulator (e.g., see...). Figure 2A Or 2C).

[0048] Tower 116 (1) is located on a portion of contact region 106 and is electrically coupled to contact region 106. Tower 116 (2) is located on a portion of contact region 108 and is electrically coupled to contact region 108. In some embodiments, there are multiple instances of tower 116 (1) on corresponding portions of contact region 106. In some embodiments, there are multiple instances of tower 116 (2) on corresponding portions of contact region 108. Tower 116 (3) is located on a portion of trapezoidal portion 115 (2) of heater 114 and is electrically coupled to trapezoidal portion 115 (2) of heater 114. Tower 116 (4) is located on a portion of trapezoidal portion 115 (3) of heater 114 and is electrically coupled to trapezoidal portion 115 (3) of heater 114.

[0049] exist Figure 1A In the top view, the thermal protection wall 118 has an arc shape. Figure 1A Assume that wall 118 is substantially concentric with ring waveguide 104. In some embodiments, wall 118 is described in a spherical coordinate system relative to a top view. When applied to wall 118, the spherical coordinate system has: an origin corresponding to the center of wall 118; a fundamental plane corresponding to the plane defined by the X and Y axes; and a zenith axis extending from the origin and parallel to the Z-axis. In terms of the spherical coordinate system, wall 118 extends in the azimuth direction. In some embodiments, the spherical coordinate system of wall 118 is substantially the same as that of ring waveguide 104.

[0050] With respect to the radius extending from the center of the ring waveguide 104, the wall 118 is located between the ring portion 115(1) of the heater 114 and the contact area 106. With respect to the radius, and relative to each other, the ring portion 115(1) of the heater 114 is closer to the center of the ring waveguide 104, while the wall 118 is further away from the center of the ring waveguide 104. With respect to the radius, and relative to each other, the wall 118 is closer to the center of the ring waveguide 104, while the contact area 106 is further away from the center of the ring waveguide 104. With respect to the radius extending from the center of the ring waveguide 104, and relative to each other, the contact area 106 is closer to the heater 114, while the contact area 108 is further away from the heater 114. With respect to the radius extending from the center of the ring waveguide 104, and relative to each other, the contact area 106 is closer to the wall 118, while the contact area 108 is further away from the wall 118.

[0051] Generally, selective heat transfer from heater 114 to the lower portion of ring waveguide 104 and / or the proximal portion of bus waveguide 102 promotes, for example, a change in the refractive index of ring waveguide 104 and / or bus waveguide 102; see; for example. Figure 1B Or similar. In some embodiments, each of semiconductor device 100A and semiconductor device 100H is described as an example of a single-wall type thermal protection architecture. In some embodiments, semiconductor device 100A and / or semiconductor device 100H includes one or more additional thermal protection walls in addition to wall 118.

[0052] Figure 1B The waveforms 132(1) and 132(2) are based on some embodiments.

[0053] Each of waveforms 132(1) and 132(2) represents the intensity / amplitude of transmitted light through a waveguide (e.g., a waveguide such as ring waveguide 104), in decibels (dB), as a function of wavelength λ (lambda). Waveform 132(1) represents the optical signal of a given waveguide (WG) at a relatively low temperature. Waveform 132(2) represents the optical signal of a given waveguide at a relatively high temperature. For waveforms 132(1) and 132(2)... Figure 1B The results show the insertion loss (IL) at resonance, the extinction ratio (ER) at resonance, and the full width at half maximum (FWHM). Figure 1BThe effects of relative temperature on waveforms 132(1) and 132(2) are shown. In some embodiments, insertion loss represents the amount of energy lost by the signal as it propagates along a given waveguide, i.e., energy attenuation directly related to the given waveguide length. In some embodiments, extinction ratio represents (i) the ratio of the power transmitted along a given waveguide when the transmitted signal represents bits with a logic value of one to (ii) the power transmitted along a given waveguide when the transmitted signal represents bits with a logic value of zero.

[0054] Let's return to the discussion Figure 1A Changing the refractive index of the ring waveguide 104 and / or bus waveguide 102 promotes, for example, control of light propagated in the ring waveguide 104 and / or bus waveguide 102, control of optical coupling in the near-field coupling region 112, or the like.

[0055] In some embodiments, the PN junction region 107 is described as exhibiting diode-like behavior. In some embodiments, the PN junction region 107 is represented as a diode in the schematic circuit; see [link to relevant documentation]. Figure 1C Or similar. In some embodiments, the PN junction region 107 is represented in the schematic circuit as parallel-coupled and polarity-aligned diodes, i.e., cathode coupled to cathode and anode coupled to anode; see also Figure 1C Or similar. In such embodiments, contact regions 106 and 108 are described as corresponding terminals of the diode, i.e., corresponding terminals of the PN junction region 107.

[0056] Figure 1C This is a schematic circuit diagram of circuit 100C according to some embodiments.

[0057] Circuit 100C includes Figure 1A An example of a circuit for a 100A semiconductor device. Besides... Figure 1A In addition to the components shown, circuit 100C also includes instances of driver 134 and diode 136. Figure 1CAssume the content of a ring modulator. Light is received at the input of the bus waveguide 102 (light input), and light is output at the output of the bus waveguide 102 (light output). Towers 116(1) and 116(2) respectively represent portions of the signal paths that pass through and include the diodes (i.e., the PN junction regions 107). Driver 134 receives a control signal CTRL, which is used to drive instances of diode 136 through the signal paths that respectively include towers 116(1) and 116(2). The control signal CTRL is a time-varying signal, in contrast to a substantially non-time-varying signal such as VDD or VSS. Since the control signal CTRL is a time-varying signal, in some embodiments, towers 116(1) and 116(2) are described as corresponding portions of a high-speed network. In some embodiments, towers 116(1) and 116(2) are described as corresponding portions of a high-speed network. In some embodiments, the high-speed signal has a frequency f1 in the range of (0 MHz) < f1 < (≈10 MHz), where MHz denotes megahertz.

[0058] Returning to Figure 1A the discussion, heat transfer from heater 114 also affects towers 116(1) and 116(2), negatively causing an increase in the resistance of towers 116(1) and 116(2) in terms of raising the temperature of towers 116(1) and 116(2), that is, reducing the conductivity of towers 116(1) and 116(2). The change in resistance of towers 116(1) and 116(2) caused by heat transfer is distance-dependent; for example, see Figure 1D and 1E or the like.

[0059] Figure 1D-1E is a corresponding temperature profile diagram according to some embodiments.

[0060] In the context of a metallization layer parallel to the X-Y Cartesian plane, such as the first metallization layer on heater 114, Figure 1D shows the temperature distribution relative to the position of heater 114 in the corresponding section of the metallization layer. Figure 1D illustrates that the change in resistance caused by heat transfer in tower 116(1) is distance-dependent.

[0061] Figure 1E shows the temperature distribution along the Z-axis within tower 116(1) relative to the position of heater 114. Figure 1E illustrates that the change in resistance caused by heat transfer in tower 116(1) is distance-dependent.

[0062] Returning to Figure 1AThe discussion of towers 116(1) and 116(2) and their resistance changes, for example, increase, which hinders the control of the diode, i.e., the PN junction region 107. Because contact region 106 is closer to heater 114 and contact region 108 is farther away from heater 114, towers 116(1) and 116(2) are correspondingly closer to and farther away from heater 114. Therefore, tower 116(1) is more susceptible to the negative effects of heat transfer from heater 114 than tower 116(2). Wall 118 is included in the semiconductor device 100A to protect towers 116(1) and 116(2) against heat transfer from heater 114. More specifically, wall 118 includes one or more materials and / or layers that protect towers 116(1) and 116(2) against heat transfer from heater 114. Examples of such materials are found in Figure 2A and 2C The discussion will take place within the content of this article.

[0063] In some embodiments, the tower is protected against heat transfer from the heater 114 by including a wall 118, which would otherwise cause a significant increase in the tower's temperature and consequently an increase in the tower's resistance, which would hinder the control of the PN junction 107, i.e., hinder the control of the diode, compared to another approach.

[0064] Figure 1F-1G These are corresponding waveform diagrams based on some embodiments.

[0065] For a given waveguide, such as the ring waveguide 104, Figure 1F Waveforms 132(3), 132(4), 132(5), and 132(6) plot the quality factor (FOM) S21 of a given waveguide in decibels (dB) as a function of frequency in gigahertz (GHz). Waveforms 132(3), 132(4), 132(5), and 132(6) represent the effect of FOM S21 on a given waveguide at different temperatures, namely at corresponding waveguide temperatures of 25°C, 100°C, 200°C, and 300°C. In some embodiments, FOM S21 represents the variation in intensity / amplitude of transmitted light between a single input port and a single output port. In some embodiments, FOM S21 represents the efficiency of signal transmission between a single input port and a single output port. Generally, waveforms 132(3), 132(4), 132(5), and 132(6) show the variation represented by FOM S21 decreasing with temperature.

[0066] For a given tower, such as tower 116(1). Figure 1GWaveforms 132(7), 132(8), 132(9), and 132(10) are included, which plot the resistance of a given tower in ohms (Ω) as a function of frequency in gigahertz (GHz). Waveforms 132(7), 132(8), 132(9), and 132(10) represent the effect of different temperatures on the resistance of a given tower, i.e., at the corresponding waveguide temperatures of 25°C, 100°C, 200°C, and 300°C. In general, waveforms 132(7), 132(8), 132(9), and 132(10) show the resistance increasing with temperature.

[0067] Figure 1H This is a cross-sectional view of a semiconductor device 100H according to some embodiments.

[0068] Semiconductor device 100H includes Figure 1A Example of a semiconductor device 100A. Figure 1H Corresponding to Figure 1A The offset profile line 1H-1H' in the middle.

[0069] Apart from Figure 1A In addition to the components shown, the semiconductor device 100H further includes: a semiconductor material 122, such as silicon (Si), in which at least a portion of the heater 114, bus waveguide 102, and ring waveguide 104 are formed; towers 116(1), 116(2), and 116(4); and a wall 118; an insulating material 124, such as silicon dioxide (SiO2), which surrounds / encapsulates at least a portion of towers 116(1), 116(2), and 116(4) and wall 118; a dummy semiconductor layer, such as a silicon (Si) layer 126; and a supporting semiconductor, such as a Si layer 128.

[0070] In some embodiments, the semiconductor material 122 and at least a portion of the components surrounded / encapsulated therein are described as a presentation layer. In some embodiments, the insulating material 124 and at least a portion of the components surrounded / encapsulated therein are described as a presentation layer.

[0071] Layer 124 and the dummy Si layer 126 are at the same level. Layers 124 and 126 are on layer 122. Supporting Si layer 128 is on layers 124 and 126.

[0072] Bus waveguide 102 includes a grating coupler 120. Supporting Si layer 128 includes a lens 130, such as a microlens. Light is input / received / at the grating coupler 120 from lens 130 and / or output / transmitted from the grating coupler 120 through lens 130.

[0073] In some embodiments, layer 124 represents a portion of a photonic integrated circuit (PIC) device (e.g., an optical interposer). In some embodiments, layer 124 represents a portion of an electronic integrated circuit (EIC) device (e.g., a semiconductor device). In some embodiments, semiconductor device 100H represents a portion of an optical package (e.g., a compact universal photonic engine (COUPE)). In some embodiments, other semiconductor devices disclosed herein correspondingly represent portions of optical packages (e.g., COUPEs).

[0074] Figure 2A This is a layout diagram of a semiconductor device 200A according to some embodiments. Figure 2B This is a cross-sectional view of a semiconductor device 200B according to some embodiments.

[0075] Figure 2A The semiconductor device 200A is similar to Figure 1A Semiconductor device 100A. For the sake of simplicity, the discussion will focus on the differences rather than similarities between semiconductor device 200A and semiconductor device 100A. Figure 2B The semiconductor device 200B is similar to Figure 1H Semiconductor device 100H. For the sake of simplicity, the discussion will focus on the differences rather than similarities between semiconductor device 200B and semiconductor device 100H.

[0076] Semiconductor device 200A is Figure 1A The example is semiconductor device 100A. Semiconductor device 200B is... Figure 2A The semiconductor device 200A is an example, and therefore also Figure 1H An example of a semiconductor device 100H. Figure 2B Corresponding to Figure 2A Section line 2B-2B' in the middle. Figure 2A In the diagram, profile line 2B-2B' is obtained along a line parallel to the diameter of the ring waveguide 104, that is, the line intersecting the center of the ring waveguide 104. Figure 2A In the middle, not only does the section line 2B-2B' correspond to Figure 2B The cross-section, and the section line 3A-3A' corresponds to Figure 3A The cross-section, section line 3B-3B' corresponds to Figure 3B The cross-section.

[0077] In some embodiments, wall 218(1) is Figure 1A An example of wall 118. In some embodiments, wall 218 (2) is Figure 1A Example of Wall 118.

[0078] Apart from Figure 1A In addition to the components displayed in the middle, Figure 2A The semiconductor device 200A further includes: a thermal protection wall 218 (1); a thermal protection wall 218 (2); and towers 116 (5), 116 (6), 116 (7), 116 (8), 116 (9) and 116 (10).

[0079] Apart from Figure 2B and Figure 1H In addition to the components displayed in the middle, Figure 2B The semiconductor device 200B further includes an example of a barrier layer 142.

[0080] In some embodiments, the unit is micrometer (μm), and relative to from Figure 2A The content includes the radius of the ring waveguide 104 extending from the center and relative to... Figure 2B The X-axis in the content: wall 218 (1) has a size / distance D1 with a range of (≈0.5μm) ≤ D1 ≤ (≈2.0μm); wall 218 (2) has a size / distance D2 with a range of (≈0.5μm) ≤ D2 ≤ (≈2.0μm); the gap between the ring 115 (1) of heater 114 and wall 218 (1) has a size / distance D3 with a range of (≈0.5μm) ≤ D3 ≤ (≈2.0μm); the gap between wall 218 (1) and wall 218 (2) has a size / distance D4 with a range of (≈0.5μm) ≤ D4 ≤ (≈2.0μm); and the gap between wall 218 (2) and tower 116 (1) has a size / distance D5 with a range of (≈0.5μm) ≤ D5 ≤ (≈2.0μm).

[0081] For example, in some embodiments, if the size / distance D1 of wall 218(1) is equal to or greater than about 0.5 μm such that (≈0.5 μm) ≤ size / distance D1, then the thermal insulation contribution provided by wall 218(1) is sufficient to protect the tower (e.g., 116(1), 116(8), 116(9), and 116(10)) against the amount of heat transfer from heater 114 that would otherwise significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significant increase in the resistance of the tower would impede the control of PN junction 107. In some embodiments, if the size / distance D1 of wall 218(1) is less than about 0.5 μm such that size / distance D1 < (≈0.5 μm), then the thermal insulation contribution provided by wall 218(1) will not be sufficient to protect the tower against the amount of heat transfer from heater 114 that would significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significant increase in the resistance of the tower would impede the control of PN junction 107.

[0082] For example, in some embodiments, if the size / distance D2 of wall 218(2) is equal to or greater than about 0.5 μm such that (≈0.5 μm) ≤ size / distance D2, then the thermal insulation contribution provided by wall 218(2) is sufficient to protect the tower (e.g., 116(1), 116(8), 116(9), and 116(10)) against the amount of heat transfer from heater 114 that would otherwise significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significant increase in the resistance of the tower would impede the control of PN junction 107. In some embodiments, if the size / distance D2 of wall 218(2) is less than about 0.5 μm such that size / distance D1 < (≈0.5 μm), then the thermal insulation contribution provided by wall 218(2) will not be sufficient to protect the tower against the amount of heat transfer from heater 114 that would significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significant increase in the resistance of the tower would impede the control of PN junction 107.

[0083] For example, in some embodiments, if the size / distance D3 of the gap between heater 114 and wall 218(1) is equal to or greater than about 0.5 μm such that (≈0.5 μm) ≤ size / distance D3, then the thermal insulation contribution provided by the size / distance of the gap between heater 114 and wall 218(1) is sufficient to protect the tower (e.g., 116(1), 116(8), 116(9) and 116(10)) against the amount of heat transfer from heater 114 that would otherwise significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significant increase in the resistance of the tower would impede the control of PN junction 107. In some embodiments, if the size / distance D3 of the gap between heater 114 and wall 218 (1) is less than about 0.5 μm such that the size / distance D3 < (≈0.5 μm), the thermal insulation contribution provided by the size / distance of the gap between heater 114 and wall 218 (1) will be insufficient to protect the tower against the amount of heat transfer from heater 114 that would significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, where the significant increase in the resistance of the tower would hinder the control of PN junction 107.

[0084] For example, in some embodiments, if the size / distance D4 of the gap between walls 218(1) and 218(2) is equal to or greater than about 0.5 μm such that (≈0.5 μm) ≤ size / distance D4, then the thermal insulation contribution provided by the size / distance of the gap between walls 218(1) and 218(2) is sufficient to protect the tower (e.g., 116(1), 116(8), 116(9) and 116(10)) against the amount of heat transfer from heater 114 that would otherwise significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significant increase in the resistance of the tower would impede the control of PN junction 107. In some embodiments, if the size / distance D4 of the gap between wall 218(1) and wall 218(2) is less than about 0.5 μm such that the size / distance D4 < (≈0.5 μm), then the thermal insulation contribution provided by the size / distance of the gap between wall 218(1) and wall 218(2) will be insufficient to protect the tower against the amount of heat transfer from heater 114, which will significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significant increase in the resistance of the tower will hinder the control of PN junction 107.

[0085] For example, in some embodiments, if the size / distance D5 of the gap between the barrier layer 142 on the wall 218 (2) and the corresponding towers 116 (1) and 116 (8) is equal to or greater than about 0.5 μm such that (≈0.5 μm) ≤ size / distance D5, then the thermal insulation contribution provided by the size / distance of the gap between the wall 218 (2) and the corresponding towers 116 (1) and 116 (8) is sufficient to protect the towers (e.g., 116 (1), 116 (8), 116 (9) and 116 (10)) against the amount of heat transfer from the heater 114 that would otherwise significantly increase the temperature of the towers and correspondingly significantly increase the resistance of the towers, wherein the significant increase in the resistance of the towers would impede the control of the PN junction 107. In some embodiments, if the size / distance D5 of the gap between the wall 218 (2) and the barrier layer 142 on the corresponding towers 116 (1) and 116 (8) is less than about 0.5 μm such that the size / distance D5 < (≈0.5 μm), then the thermal insulation contribution provided by the size / distance of the gap between the wall 218 (2) and the barrier layer 142 on the corresponding towers 116 (1) and 116 (8) will be insufficient to protect the tower against the amount of heat transfer from the heater 114, which will significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significant increase in the resistance of the tower will hinder the control of the PN junction 107.

[0086] In some embodiments, the unit is micrometer (μm), and relative to Figure 2BZ-axis in the content: Tower 116 (9) and 116 (1) each have a size / height H1 within the range (≈0.1μm) ≤ size / height H1 ≤ (≈1.45μm); and Tower 116 (1), Tower 116 (8), Wall 218 (1) and Wall 218 (2) each have a size / height H1 within the range (≈0.1μm) ≤ size / height H1 ≤ (≈1.45μm).

[0087] Walls 218(1) and 218(2) are each included in the semiconductor device 200A to protect towers 116(1), 116(8), 116(9), and 116(10) from heat transfer from heater 114. More specifically, wall 218(1) includes one or more materials and / or layers to protect towers 116(1), 116(8), 116(9), and 116(10) from heat transfer from heater 114. Wall 218(2) includes one or more materials and / or layers to protect towers 116(1), 116(8), 116(9), and 116(10) from heat transfer from heater 114.

[0088] In some embodiments, one or more materials and / or layers of wall 218 (1) include one or more materials listed in Table 1 below.

[0089]

[0090] In some embodiments, the unit expressed in W / m•K, such as in Tables 1 and 2 (the latter below), is watts per meter-kelvin.

[0091] In combination, one or more materials and / or layers of wall 218 (1) exhibit a first thermal protection mode, thereby protecting towers 116 (1), 116 (8), 116 (9), and 116 (10) against heat transfer from heater 114. In some embodiments where one or more materials and / or layers of wall 218 (1) correspond to a solid, the first mode of thermal protection provided by wall 218 (1) is primarily conduction. In some embodiments where one or more materials and / or layers of wall 218 (1) correspond to a fluid (e.g., air in an air gap), the first mode of thermal protection provided by wall 218 (1) is primarily convection. In the first mode, wall 218 (1) exhibits low thermal conductivity (high thermal insulation). In some embodiments, having low thermal conductivity is described as thermal insulation. Figure 2A-2B In the legend, wall 218(1) is Th-Ins-W. In some embodiments, the character string Th-Ins-W is intended to be a phrase thermally insulating wall.

[0092] In some embodiments, one or more materials and / or layers of wall 218 (2) include one or more materials listed in Table 2 below.

[0093]

[0094] In combination, one or more materials and / or layers of wall 218 (2) exhibit a second thermal protection mode, thereby protecting towers 116 (1), 116 (8), 116 (9), and 116 (10) against heat transfer from heater 114. In some embodiments, the second mode of thermal protection provided by wall 218 (2) is primarily radiation. In the second mode, wall 218 (2) has high reflectivity (high infrared reflectivity) relative to the infrared band of the electromagnetic spectrum. Figure 2A-2B In the legend, wall 218(2) is Th-Ref-W. In some embodiments, the character string Th-Ref-W is intended to represent a thermally reflective wall in the infrared band of the electromagnetic spectrum.

[0095] Generally, the materials included in Table 2 have medium to high thermal conductivity, i.e., provide medium to low thermal insulation. However, the materials included in Table 2 also have medium to high thermal reflectivity relative to the infrared band of the electromagnetic spectrum, i.e., high infrared reflectivity, as shown in Table 3 below.

[0096]

[0097] In some embodiments, the first thermal protection mode of wall 218 (1) is different from the second thermal protection mode of wall 218 (2). In some embodiments, the first thermal protection mode of wall 218 (1) is not substantially different from the second thermal protection mode of wall 218 (2).

[0098] In some embodiments, in combination, one or more materials and / or layers of wall 218 (1) have a thermal conductivity k in the range of less than or equal to about 35 W / m•K, such that k ≤ (≈35 W / m•K). For example, in some embodiments, if one or more materials and / or layers of wall 218 (1) have a thermal conductivity k in the range of less than or equal to about 35 W / m•K, such that k ≤ (≈35 W / m•K), then the thermal insulation contribution provided by wall 218 (1) is sufficient to protect the tower (e.g., 116 (1), 116 (8), 116 (9) and 116 (10)) against the amount of heat transfer from heater 114 that would otherwise significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, where the significantly increased resistance of the tower hinders the control of PN junction 107. In some embodiments, if one or more materials and / or layers of wall 218 (1) have a thermal conductivity k greater than about 35 W / m•K, such that (≈35 W / m•K) ≤ k, then the thermal insulation contribution provided by wall 218 (1) will be insufficient to protect the tower against the amount of heat transfer from heater 114, which will significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significantly increased resistance of the tower hinders the control of PN junction 107.

[0099] In some embodiments, the combination of materials and / or layers of wall 218(1) has a thermal conductivity k in the range of less than or equal to about 1.4 W / m•K, such that k ≤ (≈1.4 W / m•K). In some embodiments, the combination of materials and / or layers of wall 218(1) has a thermal conductivity k in the range of less than or equal to 0.3 W / m•K, such that k ≤ (≈0.3 W / m•K).

[0100] In some embodiments, in combination, one or more materials and / or layers of wall 218 (2) have a thermal conductivity k equal to or greater than about 21 W / m•K, such that (≈21 W / m•K) ≤ k. For example, in some embodiments, if one or more materials and / or layers of wall 218 (2) have a thermal conductivity k equal to or greater than about 21 W / m•K, such that (≈21 W / m•K) ≤ k, then the infrared reflection provided by wall 218 (2) is sufficient to protect the tower (e.g., 116 (1), 116 (8), 116 (9) and 116 (10)) against the amount of heat transfer from heater 114 that would otherwise significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, where the significantly increased resistance of the tower hinders the control of PN junction 107. In some embodiments, if one or more materials and / or layers of wall 218 (2) have a thermal conductivity k in the range of less than about 21 W / m•K, such that (≈21 W / m•K) ≤ k, then the infrared reflection provided by wall 218 (2) will be insufficient to protect the tower against the amount of heat transfer from heater 114, which will significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significantly increased resistance of the tower hinders the control of PN junction 107.

[0101] In some embodiments, in combination, one or more materials and / or layers of wall 218 (2) have a thermal conductivity k in the range of about 175 W / m•K, such that (≈175 W / m•K) ≤ k.

[0102] In some embodiments, semiconductor device 200A and semiconductor device 200B are each described as examples of a double-walled thermal protection configuration. In some embodiments, semiconductor device 200A and / or semiconductor device 200B include one or more additional thermal protection walls in addition to walls 218(1) and 218(2).

[0103] Figure 2C This is a layout diagram of a semiconductor device 200C according to some embodiments. Figure 2D This is a cross-sectional view of a semiconductor device 200D according to some embodiments.

[0104] Figure 2C The semiconductor device 200C is similar to Figure 2A Semiconductor device 200A. For the sake of brevity, the discussion will focus on the differences rather than similarities between semiconductor device 200C and semiconductor device 200A. Figure 2D The semiconductor device 200D is similar to Figure 2B Semiconductor device 200B. For the sake of brevity, the discussion will focus on the differences rather than similarities between semiconductor device 200D and semiconductor device 200B.

[0105] Semiconductor device 200C is Figure 1A The example is semiconductor device 100A. Semiconductor device 200D is... Figure 2C The semiconductor device 200C is an example, and therefore also Figure 1H An example of a semiconductor device 100H. Figure 2D Corresponding to Figure 2C The section line 2D-2D' in the middle. Figure 2C In the diagram, the profile line 2D-2D' is obtained along a line parallel to the diameter of the ring waveguide 104, that is, the line intersecting the center of the ring waveguide 104. Figure 2C In the middle, not only does the section line 2D-2D' correspond to Figure 2D The cross-section, and the section line 3A-3A' corresponds to Figure 3A The cross-section, section line 3B-3B' corresponds to Figure 3B The cross-section.

[0106] Semiconductor device 200C in Figure 2C This includes thermal protection wall 218 (3), rather than Figure 2A The semiconductor device 200A shown has walls 218(1) and 218(2). In some embodiments, wall 218(3) is Figure 1A Example of Wall 118.

[0107] In some embodiments, the unit is micrometer (μm), relative to from Figure 2C The content includes the radius of the ring waveguide 104 extending from the center and relative to... Figure 2D In the X-axis of the content, wall 218 (3) has a dimension / distance D6 within the range (≈1.5μm) ≤ dimension / distance D6 ≤ (≈6.0μm). In some embodiments, the dimension / distance D6 of wall 218 (3) is greater than the dimension / distance D1 of wall 218 (1), such that dimension / distance D1 < dimension / distance D6. In some embodiments, the dimension / distance D6 of wall 218 (3) is greater than the dimension / distance D2 of wall 218 (2), such that dimension / distance D2 < dimension / distance D6.

[0108] Wall 218 (3) is included in semiconductor device 200C to protect towers 116 (1), 116 (8), 116 (9) and 116 (10) from heat transfer from heater 114. More specifically, wall 218 (3) includes one or more materials and / or layers to protect towers 116 (1), 116 (8), 116 (9) and 116 (10) from heat transfer from heater 114.

[0109] In some embodiments, one or more materials and / or layers of wall 218 (3) include one or more materials listed in Table 4 below.

[0110]

[0111] In combination, one or more materials and / or layers of wall 218 (3) exhibit a third mode of thermal protection, thereby protecting towers 116 (1), 116 (8), 116 (9), and 116 (10) from heat transfer from heater 114. In some embodiments, the third mode of thermal protection provided by wall 218 (3) is at least a combination of conduction and radiation. Regarding thermal conductivity, each material included in Table 4 accordingly has: relatively low thermal conductivity, i.e., thermal conductivity comparable to alumina (Al2O3) or silicon nitride (Si3N4) in Table 1; and significant IR thermal reflectivity relative to the infrared band of the electromagnetic spectrum, i.e., significant IR reflectivity. Figure 2C-2D In the legend, wall 218 (3) is Th-2-in-1. In some embodiments, the string Th-2-in-1 is intended to represent the phrase thermal two-in-one. That is, the string Th-2-in-1 is intended to represent a third mode of thermal protection for wall 218 (3) that is a combination of the modes of primary thermal protection for walls 218 (1) and 218 (2).

[0112] In some embodiments, in combination, one or more materials and / or layers of wall 218 (3) have a thermal conductivity k in the range such that (≈21 W / m•K) ≤ k ≤ (≈29 W / m•K). For example, in some embodiments, if one or more materials and / or layers of wall 218 (3) have a thermal conductivity k in the range of less than or equal to about 29 W / m•K such that k ≤ (≈21 W / m•K), then the thermal insulation contribution provided by wall 218 (3) is sufficient to protect the tower (e.g., 116 (1), 116 (8), 116 (9) and 116 (10)) from heat transfer from heater 114 that would otherwise significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, where the significant increase in the resistance of the tower would hinder the control of PN junction 107. In some embodiments, if one or more materials and / or layers of wall 218 (3) have a thermal conductivity k greater than about 29 W / m•K, such that (≈29 W / m•K) ≤ k, then the thermal insulation contribution provided by wall 218 (3) will be insufficient to protect the tower from the amount of heat transferred from heater 114, which will significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significant increase in the resistance of the tower will hinder the control of PN junction 107.

[0113] For example, in some embodiments, if the size / distance D6 of wall 218(3) is equal to or greater than about 1.5 μm, such that (≈1.5 μm) ≤ size / distance D6, then the thermal insulation contribution provided by wall 218(3) is sufficient to protect the towers (e.g., 116(1), 116(8), 116(9), and 116(10)) from heat transfer from heater 114 that would otherwise significantly increase the temperature of the towers and correspondingly significantly increase the resistance of the towers, where the significant increase in the resistance of the towers would impede the control of PN junction 107. In some embodiments, if the size / distance D6 of wall 218(3) is less than about 1.5 μm, such that size / distance D6 < (≈1.5 μm), then the thermal insulation contribution provided by wall 218(3) will not be sufficient to protect the towers from heat transfer from heater 114 that would significantly increase the temperature of the towers and correspondingly significantly increase the resistance of the towers, where the significant increase in the resistance of the towers would impede the control of PN junction 107.

[0114] For example, in some embodiments, if the size / distance D3 of the gap between heater 114 and wall 218 (3) is equal to or greater than about 0.5 μm, such that (≈0.5 μm) ≤ size / distance D3, then the thermal insulation contribution provided by the size / distance of the gap between heater 114 and wall 218 (3) is sufficient to protect the tower (e.g., 116 (1), 116 (8), 116 (9) and 116 (10)) from the amount of heat transferred from heater 114 that would otherwise significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, where the significant increase in the resistance of the tower would impede the control of PN junction 107. In some embodiments, if the size / distance D3 of the gap between heater 114 and wall 218 (3) is less than about 0.5 μm, such that the size / distance D3 < (≈0.5 μm), then the thermal insulation contribution provided by the size / distance of the gap between heater 114 and wall 218 (3) will be insufficient to protect the tower from the amount of heat transferred from heater 114, which will significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significant increase in the resistance of the tower will hinder the control of PN junction 107.

[0115] For example, in some embodiments, if the size / distance D5 of the gap between the barrier layer 142 on the wall 218 (3) and the corresponding towers 116 (1) and 116 (8) is equal to or greater than about 0.5 μm, such that (≈0.5 μm) ≤ size / distance D5, then the thermal insulation contribution provided by the size / distance of the gap between the wall 218 (3) and the corresponding towers 116 (1) and 116 (8) is sufficient to protect the towers (e.g., 116 (1), 116 (8), 116 (9) and 116 (10)) from heat transfer from the heater 114, which would otherwise significantly increase the temperature of the towers and correspondingly significantly increase the resistance of the towers, where the significant increase in the resistance of the towers would hinder the control of the PN junction 107. In some embodiments, if the size / distance D5 of the gap between the wall 218 (3) and the barrier layer 142 on the corresponding towers 116 (1) and 116 (8) is less than about 0.5 μm, such that the size / distance D5 < (≈0.5 μm), then the thermal insulation contribution provided by the size / distance of the gap between the wall 218 (3) and the barrier layer 142 on the corresponding towers 116 (1) and 116 (8) will be insufficient to protect the tower from the amount of heat transferred from the heater 114, which will significantly increase the temperature of the tower and correspondingly significantly increase the resistance of the tower, wherein the significant increase in the resistance of the tower will hinder the control of the PN junction 107.

[0116] In some embodiments, each of semiconductor device 200C and semiconductor device 200D is described as an example of a single-wall type thermal protection architecture. In some embodiments, semiconductor device 200C and / or semiconductor device 200D include one or more additional thermal protection walls in addition to wall 218 (3).

[0117] Figure 2E-2F The diagrams are based on the corresponding waveforms 232(1), 232(2), 232(3) and 232(4) of some embodiments.

[0118] Figure 2E In waveforms 232(1) and 232(2), each represents a waveguide (e.g., a waveguide such as ring waveguide 104) in a manner such as Figure 2A The normalized transmitted light intensity / amplitude in the semiconductor device 200A is a function of wavelength λ (lambda). Figure 2F In waveforms 232(3) and 232(4), each represents a waveguide (e.g., a waveguide such as ring waveguide 104) in a manner such as Figure 2C The normalized transmitted light intensity / amplitude in the semiconductor device 200C is a function of wavelength λ (lambda).

[0119] Figure 2E Waveform 232(1) and Figure 2FEach of the waveforms 232 (3) represents the optical signal of a given waveguide (WG) (e.g., ring waveguide 104) at a relatively low temperature. Figure 2E Waveform 232(2) and Figure 2F Each of the waveforms 234(4) represents the optical signal of a given waveguide at a relatively high temperature. Figure 2E-2F Each of these is displayed accordingly: insertion loss (IL) at resonance; extinction ratio (ER) at resonance; and full width at half maximum (FWHM). Figure 1B Among other things, the different effects of relative temperature on waveforms 232(1), 232(2), 232(3) and 232(4) are shown.

[0120] In some embodiments, a larger extinction ratio is considered advantageous because the ability to distinguish bits with logic 1 from bits with logic 0 increases with increasing extinction ratio. In such embodiments, Figure 2E and Figure 2F The comparison between them shows things like Figure 2A The semiconductor device 200A is more advanced than semiconductor devices such as... Figure 2C The semiconductor device 200C exhibits a large extinction ratio.

[0121] In terms of preventing heat transfer from heater 114, generally, semiconductor devices with at least single-wall type (e.g., walls 118 and 218 (3)) thermal protection, such as Figure 1A Semiconductor device 100A, Figure 2C 200°C or similar provides a greater degree of thermal protection compared to the other method.

[0122] In terms of preventing heat transfer from heater 114, in some embodiments, a semiconductor device having double-wall type (e.g., walls 218(1) and 218(2)) thermal protection, such as Figure 2A The semiconductor device 200A or similar provides a greater degree of thermal protection compared to another method.

[0123] Figure 2G This is a block diagram of a semiconductor device 200G according to some embodiments.

[0124] The semiconductor device 200G includes: bus waveguide 202; heater 214; towers 116 (11), 116 (12), 116 (13), 116 (14), 116 (15) and 116 (16); thermal protection walls 218 (4) and 218 (5); and thermal protection walls 218 (6) and 218 (7).

[0125] exist Figure 2G In the middle, section line 3A-3A' corresponds to Figure 3AThe cross-section, section line 3B-3B' corresponds to Figure 3B The cross-section. In some embodiments, heater 214 comprises a metallic material, such as a single metal or a combination of one or more metals, or another type of conductive material. In some embodiments, each of towers 116(11)-116(16) comprises a metallic material, such as a single metal or a combination of one or more metals, or another type of conductive material.

[0126] Bus waveguide 202 is a bus waveguide extending in a first direction, for example, parallel to the X-axis. In some embodiments, light enters the bus waveguide 202 at a first / left end and exits the bus waveguide 202 at a second / right end.

[0127] In some embodiments, the heater 214 is described as having a rectangular shape relative to a top view. In some embodiments, the heater 214 is described as having a rectangular shape, i.e., a square. In some embodiments, the heater 214 has a shape other than a rectangle.

[0128] Bus waveguide 202 further includes a heated target region 211; contact region 206 (see Figure 2G ); PN junction area 207 (see Figure 2G ); and contact area 208 (see Figure 2G In some embodiments, the heating target area 211 is described as having a shape similar to that of the heater 214. Figure 2G Assume that the target heating area 211 is substantially completely overlapped by the heater 214. In some embodiments, the degree to which the target heating area 211 is overlapped by the heater 214 is... Figure 2G The two are substantially different.

[0129] Compared to the top view, Figure 2G Assume that contact region 206, PN junction region 207, and contact region 208 are adjacent, substantially parallel rectangular shapes within bus waveguide 202. Relative to the Y-axis, PN junction region 207 is located between contact regions 206 and 208. In some embodiments, relative to the Y-axis, contact regions 206 and 208 are described as corresponding to edge or peripheral regions of bus waveguide 202, and PN junction region 207 is described as the central region of bus waveguide 202.

[0130] Each of towers 116(11) and 116(15) is located on a portion of contact region 206 and is electrically coupled to contact region 206. Each of towers 116(12) and 116(16) is located on a portion of contact region 208 and is electrically coupled to contact region 208. In some embodiments, the number of towers located on corresponding portions of contact region 206 and electrically coupled to contact region 206 is greater or less. In some embodiments, the number of towers located on corresponding portions of contact region 208 and electrically coupled to contact region 208 is greater or less. Tower 116(13) is located on a portion of heater 214 and is electrically coupled to heater 214. Tower 116(14) is located on a portion of heater 214 and is electrically coupled to heater 214.

[0131] exist Figure 2G In the top view, each of walls 218(4)-218(6) is described as having a rectangular shape. In some embodiments, each of walls 218(4)-218(6) is described as having a rectangular shape, i.e., a square. In some embodiments, each of walls 218(4)-218(6) has a shape other than a rectangle.

[0132] Relative to the X-axis: walls 218(4) and 218(6) are located between heater 214 and each of towers 116(11) and 116(12); walls 218(5) and 218(7) are located between heater 214 and each of towers 116(15) and 116(16); wall 218(4) is located between heater 214 and wall 218(6); wall 218(5) is located between heater 214 and wall 218(7); wall 218(6) is located between wall 218(4) and each of towers 116(11) and 116(12); and wall 218(7) is located between wall 218(5) and each of towers 116(15) and 116(16).

[0133] Relative to the X-axis: wall 218 (4) is closer to heater 214 relative to wall 218 (6); wall 218 (5) is closer to heater 214 relative to wall 218 (7); wall 218 (6) is farther from heater 214 relative to wall 218 (4); and wall 218 (7) is farther from heater 214 relative to wall 218 (5).

[0134] Generally, selective heat transfer from heater 214 to the portion below bus waveguide 202 facilitates, for example, a change in the refractive index of bus waveguide 202. Changing the refractive index of bus waveguide 202 facilitates, for example, control of the light propagating in bus waveguide 202, such as controlling the phase shift of the light propagating in bus waveguide 202. In some embodiments, semiconductor device 200G is incorporated into a thermal phase shifter.

[0135] In some embodiments, the semiconductor device 200G is described as an example of a double-wall type thermal protection architecture. In some embodiments, the semiconductor device 200G includes one or more additional thermal protection walls in addition to walls 218(4)-218(7).

[0136] In some embodiments, the PN junction region 207 is described as exhibiting diode-like behavior. In some embodiments, the PN junction region 207 is represented as a diode in a circuit diagram; see [link to circuit diagram]. Figure 2I Or similar. In some embodiments, the PN junction region 207 is represented in the circuit diagram as parallel-coupled and polarity-aligned diodes, i.e., cathode-to-cathode and anode-to-anode; see also Figure 2I Or similar. In such embodiments, contact regions 206 and 208 are described as corresponding terminals of the diode, i.e., corresponding terminals of the PN junction region 207. The discussion will now jump to Figure 2I .

[0137] Figure 2I This is a circuit diagram of circuit 200I according to some embodiments.

[0138] Circuit 200I includes Figure 2G Circuit examples for 200G semiconductor devices. Besides... Figure 2G In addition to the components shown, circuit 200I also includes driver 234 and diodes 236(1) and 236(2). Figure 2IAssume the contents of the thermal phase shifter. Light is received at the input of bus waveguide 202 (optical input) and output at the output of bus waveguide 202 (optical output). Towers 116 (11) and 116 (12) respectively represent the portion of the signal path through and including diode 236 (1), i.e., the first portion of PN junction region 207. Towers 116 (15) and 116 (16) respectively represent the portion of the signal path through and including diode 236 (2), i.e., the second portion of PN junction region 207. Driver 234 receives a control signal CTRL for driving diodes 236 (1) and 236 (2) through the signal path correspondingly including towers 116 (11)-116 (12) and 116 (5)-116 (6). The control signal CTRL is a time-varying signal, in contrast to substantially time-invariant signals such as VDD or VSS. Since the control signal CTRL is a time-varying signal, in some embodiments, towers 116(11)-116(12) and 116(5)-116(6) are described as corresponding portions of a high-speed network (HSN). In some embodiments, towers 116(11)-116(12) and 116(5)-116(6) are described as corresponding portions of a high-speed network. In some embodiments, the control signal CTRL has a frequency f2 in the range of (≈200 MHz) ≤ f2 ≤ (≈400 MHz), where MHz represents megahertz.

[0139] Back Figure 2G The discussion also revealed that heat transfer from heater 214 affects towers 116(11)-116(12) and 116(5)-116(6), negatively increasing the temperature of towers 116(11)-116(12) and 116(5)-116(6), thus negatively increasing the resistance of towers 116(11)-116(12) and 116(5)-116(6), i.e., reducing the conductivity of towers 116(11)-116(12) and 116(5)-116(6). The changes in resistance of towers 116(11)-116(12) and 116(5)-116(6) due to heat transfer are distance-dependent.

[0140] Changes in the resistance of towers 116(11)-116(12) and 116(5)-116(6), such as an increase, impede control of the diode, i.e., the PN junction region 207. Walls 218(4)-218(7) included in the semiconductor device 200G protect towers 116(11)-116(12) and 116(5)-116(6) from heat transfer from heater 214. More specifically, walls 218(4)-218(7) correspondingly include one or more materials and / or layers to protect towers 116(11)-116(12) and 116(5)-116(6) from heat transfer from heater 214.

[0141] exist Figure 2G In the middle, wall 218(4)-218(5) is Figure 2A The counterpart of wall 218(1). Therefore, in some embodiments, the first mode of thermal protection exhibited by each of walls 218(4)-218(5) is a low thermal conductivity mode. Figure 2A The material example of wall 218(1) is used for Figure 2G Material examples of wall 218(4)-218(5). Figure 2A The thermal conductivity k-value of wall 218(1) is an example. Figure 2G Examples of thermal conductivity k values ​​shown in wall 218(4)-218(5).

[0142] exist Figure 2G In the middle, wall 218(6)-218(7) is Figure 2A The counterpart of wall 218(2). Therefore, in some embodiments, the second mode of thermal protection exhibited by each of walls 218(6)-218(7) is a high reflectivity mode relative to the infrared band of the electromagnetic spectrum. Figure 2A The material example of wall 218(2) is used for Figure 2G Material examples of wall 218(6)-218(7). Figure 2A The thermal conductivity k-value of wall 218(2) is an example. Figure 2G Examples of thermal conductivity k values ​​shown in wall 218(6)-218(7).

[0143] In some embodiments, the semiconductor device 200G is described as an example of a double-walled thermal protection configuration. In some embodiments, the semiconductor device 200G includes one or more additional thermal protection walls in addition to walls 218(4)-218(6).

[0144] Figure 2H This is a layout diagram of a semiconductor device 200H according to some embodiments.

[0145] exist Figure 2H In the middle, section line 3A-3A' corresponds to Figure 3A The cross-section, section line 3B-3B' corresponds to Figure 3B The cross-section.

[0146] Figure 2H Semiconductor device 200H and Figure 2G The semiconductor device 200H is similar to semiconductor device 200G. For the sake of brevity, the discussion will focus on the differences rather than the similarities between semiconductor device 200H and semiconductor device 200G. Semiconductor device 200H is... Figure 2H This includes thermal protection walls 218(8)-218(9), rather than Figure 2GThe semiconductor device 200G shown has walls 218(4)-218(7).

[0147] Relative to the X-axis: wall 218 (8) is located between heater 214 and each of towers 116 (11) and 116 (12); wall 218 (9) is located between heater 214 and each of towers 116 (15) and 116 (16).

[0148] exist Figure 2H In the middle, wall 218(8)-218(9) is Figure 2C The counterpart of wall 218(3). Therefore, in some embodiments, the third mode of thermal protection exhibited by each of walls 218(8)-218(9) is a combination of lower thermal conductivity and higher reflectivity relative to the infrared band of the electromagnetic spectrum. Figure 2C The material example of wall 218(3) is used for Figure 2H Material examples of wall 218(8)-218(9). Figure 2C The thermal conductivity k-value of wall 218 (3) is an example. Figure 2H Examples of thermal conductivity k values ​​shown in wall 218(8)-218(9).

[0149] In some embodiments, the semiconductor device 200H is described as an example of a single-wall thermal protection architecture. In some embodiments, the semiconductor device 200H includes one or more additional thermal protection walls in addition to walls 218(8)-218(9).

[0150] Figure 3A This is a cross-sectional view of a semiconductor device 300A according to some embodiments.

[0151] Semiconductor device 300A corresponds to Figure 1A , 2A Section lines 3A-3A' for each of 2C and 2G-2H. Figure 1B , 2A For each of 2C, the profile lines 3A-3A' are obtained along a line parallel to the radial axis extending from the center of the ring waveguide 104. Figure 2G-2H For each of them, the section line 3A-3A' is obtained along a direction parallel to the Y-axis.

[0152] The semiconductor device 300A further includes: a contact region 306, such as silicon dioxide (SiO2), on an insulating layer 344; a PN junction region 307 (1) on layer 122; a contact region 308 on layer 122; a tower 116 (17) on the contact region 308; and a tower 116 (18) on the contact region 308. The PN junction region 307 (1) includes a portion 309 (1) having N+ doping and a portion 309 (2) having P+ doping. The contact region 306 has N++ doping. The contact region 308 has P++ doping.

[0153] In some embodiments, the PN junction region 307(1) has a width W1 of about 1500 nanometers (nm), such that W1≈1500 nm. In some embodiments, the insulating layer has a height H1 of about 2000 nanometers (nm), such that H1≈2000 nm.

[0154] In field-effect transistor (FET) technology, particularly complementary metal-oxide-semiconductor (CMOS) technology, N-type dopant is the dopant type used in n-channel metal-oxide-semiconductor (NMOS) FETs (NFETs), while P-type dopant is the dopant type used in p-channel metal-oxide-semiconductor (PMOS) FETs (PFETs). The symbol N+ indicates an increase in the level / amount of N-type doping relative to a baseline N-type doping level. The symbol P+ indicates an increase in the level / amount of P-type doping relative to a baseline P-type doping level. The symbol N++ indicates an increase in the level / amount of N-type doping relative to the N+ level / amount of N-type doping. The symbol P++ indicates an increase in the level / amount of P-type doping relative to the P+ level / amount of P-type doping.

[0155] Contact area 306 corresponds to Figure 1A , 2A Contact area 106 with 2C and Figure 2G-2H The contact area 206. The PN junction area 307 (1) corresponds to Figure 1A , 2A and PN junction region 107 of 2C and Figure 2G-2H The PN junction region 207. Contact region 308 corresponds to... Figure 1A , 2A Contact area 108 with 2C and Figure 2G-2H The contact area 208. Tower 116 (17) corresponds to Figure 1A Tower 116 (1) Figure 2A and2C Tower 116 (5) and Figure 2G-2H Tower 116 (15). Tower 116 (18) corresponds to Figure 1A Tower 116 (2) Figure 2A and 2C Tower 116 (6) and Figure 2G-2H Tower 116 (16).

[0156] exist Figure 3A In the N++ contact region 306, the N+ portion 309(1) of the PN junction region 307(1) is adjacent to the N+ portion 309(1). The P++ contact region 308 is adjacent to the P+ portion 309(2) of the PN junction region 307(1). Regarding the PN junction region 307(1), a portion of the N+ portion 309(1) is adjacent to and located on a portion of the P+ portion 309(2).

[0157] In some embodiments, the PN junction region 307 is described as exhibiting diode-like behavior. In some embodiments, the PN junction region 307 is represented as a diode in a circuit diagram; see [link to circuit diagram]. Figure 1C Or 2I or the like. In some embodiments, N++ portion 309 (1) represents the cathode (C (-)) of the diode, while P+ portion 309 (2) represents the anode (A (+)) of the diode.

[0158] Generally, the conductivity of N-type semiconductors increases with increasing temperature, while the conductivity of P-type semiconductors decreases with increasing temperature. Therefore, in semiconductor device 300A corresponding to... Figure 1A , 2A In the sections 3A-3A' of 2C and 2C, the N++ contact region 306 is relatively closer to the ring 115(1) of the heater 114, while the P++ contact region 308 is relatively farther away from the ring 115(1) of the heater 114. In some embodiments, in the semiconductor device 300A corresponding to Figure 1A , 2A In the section lines 3A-3A' of 2C, the N++ contact area 306 is relatively farther away from the ring portion 115 (1) of the heater 114, while the P++ contact area 308 is relatively closer to the ring portion 115 (1) of the heater 114.

[0159] Figure 3B This is a cross-sectional view of a semiconductor device 300B according to some embodiments.

[0160] Semiconductor device 300B corresponds to Figure 1A , 2A Section lines 3B-3B' of 2C and 2G-2H. Figure 1B , 2AIn both 2C and 2C, section lines 3B-3B' are taken along a line parallel to the radial axis extending from the center of the ring waveguide 104. Figure 2G-2H In each of the sections, section line 3B-3B' is taken along a direction parallel to the Y-axis.

[0161] Figure 3B Semiconductor device 300B and Figure 3A The semiconductor device 300B is similar to semiconductor device 300A. For the sake of brevity, the discussion will focus on the differences between semiconductor device 300B and semiconductor device 300A, rather than their similarities.

[0162] Semiconductor device 300B includes a PN junction region 307 (2), which is different from the PN junction region 307 (1) included in semiconductor device 300A. The PN junction region 307 (2) includes an N+ doped portion 309 (3) and a P+ doped portion 309 (4). In some embodiments, the PN junction region 307 (2) has a width W1 of about 1500 nanometers (nm), such that the width W1 ≈ 1500 nm.

[0163] exist Figure 3B In the middle, the PN junction region 307(2) corresponds to Figure 1A , 2A and PN junction region 107 of 2C and Figure 2G-2H The PN junction region 207. The N++ contact region 306 is adjacent to the N+ portion 309 (3) of the PN junction region 307 (2). The P++ contact region 308 is adjacent to the P+ portion 309 (4) of the PN junction region 307 (2). Regarding the PN junction region 307 (2), a portion of the N+ portion 309 (3) is adjacent to a portion of the P+ portion 309 (4), but is not substantially on it.

[0164] Figures 4A-4D This is a cross-sectional view of the corresponding semiconductor device 400A-400E according to some embodiments.

[0165] Figures 4A-4D Together, we illustrate an example stage of the photolithography process used to manufacture semiconductor device 200B. Therefore, each of semiconductor devices 400A-400D is... Figure 2B The semiconductor device 200B is a precursor. More specifically, the semiconductor device 400A is a precursor of the semiconductor device 400B. The semiconductor device 400B is a precursor of the semiconductor device 400C. The semiconductor device 400C is a precursor of the semiconductor device 400D. The semiconductor device 400D is a precursor of the semiconductor device 200B.

[0166] exist Figure 4AIn the middle, layer 122 is formed. Then, a ring waveguide 104 is formed in layer 122. The formation of the ring waveguide 104 includes selective doping to produce PN junction region 107, contact region 106 and contact region 108.

[0167] Heater 114 (of which ring 115 (1) is shown in Figure 4A A layer 124 is formed on the annular waveguide 104, such that the heater 114 substantially overlaps with the target heating region 110. A layer 124 is formed on the heater 114 and the annular waveguide 104.

[0168] A photolithography mask material layer is formed on layer 124. The photolithography mask material layer is patterned to produce a photolithography mask 440. That is, the photolithography mask material layer is patterned by forming openings 418(1), 418(2), 416(1), 416(8), 416(9) and 416(10) in the photolithography mask material layer, so that the mask 440 selectively exposes the corresponding areas of layer 124.

[0169] Finally, in Figure 4A The process discussed in the content leads to the 400A semiconductor device. Recall... Figure 4A This indicates a stage in the photolithography process used to manufacture the 200B semiconductor device, with the process starting from... Figure 4A Proceed to the next stage, namely Figure 4B .

[0170] exist Figure 4B In this process, the portions of layer 124 exposed by openings 418(1), 418(2), 416(1), 416(8), 416(9), and 416(10) are etched to form corresponding grooves in layer 124. The grooves in layer 124 formed by openings 418(1) and 418(2) expose the corresponding regions of the annular waveguide. The grooves in layer 124 formed by openings 416(1) and 416(8) expose the corresponding regions of the annular waveguide 104, and are referred to herein as grooves 416(1) and 416(8). The grooves in layer 124 formed by openings 416(9) and 416(10) expose the corresponding regions of the ring portion 115(1) of heater 114, and are referred herein as grooves 416(9) and 416(10). In some embodiments, mask 440 is then removed.

[0171] The recesses in layer 124 formed by opening 418 (1) are filled with the material containing wall 218 (1). The recesses in layer 124 formed by opening 418 (2) are filled with the material containing wall 218 (2). In some embodiments, mask 440 is removed after walls 218 (1) and 218 (2) are formed.

[0172] Finally, in Figure 4B The process discussed in the content leads to the 400B semiconductor device. Recall... Figure 4B This indicates a stage in the photolithography process used to manufacture the 200B semiconductor device, with the process starting from... Figure 4B Proceed to the next stage, namely Figure 4C .

[0173] In some embodiments, the foregoing Figures 4A-4B The discussion can be summarized as the parallel formation of walls 218(1), 218(2), and grooves 416(1), 416(8), 416(9), and 416(10) (“parallel formation” embodiment). In some embodiments, each of (A) walls 218(1), (B) walls 218(2), and (C) grooves 416(1), 416(8), 416(9), and 416(10) is formed sequentially in stages (“sequential formation” embodiment). In some sequential formation embodiments, the exemplary order is: stage (A) forms wall 218(1); then stage (B) forms wall 218(2); then stage (C) forms grooves 416(1), 416(8), 416(9), and 416(10). In some sequential formation embodiments, the order differs from the exemplary order of stage (A) then stage (B) then stage (C).

[0174] In some embodiments, the exemplary details of the paradigm sequentially (again, stage (A) then stage (B) then stage (C)) include the following. Each iteration in stage (A), stage (B), and stage (C) is described through... Figure 4A The corresponding version (not shown) and Figure 4B The corresponding version (not shown).

[0175] Regarding the sequential stage (A) of the examples, in Figure 4A In the content, a first layer of photolithographic mask material (not shown) is formed, and then patterned to form an opening 418 (1), resulting in a version 440(i) of mask 440 (not shown), wherein mask 440(i) has an opening 418 (1) but does not have openings 418 (2), 416 (1), 416 (8), 416 (9), or 416 (10). Then, in Figure 4B In this process, the portion of layer 124 exposed by the opening 418(1) of mask 440(i) is etched to form corresponding grooves in layer 124. Then mask 440(i) is removed. The grooves in layer 124 created by the opening 418(1) are filled with material containing walls 218(1). In some embodiments, mask 440(i) is removed after the walls 218(1) are formed.

[0176] Regarding the sequential stage (B) of the examples, in Figure 4AIn the content, a second layer of photolithographic mask material (not shown) is formed, and then patterned to form an opening 418 (2), resulting in a version 440 (ii) of mask 440 (not shown), wherein mask 440 (ii) has an opening 418 (2) but does not have openings 418 (1), 416 (1), 416 (8), 416 (9), or 416 (10). Then, in Figure 4B In this process, the portion of layer 124 exposed by the opening 418 (2) of mask 440 (ii) is etched to form corresponding grooves in layer 124. Then mask 440 (ii) is removed. The grooves in layer 124 created by the opening 418 (2) are filled with material containing walls 218 (2). In some embodiments, mask 440 (ii) is removed after the walls 218 (2) are formed.

[0177] From stage (B) to stage (C), that is, from Figure 4B Enter Figure 4C Grooves 416(1) and 416(8) expose the corresponding areas of waveguide 104 above contact area 106; grooves 416(9) and 416(10) expose the corresponding areas of heater 114.

[0178] Regarding the stage (C) of the example sequence, in Figure 4A In the content, a third layer of photolithographic mask material (not shown) is formed, and then patterned to form openings 416(1), 416(8), 416(9) and 416(10), resulting in version 440(iii) of mask 440 (not shown), wherein mask 440(iii) has openings 416(1), 416(8), 416(9) and 416(10) but not openings 418(1) or 418(2). Then, in Figure 4B In the process, the portion of layer 124 exposed by the openings 416(1), 416(8), 416(9) and 416(10) of mask 440(iii) is etched to form corresponding grooves 416(1), 416(8), 416(9) and 416(10) in layer 124. Then mask 440(iii) is removed.

[0179] exist Figure 4CIn this process, a barrier layer 142 is formed on the exposed surface of layer 124. In some embodiments, initially, the exposed areas of the ring portion 115(1) of the annular waveguide 104 and the heater 114 are also partially covered by the barrier layer 142; subsequently, such portions of the barrier layer 142 are removed, for example by selective etching, to re-expose the areas of the ring portion 115(1) of the annular waveguide 104 and the heater 114. In some embodiments, the barrier layer 142 is formed anisotropically such that the areas of the ring portion 115(1) of the annular waveguide 104 and the heater 114 remain exposed after the barrier layer 142 is formed. In some embodiments (not shown), the exposed areas of the waveguide 104 above the contact area 106 and the exposed areas of the heater 114 are covered by the barrier layer 142 and Figures 4C-4D and Figure 2A The barrier layer 142 is maintained in a covered manner (not shown). That is, in some embodiments, portions of the barrier layer 142 (not shown) are maintained between (i) the regions of towers 116 (1) and 116 (8) and waveguide 104 above the contact region 106, and (ii) the regions of towers 116 (9) and 116 (10) and the corresponding regions of heater 114.

[0180] Examples of materials included in barrier layer 142 include: tantalum (Ta); tantalum nitride (TaN); a combination of Ta and TaN; a combination of Ta and one or more materials and / or layers other than TaN; a combination of TaN and one or more materials and / or layers other than Ta; a combination of Ta and TaN and one or more other materials; one or more materials and / or layers other than Ta or TaN; or similar.

[0181] Finally, in Figure 4C The process discussed in the content leads to 400C in semiconductor devices. Recall... Figure 4C This indicates a stage in the photolithography process for manufacturing a 200B semiconductor device, with the process starting from... Figure 4C Proceed to the next stage, namely Figure 4D .

[0182] exist Figure 4D In the process, a metal layer 419 is formed on the barrier layer 142 and on the exposed areas of the annular portion 115(1) of the ring waveguide 104 and the heater 114. The portions of the metal layer 419 in the grooves 416(1), 416(8), 416(9) and 416(10) represent the corresponding precursors of the towers 116(1), 116(8), 116(9) and 116(10).

[0183] Finally, in Figure 4D The process discussed in the content leads to the 400D semiconductor device. Recall... Figure 4C This indicates a stage in the photolithography process for manufacturing a 200B semiconductor device, with the process starting from... Figure 4CProceed to the next stage, namely Figure 2B .

[0184] Back Figure 2B In the discussion, semiconductor device 200B is the result of planarizing the upper surface of semiconductor device 400D, for example, by chemical mechanical polishing (CMP). CMP removes the portion of metal layer 419 above the horizontal portion of barrier layer 142. CMP further removes the horizontal portion of barrier layer 142 and the portion of metal layer 419 at the same level as the horizontal portion of barrier layer 142. As a result of CMP, the upper surfaces of towers 116(1), 116(8), 116(9), and 116(10) and the upper surfaces of walls 218(1) and 218(2) are exposed, as Figure 2B As shown.

[0185] Figures 5A-5D This is a cross-sectional view of the corresponding semiconductor devices 500A-500D according to some embodiments.

[0186] Figures 5A-5D Semiconductor devices 500A-500D and Figures 4A-4D The corresponding semiconductor devices 400A-400D are similar. For the sake of brevity, the discussion will focus on the differences between semiconductor devices 500A-500D and their corresponding semiconductor devices 400A-400D, rather than their similarities.

[0187] Figures 5A-5D This section illustrates an exemplary stage of the photolithography process used in manufacturing semiconductor device 200D. Therefore, each of the semiconductor devices 500A-500D is... Figure 2D The semiconductor device 200D is a precursor to the semiconductor device 500A. More specifically, the semiconductor device 500A is a precursor to the semiconductor device 500B. The semiconductor device 500B is a precursor to the semiconductor device 500C. The semiconductor device 500C is a precursor to the semiconductor device 500D. The semiconductor device 500D is a precursor to the semiconductor device 200D.

[0188] exist Figure 5A In this process, the photolithographic mask material layer is patterned by forming openings 416(1), 416(8), 416(9), 416(10), and 518(3) in the photolithographic mask material layer, so that the mask 540 selectively exposes corresponding areas of layer 124. That is, in Figure 5A An opening 518 (3) is formed in the photolithography mask material layer, rather than as Figure 4A The openings 418(1) and 418(2) are in the middle.

[0189] Finally, in Figure 5A The process discussed in the content leads to the 500A semiconductor device. Recall... Figure 5AThis represents a stage in the photolithography process for manufacturing 200D semiconductor devices, with the process starting from... Figure 5A Proceed to the next stage, namely Figure 5B .

[0190] exist Figure 5B In this process, the portion of layer 124 exposed by openings 518(3), 416(1), 416(8), 416(9), and 416(10) is etched to form corresponding grooves in layer 124. The groove in layer 124 formed by opening 518(3) exposes the corresponding region of the annular waveguide 104. In some embodiments, after the groove in layer 124 is formed, mask 440 is removed.

[0191] The grooves in layer 124 created by opening 518 (3) are filled with a material containing wall 218 (3). In some embodiments, mask 440 is removed after the wall is formed.

[0192] Finally, in Figure 5B The process discussed in the content leads to the 500B semiconductor device. Recall... Figure 5B This represents a stage in the photolithography process for manufacturing 200D semiconductor devices, with the process starting from... Figure 5B Proceed to the next stage, namely Figure 5C .

[0193] In some embodiments, the foregoing Figures 5A-5B The discussion can be summarized as the parallel formation of walls 218(3) and grooves 416(1), 416(8), 416(9), and 416(10) (“Parallel Forming” embodiment). In some embodiments, each of (D) walls 218(3) and (E) grooves 416(1), 416(8), 416(9), and 416(10) is formed in sequential stages (“Sequential Forming” embodiment). In some sequential forming embodiments, the exemplary order is: stage (D) forms wall 218(3); then stage (E) forms grooves 416(1), 416(8), 416(9), and 416(10). In some sequential forming embodiments, the order differs from the exemplary order of stage (D) then stage (E).

[0194] In some embodiments, the exemplary details of the paradigm sequentially (again, stage (D) then stage (E)) include the following. Each iteration in stage (D) and stage (E) is described through... Figure 5A The corresponding version (not shown) and Figure 5B The corresponding version (not shown).

[0195] Regarding the sequential stage (D) of the examples, in Figure 5AIn the content, a first layer of photolithographic mask material (not shown) is formed, and then patterned to form opening 518 (3), resulting in version 540(i) of mask 540 (not shown), wherein mask 540(i) has opening 518 (3) but not opening 416 (1), 416 (8), 416 (9) or 416 (10). Then, in Figure 5B In the process, the portion of layer 124 exposed by the opening 518 (3) of mask 540 (i) is etched to form a corresponding groove in layer 124. Then mask 540 (i) is removed. The groove in layer 124 formed by the opening 518 (3) is filled with a material containing wall 218 (3). In some embodiments, mask 540 (i) is removed after wall 218 (3) is formed.

[0196] Regarding the sequential stage (E) of the examples, in Figure 5A In the content, a second layer of photolithographic mask material (not shown) is formed, and then patterned to form openings 416(1), 416(8), 416(9) and 416(10), resulting in version 540(iii) of mask 540 (not shown), wherein mask 540(iii) has openings 416(1), 416(8), 416(9) and 416(10) but not opening 518(3). Then, in Figure 5B In the content, the portion of layer 124 exposed by the openings 416(1), 416(8), 416(9) and 416(10) of mask 540(iii) is etched to form corresponding grooves 416(1), 416(8), 416(9) and 416(10) in layer 124. Then mask 540(iii) is removed.

[0197] From stage (D) to stage (E), that is, from Figure 5B Enter Figure 5C Grooves 416(1) and 416(8) expose the corresponding areas of waveguide 104 above contact area 106; grooves 416(9) and 416(10) expose the corresponding areas of heater 114.

[0198] exist Figure 5C In this process, a barrier layer 142 is formed on the exposed surface of layer 124. Regions of the annular portion 115(1) of the ring waveguide 104 and the heater 114 remain exposed after the barrier layer 142 is formed. In some embodiments, portions of the barrier layer 142 (not shown) remain between (i) the regions of towers 116(1) and 116(8) and the region of the waveguide 104 above the contact region 106, and (ii) between towers 116(9) and 116(10) and the corresponding regions of the heater 114.

[0199] Finally, in Figure 5CThe process discussed in the content leads to the 500C semiconductor device. Recall... Figure 5C This represents a stage in the photolithography process for manufacturing 200D semiconductor devices, with the process starting from... Figure 5C Proceed to the next stage, namely Figure 5D .

[0200] exist Figure 5D In the process, a metal layer 419 is formed on the barrier layer 142 and on the exposed areas of the annular portion 115(1) of the ring waveguide 104 and the heater 114. The portions of the metal layer 419 in the grooves 416(1), 416(8), 416(9) and 416(10) represent the corresponding precursors of the towers 116(1), 116(8), 116(9) and 116(10).

[0201] Finally, in Figure 5D The process discussed in the content leads to the 500D semiconductor device. Recall... Figure 5C This represents a stage in the photolithography process for manufacturing 200D semiconductor devices, with the process starting from... Figure 5C Proceed to the next stage, namely Figure 2D .

[0202] Back Figure 2D The discussion of semiconductor device 200D is a result of planarizing the upper surface of semiconductor device 500D, for example, by chemical mechanical polishing (CMP). CMP removes a portion of metal layer 419 located above the horizontal portion of barrier layer 142. CMP further removes the horizontal portion of barrier layer 142 and a portion of metal layer 419 at the same level as the horizontal portion of barrier layer 142. As a result of CMP, the upper surfaces of towers 116(1), 116(8), 116(9), and 116(10), as well as the upper surfaces of walls 218(3) and 218(3), are exposed, as... Figure 2D As shown.

[0203] Figure 6 This is a flowchart (flowchart) of a method 600 for manufacturing an element according to some embodiments.

[0204] According to some embodiments, method 600 uses, for example, EDA system 800 ( Figure 8 (discussed below) and IC Manufacturing System 900 ( Figure 9 (Discussed below) to be implemented. Examples of semiconductor devices that can be manufactured according to method 600 include the semiconductor devices disclosed herein or similar devices.

[0205] exist Figure 6In this method 600, blocks 602-604 are included. In block 602, a layout diagram is generated, which, among other things, includes one or more layout diagrams corresponding to one or more semiconductor devices disclosed herein, or similar layout diagrams. According to some embodiments, block 602 uses, for example, an EDA system 800 (… Figure 8 (Discussed below) to implement. From block 602, the process proceeds to block 604.

[0206] In block 604, based on the layout diagram, at least one of the following is performed: (A) one or more photolithographic exposures; or (B) one or more photolithographic masks are fabricated; or (C) one or more components in the device layer, such as a fabrication apparatus, are fabricated. See below. Figure 9 Discussion of IC Manufacturing System 900.

[0207] Figure 7 This is a flowchart of a method 700 of a manufacturing apparatus according to some embodiments.

[0208] Method 700 is an example of block 604 (see...) Figure 6 (As discussed above). According to some embodiments, method 700 uses, for example, IC manufacturing system 900 (see above). Figure 9 (Discussed below) to be implemented. Examples of semiconductor devices that can be manufactured according to method 700 include the semiconductor devices disclosed herein or similar devices. Method 700 includes blocks 714-724.

[0209] In square 712, the first waveguide is formed. Examples of first waveguides include... Figure 1A , 1H 2A-2D ring waveguide 104 Figure 2G-2H The busbar waveguide 202 or similar. The formation of the first waveguide also... Figure 4A and 5A This will be discussed in the following sections. The process proceeds from block 712 to block 714.

[0210] In block 714, form a heater. Examples of heaters include... Figure 1A , 1H 114. Heater 2A-2D Figure 2G-2H Heater 214 or similar. The formation of the heater also... Figure 4A and 5A Discussed in the content of or similar sources. From block 714, the process proceeds to block 716.

[0211] In block 716, a first dielectric structure is formed on heater 114 and the first waveguide. An example of the first dielectric structure is... Figure 1H , 2B And 2D layer 124 or similar. The formation of the first dielectric structure also occurs in Figure 4A and5A This will be discussed in the following sections. The process proceeds from block 716 to block 718.

[0212] In block 718, grooves are etched in the first dielectric structure, including T-grooves and W-grooves. In some embodiments, the text string T-grooves is intended to represent tower grooves, grooves that will form towers. In some embodiments, the text string W-grooves is intended to represent wall grooves, grooves that will form walls.

[0213] Examples of T-grooves include Figure 4B and 5B The grooves 416(1), 416(8), 416(9) and 416(10) or similar thereof.

[0214] Examples of W-grooves include Figure 4B The grooves in layer 124 formed by openings 418(1) and 418(2) Figure 5B The groove in layer 124, etc., is created by opening 418 (3). From block 718, the process proceeds to block 720.

[0215] In block 720, a barrier layer is deposited on the exposed surface of the dielectric structure. Examples of barrier layers include... Figure 4C and 5C Barrier layer 142 or similar. From block 720, the process proceeds to block 722.

[0216] In block 722, material for the deposited tower and walls (including the first wall) is deposited in the counterparts of the T-grooves and W-grooves. Examples of the first wall include... Figure 1A and 1H Wall 118 Figure 2A-2B And the wall 218 (1) of 4B-4D Figure 2C-2D And wall 218(3) of 5B-5D or similar. Examples of towers include Figure 1A and 1H Towers 116(1)-116(2) and 116(4), Figures 2A-2D Towers 116(1), 116(8), 116(9) and 116(10) or similar. Figures 2A-2D The precursor examples of towers 116(1), 116(8), 116(9) and 116(10) include Figure 4D and 5D A portion of the metal layer 419 or similar in the recesses 416(1), 416(8), 416(9) and 416(10). Within block 722, the process proceeds to block 724.

[0217] In block 724, one or more first materials and / or layers are deposited into the counterpart of the W-groove to form a first wall for protecting the first tower against heat transfer from the heater. Regarding wall 218(1) as an example of the first wall, suitable examples of materials to be included in the first wall are... Figure 2A-2B The discussion is in the content of [the document], and more specifically in the content of Table 1. Regarding wall 218(3) as an example of the first wall, suitable examples of materials to be included in the first wall are […]. Figure 2C-2D This will be discussed in the content of [the document], and more specifically in the content of Table 3.

[0218] In some embodiments, the wall formed in block 722 includes a second wall. Examples of the second wall include... Figure 2A-2B And wall 218(2) of 4B-4D or similar thereof. In some embodiments, block 724 further includes depositing one or more second materials in the counterpart of the W-groove to form a second wall for protecting the first tower against heat transfer from the heater. Regarding wall 218(2) as an example of a second wall, suitable examples of materials to be included in the second wall are... Figure 2A-2B This will be discussed in the content of [the document], and more specifically in the content of Table 2.

[0219] Figure 8 This is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0220] In some embodiments, EDA system 800 includes an automatic placement and routing (APR) system. In some embodiments, EDA system 800 is a general-purpose computing device including a processor 802 (e.g., a hardware processor) and a non-transitory computer-readable storage medium 804. The storage medium 804, among other things, is encoded with (i.e., stored) computer program code 806 (i.e., a set of executable instructions). The processor 802 executes the instructions 806, which represent (at least partially) EDA tools, the implementation of which, according to one or more embodiments, produces part or all of one or more embodiments (hereinafter referred to as the process and / or method) of a layout corresponding to a layout diagram disclosed herein, a layout diagram corresponding to a semiconductor device disclosed herein, or the like thereof.

[0221] Storage medium 804, among other things, includes storage layout diagram 811, such as the layout diagram disclosed herein or similar thereof.

[0222] Processor 802 is electrically coupled to storage medium 804 via bus 808. Processor 802 is further electrically coupled to I / O interface 810 via bus 808. Network interface 812 is further electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and storage medium 804 to be connected to external components via network 814. Processor 802 is configured to execute computer program code 806 encoded in storage medium 804 to enable EDA system 800 to perform some or all of the process and / or method. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0223] In one or more embodiments, the storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the storage medium 804 includes semiconductor or solid-state memory, magnetic tape, portable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disc. In one or more embodiments using optical discs, the storage medium 804 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0224] In one or more embodiments, storage medium 804 stores instructions, i.e., computer program code 806, configured to enable EDA system 800 (where such execution (at least partially) represents EDA tools) to perform part or all of the process and / or method. In one or more embodiments, storage medium 804 further stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, storage medium 804 stores a library 807 of standard cells, including standard cells corresponding to components of the layout diagrams disclosed herein. Storage medium 804 stores one or more layout diagrams 816, such as one or more layout diagrams corresponding to the layout diagrams disclosed herein, one or more layout diagrams corresponding to the semiconductor devices disclosed herein, one or more compiled macros 817 based on these layout diagrams, or the like.

[0225] EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 802.

[0226] EDA system 800 further includes a network interface 812 coupled to processor 802. Network interface 812 allows EDA system 800 to communicate with network 814, to which one or more other computer systems are connected. Network interface 812 includes a wireless network interface, such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethereum, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more EDA systems 800.

[0227] EDA system 800 is configured to receive information via I / O interface 810. The information received via I / O interface 810 includes instructions, data, design rules, standard cell libraries, and / or one or more other parameters for processing by processor 802. The information is transmitted to processor 802 via bus 808. EDA system 800 is also configured to receive information related to the user interface (UI) via I / O interface 810. This information is stored as UI 842 on computer-readable medium 804.

[0228] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an EDA system 800. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, or another suitable layout generation tool.

[0229] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, memory cards), or one or more of the like.

[0230] Figure 9 This is a block diagram of an integrated circuit (IC) manufacturing system 900 and its associated IC manufacturing process according to some embodiments.

[0231] In some embodiments, based on Figure 6 The layout diagram generated by block 602 is implemented in IC manufacturing system 900. Figure 6 Block 604, wherein at least one of (A) one or more semiconductor masks or (B) at least one component in an initial semiconductor integrated circuit layer is manufactured using manufacturing system 900. In some embodiments, IC manufacturing system 900 implements Figure 6 A flowchart or something similar.

[0232] exist Figure 9 In this IC manufacturing system 900, entities such as design company 920, mask company 930, and IC manufacturer (fab) 950 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC device 960. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design company 920, mask company 930, and IC fab 950 are owned by a single larger company. In some embodiments, two or more of the design company 920, mask company 930, and IC fab 950 coexist in a shared facility and use shared resources.

[0233] Design company (or design team) 920 generates IC design layout 922. IC design layout 922 includes various geometric patterns designed for IC device 960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 960 to be manufactured. Various layers are combined to form various IC features. For example, portions of IC design layout 922 include various IC features, such as active regions, gate terminals, sources and drains, metal lines or vias for interlayer interconnects, and openings for bonding pads, to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. Source / drain regions may refer individually or collectively to sources or drains, depending on the content. Design company 920 implements appropriate design procedures to form IC design layout 922. Design procedures include one or more of logic design, physical design, or place-and-route. IC design layout 922 is presented in one or more data files containing geometric pattern information. For example, IC design layout 922 is represented in GDSII file format or DFII file format.

[0234] Mask company 930 includes data preparation 932 and mask manufacturing 934. Mask company 930 uses IC design layout 922 to manufacture one or more masks 935 for manufacturing various layers of IC device 960 according to IC design layout 922. Mask company 930 performs mask data preparation 932, in which IC design layout 922 is converted into a representative data file ("RDF"). Mask data preparation 932 provides the RDF to mask manufacturing 934. Mask manufacturing 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask) or semiconductor wafer. The design layout is manipulated by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of IC plant 950. Figure 9 In this design, mask data preparation 932, mask manufacturing 934, and mask 935 are illustrated as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 934 are collectively referred to as mask data preparation.

[0235] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, or the like. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution adjustment features, phase-shift masks, other suitable techniques, or the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is further used, which treats OPC as a reverse imaging problem.

[0236] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout already processed in the OPC. This set of mask creation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes or the like. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 934, and can undo some modifications performed by the OPC to satisfy the mask creation rules.

[0237] In some embodiments, mask preparation 932 includes lithography process checking (LPC), a simulation of a process performed by IC fab 950 to manufacture IC device 960. LPC simulates this process based on IC design layout 922 to manufacture a simulated manufacturing apparatus, such as IC device 960. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, or similar factors or combinations thereof. In some embodiments, after the simulated manufacturing apparatus has been manufactured by LPC, if the simulated apparatus is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 922.

[0238] For clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, mask data preparation 932 includes additional features such as logic operations (LOPs) to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to the IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0239] After mask data preparation 932 and during mask manufacturing 934, a mask 935 or a set of masks 935 is manufactured based on a modified IC design layout. In some embodiments, a mechanism of electron beam (e-beam, e-beam) or multiple electron beams is used to form a pattern on the mask (mask or veil) based on the modified IC design layout. The veil is formed using various techniques. In some embodiments, the veil is formed using a binary technique. In some embodiments, the veil pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the mask. In another example, the mask is formed using a phase-shifting technique. In a phase-shift mask (PSM), various features in the pattern formed on the mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, phase-shifting masks are attenuated PSMs or alternating PSMs. Masks produced by mask fabrication 934 are used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions in semiconductor wafers, and / or in other suitable processes.

[0240] IC Facility 950 is an IC manufacturing company, comprising one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC Facility 950 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end-of-line, FEOL) of multiple IC products, a second manufacturing facility for providing back-end manufacturing (back-end-of-line, BEOL) for interconnecting and packaging IC products, and a third manufacturing facility for providing other services for foundry operations.

[0241] IC fabrication plant 950 uses a mask 935 manufactured by mask company 930 and manufacturing tool 952 to manufacture IC device 960. Thus, IC fabrication plant 950 manufactures IC device 960 at least indirectly using IC design layout 922. In some embodiments, semiconductor wafer 953 is manufactured by IC fabrication plant 950 using mask 935 to form IC device 960. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate having a layer of material formed thereon. Semiconductor wafer further includes one or more of various doped regions, dielectric features, multilevel interconnects, or the like (formed in subsequent manufacturing steps).

[0242] In some embodiments, the semiconductor device includes: a first waveguide extending in a first direction; the first waveguide including a first doped contact region and a heating target region; a heater extending in the first direction and on the heating target region of the first waveguide relative to a second direction perpendicular to the first direction; a conductive tower including the first tower on the first doped contact region; a wall including the first wall on the first waveguide and between the first tower and the heater; and the first wall including one or more first materials configured to protect the first tower from heat transfer from the heater.

[0243] In some embodiments, the first direction is the azimuth direction; the second direction is the zenith direction; the first waveguide is a ring waveguide such that the heating target area is an arcuate segment of the first waveguide; the heater includes an arcuate segment that at least partially overlaps with the heating target area of ​​the first waveguide substantially concentrically; and the first wall includes an arcuate segment between the first tower and the arcuate segment of the heater.

[0244] In some embodiments, the first direction is a Cartesian direction; the first waveguide is a straight waveguide such that the heating target region is a substantially straight segment of the first waveguide; the heater includes a substantially straight segment that at least partially overlaps with the heating target region of the first waveguide; and the first wall includes a substantially straight segment between the substantially straight segments of the first tower and the heater.

[0245] In some embodiments, in combination, one or more first materials of the first wall have a conductivity k less than or equal to about 35 W / m•K, such that k ≤ (≈35 W / m•K).

[0246] In some embodiments, in combination, one or more first materials of the first wall have a conductivity k less than or equal to about 1.4 W / m•K, such that k ≤ (≈1.4 W / m•K).

[0247] In some embodiments, in combination, one or more first materials of the first wall have a low conductivity k of less than or equal to about 0.3 W / m•K, such that k ≤ (≈0.3 W / m•K).

[0248] In some embodiments, in combination, one or more first materials of the first wall have a conductivity k in the range of approximately 21 W / m•K ≤ k ≤ approximately 29 W / m•K.

[0249] In some embodiments, in combination, one or more first materials of the first wall have a conductivity k in the range of about 21 W / m•K, such that (≈21 W / m•K) ≤ k.

[0250] In some embodiments, in combination, one or more first materials of the first wall have a conductivity k in the range of about 175 W / m•K, such that (≈175 W / m•K) ≤ k.

[0251] In some embodiments, the gap between the heater and the first wall has a distance D3 in the range of (≈0.5μm) ≤ D3 ≤ (≈2.0μm).

[0252] In some embodiments, the wall further includes: a second wall on the first waveguide and between the first tower and the heater; and the second wall includes one or more second materials configured to protect the first tower from heat transfer from the heater.

[0253] In some embodiments, the first wall has a first mode configured to protect the first tower from heat transfer from the heater; the second wall has a second mode configured to protect the first tower from heat transfer from the heater; and the first mode of the first wall is different from the second mode of the second wall.

[0254] In some embodiments, the first wall is between the second wall and the heater; and the second wall is between the first wall and the first tower.

[0255] In some embodiments, the gap between the first wall and the second wall has a distance D4 in the range of (≈0.5μm) ≤ D4 ≤ (≈2.0μm).

[0256] In some embodiments, the method (manufacturing a semiconductor device) includes: forming a first waveguide extending in a first direction; the first waveguide including a first doped contact region and a heating target region; forming a heater extending in the first direction and on the heating target region of the first waveguide relative to a second direction perpendicular to the first direction; forming a first dielectric structure on the heater and the first waveguide; etching a groove including a T-groove and a W-groove in the first dielectric structure, which correspondingly exposes the first waveguide or the heater; depositing material in the T-groove and the W-groove to correspondingly form a tower and a wall, the tower including a first tower on the first doped contact region, and the wall including a first wall on the first waveguide and between the first tower and the heater; and the material deposition including: depositing one or more first materials in one of the W-grooves corresponding to the first wall, the one or more first materials being configured to protect the first tower against heat transfer from the heater.

[0257] In some embodiments, the first direction is an azimuth direction; the second direction is a zenith direction; the first waveguide is a ring waveguide such that the heating target area is an arcuate segment of the first waveguide; the heater includes an arcuate segment that is at least partially concentrically overlapping with the heating target area of ​​the first waveguide; and the first wall is an arcuate segment between the first tower and the arcuate segment of the heater.

[0258] In some embodiments, the first direction is a Cartesian direction; the first waveguide is a straight waveguide such that the heating target region is a substantially straight segment of the first waveguide; the heater includes a substantially straight segment that at least partially overlaps with the heating target region of the first waveguide; and the first wall includes a substantially straight segment between the substantially straight segments of the first tower and the heater.

[0259] In some embodiments, the deposited material further forms: a wall further includes a second wall on the first waveguide and between the first tower and the heater; and the deposited material further includes: depositing one or more second materials in one of the W grooves corresponding to the second wall, the one or more second materials being configured to protect the first tower against heat transfer from the heater.

[0260] In some embodiments, the deposited material further includes: positioning the first wall between the second wall and the heater; and positioning the second wall between the first wall and the first tower.

[0261] In some embodiments, the semiconductor device includes: a first waveguide extending in a first direction; the first waveguide including a first doped contact region and a heating target region; a heater extending in the first direction and on the heating target region of the first waveguide relative to a second direction perpendicular to the first direction; a conductive tower including the first tower on the first doped contact region; and a wall including: a first wall on the first waveguide and between the first tower and the heater, and a second wall on the first waveguide and between the first tower and the heater; the first wall including one or more first materials configured to protect the first tower against heat transfer from the heater; and the second wall including one or more second materials configured to protect the first tower against heat transfer from the heater.

[0262] In some embodiments, the first wall has a first mode configured to protect the first tower from heat transfer from the heater; the second wall has a second mode configured to protect the first tower from heat transfer from the heater; and the first mode of the first wall is different from the second mode of the second wall.

[0263] In some embodiments, the first wall is between the second wall and the heater; and the second wall is between the first wall and the first tower.

[0264] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the aforementioned advantages. Upon reading the foregoing specification, those skilled in the art will be able to implement various variations, equivalents, and other embodiments as broadly disclosed herein. Therefore, it is intended that the protection granted herein be limited only to the definitions contained in the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, include: The first waveguide extends in the first direction; The first waveguide includes a first doped contact region and a heating target region; A heater extends in the first direction and is located on the heating target region of the first waveguide relative to a second direction perpendicular to the first direction; The tower, which is conductive, includes a first tower located on the first doped contact region; The wall includes a first wall located on the first waveguide and between the first tower and the heater; and The first wall comprises one or more first materials configured to protect the first tower from heat transfer from the heater.

2. The apparatus according to claim 1, characterized in that: The first direction is the azimuth direction; The second direction is the zenith direction; The first waveguide is a ring waveguide, such that the heating target area is the arc-shaped segment of the first waveguide; The heater includes an arc-shaped segment that at least partially overlaps with the heating target region of the first waveguide substantially concentrically; as well as The first wall includes an arcuate section located between the first tower and the arcuate section of the heater.

3. The apparatus according to claim 1, characterized in that: The first direction is the Cartesian direction; The first waveguide is a linear waveguide, such that the heating target region is a substantially straight segment of the first waveguide; The heater includes a substantially straight segment that at least partially overlaps with the heating target region of the first waveguide; and The first wall includes a substantially straight segment located between the first tower and the substantially straight segment of the heater.

4. The apparatus according to claim 1, characterized in that: The wall further includes: The second wall is located on the first waveguide and between the first tower and the heater; and The second wall comprises one or more second materials and is configured to protect the first tower from heat transfer from the heater.

5. The apparatus according to claim 4, characterized in that: The first wall has a first mode, wherein the first wall is configured to protect the first tower from heat transfer from the heater; The second wall has a second pattern, wherein the second wall is configured to protect the first tower from heat transfer from the heater; as well as The first mode of the first wall is different from the second mode of the second wall.

6. The apparatus according to claim 4, characterized in that: The first wall is located between the second wall and the heater; and The second wall is located between the first wall and the first tower.

7. A method for manufacturing a semiconductor device, characterized in that, include: Forming the first waveguide, extending in the first direction; The first waveguide includes a first doped contact region and a heating target region; A heater is formed, extending in the first direction and located on the heating target region of the first waveguide, relative to a second direction perpendicular to the first direction; A first dielectric structure is formed on the heater and the first waveguide; Grooves are etched in the first dielectric structure, including T-grooves and W-grooves, which correspondingly expose the first waveguide or the heater; Material is deposited in the T-grooves and W-grooves, correspondingly forming towers and walls. The tower includes a first tower on the first doped contact region, and The wall is a first wall on the first waveguide and located between the first tower and the heater; as well as The deposition material includes: One or more first materials are deposited in one of the W-grooves corresponding to the first wall, the one or more first materials being configured to protect the first tower against heat transfer from the heater.

8. The method according to claim 7, characterized in that: The deposited material further forms: The wall further includes a second wall on the first waveguide and between the first tower and the heater; as well as The deposition material further comprises: One or more second materials are deposited in one of the W-shaped grooves corresponding to the second wall, the one or more second materials being configured to protect the first tower against heat transfer from the heater.

9. The method according to claim 8, characterized in that: The deposition material further comprises: Positioning the first wall between the second wall and the heater; and The second wall is positioned between the first wall and the first tower.

10. A semiconductor device, characterized in that, include: The first waveguide extends in the first direction; The first waveguide includes a first doped contact region and a heating target region; A heater extends in the first direction and is located on the heating target region of the first waveguide, relative to a second direction perpendicular to the first direction; The tower is conductive and includes a first tower on the first doped contact region; The wall includes: The first wall, on the first waveguide and between the first tower and the heater, and The second wall is located on the first waveguide and between the first tower and the heater; and The first wall comprises one or more first materials, configured to protect the first tower from heat transfer from the heater; and The second wall comprises one or more second materials and is configured to protect the first tower from heat transfer from the heater.

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