Heterogeneously integrated optoelectronic chip and method of making the same

Abstract

This invention relates to the field of optoelectronic integration technology and discloses a heterogeneous integrated optoelectronic chip and its fabrication method. The method includes: forming a lithium niobate structural layer on one side surface of a substrate, including a lithium niobate waveguide and a first cladding layer; forming a silicon nitride structural layer on the lithium niobate structural layer, including a silicon nitride waveguide and a second cladding layer, wherein the projection of the silicon nitride waveguide on the substrate lies within the projection of the lithium niobate waveguide on the substrate; forming a composite waveguide structure with the silicon nitride waveguide and the lithium niobate waveguide; forming a silicon-based structural layer on the silicon nitride structural layer, including multiple silicon-based units and a third cladding layer, including a germanium-silicon detector unit and a silicon-based modulation unit; and forming an electrode structure, the electrode structure including a first electrode connected to the germanium-silicon detector unit, a second electrode connected to the silicon-based modulation unit, and a third electrode corresponding to the composite waveguide structure. This design, which first forms the lithium niobate waveguide and then forms the germanium-silicon detector unit and the silicon-based modulation unit, effectively improves integration density and device performance.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic integration technology, specifically to a heterogeneous integrated optoelectronic chip and its fabrication method. Background Technology

[0002] With the rapid development of artificial intelligence, big data, and cloud computing technologies, data transmission has placed unprecedented demands on bandwidth, speed, and energy efficiency, prompting continuous evolution of core optical communication chip technologies. The performance of traditional silicon-based optical modules is gradually approaching their material physical limits. Against this backdrop, thin-film lithium niobate (TFLN), due to its excellent electro-optic coefficient, high-speed response, wide optical transparency window, and high Curie temperature, has become an ideal material for fabricating high-performance electro-optic modulators. TFLN-based thin-film lithium niobate modulators possess significant advantages such as low power consumption, large bandwidth, and small size. In silicon-based optoelectronic chips, germanium-silicon detectors are the core devices for photoelectric signal conversion. Together with silicon-based modulators, they rely on mature complementary metal-oxide-semiconductor (CMOS) technology to achieve large-scale, low-cost, and high-yield manufacturing. The efficient integration of these different types of devices is a key problem that needs to be solved in the field of optoelectronic integration.

[0003] In existing technologies, these devices are difficult to integrate monolithically on the same chip due to significant differences in material systems and manufacturing processes. They are typically fabricated separately and then integrated through back-end packaging. For example, lithium niobate modulators are manufactured independently due to the unique properties of their materials, while germanium detectors and silicon-based modulators are fabricated using a separate silicon-on-insulator (SOI) substrate and CMOS-compatible process. This separate fabrication and back-end integration approach results in low integration density, large device size, and high packaging costs, and introduces additional optical coupling losses, limiting the overall performance improvement of the chip. Furthermore, in this bonded integration structure, there is often a spatial misalignment between the optical mode field center of the lithium niobate modulator and the electric field center generated by the modulation metal, reducing the interaction efficiency between the electric and optical fields and limiting the modulation efficiency of the modulator. Moreover, integrating different devices on the same substrate presents numerous problems in the process flow design, such as thermal budget conflicts and the risk of metal contamination. Therefore, how to efficiently and reliably integrate high-performance thin-film lithium niobate modulators with mature silicon-based modulators and germanium-silicon detectors on the same chip has become one of the urgent problems to be solved. Summary of the Invention

[0004] This invention provides a heterogeneous integrated optoelectronic chip and its fabrication method to solve the problems of low integration and difficulty in guaranteeing device performance in existing optoelectronic chips.

[0005] In a first aspect, the present invention provides a method for fabricating a heterogeneous integrated optoelectronic chip, comprising: Provide a base layer; A lithium niobate structure layer is formed on one side surface of the substrate layer. The lithium niobate structure layer includes a lithium niobate waveguide and a first cladding layer covering the lithium niobate waveguide. A silicon nitride structure layer is formed on the side of the lithium niobate structure layer away from the substrate layer. The silicon nitride structure layer includes a silicon nitride waveguide and a second cladding layer covering the silicon nitride waveguide. The projection of the silicon nitride waveguide on the substrate layer is located within the projection region of the lithium niobate waveguide on the substrate layer. The silicon nitride waveguide and the lithium niobate waveguide form a composite waveguide structure. A silicon-based structural layer is formed on the side of the silicon nitride structural layer away from the substrate layer. The silicon-based structural layer includes various silicon-based units and a third cladding layer covering the silicon-based units. The silicon-based units include germanium-silicon detection units and silicon-based modulation units. An electrode structure is formed, comprising a first electrode for connecting a germanium-silicon detection unit, a second electrode for connecting a silicon-based modulation unit, and a third electrode located beside a silicon nitride waveguide and above a lithium niobate waveguide; the germanium-silicon detection unit and the first electrode are configured to form a germanium-silicon detector, the silicon-based modulation unit and the second electrode are configured to form a silicon-based modulator, and the composite waveguide structure and the third electrode are configured to form a composite waveguide modulator.

[0006] Beneficial effects: In the fabrication method of the heterogeneous integrated optoelectronic chip of the present invention, a lithium niobate structure layer including a lithium niobate waveguide is first formed, and then a silicon nitride structure layer including a silicon nitride waveguide is formed on top of it, thereby forming a composite waveguide structure of lithium niobate and silicon nitride. This can effectively improve bandwidth, reduce driving voltage, and achieve lower power consumption, and can also ensure the optical mode field between the lithium niobate waveguide and the silicon nitride waveguide, thereby improving modulation efficiency. Then, a silicon-based structure layer including a germanium-silicon detector unit and a silicon-based modulation unit is fabricated on top of the silicon nitride structure layer, and finally, the electrode structure is formed. The modulation electrode, also known as the third electrode, corresponding to the lithium niobate-silicon nitride composite waveguide structure is located above the lithium niobate waveguide, which is arranged in a large area. This structure reduces the spatial deviation between the center of the electric field generated by the third electrode and the center of the optical mode field, ensuring the interaction efficiency between the electric field and the optical field and the modulation efficiency of the modulator. This enables the efficient integration of different optoelectronic devices such as lithium niobate-silicon nitride composite waveguide modulators, silicon-based modulators, and germanium-silicon detectors on the same chip, effectively saving device size, reducing production costs, and reducing optical losses from device coupling.

[0007] In summary, this design, which first forms the lithium niobate waveguide and then the germanium-silicon detector and silicon-based modulation unit, effectively ensures a strongly coupled optical mode field between the lithium niobate and silicon nitride waveguides, improving the modulation efficiency of the lithium niobate-silicon nitride composite waveguide modulator. Furthermore, compared to schemes where subsequent heating and cooling processes affect the performance of the doped silicon-based unit when the silicon-based structure layer is formed first, this design of forming the silicon-based unit later effectively reduces such performance impact, improves the detection sensitivity of the germanium-silicon detector and the modulation efficiency of the silicon-based modulator, thereby enhancing the overall performance and lifespan of the device.

[0008] In one alternative embodiment, the substrate is a lithium niobate on insulator substrate, which includes a first substrate layer, a first insulating layer, and a lithium niobate thin film layer stacked together. The lithium niobate thin film layer is configured to form a lithium niobate waveguide by patterning. A first cladding layer covers the first insulating layer and the lithium niobate waveguide to form a lithium niobate structural layer.

[0009] Beneficial effects: Using lithium niobate on insulator substrates to fabricate lithium niobate waveguides, followed by the fabrication of silicon nitride waveguides and silicon-based components, helps reduce the contamination of subsequent structures by lithium niobate materials, improves the overall quality of devices, and provides a new approach to the fabrication of optoelectronic integrated chips, which helps promote industrialization and integration.

[0010] In one alternative embodiment, a silicon nitride structural layer is formed on the side of the lithium niobate structural layer facing away from the substrate layer, including: An initial silicon nitride device layer is formed on the entire side of the lithium niobate structural layer away from the substrate layer; The initial silicon nitride device layer is patterned to obtain a silicon nitride waveguide; A second cladding layer is disposed on the lithium niobate structural layer, which covers the surface of the lithium niobate structural layer and the silicon nitride waveguide.

[0011] Beneficial effects: A silicon nitride waveguide is formed on top of the lithium niobate structure layer through a whole-surface deposition and patterning process, thereby forming a composite waveguide structure of lithium niobate-silicon nitride. The silicon nitride waveguide can be shaped into a strip waveguide, which facilitates strong coupling with the lithium niobate waveguide, thereby obtaining a smaller optical mode field and improving modulation efficiency.

[0012] In one alternative embodiment, a silicon-based structural layer is formed on the side of the silicon nitride structural layer facing away from the substrate layer, including: An initial silicon device layer is formed on the entire side of the silicon nitride structure layer that is away from the substrate layer. The initial silicon device layer is patterned to obtain the initial silicon probe element and the initial silicon modulation element; The initial silicon probe element and the initial silicon modulation element are doped to obtain a doped silicon probe element and a doped silicon modulation element, and the doped silicon modulation element forms a silicon-based modulation unit. A first sub-cladding layer is disposed on the silicon nitride structure layer, the first sub-cladding layer covering the surface of the silicon nitride structure layer as well as the doped silicon probe element and the doped silicon modulation element; An epitaxial window is formed in the first sub-cladding layer, exposing at least a portion of the doped silicon probe element; A germanium element is placed inside the epitaxial window, and the germanium element and the doped silicon detection element constitute a germanium-silicon detection unit. A second sub-cladding layer is disposed on the first sub-cladding layer, the second sub-cladding layer covering the surface of the first sub-cladding layer and the germanium-silicon detection unit, and the first sub-cladding layer and the second sub-cladding layer constitute a third cladding layer.

[0013] Beneficial effects: The silicon-based structural layer of this invention first forms a doped silicon probe element and a doped silicon modulation element, with the doped silicon modulation element forming a silicon-based modulation unit; then, a germanium element is formed on the doped silicon probe element through epitaxial growth technology, thereby constituting a germanium-silicon probe unit. This post-epitaxy process can reduce the impact of the heating and cooling process on the dark current and lattice defects of the epitaxial germanium crystal; and then, the silicon-based element is protected by a cladding material, resulting in a stable, reliable, and high-quality silicon-based structural layer.

[0014] In one alternative embodiment, an initial silicon device layer is formed on the entire side of the silicon nitride structure layer facing away from the substrate layer, including: A silicon-on-insulator substrate is provided, the silicon-on-insulator substrate comprising a second substrate layer, a second insulating layer and an initial silicon device layer stacked thereon; With the initial silicon device layer facing the silicon nitride structure layer, the silicon-on-insulator substrate is bonded to the surface of the silicon nitride structure layer on the side away from the substrate layer; Remove the second substrate layer and the second insulating layer.

[0015] Beneficial effects: The method of bonding silicon-on-insulator substrates to silicon nitride structural layers and then removing the thick silicon layer and insulating layer in stages to the initial silicon device layer helps to accurately preserve the high-quality initial silicon device layer.

[0016] In one alternative implementation, forming the electrode structure includes: A first electrode and a second electrode are formed that penetrate the third cladding layer. The first electrode is connected to a germanium-silicon detection unit, and the second electrode is connected to a silicon-based modulation unit. A third electrode is formed that extends into the third cladding and the second cladding. The third electrode is located beside the silicon nitride waveguide and is spaced apart from the silicon nitride waveguide and the lithium niobate waveguide.

[0017] Beneficial effects: First, metal electrodes are formed to connect silicon-based components such as the germanium-silicon detection unit and the silicon-based modulation unit. These first and second electrodes can be fabricated using tungsten metal, which is then clad. Next, the modulation electrode of the lithium niobate-silicon nitride composite waveguide modulator, i.e., the third electrode, is formed. This third electrode can be fabricated using copper metal. This approach is suitable for integrating different metal electrodes on the same chip. For example, a fabrication process that first creates the tungsten metal electrode and then the copper metal electrode avoids the thermal damage and electromigration risks to the copper electrode caused by subsequent high-temperature dielectric processes. Furthermore, the tungsten plug acts as a barrier layer to effectively isolate copper ions from contaminating the germanium detection area and the silicon doped area. Simultaneously, it ensures the uniformity of deep trench etching and the filling quality of the damascene process, significantly improving the chip's reliability and high-frequency performance.

[0018] In one alternative embodiment, forming a first electrode and a second electrode through the third cladding includes: A first electrode hole and a second electrode hole are formed that penetrate the third cladding layer, with a germanium-silicon detection unit exposed in the first electrode hole and a silicon-based modulation unit exposed in the second electrode hole. A first metallic material is filled into the first electrode hole and the second electrode hole to form a first electrode connecting the germanium-silicon detection unit and a second electrode connecting the silicon-based modulation unit. A fourth cladding layer is formed on the third cladding layer, covering the third cladding layer, the first electrode, and the second electrode.

[0019] Beneficial effects: The metal electrodes of the germanium-silicon detector and silicon-based modulator in this invention are made of tungsten metal, which has excellent vertical conductivity. The device is prepared by slotting and filling metal, and CMP is used to grind off the excess tungsten on the surface, forming a dense tungsten capping layer on the surface of the silicon / germanium device. This design ensures that even if copper ions have a tendency to diffuse, they will be blocked by the tungsten metal below during subsequent copper electroplating and damascus processes, and the risk of copper contamination is completely isolated, which greatly improves the signal-to-noise ratio and yield of the germanium detector.

[0020] In one alternative embodiment, forming a third electrode that extends at least into the third cladding layer and the second cladding layer includes: A third electrode hole is formed extending from the surface of the fourth cladding layer into at least the fourth cladding layer, the third cladding layer, and the second cladding layer, as well as a first contact groove and a second contact groove penetrating the fourth cladding layer; the third electrode hole is located beside the silicon nitride waveguide and on the side of the lithium niobate waveguide relatively far from the substrate layer, and the third electrode hole is spaced apart from the silicon nitride waveguide and the lithium niobate waveguide; the first contact groove exposes the first electrode, and the second contact groove exposes the second electrode; A second metal material is filled into the third electrode hole, the first contact groove, and the second contact groove to form a third electrode, a first contact electrode connected to the first electrode, and a second contact electrode connected to the second electrode.

[0021] Beneficial effects: The modulation electrodes of the composite waveguide modulator are made of copper metal. The large cross-sectional area of ​​copper metal can carry high-frequency radio frequency signals and improve modulation efficiency. At the same time, copper contact electrodes are also set on the tungsten metal electrodes of the germanium-silicon detector and the silicon-based modulator to reduce signal input and output losses.

[0022] In one optional embodiment, after forming the electrode structure, the method further includes: forming a first interconnect electrode on the first electrode, forming a second interconnect electrode on the second electrode, and forming a third interconnect electrode on the third electrode; wherein the cross-sectional dimension of the first interconnect electrode is larger than the cross-sectional dimension of the first electrode, the cross-sectional dimension of the second interconnect electrode is larger than the cross-sectional dimension of the second electrode, and the cross-sectional dimension of the third interconnect electrode is larger than the cross-sectional dimension of the third electrode.

[0023] Beneficial effects: Such larger cross-sectional interconnect electrodes facilitate electrical connections between the first, second, and third electrodes and the outside, reduce signal transmission resistance, and improve signal transmission efficiency.

[0024] Secondly, the present invention also provides a heterogeneous integrated optoelectronic chip, comprising: a substrate layer, a lithium niobate structural layer, a silicon nitride structural layer, a silicon structural layer, and an electrode structure. The lithium niobate structural layer is formed on one side surface of the substrate layer, and includes a lithium niobate waveguide and a first cladding layer covering the lithium niobate waveguide. The silicon nitride structural layer is formed on the side of the lithium niobate structural layer opposite to the substrate layer, and includes a silicon nitride waveguide and a second cladding layer covering the silicon nitride waveguide. The projection of the silicon nitride waveguide onto the substrate layer is located within the projection region of the lithium niobate waveguide onto the substrate layer, and the silicon nitride waveguide and the lithium niobate waveguide form a composite waveguide structure. A structural layer is formed on the side of the silicon nitride structural layer away from the substrate layer. The silicon-based structural layer includes multiple silicon-based units and a third cladding layer covering the silicon-based units. The silicon-based units include a germanium-silicon detection unit and a silicon-based modulation unit. The electrode structure includes a first electrode for connecting the germanium-silicon detection unit, a second electrode for connecting the silicon-based modulation unit, and a third electrode located beside the silicon nitride waveguide and above the lithium niobate waveguide. The germanium-silicon detection unit and the first electrode are configured to form a germanium-silicon detector, the silicon-based modulation unit and the second electrode are configured to form a silicon-based modulator, and the composite waveguide structure and the third electrode are configured to form a composite waveguide modulator.

[0025] Beneficial effects: The heterogeneous integrated optoelectronic chip of the present invention features a lithium niobate and silicon nitride composite waveguide structure with the lithium niobate waveguide at the bottom and the silicon nitride waveguide at the top. This structure can effectively improve bandwidth, reduce driving voltage, and achieve lower power consumption. It can also ensure the optical mode field between the lithium niobate and silicon nitride waveguides, thereby improving modulation efficiency. Furthermore, the modulation electrode corresponding to the lithium niobate-silicon nitride composite waveguide structure, i.e., the third electrode, is located above the lithium niobate waveguide, which is arranged in a large area. This structure reduces the spatial deviation between the center of the electric field generated by the third electrode and the center of the optical mode field, ensuring the interaction efficiency between the electric field and the optical field and the modulation efficiency of the modulator. Then, a silicon-based structure layer including a germanium-silicon detector unit and a silicon-based modulation unit is formed on top of the silicon nitride structure layer. Finally, the electrode structure is formed to achieve efficient integration of different optoelectronic devices such as lithium niobate-silicon nitride composite waveguide modulator, silicon-based modulator, and germanium-silicon detector on the same chip, effectively saving device volume, reducing production costs, and reducing optical loss of device coupling.

[0026] This design, with the lithium niobate waveguide at the bottom, the silicon nitride waveguide next, and the germanium-silicon detector and silicon-based modulation unit on top, effectively ensures a strongly coupled optical mode field between the lithium niobate and silicon nitride waveguides, improving the modulation efficiency of the lithium niobate-silicon nitride composite waveguide modulator. Furthermore, compared to schemes where subsequent heating and cooling processes affect the performance of the doped silicon-based units when the silicon-based structure layer is formed first, this design, with the silicon-based unit formed last, effectively reduces such performance impact, improves the detection sensitivity of the germanium-silicon detector and the modulation efficiency of the silicon-based modulator, thereby enhancing the overall performance and lifespan of the device. Attached Figure Description

[0027] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1 This is a schematic flowchart of the fabrication method of a heterogeneous integrated optoelectronic chip according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a lithium niobate substrate on an insulator according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a lithium niobate waveguide formed on a substrate layer according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure after a first cladding layer is formed on a lithium niobate waveguide to form a lithium niobate structural layer, according to an embodiment of the present invention. Figure 5 This is a schematic diagram of the structure after the initial silicon nitride device layer is formed on the lithium niobate structural layer according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after the initial silicon nitride device layer is patterned to form a silicon nitride waveguide according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure after a second cladding layer is formed on the silicon nitride waveguide to form a silicon nitride structural layer, according to an embodiment of the present invention. Figure 8 This is a schematic diagram of the structure of the silicon insulator-on-silicon substrate bonded to the silicon nitride structural layer according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure after the second substrate layer and the second insulating layer of the silicon-on-insulator substrate are removed, and an initial silicon device layer is formed on the silicon nitride structure layer according to an embodiment of the present invention. Figure 10 This is a schematic diagram of the structure of silicon devices such as initial silicon probe elements, initial silicon modulation elements, grating structures and silicon waveguides after patterning the initial silicon device layer according to an embodiment of the present invention. Figure 11 This is a schematic diagram of the structure of the initial silicon detector element and the initial silicon modulation element after doping to form a doped silicon detector element and a doped silicon modulation element according to an embodiment of the present invention; Figure 12 This is a schematic diagram of the structure after the first sub-cladding layer is formed on the silicon-doped detector element and the silicon-doped modulation element according to an embodiment of the present invention; Figure 13 This is a schematic diagram of the structure after an epitaxial window is opened in the first sub-cladding layer on the doped silicon detector element according to an embodiment of the present invention. Figure 14 This is a schematic diagram of the structure of a germanium-silicon detector element formed by setting a germanium element in the epitaxial window according to an embodiment of the present invention; Figure 15 This is a schematic diagram of the structure after a third cladding layer is formed by setting a second sub-cladding layer on the first sub-cladding layer, which is also a silicon-based structural layer according to an embodiment of the present invention. Figure 16 This is a schematic diagram of the structure after the first electrode hole and the second electrode hole are opened in the cladding structure according to an embodiment of the present invention; Figure 17 This is a schematic diagram of the structure after the formation of the first electrode and the second electrode according to an embodiment of the present invention; Figure 18 This is a schematic diagram of the structure after the fourth cladding layer is covered on the first and second electrodes according to an embodiment of the present invention; Figure 19 This is a schematic diagram of the structure after the third electrode hole, the first contact groove and the second contact groove are formed in the cladding structure according to an embodiment of the present invention. Figure 20 This is a schematic diagram of the structure after forming the third electrode, the first contact electrode, and the second contact electrode according to an embodiment of the present invention; Figure 21 This is a schematic diagram of the structure after a fifth cladding layer is provided on the third electrode according to an embodiment of the present invention; Figure 22 This is a schematic diagram of the structure after the interconnection slots are formed in the fifth cladding layer according to an embodiment of the present invention; Figure 23 This is a schematic diagram of the structure of a heterogeneous integrated optoelectronic chip according to an embodiment of the present invention.

[0029] Explanation of reference numerals in the attached figures: 1. Substrate layer; 11. First substrate layer; 12. First insulating layer; 13. Lithium niobate thin film layer; 2. Lithium niobate structural layer; 21. Lithium niobate waveguide; 22. First cladding; 3. Silicon nitride structural layer; 31. Silicon nitride waveguide; 32. Second cladding layer; 30. Initial silicon nitride device layer; 4. Silicon-based structural layer; 41. Silicon-based unit; 411. Germanium-silicon detector unit; 4110. Initial silicon detector element; 4111. Doped silicon detector element; a1. First lightly doped region; a2. First heavily doped region; b1. Second lightly doped region; b2. Second heavily doped region; 4112. Germanium element; 412. Silicon-based modulation unit; 4120. Initial silicon modulation element; 4121. Doped silicon modulation element; a3. Third lightly doped region; a4. Third heavily doped region; b3. Fourth lightly doped region; b4. Fourth heavily doped region; 413. Grating unit; 414. Silicon waveguide; 42. Third cladding; 421. First sub-cladding; 422. Second sub-cladding; 40. Silicon-on-insulator substrate; 401. Second substrate layer; 402. Second insulating layer; 403. Initial silicon device layer; 5. Electrode structure; 51. First electrode; 52. Second electrode; 53. Third electrode; 61. First contact electrode; 62. Second contact electrode; 71. First interconnect electrode; 72. Second interconnect electrode; 73. Third interconnect electrode; 8. Fourth cladding layer; 9. Fifth cladding layer; A. Extension window; B1. First electrode hole; B2. Second electrode hole; B3. Third electrode hole; C1. First contact groove; C2. Second contact groove; D1. First interconnect groove; D2. Second interconnect groove; D3. Third interconnect groove. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] like Figures 1 to 23 As shown, this embodiment provides a method for fabricating a heterogeneous integrated optoelectronic chip. Figure 1 The diagram below illustrates the process of this preparation method, which specifically includes the following steps: Step S100: Provide the base layer 1.

[0032] For example, such as Figure 2 As shown, the substrate 1 can be a lithium niobate on insulator substrate, and the upper lithium niobate thin film layer 13 can be used to form a lithium niobate waveguide 21.

[0033] In step S200, a lithium niobate structure layer 2 is formed on one side surface of the substrate layer 1. The lithium niobate structure layer 2 includes a lithium niobate waveguide 21 and a first cladding layer 22 covering the lithium niobate waveguide 21.

[0034] refer to Figure 3 and Figure 4 According to design requirements, a lithium niobate waveguide 21 is first formed on one side of the substrate 1. Then, silicon dioxide material is deposited on it to form a cladding of the lithium niobate waveguide 21 and the exposed surface of the substrate 1. The surface of the first cladding 22 can also be chemically mechanically polished (CMP) to achieve surface planarization while ensuring that the thickness of the portion of the first cladding 22 above the lithium niobate waveguide 21 is less than 100 nm. This ensures the optical mode field between the subsequent lithium niobate waveguide 21 and the silicon nitride waveguide 31, improving modulation efficiency.

[0035] In step S300, a silicon nitride structure layer 3 is formed on the side of the lithium niobate structure layer 2 away from the substrate layer 1. The silicon nitride structure layer 3 includes a silicon nitride waveguide 31 and a second cladding 32 covering the silicon nitride waveguide 31. The projection of the silicon nitride waveguide 31 onto the substrate layer 1 is located within the projection area of ​​the lithium niobate waveguide 21 onto the substrate layer 1. The silicon nitride waveguide 31 and the lithium niobate waveguide 21 form a composite waveguide structure.

[0036] refer to Figures 5 to 7According to design requirements, a silicon nitride waveguide 31 is first formed on the lithium niobate structural layer 2, and then silicon dioxide material is deposited on it again to form a second cladding 32 covering the lithium niobate waveguide 21 and the exposed lithium niobate structural layer 2. The silicon nitride waveguide 31 is correspondingly positioned above the lithium niobate waveguide 21, and the two together form a lithium niobate-silicon nitride composite waveguide structure, which is used to form a lithium niobate-silicon nitride composite waveguide modulator.

[0037] In step S400, a silicon-based structure layer 4 is formed on the side of the silicon nitride structure layer 3 away from the substrate layer 1. The silicon-based structure layer 4 includes a variety of silicon-based units 41 and a third cladding layer 42 covering the silicon-based units 41. The silicon-based units 41 include germanium-silicon detection units 411 and silicon-based modulation units 412.

[0038] refer to Figures 8 to 15 For example, a variety of silicon-based units 41, such as germanium-silicon detection units 411, silicon-based modulation units 412, grating units 413, silicon waveguides 414, etc., can be formed on the silicon nitride structure layer 3 first; then a third cladding layer 42 covering the various silicon-based units 41 is formed.

[0039] In step S500, an electrode structure 5 is formed. The electrode structure 5 includes a first electrode 51 for connecting the germanium-silicon detection unit 411, a second electrode 52 for connecting the silicon-based modulation unit 412, and a third electrode 53 located beside the silicon nitride waveguide 31 and above the lithium niobate waveguide 21. The germanium-silicon detection unit 411 and the first electrode 51 are configured to form a germanium-silicon detector, the silicon-based modulation unit 412 and the second electrode 52 are configured to form a silicon-based modulator, and the composite waveguide structure and the third electrode 53 are configured to form a composite waveguide modulator.

[0040] For example, an electrode structure 5 is formed in the cladding structure consisting of the first cladding layer 22, the second cladding layer 32, the third cladding layer 42, and other cladding materials. For instance, a first electrode 51 is formed in connection with the germanium-silicon detection unit 411, a second electrode 52 is formed in connection with the silicon-based detection unit, and a third electrode 53 is formed in connection with the composite waveguide structure, projected into the lithium niobate waveguide 21 and adjacent to the silicon nitride waveguide 31. The end of the third electrode 53 near the lithium niobate waveguide 21 is flush with the end of the silicon nitride waveguide 31 near the lithium niobate waveguide 21. This geometric configuration allows the region with the strongest electric field generated by the third electrode 53 to be located in the bottom region of the silicon nitride waveguide 31 near the lithium niobate interface. This position coincides spatially with the concentrated region of the optical mode field of the modulation region, thereby maximizing the overlap integral of the electric field and the optical field, significantly improving the electro-optic modulation efficiency and reducing the half-wave voltage, thus forming a high-quality optoelectronic chip integrating various optoelectronic devices.

[0041] In summary, the fabrication method of the heterogeneous integrated optoelectronic chip in this embodiment first forms a lithium niobate structural layer 2 including a lithium niobate waveguide 21, and then forms a silicon nitride structural layer 3 including a silicon nitride waveguide 31 on top of it, thereby forming a composite waveguide structure of lithium niobate and silicon nitride. This can effectively improve bandwidth, reduce driving voltage, and achieve lower power consumption, and can also ensure the optical mode field between the lithium niobate waveguide 21 and the silicon nitride waveguide 31, improving modulation efficiency. Then, a silicon-based structural layer 4 including a germanium-silicon detector unit 411 and a silicon-based modulation unit 412 is fabricated above the silicon nitride structural layer 3, and finally... Electrode structure 5, in which the modulation electrode corresponding to the lithium niobate-silicon nitride composite waveguide structure, namely the third electrode 53, is located above the lithium niobate waveguide 21 which is arranged in a large area. This structure reduces the spatial deviation between the center of the electric field generated by the third electrode 53 and the center of the optical mode field, ensuring the interaction efficiency of the electric field and the optical field and the modulation efficiency of the modulator. In this way, different optoelectronic devices such as lithium niobate-silicon nitride composite waveguide modulator, silicon-based modulator, and germanium-silicon detector can be efficiently integrated on the same chip, effectively saving device volume, reducing production costs, and reducing optical loss of device coupling.

[0042] Based on this, the design of forming the lithium niobate waveguide 21 first, and then forming the germanium-silicon detection unit 411 and the silicon-based modulation unit 412, can effectively ensure the formation of a strongly coupled optical mode field between the lithium niobate waveguide 21 and the silicon nitride waveguide 31, thereby improving the modulation efficiency of the lithium niobate-silicon nitride composite waveguide modulator. On the other hand, compared with the scheme where the subsequent heating and cooling process affects the performance of the doped silicon-based unit 41 when the silicon-based structure layer 4 is formed first, the design of forming the silicon-based unit 41 later in this embodiment can effectively reduce such performance impact, improve the detection sensitivity of the germanium-silicon detector and the modulation efficiency of the silicon-based modulator, thereby improving the overall performance and service life of the device.

[0043] In some embodiments, such as Figures 2 to 4 As shown, the substrate 1 is a lithium niobate on insulator substrate, which includes a first substrate layer 11, a first insulating layer 12 and a lithium niobate thin film layer 13 stacked together. The lithium niobate thin film layer 13 is configured to form a lithium niobate waveguide 21 by patterning. The first cladding layer 22 covers the first insulating layer 12 and the lithium niobate waveguide 21 to form a lithium niobate structure layer 2.

[0044] For example, the first substrate layer 11 can be a thick silicon layer with a thickness between 500 μm and 750 μm, the first insulating layer 12 can be a silicon dioxide layer with a thickness between 1 μm and 3 μm, and the lithium niobate thin film layer 13 has a thickness between 100 nm and 600 nm. In this embodiment, lithium niobate on an insulator substrate is first used to fabricate the lithium niobate waveguide 21, and then the silicon nitride waveguide 31 and silicon-based components are fabricated. This helps to reduce the contamination of the lithium niobate material on the subsequent structure, improve the overall quality of the device, and provides a new approach to the fabrication of optoelectronic integrated chips, which helps to promote industrialization and integration.

[0045] like Figures 5 to 7 As shown, in some embodiments, step S200, which involves forming a silicon nitride structure layer 3 on the side of the lithium niobate structure layer 2 opposite to the substrate layer 1, specifically includes the following steps: Step S201: An initial silicon nitride device layer 30 is formed on the side of the lithium niobate structure layer 2 facing away from the substrate layer 1.

[0046] like Figure 5 As shown, a silicon nitride thin film with a thickness between 200 nm and 400 nm can be deposited on the lithium niobate structural layer 2 by plasma enhanced chemical vapor deposition (PECVD) process, and then the surface is planarized by chemical mechanical polishing (CMP).

[0047] Step S202: The initial silicon nitride device layer 30 is patterned to obtain the silicon nitride waveguide 31.

[0048] like Figure 6 As shown, silicon nitride waveguides 31 can be formed by patterning the silicon nitride thin film deposited on the entire surface, such as by photolithography and etching. Multiple silicon nitride waveguides 31 can be formed at the same time. Some of the silicon nitride waveguides 31 can be combined with lithium niobate to form lithium niobate-silicon nitride composite waveguides. Other silicon nitride waveguides 31 can be used alone or coupled with silicon waveguides 414 to form silicon-silicon nitride composite waveguides.

[0049] Step S203: A second cladding layer 32 is formed on the lithium niobate structural layer 2, the second cladding layer 32 covering the surface of the lithium niobate structural layer 2 and the silicon nitride waveguide 31.

[0050] like Figure 7 As shown, a silicon dioxide thin film can be deposited by PECVD process, and then its surface can be planarized by CMP process, for example, so that the thickness of the silicon dioxide material on the silicon nitride waveguide 31 is between 50nm and 150nm and the roughness is less than 0.5nm.

[0051] In summary, silicon nitride waveguide 31 is formed on top of lithium niobate structural layer 2 through whole-surface deposition and patterning processes, thereby forming a composite waveguide structure of lithium niobate-silicon nitride. Silicon nitride waveguide 31 can be shaped into a strip waveguide, which facilitates strong coupling with lithium niobate waveguide 21, thereby obtaining a smaller optical mode field and improving modulation efficiency.

[0052] In some embodiments, such as Figures 8 to 15 As shown, step S300, which involves forming a silicon-based structural layer 4 on the side of the silicon nitride structural layer 3 facing away from the substrate layer 1, specifically includes the following steps: S301, an initial silicon device layer 403 is formed on the side of the silicon nitride structure layer 3 facing away from the substrate layer 1.

[0053] For example, the initial silicon device layer 403 can be formed on the silicon nitride structure layer 3 by bonding a silicon substrate using a smart-cut technique or by directly bonding a silicon-on-insulator substrate 40, etc. Figure 8 and Figure 9 As shown.

[0054] S302, the initial silicon device layer 403 is patterned to obtain the initial silicon probe element 4110 and the initial silicon modulation element 4120.

[0055] like Figure 10 As shown, by patterning the initial silicon device layer 403, silicon structures such as grating structures, silicon waveguide structures 414, silicon substrate structures of detectors (i.e., initial silicon detector elements 4110), and silicon substrate structures of modulators (i.e., initial silicon modulation elements 4120) are formed by photolithography and etching.

[0056] S303, the initial silicon probe element 4110 and the initial silicon modulation element 4120 are doped to obtain a doped silicon probe element 4111 and a doped silicon modulation element 4121, and the doped silicon modulation element 4121 forms a silicon-based modulation unit 412.

[0057] like Figure 11As shown, the initial silicon detector element 4110 and the initial silicon modulation element 4120 are subjected to a doping process in specific regions. For example, the first doping of the first doping type and the second doping type are performed sequentially. In the first doping type and the second doping type, one of them is P-type and the other is N-type. This forms a first lightly doped region a1 and a second lightly doped region b1 with opposite doping types in the initial silicon detector element 4110, and a third lightly doped region a3 and a fourth lightly doped region b3 with opposite doping types in the initial silicon modulation element 4120. The first lightly doped region a1 and the third lightly doped region a3 have the same doping type, and the second lightly doped region b1 and the fourth lightly doped region b3 have the same doping type. Then, a second doping of the first and second doping types is performed to form a first heavily doped region a2 of the same doping type in the edge region of the first lightly doped region a1, a second heavily doped region b2 of the same doping type in the edge region of the second lightly doped region b1, a third heavily doped region a4 of the same doping type in the edge region of the third lightly doped region a3, and a fourth heavily doped region b4 of the same doping type in the edge region of the fourth lightly doped region b3. For example, a doped detection element including P+, P, N, N+ and other doped regions, and a doped modulation element including P+, P, N, N+ and other doped regions can be obtained. After doping is completed, the doped elements in the silicon device layer can be activated by a rapid annealing process to form the final doped detection element and doped modulation element.

[0058] S304, a first sub-cladding layer 421 is provided on the silicon nitride structure layer 3, the first sub-cladding layer 421 covers the surface of the silicon nitride structure layer 3 and the silicon doped probe element 4111 and the silicon doped modulation element 4121.

[0059] like Figure 12 As shown, a silicon dioxide thin film can be deposited by PECVD process, and then its surface can be planarized by CMP process to form the first sub-cladding layer 421.

[0060] S305, an epitaxial window A is opened in the first sub-cladding 421, and the epitaxial window A exposes at least part of the doped silicon probe element 4111.

[0061] like Figure 13 As shown, the region for epitaxial growth of germanium single crystal can be etched in the first sub-cladding 421 above the doped silicon detector element 4111 by an etching process, with the etching stopping on the doped silicon detector element 4111; then a thin layer of silicon oxide is grown by thermal oxidation, and then this thin layer of silicon oxide is quickly bleached away by hydrofluoric acid solution to reduce the etching damage to the surface of the doped silicon detector element 4111 by subsequent processes, which helps to epitaxially grow high-quality, low-defect germanium single crystal.

[0062] S306, a germanium element 4112 is provided in the epitaxial window A. The germanium element 4112 and the doped silicon detector element 4111 constitute a germanium-silicon detector unit 411.

[0063] like Figure 14 As shown, a high-quality, low-defect germanium single crystal is grown in the epitaxial window A by germanium epitaxy to form a germanium element 4112 with a thickness between 300 nm and 600 nm on the doped detector element. Specifically, the germanium element 4112 is formed on the first lightly doped region a1 and the second lightly doped region b1 of the doped silicon detector element 4111; then the surface is planarized by CMP process.

[0064] S307, a second sub-cladding layer 422 is disposed on the first sub-cladding layer 421. The second sub-cladding layer 422 covers the surface of the first sub-cladding layer 421 and the germanium-silicon detection unit 411. The first sub-cladding layer 421 and the second sub-cladding layer 422 constitute a third cladding layer 42.

[0065] like Figure 15 As shown, a silicon dioxide thin film with a thickness of 500 nm is deposited again by PECVD process, and then its surface is planarized by CMP process to obtain the second sub-cladding layer 422. The second sub-cladding layer 422 and the first sub-cladding layer 421 formed earlier together constitute the third cladding layer 42 covering the silicon-based device, and finally the silicon-based structure layer 4 is obtained.

[0066] In summary, in this embodiment, the silicon-based structural layer 4 first forms a doped silicon detector element 4111 and a doped silicon modulation element 4121, with the doped silicon modulation element 4121 forming a silicon-based modulation unit 412. Then, a germanium element 4112 is formed on the doped silicon detector element 4111 using epitaxial growth technology, thereby constituting a germanium-silicon detector unit 411. This post-epitaxy process can reduce the impact of heating and cooling processes on the dark current and lattice defects of the epitaxial germanium crystal. Finally, a cladding material is used to protect the silicon-based element, resulting in a stable, reliable, and high-quality silicon-based structural layer 4.

[0067] Furthermore, such as Figure 8 and Figure 9 As shown, step S301, which forms the initial silicon device layer 403 on the entire side of the silicon nitride structure layer 3 facing away from the substrate layer 1, specifically includes the following steps: Step S3011: Provide a silicon-on-insulator substrate 40, which includes a second substrate layer 401, a second insulating layer 402, and an initial silicon device layer 403 stacked together.

[0068] Specifically, a silicon-on-insulator substrate 40 is prepared, and the surface of the initial material layer therein and the surface of the subsequently bonded silicon nitride structure layer 3 are subjected to plasma activation.

[0069] In step S3012, with the initial silicon device layer 403 facing the silicon nitride structure layer 3, the silicon-on-insulator substrate 40 is bonded to the side surface of the silicon nitride structure layer 3 facing away from the base layer 1.

[0070] Specifically, the surface of the initial material layer is oriented towards the surface of the silicon nitride structural layer 3 to achieve direct bonding between the two, and then annealing is performed to enhance the bonding strength.

[0071] Step S3013: Remove the second substrate layer 401 and the second insulating layer 402.

[0072] Specifically, the second substrate layer 401 on the back side of the silicon substrate 40 on the insulator is removed by a grinding process, and then fine grinding stops at the surface of the second insulating layer 402; then the second insulating layer 402 is removed by a CMP process, which stops at the initial silicon device layer 403. Since the thickness of the thick silicon layer of the second substrate layer 401 ranges from 500μm to 750μm, and the thickness of the second insulating layer 402 is from 1 to 3μm, this stepwise removal of the thick silicon layer and the insulating layer helps to accurately preserve the initial silicon device layer 403.

[0073] In some embodiments, reference Figures 16 to 23 The step S400 of forming electrode structure 5 specifically includes the following steps: Step S401: A first electrode 51 and a second electrode 52 are formed through the third cladding 42. The first electrode 51 is connected to the germanium-silicon detection unit 411, and the second electrode 52 is connected to the silicon-based modulation unit 412. In step S402, a third electrode 53 is formed that extends into at least the third cladding 42 and the second cladding 32. The third electrode 53 is located beside the silicon nitride waveguide 31 and is spaced apart from the silicon nitride waveguide 31 and the lithium niobate waveguide 21.

[0074] That is, firstly, metal electrodes are formed to connect silicon-based elements such as the germanium-silicon detection unit 411 and the silicon-based modulation unit 412. Such first electrodes 51 and second electrodes 52 can be made of tungsten metal, which is then clad. Then, the modulation electrode of the lithium niobate-silicon nitride composite waveguide modulator, i.e., the third electrode 53, is formed. The third electrode 53 can be made of copper metal. This fabrication process of first making the tungsten metal electrode and then the copper metal electrode avoids the risk of thermal damage and electromigration to the copper electrode by the subsequent high-temperature dielectric process. It also uses the tungsten plug as a barrier layer to effectively isolate the contamination of the germanium detection area and the silicon doped area by copper ions. At the same time, it ensures the uniformity of deep trench etching and the filling quality of the damascene process, which significantly improves the reliability and high-frequency performance of the chip.

[0075] In some embodiments, specifically, step S401 of forming the first electrode 51 and the second electrode 52 penetrating the third cladding layer 42 specifically includes the following steps: In step S4011, a first electrode hole B1 and a second electrode hole B2 are formed that penetrate the third cladding 42, with a germanium-silicon detection unit 411 exposed in the first electrode hole B1 and a silicon-based modulation unit 412 exposed in the second electrode hole B2.

[0076] like Figure 16 As shown, electrode holes corresponding to the germanium-silicon detector and the silicon-based modulator are prepared by etching process. Specifically, different first electrode holes B1 are connected to the first heavily doped region a2 and the second heavily doped region b2 of the germanium-silicon detector unit 411, respectively, and different second electrode holes B2 are connected to the third heavily doped region a4 and the fourth heavily doped region b4 of the silicon-based modulator unit 412, respectively.

[0077] In step S4012, a first metal material is filled into the first electrode hole B1 and the second electrode hole B2 to form a first electrode 51 connecting the germanium-silicon detection unit 411 and a second electrode 52 connecting the silicon-based modulation unit 412.

[0078] like Figure 17 As shown, tungsten metal can be filled into the first electrode hole B1 and the second electrode hole B2 by chemical vapor deposition (CVD) of tungsten; then, the excess tungsten metal on the surface is removed by damascus process to form a first electrode 51 that connects the first heavily doped region a2 and the second heavily doped region b2, and a second electrode 52 that connects the third heavily doped region a4 and the fourth heavily doped region b4.

[0079] In step S4013, a fourth cladding layer 8 is formed on the third cladding layer 42, and the fourth cladding layer 8 covers the third cladding layer 42, the first electrode 51, and the second electrode 52.

[0080] like Figure 18 As shown, a silicon dioxide thin film is deposited over the first electrode 51 and the second electrode 52 using a PECVD process, and then its surface is planarized using a CMP process to obtain a fourth cladding layer 8 covering the third cladding layer 42 and the surfaces of the first electrode 51 and the second electrode 52.

[0081] In summary, the metal electrodes of the germanium-silicon detector and the silicon-based modulator in this embodiment are made of tungsten metal, which has excellent vertical conductivity. The device is fabricated by slotting and filling metal, and CMP is used to grind off the excess tungsten on the surface, forming a dense tungsten capping layer on the surface of the silicon / germanium device. This design ensures that even if copper ions have a tendency to diffuse, they will be blocked by the tungsten metal below during subsequent copper electroplating and damascus processes, completely isolating the risk of copper contamination and greatly improving the signal-to-noise ratio and yield of the germanium detector.

[0082] In some embodiments, specifically, step S402, which forms at least the third electrode 53 extending into the third cladding layer 42 and the second cladding layer 32, specifically includes the following steps: In step S4021, a third electrode hole B3 is formed that extends from the surface of the fourth cladding layer 8 into at least the fourth cladding layer 8, the third cladding layer 42, and the second cladding layer 32, as well as a first contact groove C1 and a second contact groove C2 penetrating the fourth cladding layer 8. The third electrode hole B3 is located beside the silicon nitride waveguide 31 and on the side of the lithium niobate waveguide 21 that is relatively far from the substrate layer 1. The third electrode hole B3 is spaced apart from the silicon nitride waveguide 31 and the lithium niobate waveguide 21. The first contact groove C1 exposes the first electrode 51, and the second contact groove C2 exposes the second electrode 52.

[0083] like Figure 19 As shown, in the composite waveguide structure composed of silicon nitride waveguide 31 and lithium niobate waveguide 21, a third electrode hole B3 is formed in the cladding structure by etching process. At the same time, contact grooves are formed in the cladding material above the first electrode 51 and the second electrode 52, that is, in the fourth cladding 8. The first contact groove C1 is connected to the surface of the first electrode 51, and the second contact groove C2 is connected to the surface of the second electrode 52.

[0084] In step S4022, a second metal material is filled into the third electrode hole B3, the first contact groove C1 and the second contact groove C2 to form a third electrode 53, a first contact electrode 61 connected to the first electrode 51, and a second contact electrode 62 connected to the second electrode 52.

[0085] Specifically, in the fabrication of the third electrode 53 of the lithium niobate modulator, the germanium-silicon detector, and the metal contact electrode of the silicon-based modulator, a 30nm thick TaN / Ta barrier layer is first sputtered into the third electrode hole B3, the first contact groove C1, and the second contact groove C2; ​​then a 20nm thick copper seed layer is sputtered; subsequently, a large amount of copper metal is filled by electroplating, and excess copper metal is removed by damascus steel plating and CMP processes to obtain the third electrode 53, the first contact electrode 61, and the second contact electrode 62, as shown below. Figure 20 As shown.

[0086] In summary, the modulation electrodes of the composite waveguide modulator are made of copper metal, and the large cross-sectional area of ​​copper metal can carry high-frequency radio frequency signals, thereby improving modulation efficiency. At the same time, copper contact electrodes are also set on the tungsten metal electrodes of the germanium-silicon detector and the silicon-based modulator to reduce signal input and output losses.

[0087] In some embodiments, such as Figures 21 to 23 As shown, after step S400 of forming electrode structure 5, the method further includes: In step S500, a first interconnect electrode 71 is formed on the first electrode 51, a second interconnect electrode 72 is formed on the second electrode 52, and a third interconnect electrode 73 is formed on the third electrode 53; the cross-sectional dimension of the first interconnect electrode 71 is larger than the cross-sectional dimension of the first electrode 51, the cross-sectional dimension of the second interconnect electrode 72 is larger than the cross-sectional dimension of the second electrode 52, and the cross-sectional dimension of the third interconnect electrode 73 is larger than the cross-sectional dimension of the third electrode 53.

[0088] Such larger cross-sectional dimensions of interconnecting electrodes help to achieve electrical connections between the first electrode 51, the second electrode 52, and the third electrode 53 and the outside, reducing signal transmission resistance and improving signal transmission efficiency.

[0089] Specifically, step S500 above includes the following steps: In step S501, a fifth cladding layer 9 is formed on the fourth cladding layer 8, and the fifth cladding layer 9 covers the fourth cladding layer 8, the third electrode 53, the first contact electrode 61, and the second contact electrode 62.

[0090] like Figure 21 As shown, silicon dioxide material can be deposited over the entire surface of the third electrode 53, the first contact electrode 61, and the second contact electrode 62 using a PECVD process. The thickness of the silicon dioxide material is set to 3 μm, and then its surface is planarized using a CMP process.

[0091] In step S502, a first interconnect trench D1, a second interconnect trench D2, and a third interconnect trench D3 are formed that penetrate the fifth cladding layer 9. The first interconnect trench D1 exposes the first contact electrode 61, the second interconnect trench D2 exposes the second contact electrode 62, and the third interconnect trench D3 exposes the third electrode 53.

[0092] like Figure 22 As shown, interconnect trenches are etched using an etching process, with the etching stopping on the copper metal electrode.

[0093] In step S503, a third metal material is filled into the first interconnect trench D1, the second interconnect trench D2, and the third interconnect trench D3 to form a first interconnect electrode 71 located in the first interconnect trench D1, a second interconnect electrode 72 located in the second interconnect trench D2, and a third interconnect electrode 73 located in the third interconnect trench D3.

[0094] like Figure 23 As shown, the interconnecting electrodes are also made of copper metal to achieve reliable connection with the third electrode 53, the first contact electrode 61 and the second contact electrode 62, while ensuring electrical communication with the external structure.

[0095] like Figure 23As shown, this embodiment also provides a heterogeneous integrated optoelectronic chip, which is fabricated by the above-described method for preparing a heterogeneous integrated optoelectronic chip. The chip includes: a substrate layer 1, a lithium niobate structural layer 2, a silicon nitride structural layer 3, a silicon structural layer, and an electrode structure 5. The lithium niobate structural layer 2 is formed on one side surface of the substrate layer 1, and includes a lithium niobate waveguide 21 and a first cladding layer 22 covering the lithium niobate waveguide 21. The silicon nitride structural layer 3 is formed on the side of the lithium niobate structural layer 2 facing away from the substrate layer 1, and includes a silicon nitride waveguide 31 and a second cladding layer 32 covering the silicon nitride waveguide 31. The projection of the silicon nitride waveguide 31 onto the substrate layer 1 is located within the projection area of ​​the lithium niobate waveguide 21 onto the substrate layer 1. The silicon nitride waveguide 31 and the lithium niobate waveguide 21 form a composite waveguide structure. A silicon-based structural layer 4 is formed on the side of the silicon nitride structural layer 3 facing away from the substrate layer 1. The silicon-based structural layer 4 includes a variety of silicon-based units 41 and a third cladding layer 42 covering the silicon-based units 41. The silicon-based units 41 include a germanium-silicon detection unit 411 and a silicon-based modulation unit 412. The electrode structure 5 includes a first electrode 51 for connecting the germanium-silicon detection unit 411, a second electrode 52 for connecting the silicon-based modulation unit 412, and a third electrode 53 located beside the silicon nitride waveguide 31 and above the lithium niobate waveguide 21. The germanium-silicon detection unit 411 and the first electrode 51 are configured to form a germanium-silicon detector, the silicon-based modulation unit 412 and the second electrode 52 are configured to form a silicon-based modulator, and the composite waveguide structure and the third electrode 53 are configured to form a composite waveguide modulator.

[0096] In this embodiment of the heterogeneous integrated optoelectronic chip, the lithium niobate waveguide 21 is located below and the silicon nitride waveguide 31 is located above in the composite waveguide structure of lithium niobate and silicon nitride. This structure can effectively improve bandwidth, reduce driving voltage, and achieve lower power consumption. Furthermore, it can maintain the optical mode field between the lithium niobate waveguide 21 and the silicon nitride waveguide 31, improving modulation efficiency. The modulation electrode corresponding to the lithium niobate-silicon nitride composite waveguide structure, i.e., the third electrode 53, is located above the lithium niobate waveguide 21, which is arranged in a large area. This structure reduces the generation of optical signals by the third electrode 53. The spatial deviation between the center of the electric field and the center of the optical mode field ensures the interaction efficiency between the electric field and the optical field, as well as the modulation efficiency of the modulator. Then, a silicon-based structure layer 4, including a germanium-silicon detector unit 411 and a silicon-based modulation unit 412, is formed on top of the silicon nitride structure layer 3. Finally, an electrode structure 5 is formed to achieve efficient integration of different optoelectronic devices such as lithium niobate-silicon nitride composite waveguide modulator, silicon-based modulator, and germanium-silicon detector on the same chip, effectively saving device size, reducing production costs, and reducing optical loss of device coupling.

[0097] This design, with lithium niobate waveguide 21 at the bottom, silicon nitride waveguide 31 next, and germanium-silicon detector unit 411 and silicon-based modulation unit 412 on top, effectively ensures a strongly coupled optical mode field between lithium niobate waveguide 21 and silicon nitride waveguide 31, improving the modulation efficiency of the lithium niobate-silicon nitride composite waveguide modulator. Furthermore, compared to schemes where subsequent heating and cooling processes affect the performance of the doped silicon-based unit 41 when the silicon-based structure layer 4 is formed first, this design, with the silicon-based unit 41 formed last, effectively reduces such performance impact, improves the detection sensitivity of the germanium-silicon detector and the modulation efficiency of the silicon-based modulator, thereby enhancing the overall performance and lifespan of the device.

[0098] Further functional descriptions of the above structures are the same as those of the corresponding embodiments described above, and will not be repeated here.

[0099] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A method for fabricating a heterogeneous integrated optoelectronic chip, characterized in that, include: Provide a base layer; A lithium niobate structural layer is formed on one side surface of the substrate layer, the lithium niobate structural layer including a lithium niobate waveguide and a first cladding layer covering the lithium niobate waveguide; A silicon nitride structure layer is formed on the side of the lithium niobate structure layer away from the substrate layer. The silicon nitride structure layer includes a silicon nitride waveguide and a second cladding layer covering the silicon nitride waveguide. The projection of the silicon nitride waveguide on the substrate layer is located within the projection region of the lithium niobate waveguide on the substrate layer. The silicon nitride waveguide and the lithium niobate waveguide form a composite waveguide structure. A silicon-based structural layer is formed on the side of the silicon nitride structural layer opposite to the substrate layer. The silicon-based structural layer includes a variety of silicon-based units and a third cladding layer covering the silicon-based units. The silicon-based units include germanium-silicon detection units and silicon-based modulation units. An electrode structure is formed, the electrode structure including a first electrode for connecting the germanium-silicon detection unit, a second electrode for connecting the silicon-based modulation unit, and a third electrode located beside the silicon nitride waveguide and above the lithium niobate waveguide; the germanium-silicon detection unit and the first electrode are configured to form a germanium-silicon detector, the silicon-based modulation unit and the second electrode are configured to form a silicon-based modulator, and the composite waveguide structure and the third electrode are configured to form a composite waveguide modulator.

2. The method for fabricating a heterogeneous integrated optoelectronic chip according to claim 1, characterized in that, The substrate is a lithium niobate on insulator substrate, which includes a first substrate layer, a first insulating layer and a lithium niobate thin film layer stacked together. The lithium niobate thin film layer is patterned to form the lithium niobate waveguide. The first cladding layer covers the first insulating layer and the lithium niobate waveguide to form the lithium niobate structural layer.

3. The method for fabricating a heterogeneous integrated optoelectronic chip according to claim 1, characterized in that, A silicon nitride structural layer is formed on the side of the lithium niobate structural layer opposite to the substrate layer, including: An initial silicon nitride device layer is formed on the entire side of the lithium niobate structural layer opposite to the substrate layer; The initial silicon nitride device layer is patterned to obtain the silicon nitride waveguide; A second cladding layer is disposed on the lithium niobate structural layer, the second cladding layer covering the surface of the lithium niobate structural layer and the silicon nitride waveguide.

4. The method for fabricating a heterogeneous integrated optoelectronic chip according to claim 1, characterized in that, The formation of a silicon-based structural layer on the side of the silicon nitride structural layer opposite to the substrate layer includes: An initial silicon device layer is formed on the entire side of the silicon nitride structure layer opposite to the substrate layer; The initial silicon device layer is patterned to obtain an initial silicon probe element and an initial silicon modulation element; The initial silicon detector element and the initial silicon modulation element are doped to obtain a doped silicon detector element and a doped silicon modulation element, wherein the doped silicon modulation element forms the silicon-based modulation unit; A first sub-cladding layer is disposed on the silicon nitride structural layer, the first sub-cladding layer covering the surface of the silicon nitride structural layer and the doped silicon probe element and the doped silicon modulation element; An epitaxial window is formed in the first sub-cladding layer, the epitaxial window exposing at least a portion of the doped silicon probe element; A germanium element is disposed within the epitaxial window, and the germanium element and the doped silicon detection element constitute the germanium-silicon detection unit. A second sub-cladding layer is disposed on the first sub-cladding layer, the second sub-cladding layer covering the surface of the first sub-cladding layer and the germanium-silicon detection unit, and the first sub-cladding layer and the second sub-cladding layer constitute the third cladding layer.

5. The method for fabricating a heterogeneous integrated optoelectronic chip according to claim 4, characterized in that, The process of forming an initial silicon device layer on the side of the silicon nitride structure layer opposite to the substrate layer includes: A silicon-on-insulator substrate is provided, the silicon-on-insulator substrate comprising a second substrate layer, a second insulating layer and an initial silicon device layer stacked thereon; With the initial silicon device layer facing the silicon nitride structure layer, the silicon-on-insulator substrate is bonded to the side surface of the silicon nitride structure layer facing away from the substrate layer; Remove the second substrate layer and the second insulating layer.

6. The method for fabricating a heterogeneous integrated optoelectronic chip according to claim 1, characterized in that, The electrode structure includes: A first electrode and a second electrode are formed that penetrate the third cladding layer, the first electrode being connected to the germanium-silicon detection unit and the second electrode being connected to the silicon-based modulation unit; A third electrode is formed that extends into the third cladding and the second cladding, the third electrode being located beside the silicon nitride waveguide and spaced apart from the silicon nitride waveguide and the lithium niobate waveguide.

7. The method for fabricating a heterogeneous integrated optoelectronic chip according to claim 6, characterized in that, The formation of the first and second electrodes penetrating the third cladding includes: A first electrode hole and a second electrode hole are formed through the third cladding layer, the germanium-silicon detection unit is exposed in the first electrode hole, and the silicon-based modulation unit is exposed in the second electrode hole; A first metal material is filled into the first electrode hole and the second electrode hole to form a first electrode connecting the germanium-silicon detection unit and a second electrode connecting the silicon-based modulation unit; A fourth cladding layer is formed on the third cladding layer, the fourth cladding layer covering the third cladding layer, the first electrode, and the second electrode.

8. The method for fabricating a heterogeneous integrated optoelectronic chip according to claim 7, characterized in that, The formation of a third electrode extending at least into the third cladding layer and the second cladding layer includes: A third electrode hole is formed extending from the surface of the fourth cladding layer into at least the fourth cladding layer, the third cladding layer, and the second cladding layer, as well as a first contact groove and a second contact groove penetrating the fourth cladding layer; the third electrode hole is located beside the silicon nitride waveguide and on the side of the lithium niobate waveguide relatively away from the substrate layer, and the third electrode hole is spaced apart from the silicon nitride waveguide and the lithium niobate waveguide; the first contact groove exposes the first electrode, and the second contact groove exposes the second electrode; A second metal material is filled into the third electrode hole, the first contact groove, and the second contact groove to form the third electrode, the first contact electrode connected to the first electrode, and the second contact electrode connected to the second electrode.

9. The method for fabricating a heterogeneous integrated optoelectronic chip according to claim 1, characterized in that, After forming the electrode structure, the process further includes: A first interconnect electrode is formed on the first electrode, a second interconnect electrode is formed on the second electrode, and a third interconnect electrode is formed on the third electrode; the cross-sectional dimension of the first interconnect electrode is larger than the cross-sectional dimension of the first electrode, the cross-sectional dimension of the second interconnect electrode is larger than the cross-sectional dimension of the second electrode, and the cross-sectional dimension of the third interconnect electrode is larger than the cross-sectional dimension of the third electrode.

10. A heterogeneous integrated optoelectronic chip, characterized in that, include: basal layer; A lithium niobate structural layer is formed on one side surface of the substrate layer; the lithium niobate structural layer includes a lithium niobate waveguide and a first cladding layer covering the lithium niobate waveguide; A silicon nitride structural layer is formed on the side of the lithium niobate structural layer opposite to the substrate layer; the silicon nitride structural layer includes a silicon nitride waveguide and a second cladding layer covering the silicon nitride waveguide, the projection of the silicon nitride waveguide on the substrate layer is located within the projection region of the lithium niobate waveguide on the substrate layer; the silicon nitride waveguide and the lithium niobate waveguide form a composite waveguide structure; A silicon-based structural layer is formed on the side of the silicon nitride structural layer opposite to the substrate layer; the silicon-based structural layer includes a variety of silicon-based units and a third cladding layer covering the silicon-based units, the silicon-based units including germanium-silicon detection units and silicon-based modulation units; An electrode structure includes a first electrode for connecting the germanium-silicon detection unit, a second electrode for connecting the silicon-based modulation unit, and a third electrode located beside the silicon nitride waveguide and above the lithium niobate waveguide; the germanium-silicon detection unit and the first electrode are configured to form a germanium-silicon detector, the silicon-based modulation unit and the second electrode are configured to form a silicon-based modulator, and the composite waveguide structure and the third electrode are configured to form a composite waveguide modulator.

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