Display panel and display device

Abstract

The present disclosure relates to the technical field of display, and discloses a display panel and a display device; the display panel comprises an array substrate, the array substrate has a display area and a non-display area arranged at least one side of the display area, the non-display area comprises a fan-out area and a binding area, and the fan-out area is connected between the display area and the binding area; the array substrate comprises a substrate, a driving circuit layer group and a first electrode layer which are sequentially stacked; the driving circuit layer group comprises a plurality of signal lines, a plurality of connection signal lines, a plurality of data lines and a plurality of gate lines, the gate lines extend along a first direction, and the signal lines, the connection signal lines and the data lines all extend along a second direction; the first electrode layer comprises a plurality of electrode blocks, and the electrode blocks are electrically connected to the signal lines; the plurality of data lines are divided into a first data line group and a second data line group which are arranged along the first direction in sequence, the data lines belonging to the first data line group are electrically connected to the connection signal lines, and do not extend to the fan-out area. The display panel is beneficial to narrow frame design.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] With the development of information technology, electronic devices are widely used in people's daily lives. Liquid crystal displays (LCDs), as the most widely used flat panel displays, occupy an important position in display panels.

[0003] However, with the development of technology, current monitors cannot meet customers' increasingly demanding requirements for narrow bezels.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device.

[0006] According to one aspect of this disclosure, a display panel is provided, including an array substrate having a display area and a non-display area disposed on at least one side of the display area, the non-display area including a fan-out region and a bonding region, the fan-out region being connected between the display area and the bonding region; the array substrate includes:

[0007] Substrate;

[0008] A driving circuit layer group is disposed on one side of the substrate. The driving circuit layer group includes multiple signal lines, multiple connection signal lines, multiple data lines and multiple gate lines. The gate lines extend along a first direction, and the signal lines, the connection signal lines and the data lines all extend along a second direction. The multiple data lines and the multiple gate lines divide the display area into multiple sub-pixel areas.

[0009] A first electrode layer is disposed on the side of the driving circuit layer group opposite to the substrate. The first electrode layer includes a plurality of electrode blocks, which are electrically connected to the signal lines.

[0010] The multiple data lines are divided into a first data line group and a second data line group arranged sequentially along the first direction. The data lines belonging to the first data line group are electrically connected to the connection signal line. The data lines belonging to the first data line group do not extend to the fan-out area. The second direction intersects with the first direction.

[0011] In one exemplary embodiment of this disclosure, the division of the plurality of data lines further includes a third data line group, which is located on the side of the second data line group away from the first data line group; the data lines belonging to the third data line group are electrically connected to the connection signal line, and the data lines belonging to the third data line group do not extend to the fan-out area.

[0012] In an exemplary embodiment of this disclosure, the non-display area further includes a data binding opposite side, which is located on the side of the display area away from the fan-out area. A first connection trace and a second connection trace are provided on the data binding opposite side. The first connection trace is connected between the data line and the connection signal line of the first data line group, and the second connection trace is connected between the data line and the connection signal line of the third data line group.

[0013] In an exemplary embodiment of this disclosure, the plurality of signal lines are divided into a first signal line group and a second signal line group arranged sequentially along the first direction; the signal lines belonging to the first signal line group are electrically connected to the connecting signal line, and the signal lines belonging to the first signal line group do not extend to the fan-out area.

[0014] In one exemplary embodiment of this disclosure, the division of the plurality of signal lines further includes a third signal line group, which is located on the side of the second signal line group away from the first signal line group; the signal line belonging to the third signal line group is electrically connected to the connecting signal line, and the signal line belonging to the third signal line group does not extend to the fan-out area.

[0015] In an exemplary embodiment of this disclosure, the non-display area further includes a data binding opposite side, which is located on the side of the display area away from the fan-out area. A third connection trace and a fourth connection trace are provided on the data binding opposite side. The third connection trace is connected between the signal line and the connection signal line of the first signal line group, and the fourth connection trace is connected between the signal line and the connection signal line of the third signal line group.

[0016] In one exemplary embodiment of this disclosure, the display panel further includes: a driver chip disposed in the bonding area, the driver chip being connected to the connection signal line via a fan-out trace disposed in the fan-out area; the array substrate connecting a display area of ​​the driver chip is a first display area.

[0017] In an exemplary embodiment of this disclosure, a plurality of the connection signal lines are disposed in the middle region of the first display area along the first direction, and no signal line is disposed between two adjacent connection signal lines; the plurality of signal lines are divided into two groups of signal lines, and the two groups of signal lines are located on opposite sides of the plurality of connection signal lines along the first direction.

[0018] In one exemplary embodiment of this disclosure, a plurality of electrode blocks are divided into a first electrode block and a second electrode block. The area of ​​the second electrode block is larger than that of the first electrode block. The orthographic projection of the connection signal line on the substrate overlaps with the orthographic projection of the second electrode block on the substrate. The orthographic projection of the connection signal line on the substrate does not overlap with the orthographic projection of the first electrode block on the substrate. The orthographic projection of the first electrode block on the substrate overlaps only with the orthographic projection of the signal line on the substrate.

[0019] In one exemplary embodiment of this disclosure, a plurality of second electrode blocks are arranged in two columns along the second direction, and the two columns of second electrode blocks are disposed in the middle region of the first display area along the first direction.

[0020] In an exemplary embodiment of this disclosure, the display area of ​​the array substrate connected to a driver chip is a first display area. The multiple connection signal lines are divided into two groups of connection signal lines. The two groups of connection signal lines are located at opposite edges of the first display area along the first direction. No signal lines are provided between adjacent two connection signal lines. The multiple signal lines are located in the middle area of ​​the first display area along the first direction.

[0021] In one exemplary embodiment of this disclosure, a plurality of electrode blocks are divided into a first electrode block and a second electrode block. The area of ​​the second electrode block is larger than that of the first electrode block. The orthographic projection of the connection signal line on the substrate overlaps with the orthographic projection of the second electrode block on the substrate. The orthographic projection of the connection signal line on the substrate does not overlap with the orthographic projection of the first electrode block on the substrate. The orthographic projection of the first electrode block on the substrate overlaps only with the orthographic projection of the signal line on the substrate.

[0022] In one exemplary embodiment of this disclosure, a plurality of second electrode blocks are arranged in two columns along the second direction, and the two columns of second electrode blocks are respectively disposed on the two opposite edges of the first display area along the first direction.

[0023] In one exemplary embodiment of this disclosure, at least one of the signal lines and at least one adjacent connecting signal line form a group of signal lines, and multiple groups of signal lines are arranged sequentially along the first direction.

[0024] In one exemplary embodiment of this disclosure, multiple sets of signal line groups are symmetrically arranged with respect to the center line extending along the second direction of the first display area, and the connection signal lines and the arrangement of the signal lines in the two symmetrically arranged signal line groups are also symmetrically arranged.

[0025] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0026] Multiple fan-out traces are provided in the fan-out area. Each fan-out trace includes a first segment, a second segment, and a third segment connected in sequence. The first segment and the third segment extend along the second direction. The angle between the extension direction of the second segment and the first direction is greater than 0° and less than or equal to 10°. A portion of the first segment is connected to the data line of the first display area, a portion of the first segment is connected to the signal line of the first display area, and a portion of the first segment is connected to the connection signal line of the first display area. The third segment is connected to the driver chip of the bonding area.

[0027] In one exemplary embodiment of this disclosure, a data line is arranged adjacent to one side of each of the signal lines, and a data line is arranged adjacent to one side of each of the connecting signal lines.

[0028] According to another aspect of this disclosure, a display device is provided, comprising:

[0029] The display panel is any of the display panels described above.

[0030] The display panel disclosed herein has data lines belonging to the first data line group electrically connected to the connection signal line, and the data lines belonging to the first data line group do not extend to the fan-out area; it can reduce the number of data lines extending to the fan-out area from at least one edge of the display area, thereby reducing the distance between one end of the first fan-out line connected to the display area and one end of the last fan-out line connected to the display area, that is, reducing the size of the bonding area along the first direction, and further reducing the size of the bonding area along the second direction, thereby achieving a narrow bezel design.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0033] Figure 1 This is a schematic diagram of the region division structure of an example embodiment of the display panel of this disclosure.

[0034] Figure 2 for Figure 1 The diagram shows a cross-sectional structure of an example implementation of the display area.

[0035] Figure 3 for Figure 1 The diagram shows a cross-sectional structure of another example implementation of the display area.

[0036] Figure 4 This is a schematic diagram of the structure of a first example embodiment of the display panel of this disclosure.

[0037] Figure 5 for Figure 1 A schematic diagram of the fan-out routing structure in the central fan-out area.

[0038] Figure 6 for Figure 1 A schematic diagram showing the connection between the fan-out traces in the middle fan-out area and the driver chip.

[0039] Figure 7 This is a schematic diagram showing the connection between the fan-out traces of the fan-out area and the driver chip in another example embodiment of the display panel disclosed herein.

[0040] Figure 8 This is a schematic diagram of the structure of a second example embodiment of the display panel of this disclosure.

[0041] Figure 9 This is a schematic diagram of the structure of a third example embodiment of the display panel of this disclosure.

[0042] Figure 10 This is a schematic diagram of the structure of a fourth example embodiment of the display panel of this disclosure.

[0043] Figure 11 In order to be in Figure 4 and Figure 10 The diagram shows a schematic representation of the relationship between the signal lines and connecting signal lines and the electrode block in an example embodiment of the signal line and connecting signal line arrangement structure shown.

[0044] Figure 12 In order to be in Figure 4 and Figure 10The diagram shows another example of the relationship between the signal lines and connecting signal lines and the electrode block in the arrangement of the signal lines and connecting signal lines shown.

[0045] Figure 13 In order to be in Figure 8 The diagram shows the relationship between the signal lines and connecting signal lines and the electrode block when the signal lines and connecting signal lines are arranged as shown.

[0046] Figure 14 In order to be in Figure 9 The diagram shows the relationship between the signal lines and connecting signal lines and the electrode block when the signal lines and connecting signal lines are arranged as shown.

[0047] Explanation of reference numerals in the attached figures:

[0048] 1. Substrate;

[0049] 2. Driver circuit layer group; 21. Gate layer; 211. Gate; 212. Gate line; 22. Gate insulating layer; 23. Active layer; 231. First conductive part; 232. Channel part; 233. Second conductive part; 24. Connecting conductor layer; 241. Data line; 241a. First data line group; 241b. Second data line group; 241c. Third data line group; 242. Source; 243. Drain; 244. Signal line; 244z. Signal line group; 244a. First signal line group; 244b. Second signal line group; 245. Connecting signal line; 245z. Connecting signal line group; 25. First insulating layer; 25a. Inorganic layer; 25b. Organic layer; 251. Connecting via;

[0050] 3. First electrode layer; 31. Electrode block; 31a. First electrode block; 31b. Second electrode block;

[0051] 4. Second insulating layer;

[0052] 5. Second electrode layer; 51. Second electrode;

[0053] 6. Fan-out routing; 61. First segment; 62. Second segment; 63. Third segment;

[0054] 71. First connection trace; 72. Second connection trace; 73. Third connection trace;

[0055] AA, Display area; NAA, Non-display area; DP, Data bonding side; DPO, Data bonding opposite side; GPL, Left side of gate signal output; GPR, Right side of gate signal output; Fanout, Fan-out region; BOD, Bonding region;

[0056] ICs and driver chips;

[0057] PXQ, subpixel region; PXH, pixel row; PXL, pixel column; ZPXL, subpixel column; PX, pixel; R, first subpixel; G, second subpixel; B, third subpixel;

[0058] X, the first direction; Y, the second direction. Detailed Implementation

[0059] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0060] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0061] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0062] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0063] This disclosure provides an example embodiment of a display panel, including an array substrate, with reference to... Figures 1-4and Figures 8-14 As shown, Figure 4 , Figures 8-10 To distinguish the various traces, line types are differentiated: the thickest solid line is the signal line 244, the thickest dashed line is the connection signal line 245, and the thicker solid line is the data line 241. The array substrate has a display area AA and a non-display area NAA located on at least one side of the display area AA. The non-display area NAA may include a fanout area (Fanout) and a bonding area (BOD). The fanout area connects the display area AA and the bonding area BOD. The array substrate may include a substrate 1, a driving circuit layer group 2, and a first electrode layer 3. The driving circuit layer group 2 is located on one side of the substrate 1 and may include multiple signal lines 244, multiple connection signal lines 245, multiple data lines 241, and multiple gate lines 212. The gate lines 212 are arranged along the first electrode layer 3. Extending in one direction X, signal line 244, connecting signal line 245, and data line 241 all extend along the second direction Y. Multiple data lines 241 and multiple gate lines 212 divide the display area AA into multiple sub-pixel areas. The first electrode layer 3 is disposed on the side of the driving circuit layer group 2 away from the substrate 1. The first electrode layer 3 may include multiple electrode blocks 31, which are electrically connected to the signal line 244. The multiple data lines 241 are divided into a first data line group 241a and a second data line group 241b arranged sequentially along the first direction X. The data lines 241 belonging to the first data line group 241a are electrically connected to the connecting signal line 245. The data lines 241 belonging to the first data line group 241a do not extend to the fanout area. The second direction Y intersects with the first direction X.

[0064] In the array substrate disclosed herein, the data lines 241 belonging to the first data line group 241a are electrically connected to the connection signal line 245, and the data lines 241 belonging to the first data line group 241a do not extend to the fanout area; this can reduce the number of data lines 241 extending to the fanout area from at least one edge of the display area AA, thereby reducing the distance between the end of the first fanout trace 6 connected to the display area AA and the end of the last fanout trace 6 connected to the display area AA, that is, reducing the size of the bonding area BOD along the first direction X, and further reducing the size of the bonding area BOD along the second direction Y, thereby achieving a narrow bezel design.

[0065] It should be noted that the second direction Y intersects with the first direction X. For example, the second direction Y can be perpendicular to the first direction X, and both the first direction X and the second direction Y are perpendicular to one side of the substrate 1 where the driving circuit layer group 2 is disposed.

[0066] Reference Figure 1As shown, the array substrate may include a display area AA (Active Area) and a non-display area NAA. Specifically, the non-display area NAA may surround the outer periphery of the display area AA. The array substrate may be rectangular, and the display area AA may be rectangular, so that the non-display area NAA is a rectangular frame. Of course, the array substrate may also be circular, elliptical, or other regular or irregular shapes; the non-display area NAA may also be located on one, two, or three sides of the display area AA.

[0067] The non-display area (NAA) may include a data pad (DP), a data pad opposite (DPO), a gate pad left (GPL), and a gate pad left (GPR). Gate driver on array (GOA) circuits are located on the gate pad left (GPL) and gate pad right (GPR). The gate pad left (GPL) and gate pad right (GPR) are positioned opposite each other in the first direction (X), with the gate pad left (GPL) generally corresponding to the left bezel coverage area and the gate pad right (GPR) generally corresponding to the right bezel coverage area. The data pad side (DP) generally corresponds to the bottom bezel coverage area. The data pad side (DP) and the data pad opposite (DPO) are positioned opposite each other in the second direction (Y), with the data pad opposite (DPO) located on the side of the display area (AA) furthest from the fanout area. The data pad opposite (DPO) generally corresponds to the top bezel coverage area.

[0068] The data bonding side DP can include a fanout area and a bonding area BOD. The display area AA and the bonding area BOD are connected on opposite sides of the fanout area in the second direction Y. That is, the fanout area is connected between the display area AA and the bonding area BOD. Specifically, the fanout area is connected to the display area AA, and the bonding area BOD is connected to the side of the fanout area away from the display area AA. The bonding area BOD is provided with multiple bonding pins, some of which are used to bond the driver chip IC.

[0069] Generally, the fanout area occupies about 50% of the space of the data binding side DP in the second direction Y. Therefore, reducing the space of the fanout area in the second direction Y can effectively meet the requirement of narrow bezel.

[0070] Reference Figure 2As shown, the array substrate may include a substrate 1, a driving circuit layer group 2, a first electrode layer 3, a second insulating layer 4, and a second electrode layer 5. The material of the substrate 1 may include inorganic materials, such as glass, quartz, or metal. The material of the substrate 1 may also include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate 1 may be formed from multiple material layers; for example, the substrate 1 may include multiple substrate layers, and the substrate layer material may be any of the aforementioned materials. Of course, the substrate 1 may also be a single layer, and may be any of the aforementioned materials.

[0071] The driving circuit layer 2 may include multiple transistors arranged in an array, specifically, referring to... Figure 2 As shown, the driving circuit layer group 2 may include a gate layer 21, a gate insulating layer 22, an active layer 23, a connecting conductor layer 24, and a first insulating layer 25. The gate layer 21 is disposed on one side of the substrate 1. The gate layer 21 may include a gate 211 and a gate line 212. The gate line 212 is connected to the gate 211, or a portion of the gate line 212 may be reused as the gate 211. The gate line 212 may extend along a first direction X. The gate layer 21 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The gate layer 21 may be a single-layer film or a multilayer film.

[0072] A gate insulating layer 22 is disposed on the side of the gate layer 21 facing away from the substrate 1. The gate insulating layer 22 may include silicon compounds, metal oxides, or the like. For example, the gate insulating layer 22 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These can be used individually or in combination. The gate insulating layer 22 may be a single-layer film or a multilayer film, wherein the multilayer film is formed as a stacked structure of different materials. The gate insulating layer 22 may be disposed only on the side of the gate layer 21 facing away from the substrate 1; of course, the gate insulating layer 22 may also be disposed over the entire surface of the substrate 1.

[0073] Reference Figure 2As shown, an active layer 23 may be disposed on the side of the gate insulating layer 22 facing away from the substrate 1. The active layer 23 may be made of, but is not limited to, metal oxide semiconductor materials. The metal oxide semiconductor materials may include any one or more of indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element-doped metal oxides (RE-OS), wherein the rare earth element-doped metal oxides may include lanthanide-doped metal oxides (Ln-OS). The crystal state of the active layer 23 material may be amorphous, partially crystalline, or polycrystalline. The active layer 23 may include a first conductive portion 231, a channel portion 232, and a second conductive portion 233 connected in sequence. For example, the first conductive portion 231 and the second conductive portion 233 are connected to opposite ends of the channel portion 232.

[0074] Reference Figure 2 As shown, the connecting conductor layer 24 is disposed on the side of the active layer 23 facing away from the substrate 1. The connecting conductor layer 24 may include at least one metal selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The connecting conductor layer 24 may be a single-layer film or a multilayer film. For example, the connecting conductor layer 24 may be formed as a stacked structure having Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0075] The connecting conductor layer 24 may include multiple signal lines 244, multiple connecting signal lines 245, multiple data lines 241, multiple sources 242, and multiple drains 243. The drain 243 may be part of a data line 241, or a source 242 connected to a data line 241. The source 242 is connected to a first conductive portion 231, and the drain 243 is connected to a second conductive portion 233. The data lines 241 extend along a second direction Y, as do the signal lines 244 and connecting signal lines 245. The multiple data lines 241 and multiple gate lines 212 divide the display area AA into multiple sub-pixel areas. The multiple signal lines 244 and multiple data lines 241 extending to the fanout area are arranged in an orderly manner with a fixed line width and spacing, and these signal lines have the same slope. The current challenge in fanout routing lies in the insufficient space for edge signal lines. Furthermore, the higher the product resolution and the narrower the DP bezel on the data bonding side, the more limited the space becomes. If a narrow bezel is achieved by reducing the line width and spacing of signal line 244 and data line 241, the reduction in line width and spacing will be limited by process capabilities. At the same time, reducing the line width will also increase the routing resistance, which will ultimately affect the yield and product quality, and may even fail to meet the customer's bezel requirements, thus hindering product competitiveness.

[0076] Of course, in some other exemplary embodiments of this disclosure, a conductive layer may also be provided. The conductive layer may include multiple signal lines 244 and multiple connection signal lines 245, that is, the multiple signal lines 244 and multiple connection signal lines 245 and the data line 241 may not be provided on the same conductive layer.

[0077] Reference Figure 2 As shown, a first insulating layer 25 is provided on the side of the connecting conductor layer 24 away from the substrate 1. The first insulating layer 25 may include an inorganic layer 25a. The material of the inorganic layer 25a may be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0078] The first insulating layer 25 may also include an organic layer 25b, which may be made of organic materials, such as polyimide (PI), polycarbonate, polyacrylate, polyetherimide, etc. Of course, the first insulating layer 25 may only include the organic layer 25b, or it may include two inorganic layers 25a.

[0079] The active layer 23, gate 211, source 242 and drain 243 constitute a thin-film transistor (TFT), that is, the transistor is a thin-film transistor (TFT).

[0080] It should be noted that the thin-film transistor TFT described in this specification is a bottom-gate thin-film transistor TFT. In other exemplary embodiments of this disclosure, the thin-film transistor TFT can also be a top-gate type or a dual-gate type (two gates 211), and its specific structure will not be described in detail here. Moreover, in cases where thin-film transistor TFTs with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source 242" and the "drain 243" are sometimes interchanged. Therefore, in this specification, the "source 242" and the "drain 243" can be interchanged.

[0081] Furthermore, the transistor described in this specification is a thin-film transistor (TFT). The following description uses a thin-film transistor (TFT) as an example of a transistor. In other exemplary embodiments of this disclosure, the transistor may also be other conventional transistors.

[0082] A first electrode layer 3 is disposed on the side of the driving circuit layer group 2 facing away from the substrate 1. Specifically, the first electrode layer 3 is disposed on the side of the first insulating layer 25 facing away from the substrate 1. The material of the first electrode layer 3 may include a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first electrode layer 3 may include multiple electrode blocks 31, and the first electrode layer 3 may be a common electrode. One electrode block 31 may cover multiple pixels.

[0083] Reference Figure 2 As shown, a second insulating layer 4 is provided on the side of the first electrode layer 3 away from the substrate 1. The material of the second insulating layer 4 can be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0084] Reference Figure 2 As shown, a second electrode layer 5 is disposed on the side of the second insulating layer 4 facing away from the substrate 1. The material of the second electrode layer 5 may include a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. A first via is disposed on the first insulating layer 25, and a second via is disposed on the second insulating layer 4 communicating with the first via. The second electrode layer 5 may include a plurality of second electrodes 51 arranged in an array. The second electrodes 51 may be pixel electrodes. The second electrodes 51 can be connected to the drain 243 through the second via on the second insulating layer 4 and the first via on the first insulating layer 25. Display driving signals can be input to the second electrodes 51 through the drain 243.

[0085] Of course, in some other exemplary embodiments of this disclosure, reference is made to Figure 3 As shown, the second electrode layer 5 can also be disposed on the side of the first insulating layer 25 away from the substrate 1. The second electrode layer 5 can be connected to the drain 243 through the first via on the first insulating layer 25, and a display driving signal can be input to the second electrode 51 through the drain 243. A second insulating layer 4 is disposed on the side of the second electrode layer 5 away from the substrate 1, and a first electrode layer 3 is disposed on the side of the second insulating layer 4 away from the substrate 1.

[0086] Reference Figure 4As shown, the array substrate may include multiple pixels PX arranged in an array. Each pixel PX may include three sub-pixels of different colors. The three sub-pixels are a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B. That is, each pixel PX may include the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B arranged sequentially along the first direction X. Specifically, the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are arranged sequentially and periodically along the first direction X to form a row of pixels PXH. In other words, multiple pixels PX are arranged along the first direction X to form a row of pixels PXH. It can also be said that within each pixel row PXH, the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are arranged sequentially and periodically along the first direction X. Multiple sub-pixels are arranged sequentially along the second direction Y to form a column of sub-pixel ZPXL. For example, multiple first sub-pixels R are arranged sequentially along the second direction Y to form a column of sub-pixel ZPXL, multiple second sub-pixels G are arranged sequentially along the second direction Y to form a column of sub-pixel ZPXL, and multiple third sub-pixels B are arranged sequentially along the second direction Y to form a column of sub-pixel ZPXL.

[0087] Multiple pixels PX are arranged sequentially along the second direction Y to form a pixel column PXL. A signal line 244 or a connection signal line 245 is provided on one side of each pixel column PXL. Of course, the arrangement of the signal line 244 and the connection signal line 245 is not limited to the above description. For example, a signal line 244 or a connection signal line 245 can be provided on one side of each data line 241.

[0088] The first sub-pixel R, the second sub-pixel G, and the third sub-pixel B can all be defined by pixel electrodes.

[0089] Reference Figure 4 As shown, a portion of the gate lines 212 are connected to the gate drive circuit GOA of the left side of the gate signal output GPL, and another portion of the gate lines 212 are connected to the gate drive circuit GOA of the right side of the gate signal output GPR. Multiple gate lines 212 are used to transmit scan signals. The scanning direction of the gate lines 212 is from the nth row pixel PX to the (n+1)th row pixel PX, where n is an integer greater than or equal to 1. The gate lines 212 can extend along a first direction X, and multiple gate lines 212 can be arranged along a second direction Y to transmit scan signals to different sub-pixels.

[0090] Data lines 241 can extend along the second direction Y, and multiple data lines 241 can be arranged along the first direction X. Multiple data lines 241 are intersected with multiple gate lines 212 to define the display area AA as multiple sub-pixel regions PXQ. Each sub-pixel is defined within a sub-pixel region PXQ, that is, each second electrode 51 is located within a sub-pixel region PXQ. This results in a column of sub-pixel lines ZPXL being provided between every two adjacent data lines 241. A data line 241 can be provided on one side of each column of sub-pixel lines PXL, so that a data line 241 is provided adjacent to one side of each signal line 244, and a data line 241 is also provided adjacent to one side of each connecting signal line 245. A row of pixels PXH is provided between every two adjacent gate lines 212.

[0091] Typically, data line 241 and signal line 244 need to extend to the fanout area and the bonding area BOD to facilitate bonding with a driver chip IC in the bonding area BOD. The display area AA connected to one driver chip IC on the array substrate is the first display area. Of course, an array substrate can also connect to two or more driver chip ICs. In this case, the display area AA is divided into two or more first display areas. The following explanation uses the example of the array substrate connecting to one driver chip IC. In this case, the display area AA is the first display area.

[0092] The size of the driver chip IC along the first direction X is smaller than the size of the display area AA along the first direction X. Therefore, the data lines 241 and signal lines 244 extending to the fanout area need to be tilted so that all the data lines 241 and signal lines 244 are connected to the bonding area BOD.

[0093] Specifically, refer to Figure 5 as well as Figure 6 As shown, multiple fan-out traces 6 are provided in the fanout area. Each fan-out trace 6 may include a first segment 61, a second segment 62, and a third segment 63 connected sequentially. The first segment 61 and the third segment 63 extend along the second direction Y. The angle θ between the extension direction of the second segment 62 and the first direction X is greater than 0° and less than or equal to 10°. For example, the angle θ between the extension direction of the second segment 62 and the first direction X can be 2°, 4°, 5°, 7°, 9°, etc. The multiple fan-out traces 6 may be the portion of multiple data lines 241 and multiple signal lines 244 extending to the fanout area; that is, a portion of the first segment 61 is connected to the data lines 241 in the display area AA, and a portion of the first segment 61 is connected to the signal lines 244 in the display area AA. The third segment 63 is connected to the bonding area BOD.

[0094] Reference Figure 5 as well as Figure 6As shown, the size of the fanout area along the first direction X is 'a', which is the distance from one end of the first fanout trace 6 connected to the display area AA to the other end of the last fanout trace 6 connected to the display area AA. The size of the fanout area along the second direction Y is 'b', which can also be the spacing between the display area AA and the bonding area BOD. 'd' is the spacing between the two outermost pins of the driver chip IC on the side closest to the display area AA along the first direction X. Since the sizes of the first segment 61 and the third segment 63 of the two outermost fanout traces 6 are very small, they can be ignored. Therefore, when multiple fanout traces 6 are symmetrically arranged, the relevant dimensions of the fanout area have the following relationship:

[0095]

[0096] In the formula, θ and d are fixed values ​​that cannot be changed; by changing the value of a, the value of b can be changed, thereby achieving a narrow bezel design.

[0097] Reference Figure 7 As shown in the figure, only the two outermost fan-out routing lines 6 are shown. When multiple fan-out routing lines 6 are asymmetrically arranged, the calculation is performed on the side with the most fan-out routing lines 6. Specifically:

[0098] b = etanθ;

[0099] In the formula, e is the distance in the first direction X between one end of the longest fan-out trace 6 and the end of the connection binding area BOD. θ is a fixed value and cannot be changed; by changing the value of e, the value of b can be changed, thereby achieving a narrow bezel design.

[0100] In some exemplary embodiments of this disclosure, the multiple data lines 241 are divided into a first data line group 241a, a second data line group 241b, and a third data line group 241c arranged sequentially along a first direction X. For example, the first data line group 241a may include at least one data line 241, the second data line group 241b may also include multiple data lines 241, and the third data line group 241c may also include at least one data line 241.

[0101] Reference Figure 10As shown, data lines 241 belonging to the first data line group 241a are electrically connected to the connection signal line 245, and the data lines 241 belonging to the first data line group 241a do not extend to the fanout area; data lines 241 belonging to the second data line group 241b extend to the fanout area and to the bonding area BOD; data lines 241 belonging to the third data line group 241c extend to the fanout area and to the bonding area BOD. In this case, the third data line group 241c can be considered to also belong to the second data line group 241b, that is, multiple data lines 241 are divided into the first data line group 241a and the second data line group 241b arranged sequentially along the first direction X. This configuration reduces the number of data lines 241 extending from one edge of the first data line group 241a in the display area AA to the fanout area, thereby reducing the distance between the end of the first fanout line 6 connecting to the display area AA and the end of the last fanout line 6 connecting to the display area AA. This reduces the size a or e of the binding area BOD along the first direction X, and further reduces the size b of the binding area BOD along the second direction Y, thus achieving a narrow bezel design. Moreover, this structure is based on existing process capabilities and does not increase additional costs.

[0102] The connection signal line 245 is connected to the driver chip IC through the fan-out trace 6 located in the fan-out area, so that the data line 241 of the first data line group 241a and the driver chip IC can transmit signals through the fan-out trace 6 and the connection signal line 245.

[0103] It should be noted that the first data line group 241a can be multiple data lines 241 near the left side of the gate signal output GPL, or multiple data lines 241 near the right side of the gate signal output GPR.

[0104] The above situation can be applied to cases where multiple fan-out routing lines 6 are asymmetrically set, which can reduce the number of fan-out routing lines 6 on the side with more fan-out routing lines 6.

[0105] Reference Figure 4 , Figure 8 and Figure 9As shown, data lines 241 belonging to the first data line group 241a are electrically connected to the connection signal line 245, and do not extend to the fanout area; data lines 241 belonging to the second data line group 241b extend to the fanout area and to the bonding area BOD; data lines 241 belonging to the third data line group 241c are electrically connected to the connection signal line 245, and do not extend to the fanout area. This configuration reduces the number of data lines 241 extending to the fanout area from the two edges of the display area AA, thereby further reducing the distance from one end of the first fanout trace 6 connecting to the display area AA to one end of the last fanout trace 6 connecting to the display area AA, i.e., further reducing the dimension a of the bonding area BOD along the first direction X, and further reducing the dimension b of the bonding area BOD along the second direction Y, thus further achieving a narrow bezel design.

[0106] The connection signal line 245 is connected to the driver chip IC through the fan-out trace 6 located in the fanout area, so that the data lines 241 of the first data line group 241a and the third data line group 241c transmit signals with the driver chip IC through the fan-out trace 6 and the connection signal line 245.

[0107] The above situation can be applied to the case where multiple fan-out routing lines 6 are symmetrically arranged, and the number of fan-out routing lines 6 reduced on both sides can be the same.

[0108] Optionally, refer to Figure 4 , Figure 8 and Figure 9 As shown, a first connection trace 71 and a second connection trace 72 are provided on the DPO on the data binding side. The first connection trace 71 connects between the data line 241 and the connection signal line 245 of the first data line group 241a, that is, the data line 241 and the connection signal line 245 of the first data line group 241a are connected through the first connection trace 71 on the DPO on the data binding side. The second connection trace 72 connects between the data line 241 and the connection signal line 245 of the third data line group 241c, that is, the data line 241 and the connection signal line 245 of the third data line group 241c are connected through the second connection trace 72 on the DPO on the data binding side. This avoids increasing the width of the DP on the data binding side.

[0109] Of course, in some other example embodiments of this disclosure, the data line 241 of the first data line group 241a and the connection signal line 245 can also be connected by a connection trace provided in the display area AA, and the data line 241 of the third data line group 241c and the connection signal line 245 can also be connected by a connection trace provided in the display area AA.

[0110] Of course, if the third data cable group 241c is not set up, the second connection cable 72 does not need to be set up.

[0111] In some exemplary embodiments of this disclosure, the plurality of signal lines 244 are divided into a first signal line group 244a, a second signal line group 244b, and a third signal line group (not shown in the figure) arranged sequentially along the first direction X. For example, the first signal line group 244a may include at least one signal line 244, the second signal line group 244b may include two or more signal lines 244, and the third signal line group may include at least one signal line 244.

[0112] Reference Figure 4 , Figures 9-10 As shown, signal line 244 belonging to the first signal line group 244a is electrically connected to the connecting signal line 245, and signal line 244 belonging to the first signal line group 244a does not extend to the fanout area; signal line 244 belonging to the second signal line group 244b extends to the fanout area and extends to the bonding area BOD; signal line 244 belonging to the third signal line group extends to the fanout area and extends to the bonding area BOD. In this case, it can be considered that the third signal line group also belongs to the second signal line group 244b, that is, the multiple signal lines 244 are divided into the first signal line group 244a and the second signal line group 244b arranged sequentially along the first direction X. This configuration reduces the number of signal lines 244 extending from one edge of the first signal line group 244a in the display area AA to the fanout area, thereby reducing the distance between the end of the first fanout line 6 connecting to the display area AA and the end of the last fanout line 6 connecting to the display area AA. This reduces the size a or e of the binding area BOD along the first direction X, and further reduces the size b of the binding area BOD along the second direction Y, thus achieving a narrow bezel design.

[0113] The connection signal line 245 is connected to the driver chip IC through the fan-out trace 6 located in the fan-out area, so that the signal line 244 of the first signal line group 244a and the driver chip IC can transmit signals through the fan-out trace 6 and the connection signal line 245.

[0114] It should be noted that the first signal line group 244a can be multiple signal lines 244 near the left side of the gate signal output GPL, or multiple signal lines 244 near the right side of the gate signal output GPR.

[0115] The above two scenarios can be applied to situations where multiple fan-out routing lines 6 are asymmetrically arranged, which can reduce the number of fan-out routing lines 6 on the side with more fan-out routing lines 6.

[0116] In some other exemplary embodiments of this disclosure, signal lines 244 belonging to the first signal line group 244a are electrically connected to the connecting signal line 245, and the signal lines 244 belonging to the first signal line group 244a do not extend to the fanout area; signal lines 244 belonging to the second signal line group 244b extend to the fanout area and to the bonding area BOD; signal lines 244 belonging to the third signal line group are electrically connected to the connecting signal line 245, and the signal lines 244 belonging to the third signal line group do not extend to the fanout area. This configuration reduces the number of signal lines 244 extending to the fanout area from the two edges of the display area AA, thereby further reducing the distance from one end of the first fanout trace 6 connected to the display area AA to one end of the last fanout trace 6 connected to the display area AA, i.e., further reducing the dimension a of the bonding area BOD along the first direction X, and further reducing the dimension b of the bonding area BOD along the second direction Y, thus further achieving a narrow bezel design.

[0117] The connection signal line 245 is connected to the driver chip IC through the fan-out trace 6 located in the fan-out area, so that the signal lines 244 of the first signal line group 244a and the third signal line group can transmit signals to the driver chip IC through the fan-out trace 6 and the connection signal line 245.

[0118] The above situation can be applied to the case where multiple fan-out routing lines 6 are symmetrically arranged, and the number of fan-out routing lines 6 reduced on both sides can be the same.

[0119] Optionally, a third connection trace 73 and a fourth connection trace (not shown in the figure) are provided on the DPO on the data binding side. The third connection trace 73 connects between the signal line 244 and the connection signal line 245 of the first signal line group 244a, that is, the signal line 244 and the connection signal line 245 of the first signal line group 244a are connected through the third connection trace 73 on the DPO on the data binding side; the fourth connection trace connects between the signal line 244 and the connection signal line 245 of the third signal line group, that is, the signal line 244 and the connection signal line 245 of the third signal line group are connected through the fourth connection trace on the DPO on the data binding side. This avoids increasing the width of the DP on the data binding side.

[0120] Of course, in some other exemplary embodiments of this disclosure, the signal line 244 of the first signal line group 244a and the connection signal line 245 can also be connected by a connection trace provided in the display area AA, and the signal line 244 of the third signal line group and the connection signal line 245 can also be connected by a connection trace provided in the display area AA.

[0121] With multiple fan-out traces symmetrically arranged, the size of the fan-out area basically satisfies the formula:

[0122]

[0123] In the formula, a is the size of the fanout along the first direction X when this scheme is not adopted, a' is the size of the fanout that can be reduced on one side of the first display area AA, b is the size of the fanout along the second direction Y, d is the spacing between the two outermost pins of the driver chip IC on the side near the display area AA along the first direction X, θ is the angle between the extension direction of the second segment 62 and the first direction X, x is the size of a pixel PX along the first direction X, m is the number of pixels PX included in the first display area AA along the first direction X, t is the number of signal lines 244, and the number of connecting signal lines 245 is mt; generally, a pixel PX needs to be set with three data lines 241 and one signal line 244, and a total of four traces need to be connected to the connecting signal lines 245, thus, the above formula one is obtained.

[0124] Therefore, according to Formula 1 and Formula 2, the larger the number m of pixels PX included in the first display area AA along the first direction X, the greater the contribution of this scheme to the narrow bezel design.

[0125] In some exemplary embodiments of this disclosure, reference is made to Figure 4 and Figure 10 As shown, multiple connection signal lines 245 are located in the middle region of the first display area AA along the first direction X. No signal line 244 is set between two adjacent connection signal lines 245, that is, the multiple connection signal lines 245 are concentrated in the middle region of the first display area AA along the first direction X. In this case, the multiple signal lines 244 are divided into two groups of signal lines 244z. The two groups of signal lines 244z are located on opposite sides of the multiple connection signal lines 245 along the first direction X, that is, the two groups of signal lines 244z are located on opposite edges of the first display area AA along the first direction X. This configuration allows more data lines 241 and signal lines 244 on both sides of the display area AA to connect to the connection signal line 245 without extending to the fanout area and the bonding area BOD. This further reduces the distance between the end of the first fanout line 6 connecting to the display area AA and the end of the last fanout line 6 connecting to the display area AA, that is, further reduces the size a of the bonding area BOD along the first direction X, and further reduces the size b of the bonding area BOD along the second direction Y, thereby further achieving a narrow bezel design.

[0126] In this case, refer to Figure 11As shown, the multiple electrode blocks 31 are divided into a first electrode block 31a and a second electrode block 31b. The area of ​​the second electrode block 31b is larger than the area of ​​the first electrode block 31a. Specifically, the length of the second electrode block 31b along the first direction X is greater than the length of the first electrode block 31a along the first direction X, and the width of the second electrode block 31b along the second direction Y is equal to the width of the first electrode block 31a along the first direction X. The orthographic projection of the connecting signal line 245 on the substrate 1 overlaps with the orthographic projection of the second electrode block 31b on the substrate 1, but does not overlap with the orthographic projection of the first electrode block 31a on the substrate 1. The orthographic projection of the first electrode block 31a on the substrate 1 only overlaps with the orthographic projection of the signal line 244 on the substrate 1. Since each electrode block 31 needs to be connected to at least one signal line 244 in order to transmit signals through the signal line 244, after the connection signal lines 245 are centrally arranged, the area of ​​the electrode block 31 that is opposite to the connection signal line 245 needs to be designed to be larger in order to meet the above requirements.

[0127] Multiple second electrode blocks 31b are arranged in two columns along the second direction Y, and the two columns of second electrode blocks are located in the middle region of the first display area AA along the first direction X.

[0128] A portion of the signal lines 244 are connected to the first electrode block 31a through the connection via 251 on the first insulating layer 25, and a portion of the signal lines 244 are connected to the second electrode block 31b through the connection via 251 on the first insulating layer 25.

[0129] Reference Figure 12 As shown, the multiple second electrode blocks 31b in a column of second electrode blocks can also be configured to gradually increase in size along the second direction Y, or gradually decrease in size along the second direction Y. This is only necessary as long as each electrode block 31 is connected to at least one signal line 244.

[0130] In some exemplary embodiments of this disclosure, reference is made to Figure 8As shown, the multiple connection signal lines 245 are divided into two groups of connection signal line groups 245z. The two groups of connection signal line groups 245z are located at the two opposite edges of the first display area AA along the first direction X. No signal line 244 is set between two adjacent connection signal lines 245. That is, the multiple connection signal lines 245 are divided into two groups and concentrated at the two opposite edges of the first display area AA along the first direction X. In this case, the multiple signal lines 244 are set in the middle area of ​​the first display area AA along the first direction X, that is, the multiple signal lines 244 are set between the two groups of connection signal line groups 245z. This configuration allows the connection signal line 245 located at the outermost edge along the first direction X to not extend to the fanout area and the bonding area BOD. It also allows the data lines 241 at both edges of the display area AA to be connected to the connection signal line 245 without extending to the fanout area and the bonding area BOD. This reduces the distance between the end of the first fanout line 6 connected to the display area AA and the end of the last fanout line 6 connected to the display area AA, i.e., reduces the size a of the bonding area BOD along the first direction X, and further reduces the size b of the bonding area BOD along the second direction Y, thus achieving a narrow bezel design.

[0131] In this case, refer to Figure 13 As shown, the multiple electrode blocks 31 are divided into a first electrode block 31a and a second electrode block 31b. The area of ​​the second electrode block 31b is larger than the area of ​​the first electrode block 31a. Specifically, the length of the second electrode block 31b along the first direction X is greater than the length of the first electrode block 31a along the first direction X, and the width of the second electrode block 31b along the second direction Y is equal to the width of the first electrode block 31a along the first direction X. The orthographic projection of the connecting signal line 245 on the substrate 1 overlaps with the orthographic projection of the second electrode block 31b on the substrate 1, but does not overlap with the orthographic projection of the first electrode block 31a on the substrate 1. The orthographic projection of the first electrode block 31a on the substrate 1 only overlaps with the orthographic projection of the signal line 244 on the substrate 1. Since each electrode block 31 needs to be connected to at least one signal line 244 in order to transmit signals through the signal line 244, after the connection signal lines 245 are centrally arranged, the area of ​​the electrode block 31 that is opposite to the connection signal line 245 needs to be designed to be larger in order to meet the above requirements.

[0132] Multiple second electrode blocks 31b are arranged in two columns along the second direction Y. The two columns of second electrode blocks are respectively located at the two opposite edges of the first display area AA along the first direction X. That is, a column of second electrode blocks is provided on one side edge of the first display area AA along the first direction X.

[0133] A portion of the signal lines 244 are connected to the first electrode block 31a through the connection via 251 on the first insulating layer 25, and a portion of the signal lines 244 are connected to the second electrode block 31b through the connection via 251 on the first insulating layer 25.

[0134] Of course, in other exemplary embodiments of this disclosure, the plurality of second electrode blocks 31b in a column of second electrode blocks can also be configured to gradually increase in size along the second direction Y, or gradually decrease in size along the second direction Y. This is as long as each electrode block 31 is connected to at least one signal line 244.

[0135] In some exemplary embodiments of this disclosure, reference is made to Figure 9 As shown, at least one signal line 244 forms a signal line group 244z with at least one adjacent connecting signal line group 245z, and multiple signal line groups 244z are arranged sequentially along the first direction X. For example, four signal lines 244 can form a signal line group 244z with two adjacent connecting signal line groups 245z, or five signal lines 244 can form a signal line group 244z with three adjacent connecting signal line groups 245z. The number of connecting signal lines 245 and signal lines 244 included in a signal line group 244z can also be other numbers, which will not be described in detail here.

[0136] Generally, the number of signal lines 244 included in a group of signal lines 244z is the same as the number of electrode blocks 31 opposite to the group of signal lines 244z in the second direction Y, so that each electrode block 31 is connected to a signal line 244; the sum of the number of signal lines 244 and the number of connected signal lines 245 is equal to the number of pixels opposite to an electrode block 31 in the first direction X.

[0137] Optionally, multiple signal line groups 244z are symmetrically arranged relative to the center line extending along the second direction Y of the first display area AA, and the arrangement of connecting signal lines 245 and signal lines 244 within the two symmetrically arranged signal line groups 244z is also symmetrical. For example, the two symmetrically arranged signal line groups 244z are a first signal line group 244a and a second signal line group 244b. Taking one signal line group 244z including four signal lines 244 and two connecting signal lines 245 as an example, the specific arrangement of the first signal line group 244a is: signal line 244, signal line 244, signal line 244, signal line 244, connecting signal line 245, connecting signal line 245; the specific arrangement of the first signal line group 244a is: connecting signal line 245, connecting signal line 245, signal line 244, signal line 244, signal line 244, signal line 244. Of course, the signal line 244 can also be located on the inner side, and the connecting signal line 245 can be located on the outer side.

[0138] This configuration allows the data lines 241 located at the two edges of the display area AA to be connected to the connection signal lines 245 without extending to the fanout area and the bonding area BOD. This reduces the distance between the end of the first fanout line 6 connected to the display area AA and the end of the last fanout line 6 connected to the display area AA, i.e., reduces the size a of the bonding area BOD along the first direction X, and further reduces the size b of the bonding area BOD along the second direction Y, thus achieving a narrow bezel design.

[0139] In this case, refer to Figure 14 As shown, the multiple electrode blocks 31 have basically the same area, and the multiple electrode blocks 31 can be arranged in an array. The signal line 244 is connected to the electrode block 31 through the connection via 251 on the first insulating layer 25.

[0140] It should be noted that the electrode block 31 can be reused as a touch electrode; that is, when implementing the display function, the electrode block 31 is used as a common electrode, and the signal line 244 can be used as a common electrode line to transmit a common (COM) signal to the electrode block 31 through the signal line 244; when implementing the touch function, the electrode block 31 is used as a touch electrode, and the signal line 244 can be used as a touch trace to transmit a touch signal to the electrode block 31 through the signal line 244.

[0141] The display panel can be a liquid crystal display panel, an OLED (Organic Light-Emitting Diode) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro-LED (micro-Light Emitting Diode) display panel, a mini-LED (mini-Light Emitting Diode) display panel, and so on.

[0142] If the display panel can be a liquid crystal display panel, the display panel may also include a color filter substrate, and the color filter substrate and the array substrate are bonded together by a frame.

[0143] Based on the same inventive concept, this disclosure provides a display device that may include the display panel described in any of the above-described embodiments. The specific structure of the display panel has been described in detail above, and therefore will not be repeated here.

[0144] The specific type of display device is not particularly limited; any type of display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, VR devices, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated further here.

[0145] It should be noted that, in addition to the array substrate, the display device also includes other necessary components and parts. Taking the display as an example, these include, for instance, the casing, circuit board, power cord, etc. Those skilled in the art can supplement these components according to the specific usage requirements of the display device, and will not be elaborated here.

[0146] Compared with the prior art, the beneficial effects of the display device provided by the exemplary embodiments of the present invention are the same as the beneficial effects of the array substrate provided by the above exemplary embodiments, and will not be repeated here.

[0147] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising an array substrate, the array substrate having a display area and a non-display area disposed on at least one side of the display area, the non-display area including a fan-out region and a bonding region, the fan-out region being connected between the display area and the bonding region; characterized in that, The array substrate includes: Substrate; A driving circuit layer group is disposed on one side of the substrate. The driving circuit layer group includes multiple signal lines, multiple connection signal lines, multiple data lines and multiple gate lines. The gate lines extend along a first direction, and the signal lines, the connection signal lines and the data lines all extend along a second direction. The multiple data lines and the multiple gate lines divide the display area into multiple sub-pixel areas. A first electrode layer is disposed on the side of the driving circuit layer group opposite to the substrate. The first electrode layer includes a plurality of electrode blocks, which are electrically connected to the signal lines. The multiple data lines are divided into a first data line group and a second data line group arranged sequentially along the first direction. The data lines belonging to the first data line group are electrically connected to the connection signal line. The data lines belonging to the first data line group do not extend to the fan-out area. The second direction intersects with the first direction.

2. The display panel according to claim 1, characterized in that, The division of the multiple data lines also includes a third data line group, which is located on the side of the second data line group away from the first data line group; the data lines belonging to the third data line group are electrically connected to the connection signal line, and the data lines belonging to the third data line group do not extend to the fan-out area.

3. The display panel according to claim 2, characterized in that, The non-display area also includes a data binding opposite side, which is located on the side of the display area away from the fan-out area. A first connection trace and a second connection trace are provided on the data binding opposite side. The first connection trace is connected between the data line and the connection signal line of the first data line group, and the second connection trace is connected between the data line and the connection signal line of the third data line group.

4. The display panel according to claim 1, characterized in that, The multiple signal lines are divided into a first signal line group and a second signal line group arranged sequentially along the first direction; the signal lines belonging to the first signal line group are electrically connected to the connecting signal line, and the signal lines belonging to the first signal line group do not extend to the fan-out area.

5. The display panel according to claim 4, characterized in that, The division of the multiple signal lines also includes a third signal line group, which is located on the side of the second signal line group away from the first signal line group; the signal lines belonging to the third signal line group are electrically connected to the connecting signal lines, and the signal lines belonging to the third signal line group do not extend to the fan-out area.

6. The display panel according to claim 5, characterized in that, The non-display area also includes a data binding opposite side, which is located on the side of the display area away from the fan-out area. A third connection trace and a fourth connection trace are provided on the data binding opposite side. The third connection trace is connected between the signal line and the connection signal line of the first signal line group, and the fourth connection trace is connected between the signal line and the connection signal line of the third signal line group.

7. The display panel according to any one of claims 1 to 6, characterized in that, The display panel further includes: a driver chip disposed in the bonding area, the driver chip being connected to the connection signal line via a fan-out trace disposed in the fan-out area; the array substrate connecting a display area of ​​the driver chip is a first display area.

8. The display panel according to claim 7, characterized in that, The multiple connection signal lines are located in the middle area of ​​the first display area along the first direction, and no signal lines are set between two adjacent connection signal lines; the multiple signal lines are divided into two groups of signal lines, and the two groups of signal lines are located on opposite sides of the multiple connection signal lines along the first direction.

9. The display panel according to claim 8, characterized in that, Multiple electrode blocks are divided into a first electrode block and a second electrode block. The area of ​​the second electrode block is larger than that of the first electrode block. The orthographic projection of the connection signal line on the substrate overlaps with the orthographic projection of the second electrode block on the substrate. The orthographic projection of the connection signal line on the substrate does not overlap with the orthographic projection of the first electrode block on the substrate. The orthographic projection of the first electrode block on the substrate overlaps only with the orthographic projection of the signal line on the substrate.

10. The display panel according to claim 9, characterized in that, Multiple second electrode blocks are arranged in two columns along the second direction, and the two columns of second electrode blocks are located in the middle region of the first display area along the first direction.

11. The display panel according to any one of claims 1 to 3, characterized in that, The array substrate connects to a display area of ​​a driver chip, which is the first display area. The multiple connection signal lines are divided into two groups of connection signal lines. The two groups of connection signal lines are located at opposite edges of the first display area along the first direction. No signal lines are provided between adjacent two connection signal lines. The multiple signal lines are located in the middle area of ​​the first display area along the first direction.

12. The display panel according to claim 11, characterized in that, Multiple electrode blocks are divided into a first electrode block and a second electrode block. The area of ​​the second electrode block is larger than that of the first electrode block. The orthographic projection of the connection signal line on the substrate overlaps with the orthographic projection of the second electrode block on the substrate. The orthographic projection of the connection signal line on the substrate does not overlap with the orthographic projection of the first electrode block on the substrate. The orthographic projection of the first electrode block on the substrate overlaps only with the orthographic projection of the signal line on the substrate.

13. The display panel according to claim 12, characterized in that, Multiple second electrode blocks are arranged in two columns along the second direction, and the two columns of second electrode blocks are respectively located at the two opposite edges of the first display area along the first direction.

14. The display panel according to claim 7, characterized in that, At least one of the signal lines and at least one adjacent connecting signal line form a group of signal lines, and multiple groups of signal lines are arranged sequentially along the first direction.

15. The display panel according to claim 14, characterized in that, Multiple signal line groups are symmetrically arranged with respect to the center line extending along the second direction of the first display area, and the connecting signal lines and the arrangement of the signal lines in the two symmetrically arranged signal line groups are also symmetrically arranged.

16. The display panel according to claim 7, characterized in that, The array substrate further includes: Multiple fan-out traces are provided in the fan-out area. Each fan-out trace includes a first segment, a second segment, and a third segment connected in sequence. The first segment and the third segment extend along the second direction. The angle between the extension direction of the second segment and the first direction is greater than 0° and less than or equal to 10°. A portion of the first segment is connected to the data line of the first display area, a portion of the first segment is connected to the signal line of the first display area, and a portion of the first segment is connected to the connection signal line of the first display area. The third segment is connected to the driver chip of the bonding area.

17. The display panel according to claim 1, characterized in that, Each of the signal lines has a data line adjacent to one side, and each of the connecting signal lines has a data line adjacent to one side.

18. A display device, characterized in that, include: The display panel is the display panel described in any one of claims 1 to 17.

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