Array substrate, test panel and display device

Abstract

The array substrate, the test panel and the display device provided by the present disclosure comprise a substrate, which comprises a display area and a non-display area located at least one side of the display area, the non-display area is provided with a driving chip, the driving chip comprises a touch terminal; a touch line is located in the display area, the touch line is electrically connected with the touch terminal; a touch test line is located in the non-display area, the touch test line comprises a first main line and a branch line connected with the first main line, the branch line is electrically connected with the touch line, and the same branch line is arranged at intervals between the first main line and the touch line.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a test panel, and a display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) dominate the current flat panel display market due to their small size, low power consumption, and lack of radiation. The key to TFT-LCDs lies in the fabrication of transistors on the array substrate and ensuring the characteristics of these transistors. By controlling the gate voltage to turn the transistors on and off, the data line voltage is written to the pixel voltage, thereby achieving the required display brightness for different pixel electrodes.

[0003] In in-cell touch solutions that integrate touch functionality into a TFT-LCD, display and touch functions can be integrated into a single driver chip (IC), enabling a single driver chip to perform both display and touch functions (i.e., TDDI technology). During the testing (CT) phase of related TDDI products, a high potential is applied to the control lines (TX SW) to turn on the transistors, and a common voltage signal (Com) is then supplied to the touch lines (TX) within the display area AA. When the module (MDL) is illuminated, a low potential is applied to the control lines to turn off the transistors, and the touch signal is then supplied to the touch lines within the display area AA via the driver chip.

[0004] However, both control lines and touch lines are long traces, which are prone to accumulating static electricity during the manufacturing process, damaging the active layer of the transistor, causing abnormal transistor characteristics, affecting the normal input of touch signals, and resulting in test point short circuit failures (TP Short NG) or grid defects. Although static electricity control during the manufacturing process can mitigate the occurrence of defects, it cannot eliminate them at the source. Summary of the Invention

[0005] In view of this, the present disclosure provides an array substrate, a test panel, and a display device to solve the problems of poor short circuits or poor grids at test points in the prior art.

[0006] Therefore, the array substrate, test panel, and display device provided in this disclosure are specifically designed as follows:

[0007] On one hand, embodiments of this disclosure provide an array substrate, including:

[0008] A substrate, the substrate including a display area and a non-display area located on at least one side of the display area, the non-display area being provided with a driving chip, the driving chip including a touch terminal;

[0009] A touch line is located in the display area, and the touch line is electrically connected to the touch terminal;

[0010] A touch test line is located in the non-display area. The touch test line includes a first main line and a branch line connected to the first main line. The branch line is electrically connected to the touch line, and the same branch line is spaced apart between the first main line and the touch line.

[0011] In some embodiments, in the array substrate provided in the present disclosure, the first main line and the branch line are integrally disposed.

[0012] In some embodiments, in the array substrate provided in the present disclosure, the first main line and the branch line are disposed on different layers.

[0013] In some embodiments, the array substrate provided in this disclosure further includes test terminals, and one or both ends of the first main line are electrically connected to the test terminals.

[0014] In some embodiments, the array substrate provided in this disclosure further includes a first connecting line disposed on a different layer from the first main line, and the first main line is electrically connected to the test terminal through the first connecting line.

[0015] In some embodiments, the array substrate provided in the present disclosure further includes a test terminal, and the touch test line further includes a second main line, one end of which is electrically connected to the test terminal and the other end of which is electrically connected to the middle position of the first main line.

[0016] In some embodiments, in the array substrate provided in the present disclosure, the non-display area includes a first non-display area where the driver chip is disposed, the touch test line is disposed in the first non-display area, and the branch line is electrically connected to the touch line through the touch terminal.

[0017] In some embodiments, in the array substrate provided in the present disclosure, the non-display area includes a first non-display area where the driver chip is disposed, and a second non-display area opposite to the first non-display area; the touch test line is disposed in the second non-display area, and the branch line is electrically connected to one end of the touch line away from the touch terminal.

[0018] In some embodiments, the array substrate provided in this disclosure further includes a common electrode located in the display area, and the first main line loads a common electrode signal onto the common electrode.

[0019] On the other hand, this disclosure provides a display device including the array substrate provided in this disclosure and a counter substrate disposed opposite to the array substrate.

[0020] On the other hand, this disclosure provides a test panel, including: the array substrate described above, and a second connecting line located in the non-display area, wherein the same branch lines arranged at intervals are connected through the second connecting line, and the touch test line loads a test signal onto the touch line.

[0021] The beneficial effects of this disclosure are as follows:

[0022] The array substrate, test panel, and display device provided in this disclosure include a substrate, which includes a display area and a non-display area located on at least one side of the display area. The non-display area has a driver chip, which includes a touch terminal; a touch line located in the display area and electrically connected to the touch terminal; and a touch test line located in the non-display area. The touch test line includes a first main line and branch lines connected to the first main line, the branch lines being electrically connected to the touch line, and the same branch line being spaced apart between the first main line and the touch line. This disclosure employs a touch test line design including a first main line and branch lines, so that during the detection phase, a common voltage signal can be sequentially provided to the touch line via the first main line and the branch lines; after the detection is completed, the branch lines are cut off, so that during the module lighting phase, the touch terminal of the driver chip can provide a touch signal to the touch line, realizing normal lighting of the module. Therefore, this disclosure eliminates transistors and control lines controlling transistor switches, thus avoiding short circuits or grid defects at the test points. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present disclosure;

[0024] Figure 2 for Figure 1 A magnified structural diagram of the Z-region in the middle;

[0025] Figure 3 for Figure 1 Another enlarged structural diagram of the Z region;

[0026] Figure 4 for Figure 1 Another enlarged structural diagram of the Z region;

[0027] Figure 5 for Figure 1 Another enlarged structural diagram of the Z region;

[0028] Figure 6 for Figure 1 Another enlarged structural diagram of the Z region;

[0029] Figure 7 for Figure 1 Another enlarged structural diagram of the Z region;

[0030] Figure 8 This is another schematic diagram of the structure of the array substrate provided in the embodiments of this disclosure;

[0031] Figure 9 The embodiments provided in this disclosure include Figure 1 The test panel of the array substrate shown;

[0032] Figure 10 for Figure 2 A schematic diagram of the structure before the middle branch line is cut;

[0033] Figure 11 for Figure 3 A schematic diagram of the structure before the middle branch line is cut;

[0034] Figure 12 for Figure 4 A schematic diagram of the structure before the middle branch line is cut;

[0035] Figure 13 for Figure 5 A schematic diagram of the structure before the middle branch line is cut;

[0036] Figure 14 for Figure 6 A schematic diagram of the structure before the middle branch line is cut;

[0037] Figure 15 for Figure 7 A schematic diagram of the structure before the middle branch line is cut;

[0038] Figure 16 for Figure 2 A schematic diagram of the structure where the middle branch line conducts across the line. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0040] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0041] Figure 1 This is a schematic diagram of an array substrate provided in an embodiment of the present disclosure. Figure 2 for Figure 1 A magnified structural diagram of the Z-region. (See diagram below.) Figure 1 and Figure 2 As shown, the array substrate provided in this embodiment may include: a substrate 101, touch lines 102, and touch test lines 103. The substrate 101 includes a display area AA and non-display areas located on at least one side of the display area AA (e.g., a first non-display area DP extending along a first direction X and arranged along a second direction Y, and a second non-display area DPO). The non-display area (e.g., the first non-display area DP) is provided with at least one driver chip IC, and the driver chip IC includes a touch terminal BP. The touch lines 102 are located in the display area AA and may be located in a gate metal layer or a source / drain metal layer. The touch lines 102 are electrically connected to the touch terminals BP. Optionally, the touch lines 102 and touch terminals BP are electrically connected in a one-to-one correspondence. The touch test line 103 is located in a non-display area (e.g., the first non-display area DP). The touch test line 103 includes a first main line 1031 and a branch line 1032 connected to the first main line 1031. The branch line 1032 is electrically connected to the touch line 102 (e.g., the branch line 1032 and the touch line 102 are electrically connected in a one-to-one correspondence). The same branch line 1032 is spaced between the touch line 102 and the first main line 1031, that is, the branch line 1032 is disconnected.

[0042] In the array substrate provided in this embodiment, a touch test line 103 is designed including a first main line 1031 and a branch line 1032. During the detection phase, a common voltage signal is sequentially provided to the touch line 102 via the first main line 1031 and the branch line 1032. After detection, the branch line 1032 is cut off, so that during the module lighting phase, the touch terminal BP of the driver chip IC can provide a touch signal to the touch line 102, achieving normal lighting. Therefore, this disclosure eliminates transistors and the control lines that control transistor switches, thus avoiding test point short circuits or grid defects caused by abnormal transistor characteristics. Optionally, the first main line 1031 of this disclosure can load a common electrode signal onto the common electrode of the display area AA during the lighting phase to achieve the display function.

[0043] See also Figure 2 It is understood that the first main line 1031 and the branch line 1032 of the touch test line 103 disclosed herein can be disposed in different layers. For example, one of the first main line 1031 and the branch line 1032 is located in the gate metal layer and the other is located in the source / drain metal layer. Thus, the touch test line 103 can be fabricated using existing film layers without the need for additional masking processes and conductive layers. In some embodiments, the first main line 1031 and the branch line 1032 can be electrically connected through a first via V1 penetrating the insulating layer between them. Alternatively, a first transfer electrode of the same layer and material as the pixel electrode or common electrode can be provided, and the first transfer electrode can be used to realize the electrical connection between the first main line 1031 and the branch line 103.

[0044] Figure 3 for Figure 1 Another enlarged structural diagram of the Z region, such as Figure 3 As shown, in this disclosure, the first main line 1031 and the branch line 1032 can also be integrally formed. That is, the first main line 1031 and the branch line 1032 can be located simultaneously in the gate metal layer or the source / drain metal layer, and formed through a single mask process. In this case, the first main line 1031 and the branch line 1032 do not need to be connected to vias, which can reduce the linewidth of the first main line 1031 and facilitate narrow bezel design.

[0045] Figure 4 and Figure 5 They are respectively Figure 1 Another enlarged structural diagram of the Z-region. (Combined with...) Figures 2 to 5 As can be seen, the array substrate provided in the embodiments of this disclosure may further include test terminals 104, and one or both ends of the first main line 1031 may be electrically connected to the test terminals 104. Optionally, when using... Figure 2 and Figure 3When the test terminal 104 applies a common voltage signal to the first main line 1031 from both ends of the first main line 1031, it can ensure that each branch line 1032 is connected to the common voltage signal almost synchronously. When using... Figure 4 and Figure 5 When a common voltage signal is applied to the first main line 1031 from one end of the test terminal 104, the number of test terminals 104 can be reduced.

[0046] In some embodiments, such as Figure 2 , Figure 4 and Figure 5 As shown, the first main line 1031 and the test terminal 104 of this disclosure can be electrically connected through a second via V2 penetrating the insulating layer between them. Alternatively, the first main line 1031 and the test terminal 104 of this disclosure can also be electrically connected through a second adapter electrode that is in the same layer and made of the same material as the pixel electrode or common electrode.

[0047] In other embodiments, such as Figure 3 As shown, this disclosure may further include a first connecting line 105 disposed on a different layer from the first main line 1031, and the first main line 1031 is electrically connected to the test terminal 104 through the first connecting line 105. Optionally, the first main line 1031 and the first connecting line 105 are electrically connected through a third via V3 penetrating the insulating layer between them; or, the first main line 1031 and the first connecting line 105 may also be electrically connected through a third adapter electrode that is on the same layer and made of the same material as the pixel electrode or common electrode. The test terminal 104 and the first connecting line 105 are electrically connected through a fourth via V4 penetrating the insulating layer between them; or, the test terminal 104 and the first connecting line 105 may also be electrically connected through a fourth adapter electrode that is on the same layer and made of the same material as the pixel electrode or common electrode.

[0048] Figure 6 and Figure 7 They are respectively Figure 1 Another enlarged structural diagram of the Z-region. (See diagram below.) Figure 6 and Figure 7 As shown, the touch test line 103 of this disclosure may further include a second main line 1033. One end of the second main line 1033 is electrically connected to the test terminal 104, and the other end is electrically connected to the middle position of the first main line 1301. This reduces the number of test terminals 104 and improves the signal delay problem when a common voltage signal is applied to one side of the test terminal 104. Optionally, the test terminal 104 and the second main line 1033 are electrically connected through a fifth via V5 penetrating the insulating layer between them (e.g., ...). Figure 6 and Figure 7(as shown); or, the test terminal 104 and the second main line 1033 can also be electrically connected through a fifth adapter electrode that is on the same layer and made of the same material as the pixel electrode or common electrode. The second main line 1033 can be integrally formed with the first main line 1031 (as shown). Figure 6 and Figure 7 (As shown), or, the second main line 1033 and the first main line 1031 are disposed on different layers. In the case where the second main line 1033 and the first main line 1031 are disposed on different layers, the first main line 1031 and the second main line 1033 are electrically connected through a sixth via penetrating the insulating layer between them; or, the first main line 1031 and the second main line 1033 can also be electrically connected through a sixth adapter electrode that is on the same layer and made of the same material as the pixel electrode or common electrode.

[0049] In some embodiments, such as Figure 1 and Figure 2 As shown, in this disclosure, both the touch test line 103 and the driver chip IC can be located in the first non-display area DP, and the branch line 1032 of the touch test line 103 can be electrically connected to the touch line 102 through the touch terminal BP of the driver chip IC. In other embodiments, Figure 8 This illustration shows another structural schematic diagram of the array substrate provided in an embodiment of the present disclosure, such as... Figure 8 As shown, this disclosure also allows the touch test line 103 to be located in the second non-display area DPO, and the driver chip IC to be located in the first non-display area DP. Optionally, the touch terminal BP of the driver chip IC is electrically connected to one end of the touch line 102, and the branch line 1032 of the touch test line 103 is electrically connected to the end of the touch line 102 away from the touch terminal BP. It is understood that... Figure 8 The specific structure of the touch test line 103 and its connection relationship with the test terminal 104 in the illustrated embodiment can be compared with... Figure 1 The specific structure of the touch test line 103 and its connection relationship with the test terminal 104 in the illustrated embodiment are the same, and will not be described in detail here.

[0050] Based on the same inventive concept, this disclosure provides a test panel including the above-described array substrate. Figure 9 For including Figure 1 The test panel of the array substrate 001 shown. Figures 10 to 15 They are respectively Figures 2 to 7 A schematic diagram before branch line 1032 is disconnected. (See diagram below.) Figures 9 to 15 As shown, the test panel may also include a second connecting line 002 located in a non-display area (e.g., a first non-display area DP). Branch lines 1032 spaced apart from each other can be connected via the second connecting line 002, allowing the touch test line 103 to apply a test signal (e.g., a common voltage signal) to the touch line 102. After the test is completed, [the following can be done / the test can be performed / the test can be completed ... Figures 10 to 15The second connecting line 002 is laser-cut at the location indicated by the dashed box, thereby disconnecting the branch line 1032 and preventing subsequent branch lines 1032 from interfering with the touch function. Optionally, the second connecting line 002 of this disclosure can be as follows: Figures 10 to 15 As shown, it is integrated with branch line 1032, or, as... Figure 16 As shown, the second connecting line 002 of this disclosure can also be connected to the branch line 1032 in a different layer.

[0051] Based on the same inventive concept, this disclosure provides a display device, including the array substrate provided in this disclosure, a counter substrate disposed opposite to the array substrate, a liquid crystal layer located between the array substrate and the counter substrate, a first polarizer located on the side of the array substrate away from the counter substrate, a second polarizer located on the side of the counter substrate away from the array substrate, and a backlight module located on the side of the first polarizer away from the array substrate.

[0052] In some embodiments, the backlight module can be a direct-lit backlight module or an edge-lit backlight module. Optionally, an edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism assemblies, etc., with the LED strips located on one side of the thickness direction of the light guide plate. A direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature LEDs (MiniLED, Micro LED, etc.). Submillimeter-scale or even micrometer-scale miniature LEDs, like organic light-emitting diodes (OLEDs), are self-emissive devices. Like OLEDs, they possess a series of advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting diodes (LEDs) emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting diodes (OLEDs) which are based on organic materials, including lower power consumption, greater resistance to high and low temperatures, and longer lifespan. When used as a backlight source, micro LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also resolving the glare issue caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0053] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0054] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0055] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, characterized in that, include: A substrate, the substrate including a display area and a non-display area located on at least one side of the display area, the non-display area being provided with a driving chip, the driving chip including a touch terminal; A touch line is located in the display area, and the touch line is electrically connected to the touch terminal; A touch test line is located in the non-display area. The touch test line includes a first main line and a branch line connected to the first main line. The branch line is electrically connected to the touch line, and the same branch line is spaced apart between the first main line and the touch line.

2. The array substrate as described in claim 1, characterized in that, The first main line and the branch line are integrated into one unit.

3. The array substrate as described in claim 1, characterized in that, The first main line and the branch line are set on different layers.

4. The array substrate according to any one of claims 1 to 3, characterized in that, It also includes test terminals, one or both ends of the first main line being electrically connected to the test terminals.

5. The array substrate as described in claim 4, characterized in that, It also includes a first connecting line disposed on a different layer from the first main line, and the first main line is electrically connected to the test terminal through the first connecting line.

6. The array substrate according to any one of claims 1 to 3, characterized in that, It also includes a test terminal, and the touch test line also includes a second main line, one end of which is electrically connected to the test terminal and the other end is electrically connected to the middle position of the first main line.

7. The array substrate as described in any one of claims 1 to 3 and 5, characterized in that, The non-display area includes a first non-display area where the driver chip is located, the touch test line is located in the first non-display area, and the branch line is electrically connected to the touch line through the touch terminal.

8. The array substrate as described in any one of claims 1 to 3 and 5, characterized in that, The non-display area includes a first non-display area where the driver chip is located, and a second non-display area opposite to the first non-display area; the touch test line is located in the second non-display area, and the branch line is electrically connected to the end of the touch line away from the touch terminal.

9. The array substrate according to any one of claims 1 to 3 and 5, characterized in that, It also includes a common electrode located in the display area, and the first main line loads a common electrode signal for the common electrode.

10. A display device, characterized in that, It includes the array substrate as described in any one of claims 1 to 9, and a counter substrate disposed opposite to the array substrate.

11. A test panel, characterized in that, include: The array substrate as described in any one of claims 1 to 9, and the second connecting line located in the non-display area, wherein the same branch lines arranged at intervals are connected through the second connecting line, and the touch test line loads a test signal for the touch line.

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