Device and method for modifying a layout plan

Abstract

An embodiment method of modifying a layout plan of a photomask set includes processing a first version of the layout plan based on a first optical proximity correction (OPC) process followed by a first inverse lithography technique (ILT) process to obtain a first processed layout plan, the first version of the layout plan including a first portion of the layout plan. The method includes identifying a second portion of the layout plan based on comparing the first version of the layout plan and a second version of the layout plan, obtaining a processed combined layout plan that merges a result of the first processed layout plan and the second portion of the layout plan processed based on a second OPC process, and processing the processed combined layout plan based on a second ILT process to obtain a modified layout plan.

Description

Technical Field

[0001] This invention relates to a device and method for modifying layout planning. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. During IC evolution, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (the scale of the smallest component (or line) produced by the manufacturing process, which can be measured as a critical dimension in some applications) has decreased. Various process steps are used to fabricate IC components on semiconductor wafers. These steps include forming one or more photoresist and / or hard mask patterns on the semiconductor wafer, combined with one or more deposition processes, removal processes, and / or cleaning processes. In some applications, photolithography is used to transfer patterns from the photomask onto the semiconductor wafer. As the density of IC components in IC chips increases, resolution enhancement techniques have been developed to achieve more accurate pattern transfer onto the wafer. Summary of the Invention

[0003] In some embodiments, the method for modifying the layout plan for a photomask assembly includes processing a first version of the layout plan based on a first optical proximity correction (OPC) process followed by a first inverse lithography (ILT) process to obtain a first processed layout plan, the first version of the layout plan including a first portion of the layout plan. The method includes identifying a second portion of the layout plan by comparing the first version and a second version of the layout plan, obtaining a processed combined layout plan that merges the first processed layout plan and the second portion of the layout plan processed based on a second OPC process, and processing the processed combined layout plan based on a second ILT process and an ILT processing region corresponding to the second portion of the layout plan to obtain a modified layout plan. The method further includes storing the modified layout plan in a memory device, and the photomask assembly is based on the modified layout plan.

[0004] In some embodiments, the processing device for obtaining a modified layout plan of the photomask assembly includes a memory device and processing circuitry coupled to the memory device. The processing circuitry is configured to process a first version of the layout plan based on a first optical proximity correction (OPC) process followed by a first inverse lithography (ILT) process to obtain a first processed layout plan, the first version of the layout plan including a first portion of the layout plan. The processing circuitry is configured to identify a second portion of the layout plan by comparing the first version and a second version of the layout plan, obtain a processed combined layout plan resulting from merging the first processed layout plan and the second portion of the layout plan processed using a second OPC process, and process the processed combined layout plan based on a second ILT process and an ILT processing region corresponding to the second portion of the layout plan to obtain a modified layout plan. The processing circuitry is further configured to store the modified layout plan in the memory device, and the photomask assembly is based on the modified layout plan.

[0005] In some embodiments, a non-transitory computer-readable medium (CML) storage instruction, when executed by the processing circuitry of a processing device, causes the processing device to process a first version of a layout plan for a photomask assembly based on a first optical proximity correction (OPC) process followed by a first inverse photolithography (ILT) process to obtain a first processed layout plan, the first version of the layout plan including a first portion of the layout plan. The instruction causes the processing device to identify a second portion of the layout plan by comparing the first version and a second version of the layout plan, obtaining a processed combined layout plan that merges the first processed layout plan and the second portion of the layout plan processed using a second optical OPC process, and to process the processed combined layout plan based on a second ILT process and an ILT processing region corresponding to the second portion of the layout plan to obtain a modified layout plan. The instruction further causes the processing device to store the modified layout plan in the processing device's memory device, and the photomask assembly is based on the modified layout plan. Attached Figure Description

[0006] The various aspects of this disclosure are best understood when read in conjunction with the following detailed description and accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for the purpose of discussing clarity.

[0007] Figure 1 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments.

[0008] Figure 2 It is a functional block diagram of a process flow for modifying layout planning according to some embodiments.

[0009] Figures 3A to 3CAccording to some embodiments Figure 2 A simplified plan view of the layout of the process flow at various processing stages.

[0010] Figure 4 This is a flowchart of a method for modifying the layout planning of a photomask assembly according to some embodiments.

[0011] Figure 5 This is a block diagram of an electronic design automation (EDA) system according to some embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, spatially relative terms, such as “below,” “under,” “lower than,” “above,” and “higher than,” are used herein to readily describe the relationship between one component or feature depicted in the diagram and another. Spatially relative terms are intended to encompass not only the directions depicted in the diagram but also the different orientations in which the component is used or operated. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein can be interpreted accordingly. Additionally, the term “composed of” can mean “included” or “consisting of.” In this disclosure, the phrase “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean a component selected from A, a component selected from B, and a component selected from C, unless otherwise described.

[0014] Figure 1 This is a block diagram of an integrated circuit (IC) manufacturing system 100 and associated IC manufacturing processes according to some embodiments. In some embodiments, the IC manufacturing system 100 is used to manufacture at least one of the following based on the layout planning of semiconductor components: (A) one or more photomasks or (B) one or more features in a layer of a semiconductor component.

[0015] exist Figure 1In this IC manufacturing system 100, entities such as design firm 120, mask manufacturing facility 130, and IC manufacturer / fabwean (wafer fab) 150 interact with each other in design, development, and manufacturing cycles and / or services related to the manufacture of IC devices 160. The entities in IC manufacturing system 100 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network includes various different networks, such as intranets and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design firm 120, mask manufacturing facility 130, and IC fab 150 are owned by a single larger company. In some embodiments, two or more of design firm 120, mask manufacturing facility 130, and IC fab 150 coexist in a shared facility and use shared resources.

[0016] Design firm (or design team) 120 generates a layout plan 122 for an IC design. In some embodiments, the layout plan 122 includes one or more layout diagrams, and each layout diagram includes various geometric patterns designed for an IC device 160 (e.g., a semiconductor component). The geometric patterns correspond to patterns of metal layers, oxide layers, or semiconductor layers that constitute various components of the IC device 160 to be manufactured. Various layers are combined to form various IC features. For example, portions of the layout plan 122 include layout patterns indicating various IC features, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, which will be formed based on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate.

[0017] Design company 120 implements appropriate design procedures to form layout plan 122. The design procedures include one or more of logic design, physical design, and / or placement and routing. In some embodiments, each layout diagram of layout plan 122 is presented in one or more data files containing geometric pattern information. For example, each layout diagram of layout plan 122 may be expressed in GDSII, DFII, or OASIS file format. In some embodiments, design company 120 performs various verification processes to ensure that layout plan 122 is suitable for fabrication at IC manufacturing plant 150 based on a given semiconductor process technology node and is electrically consistent with the original IC design. In some embodiments, verification processes include Design Rule Check (DRC), Layout Comparison Schematic (LVS) check, Electrical Rule Check (ERC), Antenna Check (regarding charge accumulation on metal layers), etc.

[0018] Mask manufacturing end 130 includes mask data preparation 132 and mask manufacturing 144. Mask manufacturing end 130 uses layout planning 122 to manufacture one or more masks 145 for fabricating various layers of IC device 160 according to layout planning 122. Mask manufacturing end 130 performs mask data preparation 132, where layout planning 122 is converted into a representative data file (RDF). Mask data preparation 132 provides the RDF to mask manufacturing 144. Mask manufacturing 144 includes a mask writer that converts the RDF into an image on a substrate, such as a mask (pattern template) 145. Layout planning 122 is manipulated by mask data preparation 132 to conform to the specific characteristics of the mask writer and / or the requirements of IC manufacturing plant 150. Figure 1 In this design, mask data preparation 132 and mask manufacturing 144 are illustrated as separate components. In some embodiments, mask data preparation 132 and mask manufacturing 144 may be collectively referred to as mask data preparation.

[0019] In some embodiments, mask data preparation 132 includes various stages, including one or more of the following: logic operation (LOP) stage 132a, resolution enhancement technique (RET) stage 132b, mask rule checker (MRC) stage 132c, and lithography process checking (LPC) stage 132d. In some embodiments, each of the above stages receives an input layout diagram in GDSII, DFII, or OASIS file format from the preceding stage and outputs the processing result as an output layout diagram in GDSII, DFII, or OASIS file format to the subsequent stage. In some embodiments, some stages and / or operations described herein are omitted, and some additional stages and / or operations are included in mask data preparation 132. In some embodiments, these stages are based on... Figure 1 The different execution order of the examples in the middle.

[0020] In some embodiments, LOP stage 132a corresponds to modifying an input layout diagram (e.g., a layout diagram from layout plan 122 from design firm 120) according to manufacturing rules. In some embodiments, LOP stage 132a includes checking whether the input layout diagram satisfies a set of rules derived based on various manufacturer constraints, and modifying the input layout diagram accordingly to obtain an output layout diagram that satisfies the set of rules. In some embodiments, LOP stage 132a includes Boolean operations (e.g., AND, OR, XOR, NOT) to identify, combine, subtract, or select layout patterns for subsequent processes. In some embodiments, LOP stage 132a includes adding or removing dummy patterns.

[0021] In some embodiments, RET stage 132b corresponds to modifying the input layout pattern (e.g., the output layout pattern from LOP stage 132a) to obtain an output layout pattern that compensates for various limitations in the lithography process used to manufacture IC device 160. In some embodiments, RET stage 132b includes rule-based optical proximity correction (OPC) processes and / or model-based OPC processes, which correspond to using lithographic enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, or the like. In some embodiments, RET stage 132b further includes one or more other enhancement techniques, such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, RET stage 132b includes modifying the layout pattern based on inverse lithography technology (ILT), which corresponds to identifying a target wafer image and then determining the modified layout pattern as an inverse imaging problem.

[0022] In some embodiments, MRC phase 132c corresponds to examining the layout diagram that has undergone the process in RET phase 132b using a mask creation rule set, which includes specific geometric and / or connectivity constraints to ensure sufficient margin to account for variability or the like in the semiconductor manufacturing process. In some embodiments, MRC phase 132c also corresponds to modifying the layout diagram to compensate for lithographic implementation effects during mask fabrication 144, which may revert some modifications performed in RET phase 132b to satisfy the mask creation rules.

[0023] In some embodiments, LPC phase 132d corresponds to a simulation of a process that will be implemented by IC manufacturing plant 150 to manufacture IC device 160. The simulation of LPC phase 132d is based on a layout diagram from a previous phase (e.g., MRC phase 132c) to create one or more simulated manufacturing features representing corresponding portions of the IC device 160 to be manufactured based on the layout diagram from MRC phase 132c. Processing parameters in the LPC simulation include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The simulation of LPC phase 132d considers various factors such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitability factors or similar, or combinations thereof. In some embodiments, after one or more simulated manufacturing features have been created in LPC stage 132d, if the size, shape and / or spatial relationship of the simulated features fails to meet the design rules or design specifications, the process is repeated in RET stage 132b and / or MRC stage 132c to further refine the layout diagram.

[0024] In this example, following LPC stage 132d, mask data preparation 132 further includes a fracturing process (FRAC) stage 132e. In some embodiments, FRAC stage 132e receives input layout diagrams in GDSII, DFII, or OASIS file formats from the previous stage (e.g., LPC stage 132d) and outputs the processing results to a subsequent stage (e.g., mask manufacturing 144) as a mask archive in RDF format. In some embodiments, FRAC stage 132e corresponds to “fragmenting” design features into polygonal or other component shapes suitable for mask production.

[0025] Following mask data preparation 132 and during mask manufacturing 144, a mask 145 or a set of masks 145 (collectively, “masks 145”) is manufactured based on a modified layout plan and / or a mask file converted from the modified layout plan. In some embodiments, mask manufacturing 144 includes performing one or more photolithographic exposures based on the modified layout plan and / or mask file from mask data preparation 132. In some embodiments, a pattern is formed on the mask (photomask or pattern template) (e.g., mask 145) using a mechanism of electron beam (e-beam) or multiple electron beams based on the modified layout plan and / or mask file. Mask 145 can be formed using various techniques. In some embodiments, mask 145 is formed using a binary technique. In some embodiments, the mask pattern of the mask includes opaque areas and transparent areas. Radiation beams (such as ultraviolet (UV) beams) used to expose image-sensitive material layers (e.g., photoresist) coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary mask version of mask 145 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask 145 is formed using a phase-shifting technique. In the phase-shift mask (PSM) version of mask 145, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shift mask is an attenuating PSM or an alternating PSM. The mask produced by mask fabrication 144 is used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 153, in etching processes to form various etched regions in semiconductor wafer 153, and / or for other suitable processes.

[0026] IC manufacturing plant 150 is an IC manufacturing business, including one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturing plant 150 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (e.g., front-end-of-line FEOL manufacturing) of multiple IC products, a second manufacturing facility that provides back-end manufacturing (e.g., back-end-of-line, BEOL manufacturing) for the interconnection and packaging of IC products, and a third manufacturing facility that provides other services for the foundry business.

[0027] IC manufacturing plant 150 includes manufacturing tools 152 configured to perform various manufacturing operations on semiconductor wafers 153 to manufacture IC devices 160 according to a mask (e.g., mask 145). In various embodiments, manufacturing tools 152 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a chemical vapor deposition (CVD) chamber or a low-pressure chemical vapor deposition (LPCVD) furnace), a chemical mechanical polishing (CMP) system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0028] IC manufacturing plant 150 uses a mask 145 manufactured by mask manufacturing end 130 to manufacture IC device 160. Therefore, IC manufacturing plant 150 uses at least indirectly one or more layout patterns of layout plan 122 to manufacture IC device 160. In some embodiments, semiconductor wafer 153 is manufactured by IC manufacturing plant 150 using mask 145 to form IC device 160. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures based at least indirectly on one or more layout patterns of layout plan 122. Semiconductor wafer 153 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 153 further includes one or more of various doped regions, dielectric features, multilayer interconnects, or the like (formed at subsequent manufacturing steps).

[0029] In some embodiments, the design firm provides (e.g., also referred to as “delivery”) the layout design of the IC design after the layout design is completed and verified (e.g., via DRC, LVS, ERC, antenna inspection, or the like). In some embodiments, the design firm can complete 70% to 90% of the layout planning fairly quickly (e.g., based on one or more circuit blocks from a verified circuit library, one or more circuit blocks from a previous IC design that has been verified or even used in manufacturing, one or more circuit blocks that have been designed and verified in a timely manner, or the like). In some embodiments, the design firm may then need a considerable amount of time to complete the remaining portion of the layout planning (e.g., corresponding to circuit blocks based on a new design circuit, circuit blocks with increased operating frequencies, circuit blocks based on new design components, or the like). However, for OPC and ILT processing during mask data preparation, processing time tends to be based on layout complexity and / or circuit block size, regardless of the time spent completing the corresponding layout design for some circuit blocks.

[0030] Therefore, in some embodiments, layout planning can be divided into at least two parts. In some embodiments, while the first part of the layout planning is submitted to and processed by the mask manufacturing end, the design firm continues to process the second part of the layout planning. The mask manufacturing end then processes the second part of the layout planning and combines the processed second part with the result of processing the first part of the layout planning. Thus, the generation of the layout planning and its mask data preparation are performed in a pipeline manner. In some embodiments, the overall cycle time of layout design and mask preparation based on one or more paradigms of this disclosure (e.g., from the start of the design project at the design firm to the completion of mask preparation for the layout design at the mask manufacturing end) is 10 times faster than processing the entire layout planning after it is completed.

[0031] Figure 2 This is a functional block diagram of a process flow 200 for modifying layout planning to manufacture a photomask assembly according to some embodiments. In some embodiments, the process flow 200 corresponds to... Figure 1 The components and operations of the mask manufacturing end 130 are used to perform mask data preparation 132, such as operations of LOP stage 132a and / or RET stage 132b. In some embodiments, the layout plan corresponds to the IC design of the semiconductor component, and the photomask set manufactured based on the modified layout plan is used for the manufacturing of the semiconductor component.

[0032] exist Figure 2 In the process flow 200, the first version 212 of the layout plan is received (in Figure 2 The layout is marked as "A1 layout plan" and the second version 216 of the layout plan (in Figure 2 (This is labeled "A2 Layout Plan"). In some embodiments, a first version 212 of the layout plan originates from design firm 120 and is prepared for LOP phase 132a (e.g., it has been validated at design firm 120). Similarly, a second version 216 of the layout plan originates from design firm 120 and is prepared for LOP phase 132a (e.g., it has been validated at design firm 120). In some embodiments, the first version 212 of the layout plan includes a first portion of the layout plan but does not include a second portion of the layout plan. In some embodiments, the second version 216 of the layout plan includes a second portion of the layout plan. In some embodiments, the second version 216 of the layout plan also includes a first portion of the layout plan.

[0033] In some embodiments, design company 120 provides a first portion of the layout plan to mask manufacturing end 130 for mask preparation before the second portion of the layout plan is completed and / or verified. In some embodiments, the first portion of the layout plan includes one or more first circuit blocks and a first dummy layout pattern surrounding the first or more circuit blocks, and the second portion of the layout plan includes a second or more circuit blocks and a second dummy layout pattern surrounding the second or more circuit blocks. In some embodiments, the first portion of the layout plan includes one or more first circuit blocks occupying a first area of ​​the total layout plan area, and the second portion of the layout plan includes a second or more circuit blocks occupying a second area of ​​the total layout plan area. In some embodiments, the ratio of the first area to the sum of the first and second areas ranges from 70% to 90%. In some embodiments, when the first portion is nearing completion (e.g., the ratio is greater than 90%), the additional overhead of processing different portions of the layout plan based on individual OPC and / or ILT processes no longer justifies the time savings. In some embodiments, after the OPC and ILT processes are performed on the first part of the layout planning at the mask manufacturing end, but before the design company completes the second part of the layout planning, there is a significant waiting time that outweighs the time saved when the first part is insufficient (e.g., the ratio is less than 70%). In some embodiments, the range of the ratio may be determined based on the processing capacity of the mask manufacturing end and / or the design company.

[0034] In some embodiments, the mask manufacturing end 130 begins processing a first portion of the layout plan without waiting for a second portion of the layout plan that the design company 120 is still processing. In some embodiments, the mask manufacturing end 130 processes the second portion of the layout plan at a later time and merges the processed first portion and the processed second portion to obtain a complete RET-processed layout plan. Therefore, the overall cycle time for mask preparation is accelerated.

[0035] exist Figure 2 In this context, block 222 serves as a non-limiting example. After the first version 212 of the layout plan becomes available for use by the mask manufacturing end 130, the first version 212 of the layout plan is processed by a first Boolean process (e.g., in...). Figure 1In block 222, the first version 212 of the layout plan is processed to obtain a first set of Boolean parameters corresponding to the first version 212 of the layout plan. In some embodiments, the first set of Boolean parameters identifies the range of a first portion of the layout plan in the first version 212 of the layout plan. In some embodiments, the first set of Boolean parameters specifies the presence or absence of layout patterns in the first portion of the layout plan and / or organizes the layout patterns into a pattern group for subsequent OPC processes. In block 224, the first version 212 of the layout plan is processed based on the first OPC process and the range of the first portion of the layout plan identified in block 222. In block 226, the output of block 224 is further processed by the first ILT process to obtain a first processed layout plan 228 (in Figure 2 (The layout is marked as "A1" in the middle).

[0036] exist Figure 2 In block 232, as a non-limiting example, after the second version 216 of the layout plan is available for use by the mask manufacturing end 130, the second version 216 of the layout plan is processed by a second Boolean process to obtain a second set of Boolean parameters corresponding to the second version 216 of the layout plan. In some embodiments, the first set of Boolean parameters specifies the presence or absence of layout patterns in the first portion of the layout plan and / or the organization of layout patterns into a pattern group for subsequent OPC processes. In some embodiments, the second set of Boolean parameters identifies the second portion of the layout plan in the second version 216 of the layout plan and the range of the first portion of the layout plan. In some embodiments, the second portion of the layout plan is identifiable based on a comparison of the first version 212 of the layout plan and the second version 216 of the layout plan. In this example, in block 234, the second portion 236 of the layout plan (in Figure 2 The difference (marked as "layout difference") is identified based on applying a mutually exclusive OR (XOR) operation to the first set of Boolean parameters from block 222 and the second set of Boolean parameters from block 232 (e.g., in...). Figure 1 Mid-LOP stage 132a).

[0037] In block 242, the first processed layout plan 228 and the second part of the layout plan 236 are processed to obtain the processed combined layout plan 244 (in Figure 2(Catalyzed as "A3 Layout Plan"). In some embodiments, the post-processed combined layout plan 244 is the result of merging the first post-processed layout plan 228 and the second portion 236 of the layout plan processed based on the second OPC process. In some embodiments, block 242 includes obtaining a combined layout plan that merges the first post-processed layout plan 228 and the second portion 236 of the layout plan, and then processing the combined layout plan based on the second OPC process and the OPC processing region corresponding to the second portion 236 of the layout plan to obtain the post-processed combined layout plan 244. In some other embodiments, block 242 includes processing the OPC processing region corresponding to the second portion 236 of the layout plan based on the second OPC process to obtain the OPC-processed region, and then obtaining the post-processed combined layout plan 244 based on merging the first post-processed layout plan 228 and the OPC-processed region.

[0038] In block 246, based on the second ILT process and the ILT processing area corresponding to the second part of the layout plan, the processed combined layout plan 244 is processed to obtain the modified layout plan 248 (in Figure 2 (This is marked as "A3 Layout Plan"). In some embodiments, the ILT processing area is based on extending the outer edge of the second portion 236 of the layout plan outward by a merging ambit distance. In some embodiments, the merging ambit distance ranges from 6 nanometers (nm) to 20 nm. In some embodiments, the merging ambit distance is set large enough to ensure that optical interference between layout patterns at adjacent portion boundaries is taken into account during the second ILT process. However, in some embodiments, accuracy does not improve further after the merging ambit distance is set to be greater than a certain threshold.

[0039] In some embodiments, Figure 2 At any stage, the corresponding layout plan is stored or prepared in a file format, such as GDSII, DFII, or OASIS file format.

[0040] Figures 3A to 3C According to some embodiments, in Figure 2 A simplified plan view of the IC design layout planning for various processing stages of the 200-step process flow. In some embodiments, Figures 3A to 3C The various circuit blocks used to indicate the IC design are simplified, and details of the different layers and layout patterns of the IC design are not included. Figures 3A to 3C middle.

[0041] Figure 3AThis is a floor plan of the first version 300A of the IC design layout plan. In some embodiments, the first version 300A of the layout plan corresponds to... Figure 2 The first version of the layout plan, 212. Figure 3A In the first version 300A of the layout plan, the boundary 310 of the entire layout plan for the IC design is included. Figure 3A In this layout plan, the first version 300A includes a first portion 312 of the layout plan and the remaining portion 314 of the layout plan. The first portion 312 of the layout plan includes one or more circuit blocks 322, 324, 326, 328, 332, 334, 336, 338, 342, 344, 346, and 348, and a first dummy layout pattern (not labeled) surrounding the one or more circuit blocks. In some embodiments, the placement and size of the area of ​​the first dummy layout pattern are determined based on suitable design rules for the corresponding manufacturing process. In some embodiments, the area of ​​the first dummy layout pattern ranges from 10% to 20% of the area of ​​the first portion 312 of the layout plan.

[0042] In this example, circuit block 322 corresponds to the inter-integrated circuit block (I2C), circuit block 324 corresponds to the Mobile Industry Processor Interface (MIPI), circuit block 326 corresponds to the Digital Signal Processor (DSP), and circuit block 328 corresponds to the Display Controller (DISP). In this example, circuit block 332 corresponds to the Graphics Processing Unit (GPU), circuit blocks 334 and 336 correspond to two Central Processing Unit (CPU1) and CPU2) blocks, and circuit block 338 corresponds to the Level 3 Cache (L3 Cache). Similarly, in this example, circuit block 342 corresponds to NAND solid-state memory (NAND), circuit block 344 corresponds to the High Resolution Multimedia Interface (HDMI), circuit block 346 corresponds to the Universal Serial Bus controller (USB), and circuit block 348 corresponds to the Serial Advanced Technology Attachment Controller (SATA).

[0043] Figure 3B This is a plan view of the second version 300B of the IC design layout plan. In some embodiments, the second version 300B of the layout plan corresponds to... Figure 2 The second version of the layout plan, 216. Figure 3B In the second version of the layout plan 300B, besides the first part 312 of the layout plan (in... Figure 3A In, not described in Figure 3BIn addition to the first part (the middle part), the layout plan further includes a second portion 316. In this example, the second portion 316 of the layout plan includes one or more second circuit blocks 352, 354, 356, and 358, and a second dummy layout pattern (not labeled) surrounding the second one or more circuit blocks. In some embodiments, the placement and size of the area of ​​the second dummy layout pattern are determined based on suitable design rules for the corresponding manufacturing process. In some embodiments, the area of ​​the second dummy layout pattern ranges from 10% to 20% of the area of ​​the second portion 316 of the layout plan.

[0044] In this example, circuit block 352 corresponds to Double Data Rate Synchronous Dynamic Random Access Memory (labeled "DDR"), circuit block 354 corresponds to Serial Peripheral Interface (labeled "SPI"), circuit block 356 corresponds to Universal Asynchronous Receiver / Transmitter block (labeled "UART"), and circuit block 358 corresponds to another Serial Peripheral Interface (also labeled "SPI").

[0045] Figure 3C This is a plan view of the modified layout plan 300C for the IC design. In some embodiments, the modified layout plan 300C corresponds to... Figure 2 The modified layout plan 248. Figure 3C In this process, various circuit blocks have been processed based on one or more of the first OPC process, the second OPC process, the first ILT process, and the second ILT process, such as... Figure 2 As described in the example. For clarity of disclosure, Figure 3C The circuit blocks in the middle are still given to Figure 3A and Figure 3B The corresponding circuit block has the same reference number.

[0046] Figure 3C This includes an ILT processing region 318, within which a second ILT process is performed. In some embodiments, the ILT processing region 318 is based on a second portion 316 (in which the layout is planned) Figure 3B In, not described in Figure 3C The outer edge of the (middle) extends outward to form the merging ambit distance. In some embodiments, the merging ambit distance ranges from 6 nanometers to 20 nanometers.

[0047] Figure 4 This is a flowchart of a method 400 for modifying the layout planning of a photomask assembly according to some embodiments. In some embodiments, the layout planning corresponds to the IC design of a semiconductor component, and the photomask assembly is used for the fabrication of the semiconductor component.

[0048] According to some embodiments, method 400 uses, for example, an electronic design automation (EDA) system 500 (… Figure 5 (Discussed below) and Figure 1 The method 400 is implemented in an integrated circuit (IC) manufacturing system 100. In some embodiments, the method 400 is part of a mask data preparation process, such as... Figure 1 Mask data preparation 132. In some embodiments, method 400 corresponds to Figure 2 The process flow in 200. Figure 4 In the middle, method 400 includes blocks 410-450.

[0049] In block 410, the first version of the layout plan (e.g., Figure 3A The first version 300A in the first OPC process (e.g., Figure 2 Block 224 in the middle) continues the first ILT process (e.g., Figure 2 The block 226 in the middle is processed to obtain the first processed layout plan (e.g., Figure 2 The first post-processed layout plan 228). In some embodiments, the first version of the layout plan (e.g., Figure 3A The first version 300A in the document includes the first part of the layout plan (e.g., Figure 3A Part 1 of 312).

[0050] In block 420, based on a comparison of the first version of the layout plan and the second version of the layout plan (e.g., Figure 2 (234 in the middle) identifies the second part of the layout plan (e.g., Figure 3B The second part 316). In some embodiments, the second part of identifying the layout plan in block 420 includes obtaining a first set of Boolean parameters corresponding to a first version of the layout plan (e.g., Figure 2 (in block 222), obtain the second set of Boolean parameters corresponding to the second version of the layout plan (e.g., Figure 2 (block 232 in the middle), and based on applying a mutual exclusive OR (XOR) operation to the first set of Boolean parameters and the second set of Boolean parameters (e.g., Figure 2 (234) Identify the second part of the layout plan.

[0051] In some embodiments, a first portion of the layout plan includes one or more first circuit blocks and a first dummy layout pattern surrounding the first or more circuit blocks, and a second portion of the layout plan includes a second or more circuit blocks and a second dummy layout pattern surrounding the second or more circuit blocks. In some embodiments, the first portion of the layout plan includes one or more first circuit blocks occupying a first area of ​​the total area of ​​the layout plan, and the second portion of the layout plan includes a second or more circuit blocks occupying a second area of ​​the total area of ​​the layout plan. In some embodiments, the ratio of the first area to the sum of the first area and the second area ranges from 70% to 90%.

[0052] In block 430, obtain the processed combined layout diagram (e.g., Figure 2 The post-processing combined layout diagram 244 in the figure combines the results of the first post-processing layout plan and the second part of the layout plan based on the second OPC process (e.g., Figure 2 (244 in the middle).

[0053] In some embodiments, block 430 obtains a combined layout diagram based on obtaining a combined layout diagram that merges a first processed layout plan and a second part of the layout plan, and processes the combined layout diagram based on a second OPC process and an OPC processing area corresponding to the second part of the layout plan to obtain a processed combined layout diagram. In some other embodiments, block 430 obtains a processed OPC area based on processing an OPC processing area corresponding to the second part of the layout plan using a second OPC process, and obtains a processed combined layout diagram based on merging the first processed layout plan and the processed OPC area.

[0054] In block 440, based on the second ILT process (e.g., Figure 2 (block 246 in the middle) and ILT processing area (e.g., Figure 3C The ILT processing area 318 in the middle is processed and combined to obtain the modified layout plan (e.g., Figure 2 Modified layout plan 248 or Figure 3C (Modified layout plan 300C in the original text). In some embodiments, the ILT processing region corresponds to the second part of the layout plan. In some embodiments, the ILT processing region is based on extending the outer edge of the second part of the layout plan outward by a merging ambit distance. In some embodiments, the merging ambit distance ranges from 6 nanometers to 20 nanometers.

[0055] In block 450, the modified layout plan is stored in the memory device. In some embodiments, the photomask assembly is based on the modified layout plan.

[0056] Figure 5This is a block diagram of an electronic design automation (EDA) system 500 according to some embodiments.

[0057] In some embodiments, the EDA system 500 includes an automatic placement and routing (APR) system. According to one or more embodiments, the method of representing wire routing arrangements in the design layout diagrams described herein can be implemented, for example, using the EDA system 500 according to some embodiments.

[0058] In some embodiments, the EDA system 500 is a general-purpose computing device, including a hardware processor 502 and a non-transitory computer-readable storage medium 504. The storage medium 504 is encoded, among other things, to store computer program code 506, i.e., a set of executable instructions. The hardware processor 502 executes the instructions 506, which represent (at least partially represent) an EDA tool that implements some or all of the methods described herein (hereinafter referred to as the process and / or method) according to one or more embodiments.

[0059] Processor 502 is electrically coupled to computer-readable storage medium 504 via bus 508. Processor 502 is also electrically coupled to I / O interface 510 via bus 508. Network interface 512 is also electrically connected to processor 502 via bus 508. Network interface 512 is connected to network 514, enabling processor 502 and computer-readable storage medium 504 to be connected to external components via network 514. Processor 502 is configured to execute computer program code 506 encoded in computer-readable storage medium 504, such that system 500 can be used to perform part or all of the process and / or method. In one or more embodiments, processor 502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0060] In one or more embodiments, the computer-readable storage medium 504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 504 includes semiconductor or solid-state memory, magnetic tape, portable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 504 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0061] In one or more embodiments, storage medium 504 stores computer program code 506 configured to enable system 500 (where such execution (at least partially) represents an EDA tool) to perform part or all of the process and / or method. In one or more embodiments, storage medium 504 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, storage medium 504 stores a standard cell library 507, including standard cells as disclosed herein. In one or more embodiments, storage medium 504 stores one or more layout plans 509 corresponding to one or more layouts disclosed herein.

[0062] EDA system 500 includes an I / O interface 510. The I / O interface 510 is coupled to an external circuit system. In one or more embodiments, the I / O interface 510 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor arrow keys for transmitting information and commands to processor 502.

[0063] EDA system 500 also includes a network interface 512 coupled to processor 502. Network interface 512 allows system 500 to communicate with network 514, to which one or more other computer systems are connected. Network interface 512 includes wireless network interfaces such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired network interfaces such as Ethereum, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 500.

[0064] System 500 is configured to receive information via I / O interface 510. The information received via I / O interface 510 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 502. The information is transmitted to processor 502 via bus 508. EDA system 500 is configured to receive information related to the user interface (UI) via I / O interface 510. The information is stored as user interface (UI) 542 in computer-readable storage medium 504.

[0065] In some embodiments, a portion or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, a portion or all of the process and / or method is implemented as a software application, which is part of an additional software application. In some embodiments, a portion or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one embodiment of the process and / or method is a software application, which is part of an EDA tool. In some embodiments, a portion or all of the process and / or method is implemented as a software application used by an EDA system 500. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, or another suitable layout generation tool.

[0066] In some embodiments, a method for modifying a layout plan for a photomask assembly includes processing a first version of the layout plan based on a first optical proximity correction (OPC) process followed by a first inverse lithography (ILT) process to obtain a first processed layout plan, the first version of the layout plan including a first portion of the layout plan. The method includes identifying a second portion of the layout plan by comparing the first version and a second version of the layout plan, obtaining a processed combined layout plan that merges the first processed layout plan and the second portion of the layout plan processed based on a second OPC process, and processing the processed combined layout plan based on a second ILT process and an ILT processing region corresponding to the second portion of the layout plan to obtain a modified layout plan. The method further includes storing the modified layout plan to a memory device, with the photomask assembly based on the modified layout plan.

[0067] In some embodiments, a processing device for obtaining a modified layout plan of a photomask assembly includes a memory device and processing circuitry coupled to the memory device. The processing circuitry is configured to process a first version of the layout plan based on a first optical proximity correction (OPC) process followed by a first inverse lithography (ILT) process to obtain a first processed layout plan, the first version of the layout plan including a first portion of the layout plan. The processing circuitry is configured to identify a second portion of the layout plan by comparing the first version and a second version of the layout plan, obtain a processed combined layout plan resulting from merging the first processed layout plan and the second portion of the layout plan processed using a second OPC process, and process the processed combined layout plan based on a second ILT process and an ILT processing region corresponding to the second portion of the layout plan to obtain a modified layout plan. The processing circuitry is further configured to store the modified layout plan in the memory device, and the photomask assembly is based on the modified layout plan.

[0068] In some embodiments, a non-transitory computer-readable medium (CML) storage instruction, when executed by the processing circuitry of a processing device, causes the processing device to process a first version of a layout plan for a photomask assembly based on a first optical proximity correction (OPC) process followed by a first inverse photolithography (ILT) process to obtain a first processed layout plan, the first version of the layout plan including a first portion of the layout plan. The instruction causes the processing device to identify a second portion of the layout plan by comparing the first version and a second version of the layout plan, obtaining a processed combined layout plan that merges the first processed layout plan and the second portion of the layout plan processed using a second optical OPC process, and to process the processed combined layout plan based on a second ILT process and an ILT processing region corresponding to the second portion of the layout plan to obtain a modified layout plan. The instruction further causes the processing device to store the modified layout plan in the processing device's memory device, and the photomask assembly is based on the modified layout plan.

[0069] The foregoing has outlined the features of several embodiments or examples to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to implement the same purposes as the embodiments or examples introduced herein and / or achieve the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A method for modifying the layout planning of a photomask assembly, characterized in that, include: The first version of the layout plan is processed by a first optical proximity correction process followed by a first reverse lithography process to obtain a first processed layout plan, wherein the first version of the layout plan includes a first part of the layout plan. The second part of the layout plan is identified by comparing the first version of the layout plan with the second version of the layout plan; A processed combined layout diagram is obtained, which combines the first processed layout plan and the second part of the layout plan processed based on the second optical proximity correction process; The processed combined layout diagram is processed based on the second reverse lithography process and the reverse lithography processing area corresponding to the second part of the layout plan to obtain the modified layout plan; as well as The modified layout plan is stored in a memory device, and the photomask group is based on the modified layout plan.

2. The method according to claim 1, characterized in that, in: The layout plan corresponds to the integrated circuit design of semiconductor components, and The photomask set is used for the manufacture of the semiconductor component.

3. The method according to claim 1, characterized in that, The reverse lithography processing area is based on extending the outer edge of the second part of the layout plan outward to merge the influence distance.

4. The method according to claim 3, characterized in that, The range of the merging influence distance is 6 nanometers to 20 nanometers.

5. The method according to claim 1, characterized in that, The process of obtaining the combined layout diagram includes: Obtain a combined layout plan that merges the first processed layout plan and the second part of the layout plan; and The combined layout plan is processed based on the second optical proximity correction process and the optical proximity correction processing area corresponding to the second part of the layout plan to obtain the processed combined layout diagram.

6. The method according to claim 1, characterized in that, The process of obtaining the combined layout diagram includes: The optical proximity correction processing area corresponding to the second part of the layout plan is processed based on the second optical proximity correction process to obtain the optical proximity correction processed area; and The processed combined layout diagram is obtained by merging the first processed layout plan and the processed region of the optical proximity correction.

7. The method according to claim 1, characterized in that, The second part of identifying the layout plan includes: Obtain the first set of Boolean parameters corresponding to the first version of the layout plan; Obtain the second set of Boolean parameters corresponding to the second version of the layout plan; and The second part of the layout plan is identified by applying a mutually exclusive OR (XOR) operation to the first set of Boolean parameters and the second set of Boolean parameters.

8. The method according to claim 1, characterized in that, in: The first part of the layout plan includes a first or more circuit blocks and a first dummy layout pattern surrounding the first or more circuit blocks, and The second part of the layout plan includes a second or more circuit blocks and a second dummy layout pattern surrounding the second or more circuit blocks.

9. A processing device for obtaining a modified layout plan of a photomask assembly, characterized in that, include: Memory devices; as well as Processing circuitry, coupled to the memory device and configured to: The first version of the layout plan is processed by a first optical proximity correction process followed by a first reverse lithography process to obtain a first processed layout plan, wherein the first version of the layout plan includes a first part of the layout plan. The second part of the layout plan is identified by comparing the first version of the layout plan and the second version of the layout plan; A processed combined layout plan is obtained, which combines the first processed layout plan and the second part of the layout plan processed based on a second optical proximity correction process; The processed combined layout plan is processed based on the second reverse lithography process and the reverse lithography processing area corresponding to the second part of the layout plan to obtain the modified layout plan; as well as The modified layout plan is stored in the memory device, and the photomask group is based on the modified layout plan.

10. A non-transitory computer-readable medium, characterized in that, Its stored instructions, when executed by the processing circuitry of the processing device, cause the processing device to: The first version of the layout plan for the photomask assembly is processed by a first optical proximity correction process followed by a first reverse lithography process to obtain a first processed layout plan, wherein the first version of the layout plan includes a first part of the layout plan. The second part of the layout plan is identified by comparing the first version of the layout plan with the second version of the layout plan; A post-processed combined layout plan is obtained by merging the first processed layout plan and the second part of the layout plan processed based on the second optical proximity correction process; The processed combined layout plan is processed based on the second reverse lithography process and the reverse lithography processing area corresponding to the second part of the layout plan to obtain the modified layout plan; as well as The modified layout plan is stored in the memory device of the processing device, and the photomask group is based on the modified layout plan.

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