SRAF layout method, SRAF layout system, storage medium, and electronic device

Abstract

The application provides an SRAF layout method, an SRAF layout system, a storage medium and an electronic device. The SRAF layout method comprises obtaining graphic data of a target layer and loading hierarchical constraint conditions; performing pixelization processing on an SRAF addable area in the graphic data to form a pixel matrix, and classifying all pixel units in the pixel matrix; performing a brute force search on the pixel units based on a classification result to generate a plurality of candidate layout schemes of the SRAF; performing hierarchical checking on each candidate layout scheme according to the hierarchical constraint conditions; performing multi-dimensional quantitative evaluation on the candidate layout schemes that pass the checking, and screening an optimal SRAF layout scheme according to an evaluation result. In this way, the complex layout requirement can be met, and the optimal SRAF layout scheme can be screened.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to an SRAF layout method, an SRAF layout system, a storage medium, and an electronic device. Background Technology

[0002] In the semiconductor field, to improve exposure resolution and reliability, sub-resolution auxiliary features (SRAFs) are typically placed on the mask. SRAFs are generally located around the sparse main pattern in the mask and are smaller than the main pattern. They optimize the local illumination distribution (by scattering incident light) and are a key means of ensuring chip imaging quality.

[0003] As semiconductor technology continues to advance, chip design is becoming increasingly complex. This demands that SRAF placement methods be able to handle more detailed and complex patterns, and effective SRAF placement requires high precision in placement positions. Traditional SRAF placement methods primarily rely on rule-based insertion. For example... Figure 1 a~ Figure 1 As shown in b, optical simulation is first performed on the main graphic 01 of the test to determine the parameter rules of the unified SRAF based on the spacing of the main graphic 01. Then, the rules are directly applied to all main graphics 01 of the entire layout. However, problems such as additional development may occur, and manual debugging is required one by one. Therefore, the traditional method relies on experience, has poor adaptability, is easy to miss, and is difficult to meet the needs of complex layouts. Summary of the Invention

[0004] The purpose of this application is to provide an SRAF layout method, system, storage medium, and electronic device to solve the technical problem of relying on manual debugging and being difficult to meet the requirements of complex layouts, and to select a suitable SRAF layout scheme.

[0005] This application provides an SRAF layout method, including:

[0006] Obtain the graphic data of the target layer and load the hierarchical constraints;

[0007] The SRAF-addable regions in the graphic data are pixelated to form a pixel matrix, and all pixel units in the pixel matrix are classified.

[0008] Based on the classification results, a brute-force search is performed on the pixel units to generate several candidate layout schemes for SRAF.

[0009] Each candidate layout scheme is validated hierarchically according to the hierarchical constraints.

[0010] The candidate layout schemes that pass the verification are subjected to multi-dimensional quantitative evaluation, and the optimal SRAF layout scheme is selected based on the evaluation results.

[0011] Furthermore, in the SRAF layout method, before the step of pixelating the SRAF-addable region in the graphic data to form a pixel matrix, the method further includes:

[0012] A layout processing model is constructed, which is used to discretize the SRAF addable area in the graphic data into a number of pixel units based on the lithographic resolution, and the number of pixel units constitutes the pixel matrix.

[0013] Furthermore, in the SRAF layout method, the step of classifying all pixel units in the pixel matrix includes:

[0014] Based on the degree of influence of the pixel unit on photolithography imaging, all the pixel units are divided into effective pixels, critical pixels and invalid pixels, and the invalid pixels are eliminated in order to perform a brute-force search on the effective pixels and the critical pixels.

[0015] Furthermore, in the SRAF layout method, the step of performing a brute-force search on the pixel units based on the classification results to generate several candidate layout schemes for SRAF includes:

[0016] Binary encoding is performed on all the valid pixels and the critical pixels;

[0017] Divide all the binary-encoded pixel units into multiple search blocks;

[0018] A multi-threaded parallel enumeration of all binary sequences in each search block is employed, with each binary sequence corresponding to a candidate layout scheme; and,

[0019] Reverse the logical state of the binary sequence in the candidate layout scheme to obtain a new candidate layout scheme.

[0020] Furthermore, in the SRAF layout method, the hierarchical constraints include static constraints based on mask manufacturing rules and dynamic constraints based on the local complexity of the main graphic, and the static constraints are executed before the dynamic constraints during the verification phase.

[0021] Furthermore, in the SRAF layout method, the step of performing hierarchical verification on each candidate layout scheme according to the hierarchical constraints includes:

[0022] For each of the candidate layout schemes, static constraint verification and dynamic constraint verification are performed sequentially.

[0023] If the static constraints are violated, the candidate layout scheme is discarded directly.

[0024] If the dynamic constraints are violated, a score penalty will be applied to the candidate layout scheme currently being verified.

[0025] Furthermore, the SRAF layout method also includes:

[0026] If all the candidate layout schemes fail the verification, the threshold of the dynamic constraint is dynamically relaxed, and the brute-force search and subsequent processes are re-executed until at least one of the candidate layout schemes exists during the multi-dimensional quantitative evaluation process.

[0027] Furthermore, in the SRAF layout method, the step of performing multi-dimensional quantitative evaluation on the candidate layout schemes that have passed the verification includes:

[0028] For each candidate layout scheme, calculate the performance score of the candidate layout scheme under multiple indicators, and sum the scores of each indicator by weight to obtain the comprehensive score of the candidate layout scheme.

[0029] Furthermore, in the SRAF layout method, the multiple indicators include at least: linewidth uniformity, pattern edge roughness, process window, mask error enhancement factor, and SRAF manufacturing complexity. The scores for each indicator are obtained through rapid lithography simulation of the candidate layout schemes. The weighted summation is calculated as follows: Comprehensive Score = Σ (Indicator Score × Corresponding Weight), where the weight of linewidth uniformity is 25%–35%, the weight of pattern edge roughness is 20%–30%, the weight of process window is 15%–25%, the weight of mask error enhancement factor is 10%–20%, and the weight of SRAF manufacturing complexity is 5%–15%, with the sum of all weights being 100%.

[0030] Furthermore, in the SRAF layout method, the step of selecting the optimal SRAF layout scheme based on the evaluation results includes: traversing the comprehensive scores of all candidate layout schemes and selecting the candidate layout scheme with the highest comprehensive score; matching the selected candidate layout scheme with preset scoring conditions, and after satisfying the preset scoring conditions, taking the selected candidate layout scheme as the globally optimal SRAF layout scheme.

[0031] If all the candidate layout schemes fail the verification, or if the candidate layout scheme with the highest comprehensive score does not meet the preset scoring conditions, then the threshold of the dynamic constraint is dynamically relaxed, and the brute-force search and subsequent processes are re-executed until at least one of the candidate layout schemes exists in the multi-dimensional quantitative evaluation process, and the comprehensive score meets the preset scoring conditions.

[0032] Furthermore, in the SRAF layout method, the step of selecting the optimal SRAF layout scheme based on the evaluation results includes:

[0033] The globally optimal SRAF layout scheme is converted into a standard mask data format and then interfaced with an optical proximity correction system.

[0034] This application also provides an SRAF layout system, including: a data acquisition module, a graphics processing module, a pixel search module, a scheme verification module, and a scheme filtering module, wherein...

[0035] The data acquisition module is used to acquire the graphic data of the target layer and load hierarchical constraints;

[0036] The graphics processing module is used to pixelate the SRAF-addable regions in the graphics data to form a pixel matrix, and to classify all pixel units in the pixel matrix.

[0037] The pixel search module is used to perform a brute-force search on the pixel units based on the classification results and generate several candidate layout schemes for SRAF.

[0038] The scheme verification module is used to perform hierarchical verification on each of the candidate layout schemes according to the hierarchical constraints.

[0039] The scheme selection module is used to perform multi-dimensional quantitative evaluation of the candidate layout schemes that have passed the verification, and select the optimal SRAF layout scheme based on the evaluation results.

[0040] This application also provides a storage medium storing a plurality of instructions adapted for loading by a processor to perform the steps of any of the SRAF layout methods described herein.

[0041] In another aspect, this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of any of the SRAF layout methods described above.

[0042] In summary, the SRAF layout method, SRAF layout system, storage medium, and electronic device provided in this application acquire graphic data of a target layer, load hierarchical constraints, then pixelate the SRAF-addable regions in the graphic data to form a pixel matrix, classify all pixel units in the pixel matrix, and then perform a brute-force search on the pixel units based on the classification results to generate several candidate SRAF layout schemes. Next, each candidate layout scheme is validated hierarchically according to the hierarchical constraints, and then the validated candidate layout schemes are evaluated quantitatively in multiple dimensions. Based on the evaluation results, the optimal SRAF layout scheme is selected. This configuration overcomes the precision limitations of traditional regional addition, and through a pixel-level full traversal search logic, it offers high freedom, thoroughly checking the SRAF addition possibility of each pixel unit. Based on obtaining a suitable SRAF layout scheme, it can accurately lock the globally optimal addition scheme and ensure maximized fidelity of the lithographic pattern. Attached Figure Description

[0043] Those skilled in the art will understand that the accompanying drawings are provided to better understand this application and do not constitute any limitation on the scope of this application.

[0044] Figure 1 a~1b is a schematic diagram of the effect of a traditional SRAF layout method;

[0045] Figure 2 This is a flowchart illustrating an SRAF layout method provided in an embodiment of this application;

[0046] Figure 3 a~3d are schematic diagrams illustrating the effect of the SRAF layout method provided in the embodiments of this application;

[0047] Figure 4 This is a structural block diagram of an SRAF layout system provided in an embodiment of this application. Detailed Implementation

[0048] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of systems and methods consistent with some aspects of this application as detailed in the appended claims.

[0049] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0050] It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. In the following description, suffixes such as "module," "part," or "unit" used to denote elements are used solely for illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.

[0051] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the system or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0052] The purpose of this application is to provide an SRAF layout method, SRAF layout system, storage medium, and electronic device to solve the problems of traditional SRAF layout methods, such as reliance on experience, poor adaptability, easy omissions, and difficulty in meeting complex layout requirements. The following description refers to the accompanying drawings.

[0053] Please refer to Figure 2 This application provides an SRAF layout method, which may include the following steps:

[0054] Step S11: Obtain the graphic data of the target layer and load the hierarchical constraints.

[0055] In one implementation, the target layer refers to the set of geometric data in an integrated circuit design layout file (such as a GDSII file or an OASIS file) that is to be lithographically corrected and have SRAF added or supplemented.

[0056] like Figure 3 As shown in Figure a, after obtaining the graphic data of the target layer, the graphic data related to the main graphic 100 is determined. To further explain, graphic data refers to the shape, position, and layout information of all design graphics on the target layer, as well as die boundaries or tile division information. For example, in the application scenario of via layers, the graphic data is the geometric boundaries and distribution of all vias in that layer. In conventional SRAF layout methods, auxiliary features are arranged around the main graphic of the target layer based on the geometric rules and process constraints of the target layer (e.g., minimum spacing, minimum width, etc.).

[0057] In one implementation, the hierarchical constraints include static constraints based on Mask Rule Check (MRC) and dynamic constraints based on the local complexity of the main graphic, with static constraints taking precedence over dynamic constraints during the verification phase. Furthermore, if a candidate layout scheme (test data) has not undergone static constraint verification, it is directly discarded, and dynamic constraint verification is not performed.

[0058] Furthermore, static constraints refer to inviolable hard limits set based on the Mask Manufacturing Rules (MRC), including at least the minimum width of the SRAF, the minimum spacing between the SRAF and the main graphic, and the minimum spacing between SRAFs. Dynamic constraints refer to soft limits that adaptively adjust based on the local complexity of the main graphic (e.g., graphic density, number of corners).

[0059] Step S12: Pixelate the SRAF-addable regions in the graphic data to form a pixel matrix, and classify all pixel units in the pixel matrix.

[0060] In a specific implementation, the SRAF addable area refers to the spatial location around the main image that conforms to specific rules and can be used to place sub-resolution auxiliary graphics (SRAF) to optimize the imaging effect. Before executing step S12, the method further includes: Figure 3 As shown in b, the graphic data of the target layer is divided into regions, namely the main graphic 100 and the SRAF addable region 200.

[0061] In one embodiment, such as Figure 3 As shown in c, before the step of pixelating the SRAF addable region 200 in the graphic data to form a pixel matrix, the following steps are also included: constructing a layout processing model. The layout processing model is used to discretize the SRAF addable region 200 in the graphic data into several pixel units based on the lithographic resolution, and the pixel matrix 210 is composed of several pixel units.

[0062] The lithography resolution is matched to the minimum lithography unit size of the lithography machine. In other words, the SRAF addable area 200 is divided into several pixel units according to the minimum lithography unit size.

[0063] In one embodiment, the step of classifying all pixel units in the pixel matrix 210 includes: dividing all pixel units into effective pixels, critical pixels, and invalid pixels according to the degree of influence of the pixel units on photolithography imaging, and removing invalid pixels in order to perform a brute-force search on the effective pixels and critical pixels.

[0064] To further explain, after the SRAF-addable region 200 is discretized into several pixel units, the light transmission / phase change of each pixel unit will alter the light intensity of the main image through diffraction interference. The sensitivity / contribution weight of the pixel unit is the degree of influence of that pixel unit on the imaging of the main image. Furthermore, the closer the pixel unit is to the critical edge of the main image and falls within the optical diffraction coherence radius, the higher the degree of influence; conversely, the influence decays exponentially to 0 beyond the coherence radius. In this embodiment, the influence degree of the pixel unit can be directly calculated using the TCC transfer function, or the influence degree of the pixel unit can be measured using pixel perturbation differential simulation; this embodiment does not limit the specific method used.

[0065] To further clarify, effective pixels are located in the vicinity of the main image and have a significant impact on image quality; critical pixels are located at the edge of the process window or in areas sensitive to critical dimensions; and invalid pixels are located far from the main image or in areas where SRAF is prohibited by mask manufacturing rules. This embodiment classifies all pixel units in the pixel matrix to reduce the search space and improve the algorithm's computational efficiency.

[0066] Step S13: Perform a brute-force search on the pixel units based on the classification results to generate several candidate layout schemes for SRAF.

[0067] Brute-force search is a simple and direct search method that finds all feasible solutions by traversing all possible pixel units and checking each one to see if it meets the requirements. In this embodiment, the brute-force search is performed based on the classification results. It iterates through the binary state combination of "SRAF exists / SRAF does not exist" for each pixel unit. Furthermore, this embodiment uses binary encoding for the binary state combinations, where 0 represents no SRAF and 1 represents SRAF.

[0068] In one implementation, the step of performing a brute-force search on pixel units based on classification results to generate several candidate layout schemes for SRAF includes: binary encoding all valid pixels and critical pixels; dividing all binary-encoded pixel units into multiple search blocks; using multi-threaded parallel enumeration of all binary sequences in each search block, with each binary sequence corresponding to a candidate layout scheme; and flipping the logical state of the binary sequences in the candidate layout scheme to obtain a new candidate layout scheme.

[0069] For example, during the binary encoding of all valid pixels and critical pixels, "1" indicates that the pixel unit has an SRAF, and "0" indicates that the pixel unit does not have an SRAF. For example, in a search block of 8 pixel units, the binary sequence can be 01010101 or 10101010. 01010101 is a candidate layout scheme, and 10101010 is also a candidate layout scheme. For example, if a candidate layout scheme is 11110000, then after flipping the logical state (1 / 0) of the binary sequence, the resulting candidate layout scheme is 00001111.

[0070] This embodiment adopts a parallel computing architecture, which divides the binary combinations of all effective pixels and critical pixels into multiple search blocks, and uses multiple threads to enumerate all binary sequences in each search block in parallel.

[0071] To further explain, a parallel computing architecture is a computational organization method that decomposes the massive task of enumerating all candidate layout schemes into multiple independent subtasks using a specific strategy. These subtasks are then distributed to multiple computing units (such as CPU cores, threads, or computing nodes) for simultaneous execution, and the results of each subtask are finally merged to obtain the globally optimal solution. As an example, a block-based task allocation strategy can be used in a parallel computing architecture. Based on the first few bits of the binary sequence, the binary combinations of all effective pixels and critical pixels are divided into continuous and non-overlapping search blocks. These search blocks are allocated to independent threads for enumeration, and there are no data dependencies between the threads.

[0072] Step S14: Perform hierarchical verification on each candidate layout scheme according to the hierarchical constraints.

[0073] In one implementation, the step of performing hierarchical verification of each candidate layout scheme according to hierarchical constraints includes: for each candidate layout scheme, performing static constraint verification and dynamic constraint verification in sequence; if the static constraint is violated, the candidate layout scheme is directly discarded; if the dynamic constraint is violated, a score penalty is applied to the currently verified candidate layout scheme.

[0074] Step S15: Perform multi-dimensional quantitative evaluation on the candidate layout schemes that have passed the verification, and select the optimal SRAF layout scheme based on the evaluation results.

[0075] In one implementation, the step of performing multi-dimensional quantitative evaluation on the candidate layout schemes that have passed the verification includes: for each candidate layout scheme, calculating the performance score of the candidate layout scheme under multiple indicators, and weighting and summing the scores of each indicator to obtain the comprehensive score of the candidate layout scheme.

[0076] For example, the multiple metrics include at least: linewidth uniformity (CDU), pattern edge roughness (LER), process window (PW), mask error enhancement factor (MEEF), and SRAF manufacturing complexity, wherein the scores of each metric are obtained by performing rapid lithography simulation on candidate layout schemes.

[0077] Furthermore, the weighted summation is calculated as follows: Comprehensive score = Σ (index score × corresponding weight), where the weight of line width uniformity is 25%~35%, the weight of graphic edge roughness is 20%~30%, the weight of process window is 15%~25%, the weight of mask error enhancement factor is 10%~20%, and the weight of SRAF manufacturing complexity is 5%~15%, and the sum of each weight is 100%.

[0078] For example, linewidth uniformity (CDU) has a weight of 30%, graphic edge roughness (LER) has a weight of 25%, process window (PW) has a weight of 20%, mask error enhancement factor (MEEF) has a weight of 15%, and SRAF manufacturing complexity has a weight of 10%, based on the number and size uniformity of SRAFs.

[0079] The steps for selecting the optimal SRAF layout scheme based on the evaluation results include: traversing the comprehensive scores of all candidate layout schemes and selecting the candidate layout scheme with the highest comprehensive score; matching the selected candidate layout scheme with preset scoring conditions, and if the preset scoring conditions are met, selecting the selected candidate layout scheme as the globally optimal SRAF layout scheme. Figure 3 (d) shows a schematic diagram of the globally optimal SRAF layout scheme 211 selected.

[0080] Optionally, if the candidate layout scheme with the highest comprehensive score does not meet the preset scoring conditions, the threshold of the dynamic constraint is dynamically relaxed, and the brute-force search and subsequent processes are re-executed until at least one candidate layout scheme exists in the multi-dimensional quantitative evaluation process and the comprehensive score meets the preset scoring conditions.

[0081] Furthermore, when a candidate layout scheme passes the static constraint verification but violates the dynamic constraints, this embodiment applies a scoring penalty to the currently verified candidate layout scheme. This scoring penalty directly affects the total score after multi-dimensional quantitative evaluation. Therefore, this embodiment pre-sets the scoring conditions for the comprehensive score to ensure the quality of the final candidate layout scheme.

[0082] The step of selecting the optimal SRAF layout scheme based on the evaluation results includes: converting the globally optimal SRAF layout scheme into a standard mask data format and interfacing it with the Optical Proximity Correction (OPC) system.

[0083] In one embodiment, if all candidate layout schemes fail the validation, the threshold of the dynamic constraint is dynamically relaxed, and the brute-force search and subsequent processes are re-executed until at least one candidate layout scheme is found during the multi-dimensional quantitative evaluation. In other words, no candidate layout schemes are found during the multi-dimensional quantitative evaluation.

[0084] For example, the target layer's graphic data includes four parallel main graphic lines with a line width CD = 20 nanometers and very small spacing. The graphic data contains N = 30 effective pixels / critical pixels. The static constraint is that the spacing between the SRAF and the main graphic is ≥ 60 nanometers (MRC rule). The dynamic constraints include T1, T2, and T3, where T1 is that the number of local SRAF data points is less than 3, T2 is that the total area of ​​SRAF is less than 25%, and T3 is that the ratio deviation between the SRAF line width and the CD of the main graphic is less than ±8%. The relaxation step size is 2 increments for T1, 5% for T2, and 3% for T3. In the first round of search, all candidate layout schemes are enumerated in parallel. 30From approximately 1.07 billion candidate layout schemes, 120,000 physically feasible schemes were selected after static constraint verification (spacing ≥ 60 nm), and 800 schemes were selected after dynamic constraint verification (simultaneously satisfying T1, T2, and T3). Next, a multi-dimensional quantitative evaluation was performed. The candidate layout scheme with the highest comprehensive score after the first round of search had 3 SRAFs, a density of 24%, a size deviation of +7%, and a CDU score of 82. Although it met the dynamic constraints, its CDU score was lower than a preset tolerance threshold (e.g., 85), triggering dynamic relaxation to enter the second round of search. Before the second round of search, the first relaxation of dynamic constraints was performed, adjusting the step sizes of T1, T2, and T3. Specifically, T1 was defined as less than 5 local SRAFs, T2 as less than 30% of the total SRAF area, and T3 as less than ±11% of the ratio between the SRAF linewidth and the main graphic CD. Next, the brute-force search was repeated to filter out 5000 candidate layout schemes. Then, a multi-dimensional quantitative evaluation was performed. The candidate layout scheme with the highest comprehensive score in the evaluation results was 5 SRAFs, density of 28%, size deviation of +9%, and CDU score of 89. Thus, the globally optimal SRAF layout scheme was obtained.

[0085] Assuming that the globally optimal SRAF layout scheme is not found in the multi-dimensional quantitative evaluation after the second round of search, a second relaxation of the dynamic constraints is performed, adjusting the step sizes of T1, T2, and T3. Specifically, T1 is defined as less than 7 local SRAF data points, T2 as the total SRAF area ratio being less than 35%, and T3 as the deviation between the SRAF linewidth and the main graphic CD ratio being less than ±14%. Then, the brute-force search is repeated to select 15,000 candidate layout schemes, followed by multi-dimensional quantitative evaluation and selection. This process is repeated until the globally optimal SRAF layout scheme that meets all requirements is found.

[0086] Please refer to Figure 4 This application provides an SRAF layout system, including a data acquisition module 21, a graphics processing module 22, a pixel search module 23, a scheme verification module 24, and a scheme filtering module 25.

[0087] The data acquisition module 21 is used to acquire the graphic data of the target layer and load the hierarchical constraints;

[0088] The graphics processing module 22 is used to perform pixelation processing on the SRAF addable regions in the graphics data to form a pixel matrix, and to classify all pixel units in the pixel matrix.

[0089] The pixel search module 23 is used to perform a brute-force search on the pixel units based on the classification results and generate several candidate layout schemes for SRAF.

[0090] The scheme verification module 24 is used to perform hierarchical verification on each of the candidate layout schemes according to the hierarchical constraints.

[0091] The scheme selection module 25 is used to perform multi-dimensional quantitative evaluation of the candidate layout schemes that have passed the verification, and select the optimal SRAF layout scheme based on the evaluation results.

[0092] This application also provides a storage medium storing multiple instructions adapted for loading by a processor to execute the steps of the SRAF layout method described above. In specific implementations, the storage medium may include ROM, RAM, a magnetic disk, or an optical disk, etc.

[0093] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the SRAF layout method as described in any of the above claims.

[0094] In summary, by acquiring the graphic data of the target layer and loading hierarchical constraints, the SRAF-addable regions in the graphic data are pixelated to form a pixel matrix, and all pixel units in the pixel matrix are classified. Based on the classification results, a brute-force search is performed on the pixel units to generate several candidate SRAF layout schemes. Each candidate layout scheme is then validated hierarchically according to the hierarchical constraints. The validated candidate layout schemes are then subjected to multi-dimensional quantitative evaluation, and the optimal SRAF layout scheme is selected based on the evaluation results. This configuration overcomes the precision limitations of traditional regional addition. Through a pixel-level full-scale search logic, it offers high freedom, thoroughly checking the SRAF addition possibilities of each pixel unit. Based on obtaining a suitable SRAF layout scheme, it can accurately lock the globally optimal addition scheme while ensuring maximum fidelity of the lithographic pattern.

[0095] Regarding the modules / units included in the various systems and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various systems and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various systems and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various systems and products applied to or integrated into the terminal, all of their components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0096] It should be noted that the above embodiments can be combined with each other. The above description is only a description of preferred embodiments of this application and is not intended to limit the scope of this application in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of this application.

Claims

1. An SRAF layout method, characterized in that, include: Obtain the graphic data of the target layer and load the hierarchical constraints; The SRAF-addable regions in the graphic data are pixelated to form a pixel matrix, and the pixel units in the pixel matrix are classified. Based on the classification results, a brute-force search is performed on the pixel units to generate several candidate layout schemes for SRAF. Each candidate layout scheme is validated hierarchically according to the hierarchical constraints. The candidate layout schemes that pass the verification are subjected to multi-dimensional quantitative evaluation, and the optimal SRAF layout scheme is selected based on the evaluation results.

2. The SRAF layout method according to claim 1, characterized in that, Before the step of pixelating the SRAF-addable region in the graphic data to form a pixel matrix, the method further includes: A layout processing model is constructed, which is used to discretize the SRAF addable area in the graphic data into a number of pixel units based on the lithographic resolution, and the number of pixel units constitutes the pixel matrix.

3. The SRAF layout method according to claim 1, characterized in that, The steps for classifying all pixel units in the pixel matrix include: Based on the degree of influence of the pixel unit on photolithography imaging, all the pixel units are divided into effective pixels, critical pixels and invalid pixels, and the invalid pixels are eliminated in order to perform a brute-force search on the effective pixels and the critical pixels.

4. The SRAF layout method according to claim 3, characterized in that, The steps of performing a brute-force search on the pixel units based on the classification results to generate several candidate layout schemes for SRAF include: Binary encoding is performed on all the valid pixels and the critical pixels; Divide all the binary-encoded pixel units into multiple search blocks; A multi-threaded parallel enumeration of all binary sequences in each search block is employed, with each binary sequence corresponding to a candidate layout scheme; and, The logical state of the binary sequence in the candidate layout scheme is flipped to obtain a new candidate layout scheme.

5. The SRAF layout method according to claim 1, characterized in that, The hierarchical constraints include static constraints based on mask manufacturing rules and dynamic constraints based on the local complexity of the main graphic, and the static constraints are executed before the dynamic constraints during the verification phase.

6. The SRAF layout method according to claim 5, characterized in that, The steps of performing hierarchical verification on each candidate layout scheme according to the hierarchical constraints include: For each of the candidate layout schemes, static constraint verification and dynamic constraint verification are performed sequentially. If the static constraints are violated, the candidate layout scheme is discarded directly. If the dynamic constraints are violated, a score penalty will be applied to the candidate layout scheme currently being verified.

7. The SRAF layout method according to claim 1, characterized in that, The steps for performing multi-dimensional quantitative evaluation of the candidate layout schemes that have passed the verification include: For each candidate layout scheme, calculate the performance score of the candidate layout scheme under multiple indicators, and sum the scores of each indicator by weight to obtain the comprehensive score of the candidate layout scheme.

8. The SRAF layout method according to claim 7, characterized in that, The multiple indicators include at least: linewidth uniformity, pattern edge roughness, process window, mask error enhancement factor and SRAF manufacturing complexity, wherein the scores of each indicator are obtained by performing rapid lithography simulation on the candidate layout scheme; The weighted summation is calculated as follows: Overall score = Σ (indicator score × corresponding weight). The weights of the line width uniformity are 25% to 35%, the weights of the graphic edge roughness are 20% to 30%, the weights of the process window are 15% to 25%, the weights of the mask error enhancement factor are 10% to 20%, and the weights of the SRAF manufacturing complexity are 5% to 15%, and the sum of all weights is 100%.

9. The SRAF layout method according to claim 5, characterized in that, The steps for selecting the optimal SRAF layout scheme based on the evaluation results include: Iterate through the comprehensive scores of all the candidate layout schemes and select the candidate layout scheme with the highest comprehensive score; The selected candidate layout schemes are matched with preset scoring conditions. If the preset scoring conditions are met, the selected candidate layout schemes are taken as the globally optimal SRAF layout schemes. If all the candidate layout schemes fail the verification, or if the candidate layout scheme with the highest comprehensive score does not meet the preset scoring conditions, then the threshold of the dynamic constraint is dynamically relaxed, and the brute-force search and subsequent processes are re-executed until at least one of the candidate layout schemes exists in the multi-dimensional quantitative evaluation process, and the comprehensive score meets the preset scoring conditions.

10. The SRAF layout method according to claim 9, characterized in that, The steps following the selection of the optimal SRAF layout scheme based on the evaluation results include: The globally optimal SRAF layout scheme is converted into a standard mask data format and then interfaced with an optical proximity correction system.

11. An SRAF layout system, characterized in that, include: The data acquisition module is used to acquire the graphic data of the target layer and load hierarchical constraints. The graphics processing module is used to pixelate the SRAF-addable regions in the graphics data to form a pixel matrix, and to classify all pixel units in the pixel matrix. The pixel search module is used to perform a brute-force search on the pixel units based on the classification results and generate several candidate layout schemes for SRAF. The scheme verification module is used to perform hierarchical verification on each of the candidate layout schemes according to the hierarchical constraints. The scheme selection module is used to perform multi-dimensional quantitative evaluation of the candidate layout schemes that have passed the verification, and select the optimal SRAF layout scheme based on the evaluation results.

12. A storage medium, characterized in that, The storage medium stores a plurality of instructions adapted for loading by a processor to execute the steps of the SRAF layout method according to any one of claims 1-10.

13. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the SRAF layout method as described in any one of claims 1-10.

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