Photomask layout structure, wafer and wafer processing method

Abstract

The application provides a photomask layout structure, a wafer and a wafer processing method, and relates to the technical field of wafer processing. The photomask layout structure comprises a chip pattern area, an inner cutting path pattern area surrounding the chip pattern area and an outer cutting path pattern area surrounding the inner cutting path pattern area, the chip pattern area comprises a plurality of chip pattern areas arranged in an array, and there is a chip cutting path pattern area between adjacent chip pattern areas; the outer cutting path pattern area is used for arranging a baffle, and the inner cutting path pattern area is used for arranging a layout structure; wherein the sum of the widths of the inner cutting path pattern area and the outer cutting path pattern area is less than the width of the chip cutting path pattern area, the widths of the inner cutting path pattern area and the outer cutting path pattern area are equal, and the width of the outer cutting path pattern area is equal to the overlapping width between adjacent exposure areas when wafer exposure is performed based on the photomask layout structure. The photomask layout structure can arrange necessary layout structures in the cutting path on the basis of retaining the baffle and not occupying too much chip space.

Description

Technical Field

[0001] This application relates to the field of wafer fabrication technology, and more specifically, to a photomask layout structure, a wafer, and a wafer fabrication method. Background Technology

[0002] The dicing channels on a photomask are typically designed with layout structures such as photolithography marks, monitoring pads, and test keys. Furthermore, baffles are placed in some areas of the dicing channels. When the dicing channels are insufficient to accommodate the necessary layout structures, the size of the dicing channels needs to be increased. However, dicing channels that are too wide will occupy chip space. How to arrange the necessary layout structures on the dicing channels while retaining the baffles and not occupying too much chip space has become an urgent problem to be solved. Summary of the Invention

[0003] The purpose of this application includes, for example, providing a photomask layout structure, a wafer, and a wafer fabrication method, which enables the necessary layout structure to be arranged on the dicing channel while retaining the baffle and not occupying too much chip space.

[0004] The embodiments of this application can be implemented as follows: In a first aspect, embodiments of this application provide a photomask layout structure, including: The chip pattern area includes multiple chip patterns arranged in an array, and adjacent chip patterns have chip dicing pattern areas between them. The chip pattern area includes an inner dicing pattern area and an outer dicing pattern area. The outer dicing pattern area is used to set up a baffle, and the inner dicing pattern area is used to set up a layout structure. Wherein, the sum of the widths of the inner dicing pattern area and the outer dicing pattern area is less than the width of the chip dicing pattern area, the widths of the inner dicing pattern area and the outer dicing pattern area are equal, and the width of the outer dicing pattern area is equal to the overlap width between adjacent exposure areas when wafer exposure is performed based on the photomask layout structure.

[0005] Optionally, the width of the outer dicing pattern area is equal to one-third of the width of the chip dicing pattern area.

[0006] Optionally, the width of the chip dicing pattern area is equal to the sum of the widths of the two inner dicing pattern areas and the width of the outer dicing pattern area.

[0007] Optionally, the width of the outer cutting pattern area is a preset width or a multiple of a preset width, wherein the preset width is 60um, 62um or 80um.

[0008] Optionally, the width of the baffle is equal to the width of the outer cutting groove pattern area.

[0009] Optionally, the length of the baffle is half the length of the outer cutting groove pattern area or equal to the length of the outer cutting groove pattern area.

[0010] Optionally, the number of baffles is two, and the two baffles are in an L-shape.

[0011] Secondly, embodiments of this application provide a wafer including a plurality of exposure regions arranged in an array, each exposure region corresponding to the photomask layout structure, and each exposure region comprising: The chip area includes multiple chips arranged in an array, with chip dicing channels between adjacent chips; An inner dicing channel area surrounding the chip region and an outer dicing channel area surrounding the inner dicing channel area; The adjacent exposure areas partially overlap, and the width of the overlap between the adjacent exposure areas is equal to the width of the outer cutting channel area.

[0012] Optionally, the spacing between adjacent chip areas of the exposure area is equal to the width of the chip dicing area.

[0013] Thirdly, this application also provides a wafer fabrication method, comprising: Provide initial wafers; The initial wafer is exposed based on the photomask layout structure to form the wafer, wherein the distance between any adjacent chips of the wafer is equal.

[0014] The beneficial effects of the photomask layout structure, wafer, and wafer processing method provided in this application include, for example, that the photomask layout structure divides the traditional single dicing track surrounding the chip pattern area into two functionally separated regions, namely the inner dicing track pattern area and the outer dicing track pattern area. The baffle is retained in the outer dicing track pattern area, while the necessary layout structure can be arranged in the inner dicing track pattern area without increasing the overall width of the dicing track area. Therefore, when exposing the wafer based on the photomask layout structure, it will not occupy too much space on the chip, which can effectively increase the total number of chips that are finally actually cut on the wafer. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1This is a schematic diagram showing the arrangement relationship between the chip pattern area, the inner dicing pattern area, and the outer dicing pattern area in the photomask layout structure; Figure 2 A first schematic diagram showing two chip graphics in a photomask layout structure; Figure 3 A second schematic diagram showing two chip graphics in the chip graphic area of ​​the photomask layout structure; Figure 4 A schematic diagram showing a chip graphic area in a photomask layout structure; Figure 5 A schematic diagram showing the arrangement of an L-shaped baffle structure in the outer cutting path graphic area of ​​the photomask layout structure; Figure 6 This is a schematic diagram of the entire wafer. Figure 7 This is a partial schematic diagram of the wafer.

[0017] Icons: 100 - Mask layout structure; 110 - Chip pattern area; 111 - Chip pattern; 112 - Chip dicing pattern area; 120 - Inner dicing pattern area; 130 - Outer dicing pattern area; 140 - Baffle; 200 - Wafer; 210 - Exposure area; 220 - Chip; 230 - Chip dicing pattern area. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of this application, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, they are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0022] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0023] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0024] Please refer to Figures 1-3 This application provides a photomask layout structure 100, which may include a chip pattern area 110, an inner dicing pattern area 120 surrounding the chip pattern area 110, and an outer dicing pattern area 130 surrounding the inner dicing pattern area 120. The chip pattern area 110 includes a plurality of chip patterns 111 arranged in an array, and a chip dicing pattern area 112 is provided between adjacent chip patterns 111. The outer dicing pattern area 130 is used to set a baffle 140, and the inner dicing pattern area 120 is used to set the layout structure. The sum of the widths of the inner dicing pattern area 120 and the outer dicing pattern area 130 is less than the width of the chip dicing pattern area 112. The widths of the inner dicing pattern area 120 and the outer dicing pattern area 130 are equal, and the width of the outer dicing pattern area 130 is equal to the overlap width between adjacent exposure areas 210 when the wafer 200 is exposed based on the photomask layout structure 100.

[0025] In this embodiment, the chip pattern area 110 is provided with a plurality of chip patterns 111, and the plurality of chip patterns 111 are arranged in an array. The chip dicing pattern area 112 is disposed between two adjacent chip patterns 111 in the chip pattern area 110. The chip pattern area 110 corresponds to a chip area on the wafer 200, and each chip pattern 111 corresponds to a chip 220 on the wafer 200.

[0026] In this embodiment, the outer dicing pattern area 130 is arranged around the inner dicing pattern area 120, and a baffle 140 is provided on it. The width of the outer dicing pattern area 130 is set to the width of the baffle 140 area necessary for the photolithography stepper to overlap adjacent exposure fields. The inner dicing pattern area 120 is arranged adjacent to the chip pattern area 110 and does not participate in exposure overlap. Therefore, it can be used entirely for arranging necessary layout structures such as photolithography marks, monitoring pads, and test keys.

[0027] In this embodiment, the inner dicing pattern area 120 and the outer dicing pattern area 130 have the same width. The width of the outer dicing pattern area 130 is equal to the overlap width between adjacent exposure areas 210 when the wafer 200 is exposed based on the photomask layout structure 100. The baffle 140 is set in the outer dicing pattern area 130 to play a standard shielding and process protection role. Since the inner dicing pattern area 120 is not covered by overlap, its entire width can be effectively utilized, and the layout structure can be arranged without increasing the overall dicing size.

[0028] This embodiment can be understood as follows: by dividing the traditional single dicing track surrounding the chip pattern area 110 into two functionally separate regions, namely the inner dicing track pattern area 120 and the outer dicing track pattern area 130, the baffle 140 is retained in the outer dicing track pattern area 130, while the necessary layout structure can be arranged in the inner dicing track pattern area 120 without increasing the overall width of the dicing track area. As a result, when exposing the wafer 200 based on the photomask layout structure 100, it will not occupy too much space on the chip 220, which can effectively increase the total number of chips 220 that are finally actually cut from the wafer 200.

[0029] In this embodiment, the width of the outer dicing pattern area 130 is equal to one-third of the width of the chip dicing pattern area 112.

[0030] This can be understood as follows: the sum of the widths of the inner dicing pattern area 120 and the outer dicing pattern area 130 is less than the width of the chip dicing pattern area 112, while the width of the outer dicing pattern area 130 is equal to one-third of the width of the chip dicing pattern area 112, and the width of the outer dicing pattern area 130 is equal to the overlap width between adjacent exposure areas 210, that is, the non-overlapping width between adjacent exposure areas 210 is equal to two-thirds of the width of the chip dicing pattern area 112.

[0031] In an optional embodiment, the width of the chip dicing pattern area 112 is equal to the sum of the widths of the two inner dicing pattern areas 120 and the width of the outer dicing pattern area 130.

[0032] Since the width of the outer dicing pattern area 130 is equal to one-third of the width of the chip dicing pattern area 112, the remaining two-thirds of the width of the chip dicing pattern area 112 corresponds to the width of the two inner dicing pattern areas 120 of the adjacent exposure area 210. That is, the sum of the width of the two inner dicing pattern areas 120 and the width of the outer dicing pattern area 130 is equal to the width of the chip dicing pattern area 112.

[0033] When the stepper stitches adjacent exposure fields together, the exposure overlap is precisely set to the width of the outer dicing pattern area 130. This overlap merges the outer dicing pattern areas 130, which were originally distributed in the two exposure areas 210, into a single continuous region, while the inner dicing pattern areas 120 on both sides remain separate and do not participate in the overlap. Therefore, although adjacent exposure areas 210 overlap during the exposure stage, the resulting dicing traces on the wafer 200 surface have a uniform size, which is the sum of the width of the outer dicing pattern area 130 and the widths of the two inner dicing pattern areas 120. This size simultaneously meets the requirements for consistency in the cutting process and the space requirements for layout.

[0034] This embodiment can be understood as follows: by making the width of the overlapping portion of adjacent exposure areas 210 equal to the width of the outer dicing pattern area 130 itself, the spacing of the chip areas finally formed on the wafer 200 is strictly equal to the sum of the width of one outer dicing pattern area 130 and the width of two inner dicing pattern areas 120.

[0035] Optionally, the photomask layout structure 100 has two or four chip patterns 111 in a single chip pattern area 110. In the case of two chip patterns 111, such as... Figure 2 and Figure 3 As shown, the two chip patterns 111 can be arranged symmetrically up and down or symmetrically left and right; when there are four chip patterns 111, the four chip patterns 111 are arranged in a rectangular array.

[0036] In other embodiments, such as Figure 4 As shown, the photomask layout structure 100 has only one chip pattern 111 in a single chip pattern area 110, and at this time there is no chip dicing pattern area 112.

[0037] In this embodiment, the width of the outer cutting pattern area 130 is a preset width or a multiple of the preset width, wherein the preset width is 60um, 62um or 80um.

[0038] In this embodiment, the outer cut pattern area 130 serves as the baffle 140 arrangement area. 60μm, 62μm and 80μm are typical overlap reference values ​​verified in current mainstream processes. By using these values ​​or multiples thereof, the baffle 140 of the outer cut pattern area 130 can achieve the shielding effect of the outer cut pattern area 130 in the overlap area during exposure without adjusting the exposure equipment parameters.

[0039] It can be understood that this embodiment ensures that the structure is fully compatible with the overlap parameters of existing photolithography stepper exposure machines by setting the width of the outer cutting pattern area 130 to a preset width commonly used in the industry, namely any value among 60μm, 62μm or 80μm, or an integer multiple thereof.

[0040] In an optional embodiment, the width of the baffle 140 is equal to the width of the outer cutting pattern area 130.

[0041] It can be understood that when the baffle 140 is arranged in the outer cut track pattern area 130, it completely overlaps with the outer cut track pattern area 130. During exposure, the baffle 140 of the outer cut track pattern area 130 can achieve the complete masking effect of the outer cut track pattern area 130 in the overlapping area.

[0042] In an optional embodiment, the length of the baffle 140 is half the length of the outer cutting pattern area 130 or equal to the length of the outer cutting pattern area 130.

[0043] With the length of the baffle 140 being half the length of the outer dicing pattern area 130, the outer dicing pattern area 130 is distributed in a rectangular ring around the chip pattern area 110, with a baffle 140 arranged on each of its four sides: the top, bottom, left, and right sides. Each baffle 140 extends along the direction of its side, and its length is exactly half the total length of that side. For example, the top baffle 140 covers 50% of the upper area, the bottom baffle 140 covers 50% of the lower area, and the same applies to the left and right sides. This layout ensures that the baffle 140 can effectively cover the overlapping area of ​​adjacent exposure fields, providing available space for subsequent layout of the pattern structure in the unmasked parts of the inner dicing pattern area 120 and the outer dicing pattern area 130.

[0044] By setting the length of the baffle 140 to half the length of one side of the outer dicing pattern area 130, and setting one baffle 140 on each side of the outer dicing pattern area 130, a total of four baffles 140 are formed on the entire outer dicing pattern area 130 at intervals. The baffles 140 around the chip pattern area 110 are staggered vertically or horizontally, so that after exposure overlap, the overlapping part of adjacent exposure areas 210 is exactly covered by two baffles 140.

[0045] When the length of the baffle 140 is equal to the length of the outer dicing pattern area 130, the length of the baffle 140 is set to the full length of a single side of the outer dicing pattern area 130, so that each baffle 140 completely covers the outer dicing pattern area 130 on that side. For example, the top baffle 140 extends horizontally along the entire outer dicing pattern area 130, and the right baffle 140 extends vertically along the entire outer dicing pattern area 130. The two meet at the upper right corner of the chip pattern area 110 to form an L-shaped structure; or, the bottom baffle 140 extends horizontally along the entire outer dicing pattern area 130, and the left baffle 140 extends vertically along the entire outer dicing pattern area 130. The two meet at the lower left corner of the chip pattern area 110 to form an L-shaped structure.

[0046] In practical applications, this full-length coverage method ensures that the baffle 140 provides seamless shielding for the overlapping areas of adjacent exposure fields at the side boundary. Meanwhile, since only two orthogonal baffles 140 are provided, the outer dicing pattern areas 130 on the other two sides remain completely open, working together with the inner dicing pattern area 120 to form a continuous layout space for integrating lithography marks, monitoring pads, and test keys.

[0047] In an optional embodiment, two baffles 140 are provided on the outer cutting pattern area 130, wherein, as Figure 5 As shown, the two baffles 140 are L-shaped as a whole.

[0048] Two baffles 140 are provided on the outer dicing pattern area 130, and the two baffles 140 are L-shaped as a whole, that is, they cover the two adjacent sides of the outer dicing pattern area 130 respectively. For example, one baffle 140 extends horizontally along the bottom of the outer dicing pattern area 130, and the other baffle 140 extends vertically along the left side of the outer dicing pattern area 130, and they meet in the lower left corner of the chip pattern area 110 to form an L-shaped structure.

[0049] The L-shaped baffle 140 layout can effectively shield the overlapping areas of adjacent exposure fields at the corners, while the other two sides of the outer cut track pattern area 130 remain open, providing continuous space for the inner cut track pattern area 120 and the unshielded portion of the outer cut track pattern area 130 to arrange the necessary layout structure.

[0050] Please see Figure 6 , Figure 7 The embodiments of this application also provide a wafer 200, including a plurality of exposure regions 210 arranged in an array, each exposure region 210 corresponding to the photomask layout structure 100 described above. Each exposure region 210 includes: a chip region, an inner dicing channel region surrounding the chip region, and an outer dicing channel region surrounding the inner dicing channel region. The chip region includes a plurality of chips 220 arranged in an array, and adjacent chips 220 have chip dicing channel regions 230 between them; wherein, adjacent exposure regions 210 partially overlap, and the width of the overlap between adjacent exposure regions 210 is equal to the width of the outer dicing channel region.

[0051] It should be noted that the aforementioned wafer 200 is a product obtained by exposing the initial wafer using a stepper exposure machine based on the photomask layout structure 100. It includes multiple exposure areas 210 arranged in an array. Each exposure area 210 corresponds to the photomask layout structure 100, that is, the chip area corresponds to the chip pattern area 110, the inner dicing area corresponds to the inner dicing pattern area 120, the outer dicing area corresponds to the outer dicing pattern area 130, the chip 220 corresponds to the chip pattern 111, and the chip dicing area 230 corresponds to the chip dicing pattern area 112. In adjacent exposure areas 210, the outer dicing areas of adjacent exposure areas 210 overlap.

[0052] This can be understood as follows: after step-out exposure based on the photomask layout structure 100, multiple exposure areas 210 are formed in an array on the wafer 200. The outer dicing areas of adjacent exposure areas 210 overlap, so that the spacing between the two chip areas of any adjacent exposure area 210 is equal to the sum of the widths of the two inner dicing areas and the width of the outer dicing area.

[0053] In this embodiment, the spacing between the chip areas of adjacent exposure areas 210 is equal to the width of the chip dicing area 230.

[0054] This can be understood as the width of the chip dicing channel 230 being equal to the distance between adjacent chips 220. When the spacing between chip areas in adjacent exposure areas 210 is equal to the width of the chip dicing channel 230, the spacing between any two adjacent chips 220 is equal to the width of the chip dicing channel 230, enabling the wafer 200 to meet the requirements for consistency in the dicing process.

[0055] Embodiments of this application also provide a wafer fabrication method, which may include: Step S1: Provide the initial wafer.

[0056] Step S2: Expose the initial wafer based on the photomask layout structure 100 to form the wafer 200. The distance between any adjacent chips 220 of the wafer 200 is equal.

[0057] In the above steps, based on the photomask layout structure 100, the initial wafer is exposed by a stepper to form the wafer 200. In the wafer 200 structure, the distance between any adjacent chips 220 is equal and equal to the width of the chip dicing area 230, which is equal to the sum of the widths of the two inner dicing areas and the outer dicing area.

[0058] The wafer 200 produced by this wafer fabrication method has at least the following characteristics: the inner dicing area is arranged adjacent to the chip area and does not participate in the exposure overlap design; the outer dicing area surrounds the inner dicing area, and its width is consistent with the width of the outer dicing pattern area 130, both being preset widths (such as 60μm, 62μm, or 80μm); the overlap width of adjacent exposure areas 210 is the width of the outer dicing area. During this process, the overlap causes the outer dicing areas of adjacent exposure areas 210 to merge, while the inner dicing area does not participate in the overlap.

[0059] This method does not require modification of exposure equipment parameters or expansion of the total dicing width, significantly improving the space utilization of the dicing area. It is particularly suitable for the high integration manufacturing needs of large-size chips 220 under limited exposure fields.

[0060] In summary, this application provides a photomask layout structure 100, a wafer 200, and a wafer processing method. The photomask layout structure 100 includes a chip pattern area 110, an inner dicing pattern area 120, and an outer dicing pattern area 130. The outer dicing pattern area 130 is used to set a baffle 140, and the inner dicing pattern area 120 is used to set the layout structure. By dividing the traditional single dicing around each chip pattern area 110 into functionally separated inner dicing pattern area 120 and outer dicing pattern area 130, and setting a baffle 140 in the outer dicing pattern area 130, the inner dicing pattern area 120 can be arranged with the necessary layout structure without increasing the overall width of the dicing. Therefore, when exposing the wafer 200 based on the photomask layout structure 100, it will not occupy too much space of the chip 220, which can effectively increase the total number of chips 220 that are finally actually cut on the wafer 200.

[0061] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A photomask layout structure, characterized in that, include: The chip pattern area includes multiple chip patterns arranged in an array, and adjacent chip patterns have chip dicing pattern areas between them. The chip pattern area includes an inner dicing pattern area and an outer dicing pattern area. The outer dicing pattern area is used to set up a baffle, and the inner dicing pattern area is used to set up a layout structure. Wherein, the sum of the widths of the inner dicing pattern area and the outer dicing pattern area is less than the width of the chip dicing pattern area, the widths of the inner dicing pattern area and the outer dicing pattern area are equal, and the width of the outer dicing pattern area is equal to the overlap width between adjacent exposure areas when wafer exposure is performed based on the photomask layout structure.

2. The photomask layout structure according to claim 1, characterized in that, The width of the outer dicing pattern area is equal to one-third of the width of the chip dicing pattern area.

3. The photomask layout structure according to claim 1, characterized in that, The width of the chip dicing pattern area is equal to the sum of the widths of the two inner dicing pattern areas and the width of the outer dicing pattern area.

4. The photomask layout structure according to claim 1, characterized in that, The width of the outer cutting pattern area is a preset width or a multiple of a preset width, wherein the preset width is 60um, 62um or 80um.

5. The photomask layout structure according to claim 1, characterized in that, The width of the baffle is equal to the width of the outer cutting pattern area.

6. The photomask layout structure according to claim 5, characterized in that, The length of the baffle is either half the length of the outer cutting groove pattern area or equal to the length of the outer cutting groove pattern area.

7. The photomask layout structure according to claim 5, characterized in that, There are two baffles, and the two baffles are in an L-shape.

8. A wafer, characterized in that, The array includes multiple exposure areas, each of which corresponds to the photomask layout structure according to any one of claims 1 to 7, and each exposure area includes: The chip area includes multiple chips arranged in an array, with chip dicing channels between adjacent chips; An inner dicing channel area surrounding the chip region and an outer dicing channel area surrounding the inner dicing channel area; The adjacent exposure areas partially overlap, and the width of the overlap between the adjacent exposure areas is equal to the width of the outer cutting channel area.

9. The wafer according to claim 8, characterized in that, The spacing between adjacent chip areas of the exposure area is equal to the width of the chip dicing area.

10. A wafer fabrication method, characterized in that, include: Provide initial wafers; The initial wafer is exposed based on the photomask layout structure according to any one of claims 1 to 7 to form the wafer according to claim 8 or 9, wherein the distance between any adjacent chips of the wafer is equal.

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