Electronic voltage regulating voltage stabilizer voltage compensation method and system

Abstract

The application discloses a voltage compensation method and system of an electronic voltage-regulating stabilizer, and belongs to the technical field of voltage stabilization and regulation, which comprises the following steps: synchronously collecting power grid voltage, loop current, winding temperature and harmonic data, aligning time stamps and generating a multi-parameter sampling sequence, extracting three-dimensional discriminant factors, constructing an intelligent classification and identification model of power grid load disturbance to identify the load type, and dividing the load interval according to power data; relying on fuzzy logic to establish a linkage compensation coefficient dynamic correction model, iteratively solving four compensation sub-items and obtaining a total target compensation voltage through weighted fusion; dividing three-level intervals according to voltage-regulating deviation to match corresponding tap step length, synchronously switching passive compensation branches to output buffer voltage to suppress switching impact, and stabilizing the output in the rated interval through double closed-loop correction; the application can adapt to multiple types and multiple gradient load conditions, suppress voltage disturbance caused by harmonics, temperature rise and line loss, eliminate voltage mutation caused by tap cross-step switching, and significantly improve voltage stabilization precision and dynamic response performance.

Description

Technical Field

[0001] This invention belongs to the field of voltage regulation technology, specifically a voltage compensation method and system for electronic voltage regulators. Background Technology

[0002] Current electronic voltage regulators mostly employ fixed compensation coefficients and single-stage voltage regulation control schemes, which are suitable for a limited range of load types. When faced with mixed loads of resistive, inductive, capacitive, and nonlinear characteristics, they cannot dynamically match compensation parameters, making it difficult to address multiple interferences such as load fluctuations, line impedance losses, and device harmonic temperature rise. Traditional voltage regulation strategies do not differentiate between light load, constant load, heavy load, and full load gradient conditions, resulting in large calculation deviations in compensation amounts and insufficient output voltage regulation accuracy. Existing tap-type voltage regulation devices switch taps directly based on voltage deviations, lacking buffering measures during cross-stage switching, which can easily cause voltage surges and damage to both the circuit and the device. The conventional compensation algorithm only collects voltage and current signals and does not integrate multi-dimensional parameters such as winding temperature and harmonic amplitude, so it cannot quantify the interference of harmonic thermal stress on the voltage regulation effect. In addition, the traditional voltage regulation control lacks a periodic iterative correction mechanism. After the continuous change of the power grid conditions, the compensation error accumulates, making it difficult to keep the output voltage stable in the rated range for a long time. The overall dynamic response speed, anti-disturbance ability and adaptability to the operating conditions are poor, which cannot meet the actual use requirements of high-precision and shock-free voltage regulation in complex industrial power grids and multi-type nonlinear load scenarios. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention proposes a voltage compensation method and system for electronic voltage regulators. It simultaneously collects grid voltage, loop current, winding temperature, and harmonic data, aligns the timestamps to generate a multi-parameter sampling sequence, extracts three-dimensional discriminant factors, constructs an intelligent classification and identification model for grid load disturbances to identify load types, and divides load intervals based on power data. A dynamic correction model for the linkage compensation coefficient is established based on fuzzy logic, iteratively solves the four-element compensation components, and weighted fuses them to obtain the total target compensation voltage. Three-level intervals are divided according to voltage regulation deviation, matching corresponding tap step sizes. The passive compensation branch output buffer voltage is simultaneously switched to suppress switching shocks, and the output is stabilized within the rated range through dual closed-loop correction. This invention is adaptable to various types and gradient load conditions, suppresses voltage disturbances caused by harmonics, temperature rise, and line losses, eliminates voltage abrupt changes during tap switching, and significantly improves voltage regulation accuracy and dynamic response performance.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A voltage compensation method for an electronic voltage regulator includes:

[0006] Acquire the synchronous multi-parameter sampling sequence of the target power grid, extract three-dimensional discriminant factors based on the synchronous multi-parameter sampling sequence, and build a smart classification and identification model of power grid load disturbance based on the three-dimensional discriminant factors;

[0007] Based on the intelligent classification and identification model of power grid load disturbance, the power grid load type is identified, a four-level gradient load operation range is defined, and a dynamic correction model of linkage compensation coefficient is constructed to adapt to different load conditions.

[0008] The total target compensation voltage is obtained by iteratively solving the four-element compensation components of power grid feedforward deviation, load dynamic fluctuation, line impedance loss, and harmonic temperature rise interference through the linkage compensation coefficient correction model.

[0009] Based on the total target compensation voltage, the voltage regulation deviation range is divided into three levels and the corresponding tap voltage regulation step size is matched. When the voltage regulation operation is performed and there is a need for cross-level switching of tap position, the voltage zero-crossing time sequence characteristics are analyzed based on the real-time collected grid input voltage. The voltage zero-crossing time sequence characteristics are used as the synchronous control reference to synchronously drive the passive compensation branch to output micro buffer voltage and control the conduction and cutoff of bidirectional thyristors.

[0010] After completing this round of voltage synchronization regulation, the actual output voltage of the voltage regulator is re-acquired at an interval of half a power grid frequency cycle. The correction coefficients corresponding to the four-element compensation sub-items are iteratively corrected. Through the voltage dual closed-loop correction mechanism, the output voltage of the voltage regulator is converged and corrected to the rated operating range.

[0011] Specifically, the acquisition of the synchronous multi-parameter sampling sequence of the target power grid includes:

[0012] Based on the embedded data acquisition terminal, the grid input voltage waveform data and the voltage regulator output voltage waveform data output from the secondary side of the voltage transformer and the instantaneous circuit current waveform data output from the secondary side of the current transformer are synchronously acquired at a preset sampling frequency.

[0013] The device winding temperature value output by the distributed optical fiber temperature measurement device is received simultaneously, as well as the set of power grid subharmonic amplitude values ​​generated by the harmonic analyzer after analyzing the voltage and current waveforms of each phase based on the fast Fourier transform algorithm.

[0014] The collected power grid input voltage waveform data, voltage regulator output voltage waveform data, and circuit instantaneous current waveform data are aligned and packaged with the received device winding temperature value and power grid subharmonic amplitude set according to a unified timestamp to generate a synchronous multi-parameter sampling sequence.

[0015] Specifically, the process of extracting the three-dimensional discriminant factors includes:

[0016] Read the grid input voltage waveform data, regulator output voltage waveform data, circuit instantaneous current waveform data, device winding temperature value, and grid subharmonic amplitude set from the synchronous multi-parameter sampling sequence;

[0017] The instantaneous power theory algorithm is used to calculate the active and reactive power of the load based on the grid input voltage waveform and the instantaneous current waveform of the circuit. The first discriminant factor, namely the load power factor angle, is defined based on the ratio of active power to reactive power.

[0018] The voltage amplitude comparison method is used to calculate the voltage drop depth and voltage distortion rate based on the grid input voltage waveform and the voltage regulator output voltage waveform. The second discriminant factor, namely the voltage quality degradation index, is defined based on the weighted sum of the voltage drop depth and voltage distortion rate.

[0019] The thermal accumulation effect model is used to calculate the winding temperature rise rate based on the device winding temperature value. The third-dimensional discriminant factor, namely the harmonic thermal stress factor, is defined based on the product of the winding temperature rise rate and the sum of the squares of the amplitudes of each harmonic in the set of subharmonic amplitudes of the power grid.

[0020] The load power factor angle, voltage quality degradation index, and harmonic thermal stress factor are combined into a three-dimensional discriminant factor.

[0021] Specifically, the process of building the intelligent classification and identification model for power grid load disturbances is as follows:

[0022] Using the load power factor angle, voltage quality degradation index and harmonic thermal stress factor in the three-dimensional discriminant factors as input feature vectors, an initial classifier based on the support vector machine algorithm is constructed.

[0023] A sample dataset labeled with load types is retrieved from the historical power grid database. The initial classifier is trained using the sample dataset. During training, a grid search algorithm is used to optimize the kernel function parameters and penalty factor of the support vector machine. The trained classifier is then denoted as the intelligent classification and identification model for power grid load disturbances.

[0024] Specifically, the method of identifying grid load types based on the intelligent classification and identification model for grid load disturbances and delineating four-level gradient load operating ranges includes:

[0025] The three-dimensional discrimination factor is input into the trained intelligent classification and identification model of power grid load disturbance. After forward calculation by the intelligent classification and identification model of power grid load disturbance, the load type discrimination result is output. Based on the discrimination result, the load type of the current power grid is determined, and a load type identifier code uniquely corresponding to the load type is generated. The load types include resistive load, inductive load, capacitive load and nonlinear load.

[0026] Retrieve the corresponding historical operating power dataset based on the load type identifier code, and calculate the median power and standard deviation of the historical operating power dataset.

[0027] Based on the median power value, four gradient intervals were defined: light-load operation interval, normal-load operation interval, heavy-load operation interval, and full-load operation interval, respectively, using 0.5 times, 1 times, and 2 times the standard deviation of power as interval boundary thresholds.

[0028] The calculated active power of the load is compared with the four gradient intervals one by one to determine the gradient load operating interval to which the current active power belongs, and an interval level code is generated.

[0029] Specifically, the construction of a dynamic correction model for the linkage compensation coefficient adapted to different load conditions includes:

[0030] The current gradient load operating range is determined based on the range level code, and the initial value of the basic compensation coefficient matching the gradient load operating range is retrieved; the initial value of the basic compensation coefficient includes the voltage feedforward basic coefficient, the load fluctuation basic coefficient, the line impedance basic coefficient, and the harmonic temperature rise basic coefficient.

[0031] A fuzzy logic control algorithm is adopted, with the load power factor angle and voltage quality degradation index as fuzzy input variables and the correction amount of each basic compensation coefficient as fuzzy output variables. After fuzzification processing, fuzzy inference and defuzzification operation, the dynamic correction amount of each basic compensation coefficient is obtained.

[0032] The initial values ​​of each basic compensation coefficient are superimposed with the corresponding dynamic correction values ​​to generate a dynamic correction model for the linkage compensation coefficient.

[0033] Specifically, the process of generating the total target compensation voltage includes:

[0034] The current cycle's grid input voltage waveform, regulator output voltage waveform, and circuit instantaneous current waveform are input into the linkage compensation coefficient dynamic correction model. After calculation by the linkage compensation coefficient dynamic correction model, the feedforward gain correction coefficient, fluctuation suppression correction coefficient, impedance compensation correction coefficient, and temperature rise attenuation correction coefficient are obtained respectively.

[0035] The difference between the grid input voltage waveform and the regulator output voltage waveform is taken as the voltage deviation. The feedforward gain correction coefficient is multiplied by the voltage deviation to obtain the grid feedforward deviation compensation item. The difference between the current load active power and the previous load active power is taken as the power change rate. The fluctuation suppression correction coefficient is multiplied by the power change rate to obtain the load dynamic fluctuation compensation item. The instantaneous current waveform of the circuit is squared and multiplied by the impedance compensation correction coefficient to obtain the line impedance loss compensation item. The deviation between the device winding temperature value and the preset rated temperature value is multiplied by the temperature rise attenuation correction coefficient to obtain the harmonic temperature rise interference compensation item.

[0036] The weight coefficients corresponding to the current gradient load operating range are read from the linkage compensation coefficient dynamic correction model; the weight coefficients include feedforward weight, fluctuation weight, impedance weight and temperature rise weight;

[0037] The power grid feedforward deviation compensation item, load dynamic fluctuation compensation item, line impedance loss compensation item, and harmonic temperature rise interference compensation item are multiplied by their respective weighting coefficients and then added together to obtain a weighted compensation sum. The weighted compensation sum is then added to the instantaneous sampled value of the current voltage regulator output voltage to obtain the total target compensation voltage, which is then stored in the cache register.

[0038] Specifically, the step of dividing the voltage regulation deviation range into three levels based on the total target compensation voltage and matching the corresponding tap voltage regulation step size includes:

[0039] Read the total target compensation voltage from the cache register, and calculate the difference between the total target compensation voltage and the current regulator output voltage as the voltage regulation deviation value;

[0040] The absolute value of the voltage regulation deviation is compared with a preset first deviation threshold and a second deviation threshold. When the absolute value of the voltage regulation deviation is less than or equal to the first deviation threshold, it is determined to be a first-level voltage regulation deviation range and matched with a first tap voltage regulation step size. When the absolute value of the voltage regulation deviation is greater than the first deviation threshold and less than or equal to the second deviation threshold, it is determined to be a second-level voltage regulation deviation range and matched with a second tap voltage regulation step size. When the absolute value of the voltage regulation deviation is greater than the second deviation threshold, it is determined to be a third-level voltage regulation deviation range and matched with a third tap voltage regulation step size. The voltage regulation deviation range level and the corresponding tap voltage regulation step size are output to the tap switching actuator. The first deviation threshold is less than the second deviation threshold.

[0041] Specifically, when the voltage regulation operation is performed and a tap position switching requirement occurs, the voltage zero-crossing timing characteristics are analyzed based on the real-time collected grid input voltage, including:

[0042] After receiving the voltage regulation deviation range level and the tap voltage regulation step size, the tap switching actuator determines whether the difference between the current tap position and the target tap position is greater than 1. If it is greater than 1, it is determined that there is a tap position cross-level switching requirement.

[0043] When a cross-level switching requirement is determined, the grid input voltage waveform is collected in real time. The moment when the grid input voltage waveform crosses from the negative half cycle to the positive half cycle is recorded as the positive zero-crossing moment, and the moment when it crosses from the positive half cycle to the negative half cycle is recorded as the negative zero-crossing moment. The periodic stability and frequency offset of the grid voltage are calculated based on the positive and negative zero-crossing moments of multiple consecutive power frequency cycles.

[0044] The nearest positive or negative zero-crossing moment after the current moment is recorded as the synchronous zero-crossing moment;

[0045] The timing of the synchronous zero-crossing point, periodic stability, and frequency offset are used as the timing characteristics of the voltage zero-crossing point.

[0046] An electronic voltage regulator voltage compensation system includes:

[0047] A multi-channel synchronous acquisition module is used to generate synchronous multi-parameter sampling sequences;

[0048] The load intelligent identification module reads the synchronous multi-parameter sampling sequence, calculates the three-dimensional discrimination factor, runs the trained intelligent classification and identification model of power grid load disturbance with the three-dimensional discrimination factor as input, outputs the load type and generates an identification code, and then combines historical power data to divide the four-level gradient load operation range and outputs the range level code.

[0049] The compensation voltage module retrieves the initial value of the basic compensation coefficient based on the interval level code, uses a fuzzy logic control algorithm to solve the dynamic correction amount of each coefficient, builds a dynamic correction model of the linkage compensation coefficient, solves the four-element compensation sub-items based on the dynamic correction model of the linkage compensation coefficient, and superimposes them to generate the total target compensation voltage.

[0050] The voltage regulation deviation range determination module reads the total target compensation voltage in the cache register, divides the voltage regulation deviation range and matches the corresponding tap voltage regulation step size, and determines whether there is a tap cross-stage switching requirement.

[0051] The buffer voltage regulation control module collects the grid input voltage in real time, analyzes the zero-crossing timing characteristics through a zero-crossing comparator, and synchronously drives the bidirectional thyristor to conduct at the zero-crossing point to connect to the passive compensation branch and output micro-buffered voltage with half a power frequency cycle as the driving window. After the window ends, the pulse is removed to allow the thyristor current to cross zero and naturally turn off to disconnect the compensation branch.

[0052] Compared with the prior art, the beneficial effects of the present invention are:

[0053] 1. This invention proposes a voltage compensation method for electronic voltage regulators. This invention integrates multi-parameter synchronous sampling of voltage, current, winding temperature, and harmonic data to construct a three-dimensional discriminant factor and SVM intelligent classification model. This model can accurately identify four types of loads and divide them into four graded load ranges. Combined with fuzzy logic to dynamically correct the compensation coefficients, it calculates the compensation voltage by weighting four compensation components: grid feedforward deviation, load fluctuation, line impedance loss, and harmonic temperature rise. Unlike traditional fixed compensation parameter schemes, this method can dynamically adjust the compensation amount to adapt to different load conditions, effectively offsetting voltage deviations caused by line voltage drop, load abrupt changes, and harmonic heating, thus improving the accuracy of voltage compensation calculations under complex grid conditions. Simultaneously, it employs a half-frequency cycle iterative update of the correction coefficients combined with a dual closed-loop voltage correction mechanism to continuously converge the output voltage error, avoiding the accumulation of compensation errors caused by changes in operating conditions. This maintains the output voltage within the rated operating range over the long term, improving the steady-state voltage regulation accuracy and anti-disturbance capability of the voltage regulator.

[0054] 2. This invention proposes a voltage compensation method for electronic voltage regulators. Addressing the impact problem of tap switching across levels, this invention extracts the timing characteristics of the grid voltage zero-crossing point as a synchronous control benchmark. At the zero-crossing point, it synchronously switches the output micro-buffer voltage of the passive compensation branch. Combined with the bidirectional thyristor zero-crossing conduction and natural turn-off control, it effectively suppresses voltage surges during tap switching, reduces device impact losses, and extends the service life of the thyristor and voltage regulation equipment. Furthermore, based on the voltage regulation deviation, it divides the range into three levels to match differentiated tap voltage regulation step sizes. Small deviations result in small adjustments, while large deviations result in rapid voltage regulation, balancing voltage regulation stability and response speed. The entire control logic balances steady-state compensation accuracy and dynamic switching without impact characteristics, adapting to industrial nonlinear and multi-gradient mixed load scenarios. The overall voltage regulation performance and equipment reliability are significantly optimized compared to traditional voltage regulation solutions. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of a voltage compensation method for an electronic voltage regulator according to the present invention;

[0056] Figure 2 This is a flowchart illustrating the principle of a voltage compensation method for an electronic voltage regulator according to the present invention.

[0057] Figure 3 This is a voltage compensation system architecture diagram for an electronic voltage regulator according to the present invention. Detailed Implementation

[0058] Example 1

[0059] Please see Figures 1-2 The present invention provides an embodiment of a voltage compensation method for an electronic voltage regulator, the method comprising steps S1 to S4, including the following steps:

[0060] S1: Obtain the synchronous multi-parameter sampling sequence of the target power grid, extract the three-dimensional discrimination factor based on the synchronous multi-parameter sampling sequence, and build a smart classification and identification model of power grid load disturbance based on the three-dimensional discrimination factor;

[0061] The acquisition of the synchronous multi-parameter sampling sequence of the target power grid includes:

[0062] S1.1: Based on the embedded data acquisition terminal, synchronously acquire the grid input voltage waveform data and voltage regulator output voltage waveform data output from the secondary side of the voltage transformer and the instantaneous circuit current waveform data output from the secondary side of the current transformer at a preset sampling frequency.

[0063] This embodiment selects an electronic voltage regulator for distribution networks in urban-rural fringe residential areas as the practical application carrier. The power supply lines of this distribution network cover multi-story residential buildings, small processing equipment in street shops, and public lighting systems in the community. It also includes inductive equipment such as household air conditioners and water pumps, as well as nonlinear loads such as charging piles and frequency converters. The power grid load conditions are complex and changeable, and faults such as voltage drops, harmonic distortion, and excessive winding temperature rise occur frequently.

[0064] Furthermore, the embedded data acquisition terminal uses an industrial-grade multi-channel synchronous acquisition module. The multi-channel synchronous acquisition module integrates independent analog-to-digital conversion acquisition channels. Each acquisition channel corresponds to a set of voltage transformers and current transformers. All acquisition channels share the same local high-precision clock source, ensuring the synchronization of multi-channel waveform data acquisition from the hardware level and eliminating the problem of time offset caused by different electrical parameter acquisitions, which leads to distortion in subsequent discrimination factor calculations.

[0065] Furthermore, the voltage transformer adopts a low-voltage indoor precision voltage transformer. The primary side is directly connected in parallel to the input and output buses of the voltage regulator. The secondary side outputs a weak voltage waveform with an amplitude adapted to the input range of the embedded acquisition terminal, completely replicating the real-time fluctuation pattern of the primary side grid input voltage and the voltage regulator output voltage. The current transformer adopts a switchable through-core current transformer, which is connected in series to the main power circuit of the voltage regulator. On-site installation can be completed without power-off disassembly and assembly. The secondary side of the transformer continuously outputs an instantaneous current waveform signal that follows the changes in the main circuit current.

[0066] Furthermore, the preset sampling frequency is set to 10kHz, which is much higher than the 50Hz fundamental frequency of the power frequency. This allows for the complete capture of short-term electrical disturbances such as instantaneous voltage drops, instantaneous peak currents, and minor harmonic distortions, without losing disturbance details due to excessively large sampling intervals. The embedded data acquisition terminal has internal hardware sampling trigger logic. Each sampling trigger signal is synchronously sent to all voltage and current acquisition channels, and the instantaneous values ​​of the three waveforms are simultaneously latched at the same trigger moment, avoiding phase deviation caused by time-division acquisition.

[0067] Furthermore, the data acquisition process continues. The terminal is equipped with a ring-shaped data buffer. The buffer is divided into independent storage segments to store the power grid input voltage waveform data, the voltage regulator output voltage waveform data, and the circuit instantaneous current waveform data. Each buffer segment stores continuous waveform sampling points for a fixed duration. When the buffer is full, it automatically overwrites the earliest sampled data, ensuring uninterrupted acquisition while avoiding storage resource overflow. The complete waveform data that has not been covered in the buffer can be retrieved at any time for parametric fusion calculation.

[0068] S1.2: Synchronously receive the device winding temperature value output by the distributed optical fiber temperature measurement device, and the set of power grid subharmonic amplitude values ​​generated by the harmonic analyzer after analyzing the voltage and current waveforms of each phase based on the fast Fourier transform algorithm.

[0069] Furthermore, in this embodiment, distributed fiber optic temperature sensing probes are deployed on all the main voltage regulating winding, power conversion winding, and tap-switching reactor winding inside the electronic voltage regulator. The fiber optic probes are closely attached to the surface of the winding insulation layer and adopt a high-temperature resistant insulating encapsulation structure, which will not interfere with the conductivity of the windings or cause temperature measurement errors due to the alternating magnetic field of the windings. Multiple fiber optic temperature measurement lines are connected to the host of the distributed fiber optic temperature measurement device. The host continuously scans all temperature measurement points and outputs a set of real-time temperature values ​​of all windings every 20 milliseconds, i.e., the device winding temperature values.

[0070] Furthermore, the distributed fiber optic temperature measurement device and the embedded data acquisition terminal establish a real-time data interaction link through an industrial bus. The bus communication protocol is set with a millisecond-level synchronous response mechanism. Whenever the embedded acquisition terminal completes a set of voltage and current waveform synchronous sampling, it sends a synchronous reading command to the fiber optic temperature measurement host. The temperature measurement host immediately returns the latest winding temperature data, realizing the alignment of the acquisition sequence of electrical waveform data and winding temperature data, preventing the temperature data from lagging behind or leading the waveform data, which would cause deviations in the calculation of harmonic thermal stress factor.

[0071] Furthermore, the harmonic analyzer is an embedded integrated unit, directly mounted inside the embedded data acquisition terminal, eliminating the need for external independent devices. The harmonic analyzer reads the original waveform sampling sequences of each phase voltage and current synchronously acquired by the terminal in real time, continuously calling the Fast Fourier Transform processing flow to analyze the waveform spectrum components frame by frame; the analysis range covers the 2nd to 50th harmonics, extracting the corresponding amplitude information for each harmonic separately, and arranging all harmonic amplitudes in ascending order of harmonic order to form a standardized set of power grid harmonic amplitudes. Each set of amplitude data in the standardized power grid harmonic amplitude set is bound to the time identifier of the corresponding waveform sampling period.

[0072] Furthermore, the harmonic analyzer also receives the terminal hardware synchronous trigger signal and starts the spectrum analysis operation synchronously with the voltage and current waveform acquisition. After each round of waveform sampling is completed, it synchronously outputs a set of updated subharmonic amplitude values ​​to ensure that the acquisition cycles of harmonic amplitude data, winding temperature data, and voltage and current waveform data are completely matched.

[0073] S1.3: Align and package the collected grid input voltage waveform data, regulator output voltage waveform data, and circuit instantaneous current waveform data with the received device winding temperature value and grid subharmonic amplitude set according to a unified timestamp to generate a synchronous multi-parameter sampling sequence.

[0074] Furthermore, the embedded data acquisition terminal is equipped with a global timestamp generation unit. The global timestamp generation unit generates continuously increasing microsecond-level timestamps based on the terminal's local high-precision crystal oscillator. At the moment of each hardware synchronization sampling trigger, the global timestamp generation unit latches the current precise time value as a unified reference time identifier for all acquisition parameters in this round.

[0075] Furthermore, the timestamp alignment operation is further refined into a multi-layer verification process: The global reference timestamp of the current latch is extracted, and the sampling sub-timestamps inherent in the voltage waveform, output voltage waveform, and instantaneous current waveform are read respectively. The difference between the three types of waveform sub-timestamps and the global reference timestamp is verified to be within the allowable microsecond error range. If it exceeds the error range, the waveform data of this group is discarded, and a new synchronous sampling is restarted. The communication timestamp carried by the synchronously received device winding temperature value and the parsing timestamp bound to the power grid subharmonic amplitude set are retrieved and compared with the global reference timestamp. Only the temperature and harmonic data whose time difference meets the synchronization error standard are retained. All five types of parameter data that have passed verification and are time-aligned are uniformly mounted under the global reference timestamp to form a complete single-cycle multi-parameter data packet.

[0076] Furthermore, the packaging process adopts a layered structured encapsulation format. The header of the data packet is fixed with a unified global timestamp, the current power grid phase sequence identifier, and the sampling period number. The main body of the data packet stores five types of parameters in segments: the first segment stores a continuous multi-point power grid input voltage waveform sampling array; the second segment stores a voltage regulator output voltage waveform sampling array; the third segment stores a circuit instantaneous current waveform sampling array; the fourth segment stores an array of device winding temperature values ​​corresponding to all winding points; and the fifth segment stores an ordered set of power grid subharmonic amplitude values. A checksum field is added to the tail of the data packet, and a checksum value is generated by a cyclic redundancy check algorithm. This checksum is used to verify data integrity when reading the data packet and to prevent data loss or garbled characters during transmission or storage.

[0077] Furthermore, the terminal continuously generates standardized multi-parameter data packets according to a fixed period, and then sequentially stores the data packets from multiple consecutive periods into a local large-capacity storage medium in chronological order, forming a synchronous multi-parameter sampling sequence with continuous timing and strict synchronization of all parameters.

[0078] The process of extracting the three-dimensional discriminant factors includes:

[0079] S1.4: Read the grid input voltage waveform data, regulator output voltage waveform data, circuit instantaneous current waveform data, device winding temperature value and grid subharmonic amplitude set from the synchronous multi-parameter sampling sequence;

[0080] Furthermore, after the reading is completed, preprocessing operations are performed on the five types of raw parameters: For the three sets of waveform data, out-of-range abnormal peak sampling points that occasionally occur during the sampling process are removed, and the abnormal values ​​are replaced by the average of adjacent effective sampling points; the average temperature of all winding points in the device winding temperature value array is calculated as the unified winding temperature reference value for this round; the set of power grid subharmonic amplitudes is numerically normalized, removing small high-order harmonic amplitudes that are infinitely close to zero and have no practical impact, while retaining effective harmonic amplitude data that have a heat loss effect, and the normalized harmonic amplitude data retains the original order of harmonics; after all raw parameter reading and preprocessing operations are completed, the processed voltage, current, temperature, and harmonic data are stored in the program's independent memory cache area. The memory cache area stores various parameters in a separate partition to avoid data overlap between different parameters.

[0081] S1.5: The instantaneous power theory algorithm is used to calculate the active and reactive power of the load based on the grid input voltage waveform and the instantaneous current waveform of the circuit. The first discriminant factor, namely the load power factor angle, is defined based on the ratio of active power to reactive power.

[0082] Furthermore, the calculation process of the instantaneous power theory algorithm includes:

[0083] (1) Read the instantaneous sampling points of the grid input voltage and the instantaneous sampling points of the loop current in the same synchronization cycle from the memory buffer. The two sets of sampling points are completely matched one-to-one based on the same timestamp, and there is no phase shift.

[0084] (2) Multiply the instantaneous voltage value and the instantaneous current value at the same moment point by point to obtain the instantaneous apparent power value corresponding to each sampling moment. Sum all the instantaneous apparent power values ​​in a complete power frequency cycle, and then divide by the total number of sampling points in this cycle to calculate the cycle average apparent power.

[0085] (3) Decompose the voltage waveform and current waveform into active components in phase and reactive components in quadrature. Perform the whole-cycle average operation on the product of active components and the product of reactive components respectively, and solve for the current load cycle average active power and cycle average reactive power respectively.

[0086] Furthermore, active power represents the actual power consumed by the load, while reactive power represents the alternating power exchanged between the grid and the load without performing external work. The ratio of periodic average active power to periodic average reactive power can intuitively reflect the overall electrical properties of the load. The ratio of the obtained active and reactive power is converted, and the power ratio is mapped to an angle value based on the trigonometric function correspondence. This angle value fully characterizes the degree of phase shift of the load current lagging or leading the grid voltage, and is directly used as the first discriminant factor, the load power factor angle.

[0087] Furthermore, the characteristics of power factor angle changes under different load conditions are recorded in real time: under purely resistive load conditions, reactive power approaches zero, and the power factor angle value is infinitely close to zero; under inductive load conditions, reactive power is positive, and the power factor angle is positive; under capacitive load conditions, reactive power is negative, and the power factor angle is negative; under nonlinear load conditions, harmonic components will cause fluctuations in active and reactive power, and the power factor angle value will continue to oscillate slightly.

[0088] S1.6: The voltage amplitude comparison method is used to calculate the voltage drop depth and voltage distortion rate based on the power grid input voltage waveform and the voltage regulator output voltage waveform. The second discriminant factor, namely the voltage quality degradation index, is defined based on the weighted sum of the voltage drop depth and voltage distortion rate.

[0089] Furthermore, the calculation process for the voltage amplitude comparison method is as follows:

[0090] (1) Extract the amplitude of all sampling points of the grid input voltage waveform within a complete power frequency cycle, and obtain the effective value of the periodic voltage as the grid reference input voltage; simultaneously extract the effective value of the periodic output voltage waveform of the regulator as the actual output reference voltage of the regulator;

[0091] (2) Compare the difference between the grid reference input voltage and the standard rated supply voltage, and calculate the voltage drop depth. If the input voltage is lower than the rated standard, the drop depth value increases in the positive direction. When the input voltage is higher than the rated standard, the drop depth value is negative in the reverse direction, which fully reflects the overall voltage deviation of the grid side.

[0092] (3) Analyze the waveform distortion of the grid input voltage waveform, compare the amplitude difference between the actual voltage waveform and the standard sinusoidal reference waveform point by point, count the total cumulative difference over the whole cycle, and calculate the voltage distortion rate by combining the rated voltage reference. The larger the distortion rate, the more serious the distortion of the grid voltage waveform, and the more obvious the waveform deformation caused by harmonics and instantaneous disturbances.

[0093] Furthermore, this embodiment relies on tens of thousands of sets of multi-parameter sample data collected from the uninterrupted on-site operation of urban and rural residential power distribution networks over the past three years to complete the solidification and calibration of weighting parameters. Long-term on-site statistical results show that overall voltage dips and rises, or other overall amplitude deviations in the power grid, directly cause the voltage regulator's output voltage to continuously deviate from the rated range, requiring the regulator to continuously output a constant compensation for steady-state correction. Voltage distortion, on the other hand, only causes minor local waveform fluctuations, and its interference with the steady-state voltage regulation reference value is far lower than that of overall voltage deviation. Therefore, in the weighted calculation, the weight allocated to the voltage dip depth is significantly higher than the weight allocated to the voltage distortion rate. Thus, in this embodiment, the first weighting coefficient is set to 0.7, and the second... The weighting coefficient is set to 0.3. In the specific calculation, the calculated voltage drop depth is multiplied by the corresponding first weighting coefficient, and the voltage distortion rate is multiplied by the corresponding second weighting coefficient. The two weighted results are directly added together to obtain a comprehensive value that reflects the dual degradation of grid voltage deviation and waveform distortion. The comprehensive value is the second-dimensional discriminant factor voltage quality degradation index. When the second-dimensional discriminant factor voltage quality degradation index approaches zero, it means that the grid voltage amplitude is stable, the waveform is close to a standard sine wave, and the voltage quality is excellent. When the second-dimensional discriminant factor voltage quality degradation index continues to increase positively, it means that the voltage drop is serious, the waveform distortion is aggravated, the grid power supply quality continues to deteriorate, and the voltage compensation required by the voltage regulator increases accordingly.

[0094] S1.7: The thermal accumulation effect model is used to calculate the winding temperature rise rate based on the device winding temperature value. The third-dimensional discriminant factor, namely the harmonic thermal stress factor, is defined based on the product of the winding temperature rise rate and the sum of the squares of the amplitudes of each harmonic in the set of subharmonic amplitudes of the power grid.

[0095] Furthermore, the calculation process of the heat accumulation effect model is as follows:

[0096] (1) Retrieve the reference value of the average winding temperature in the current synchronous cycle, and at the same time read the historical value of the average winding temperature stored in the previous adjacent synchronous cycle. The time interval between the two cycles is fixed and known. Subtract the historical temperature from the current temperature to obtain the change in winding temperature within the cycle.

[0097] (2) Divide the temperature change by the fixed time interval between two sampling periods to calculate the winding temperature rise rate. A positive temperature rise rate indicates that the winding is continuously heating up, while a negative value indicates that the winding is cooling down. The larger the absolute value, the faster the winding temperature changes.

[0098] (3) Traverse all effective harmonic amplitudes in the set of subharmonic amplitudes of the power grid, perform a square operation on each harmonic amplitude separately, and sum all the square operation results in sequence to obtain the sum of squares of all subharmonic amplitudes. The harmonic current will generate additional eddy current losses inside the winding. The heat generated by the loss is directly related to the square of the harmonic amplitude. The sum of squares can quantify the total amount of additional heat generated by the harmonic.

[0099] Furthermore, the obtained winding temperature rise rate is directly multiplied by the sum of squares of the harmonic amplitudes. The product fully integrates the two major heat source factors: the winding temperature change rate and harmonic heating loss. This quantifies the thermal load impact on the winding under continuous harmonic action. The value of this product is defined as the third-dimensional discriminant factor, the harmonic thermal stress factor. The larger the value of the harmonic thermal stress factor, the more severe the harmonic loss and the faster the winding temperature rise under the current operating conditions. The higher the risk of overheating and aging of the voltage regulator winding and power devices, the higher the weight of the harmonic temperature rise interference compensation item will be during the compensation calculation process. This will specifically offset the problem of voltage regulation accuracy attenuation caused by harmonic heating.

[0100] S1.8: Combine the load power factor angle, voltage quality degradation index, and harmonic thermal stress factor into a three-dimensional discriminant factor.

[0101] The process of building the intelligent classification and identification model for power grid load disturbances is as follows:

[0102] S1.9: Using the load power factor angle, voltage quality degradation index and harmonic thermal stress factor in the three-dimensional discriminant factors as input feature vectors, an initial classifier based on the support vector machine algorithm is constructed.

[0103] Furthermore, the initial classifier construction process is as follows:

[0104] (1) The model input dimension is determined to be three-dimensional. The input interface is fixed to receive the three-dimensional discriminant feature vector generated above. The input layer does not perform additional feature transformation and directly sends the original values ​​of the three discriminant factors into the internal computing unit of the classifier. The classifier is the existing technology in this field and is not an inventive solution of this application. It will not be described in detail here.

[0105] (2) The radial basis kernel function is selected as the core kernel function of the support vector machine. This kernel function is suitable for the three-dimensional nonlinear feature space partitioning and can accurately distinguish the three-dimensional discriminant factor distribution intervals corresponding to different load types. Compared with linear kernel function and polynomial kernel function, it has higher accuracy in identifying the discrete distribution of features under multiple disturbance coupling conditions of the power grid.

[0106] (3) Build a basic operational framework for the classifier. The framework includes a kernel function operation unit, a margin constraint unit, and a classification output unit. The operation unit completes the high-dimensional space mapping of the three-dimensional feature vector, the margin constraint unit controls the tolerance range of the classification boundary, and the classification output unit outputs discrete discriminant labels for the load type, thus completing the initial basic structure of the classifier without training parameters.

[0107] S1.10: Retrieve a sample dataset labeled with load types from the historical power grid database, and use the sample dataset to train the initial classifier. During training, a grid search algorithm is used to optimize the kernel function parameters and penalty factor of the support vector machine. The trained classifier is denoted as the intelligent classification and identification model of power grid load disturbance. The grid search algorithm is existing technology in this field and is not an inventive solution of this application, so it will not be described in detail here.

[0108] Furthermore, the historical power grid database completed the collection and labeling of massive amounts of field samples in advance. The sample collection scenarios covered various distribution network locations such as residential areas, shops and factories, charging pile stations, and factory lighting. Each sample data was bound to a corresponding synchronous multi-parameter sampling sequence and a three-dimensional discriminant factor vector. At the same time, the corresponding load type labels were manually labeled. The labels were divided into four categories: resistive load, inductive load, capacitive load, and nonlinear load. Some mixed load samples were simultaneously labeled with the main load type as the classification benchmark. The database internally balanced the samples, so that the number of samples of the four types of loads was basically equal, avoiding the model classification bias caused by the excessive proportion of samples of a single type.

[0109] Furthermore, the model training process is as follows: the entire labeled sample dataset is divided into a training set and a validation set. The training set accounts for 80% of the total samples and is used for iterative learning of model parameters. The validation set accounts for 20% and is used to verify the classification accuracy after each round of parameter optimization. All three-dimensional discriminant factor samples in the training set are input into the initial classifier to start iterative training. During the training process, a grid search algorithm is called simultaneously. The algorithm predefines the range of values ​​for the kernel function width parameter and the penalty factor, and iterates through all parameter combinations within the range according to a fixed step size. After each set of parameter combinations is substituted into the classifier to complete one round of training, the corresponding score is calculated using the validation set samples. Class accuracy; after fully traversing all parameter combinations, the set of kernel function parameters and penalty factors with the highest recognition accuracy on the validation set are selected as the optimal parameters, and the optimal parameters are solidified and written into the support vector machine classifier; the optimal parameters are used to retrain all training set samples once to complete model convergence. The convergence criterion is that the fluctuation of the recognition accuracy on the validation set is lower than the preset minimum threshold for two consecutive rounds of training. After the model converges, all operation parameters are locked. The final converged classifier is officially named the Power Grid Load Disturbance Intelligent Classification and Identification Model. The model is solidified and stored on the local storage medium of the embedded terminal, and can be called in real time to complete the online identification of load type.

[0110] S2: Based on the intelligent classification and identification model of power grid load disturbance, identify the power grid load type, delineate the four-level gradient load operation range, and construct a dynamic correction model of linkage compensation coefficient that adapts to different load conditions.

[0111] The intelligent classification and identification model based on power grid load disturbance identifies power grid load types and delineates four-level gradient load operating ranges, including:

[0112] S2.1: Input the three-dimensional discriminant factor into the trained intelligent classification and identification model for power grid load disturbances. After forward calculation by the intelligent classification and identification model for power grid load disturbances, output the load type discrimination result. Determine the load type of the current power grid based on the discrimination result and generate a load type identifier code that uniquely corresponds to the load type. The load types include resistive loads, inductive loads, capacitive loads, and nonlinear loads.

[0113] Furthermore, the real-time execution process of online load identification is as follows:

[0114] (1) Each time a new set of three-dimensional discriminant factor feature vectors is generated, the vectors are automatically pushed to the input interface of the intelligent classification and identification model for power grid load disturbances. No manual intervention is required, and the entire process of sampling, factor extraction and load identification is automated and continuous.

[0115] (2) The intelligent classification and identification model for power grid load disturbance starts forward calculation. First, the three-dimensional low-dimensional features are mapped to the high-dimensional feature space through the radial basis kernel function. In the high-dimensional space, the optimal classification hyperplane that has been trained is called to make feature partitioning judgment and match the load feature partition to which the current three-dimensional factor belongs.

[0116] (3) The power grid load disturbance intelligent classification and identification model outputs discrete load type discrimination results, which correspond to one of the four types of loads: resistive, inductive, capacitive, and nonlinear. If the three-dimensional factor features are in the transition range between the two types of loads, the power grid load disturbance intelligent classification and identification model determines the main load type with the highest current power grid proportion based on the sample training weight as the output result.

[0117] (4) After identifying the load type, immediately retrieve the corresponding digital identifier code. The system pre-stores fixed digital identifier codes corresponding to four types of loads: resistive load corresponds to identifier code 1, inductive load corresponds to identifier code 2, capacitive load corresponds to identifier code 3, and nonlinear load corresponds to identifier code 4. The identifier code is stored synchronously with all parameter data in this round.

[0118] S2.2: Retrieve the corresponding historical operating power dataset based on the load type identifier code, and calculate the median power and standard deviation of the historical operating power dataset;

[0119] Furthermore, the local storage partition of the embedded terminal is divided into independent historical databases according to the load type identification code. Each type of identification code corresponds to a unique historical operating power dataset. The dataset accumulates and stores the active power value of the load calculated in each synchronization cycle under this type of load condition. The data is automatically updated on a rolling basis. Old historical power data older than 90 days is automatically cleaned up, and only the effective operating data of the last three months is retained, balancing storage space occupation and data statistical representativeness. After the program recognizes the current load type identification code, it directly jumps to read the complete historical operating power dataset in the corresponding independent partition.

[0120] Furthermore, the complete calculation process for the median power value is as follows: All historical active power values ​​in the historical operating power dataset are sorted in ascending order from smallest to largest; the total number of power values ​​after sorting is counted. If the total number is odd, the power value in the middle of the sorted sequence is taken as the median power value; if the total number is even, the average of the two adjacent power values ​​in the middle of the sequence is taken as the median power value. The median value is not affected by extreme ultra-large or ultra-small instantaneous power anomalies and can stably represent the long-term normal operating power level of this type of load.

[0121] Furthermore, the power standard deviation calculation process is as follows: subtract the solved power median value from each historical active power value in the historical operating power data set to obtain the power deviation of a single data point; square all deviations respectively, and calculate the arithmetic mean of all squared results to obtain the variance; take the square root of the variance to obtain the power standard deviation; the standard deviation quantifies the long-term fluctuation range of the active power of this type of load. The larger the standard deviation value, the more frequent and significant the load power fluctuations, and the stronger the load dynamic disturbance.

[0122] S2.3: Based on the median power value, four gradient intervals are defined: light load operation interval, normal load operation interval, heavy load operation interval, and full load operation interval, respectively using 0.5 times, 1 times, and 2 times the standard deviation of power as interval boundary thresholds.

[0123] Furthermore, the interval boundary thresholds are calibrated in steps: using the median power value as the central benchmark for interval division, the first interval boundary threshold is the median power value plus 0.5 times the power standard deviation, the second interval boundary threshold is the median power value plus 1 times the power standard deviation, and the third interval boundary threshold is the median power value plus 2 times the power standard deviation. Based on the three sets of thresholds, four continuous power intervals are divided: active power values ​​less than or equal to the first interval boundary threshold are defined as light-load operation intervals; active power values ​​greater than the first interval boundary threshold and less than or equal to the second interval boundary threshold are defined as normal-load operation intervals; active power values ​​greater than the second interval boundary threshold and less than or equal to the third interval boundary threshold are defined as heavy-load operation intervals; and active power values ​​greater than the third interval boundary threshold are defined as full-load operation intervals.

[0124] Furthermore, the four types of gradient load operating ranges correspond to different load losses and voltage regulation compensation requirements: under light load conditions, line losses are small and power fluctuations are gentle, requiring a smaller compensation correction range; under constant load conditions, the equipment operates under long-term standard conditions, and the compensation coefficient adopts the basic standard value; under heavy load conditions, winding heating intensifies and line losses increase, and the compensation correction amount increases accordingly; under full load conditions, the power is close to the rated output limit of the voltage regulator, and the superposition of harmonic thermal stress and voltage fluctuation disturbances is the strongest, with the compensation coefficient correction range reaching its maximum. After the range is divided, the four sets of range boundary thresholds are bound and stored with the corresponding load type identifier codes, remaining valid until the next round of load type switching and recalculation and update.

[0125] S2.4: Compare the currently calculated active power of the load with the four gradient intervals one by one to determine the gradient load operating interval to which the current active power belongs, and generate the interval level code.

[0126] The construction of a dynamic correction model for the linkage compensation coefficient adapted to different load conditions includes:

[0127] S2.5: Determine the current gradient load operating range based on the range level code, and retrieve the initial value of the basic compensation coefficient that matches the gradient load operating range; the initial value of the basic compensation coefficient includes the voltage feedforward basic coefficient, the load fluctuation basic coefficient, the line impedance basic coefficient, and the harmonic temperature rise basic coefficient.

[0128] Furthermore, the embedded terminal has a pre-set independent compensation coefficient storage table. The storage table is divided into four levels of storage units according to the interval level code. Each level of unit stores four sets of fixed basic compensation coefficient initial values ​​adapted to the power load interval. The four sets of coefficients correspond to the reference correction base of four types of compensation items: the voltage feedforward basic coefficient is used to offset the voltage regulation deviation caused by the overall deviation of the grid input voltage; the load fluctuation basic coefficient is used to suppress the output voltage oscillation caused by the rapid change of load power; the line impedance basic coefficient is used to compensate for the voltage drop loss generated by the main circuit current on the line impedance; and the harmonic temperature rise basic coefficient is used to offset the voltage regulation accuracy attenuation caused by winding heating and harmonic loss. The initial values ​​of the four types of basic coefficients are all calibrated based on a large number of on-site operating condition tests. The coefficient values ​​of different gradient intervals increase step by step, and the initial value of the basic coefficient in the full load interval is the maximum value in all intervals.

[0129] Furthermore, after reading the current period interval level code, the corresponding storage unit of the compensation coefficient storage table is directly indexed, and the initial values ​​of the four basic compensation coefficients are read in one go and stored in the dedicated memory cache of the dynamic correction model as the reference initial values ​​for coefficient correction calculation. If the load power fluctuation switches to other gradient intervals, the interval level code is updated synchronously, and the power grid load disturbance intelligent classification and identification model automatically retrieves the new basic coefficient initial values ​​of the corresponding interval and updates the reference values ​​in the cache in real time.

[0130] S2.6: The fuzzy logic control algorithm is adopted, with the load power factor angle and voltage quality degradation index as fuzzy input variables and the correction amount of each basic compensation coefficient as fuzzy output variables. After fuzzification processing, fuzzy inference and defuzzification operation, the dynamic correction amount of each basic compensation coefficient is obtained.

[0131] Furthermore, the execution process of the fuzzy logic control algorithm is as follows:

[0132] (1) The fuzzy input variables are determined as the first-dimensional discriminant factor load power factor angle and the second-dimensional discriminant factor voltage quality degradation index. The two types of variables are respectively built into independent fuzzy domains. The variable value range is defined according to the long-term field operation data, and multiple fuzzy language subsets are divided. For example, the power factor angle is divided into four levels: leading, standard, slight lag, and heavy lag, and the voltage quality degradation index is divided into four levels: excellent, slight degradation, moderate degradation, and severe degradation.

[0133] (2) Map the two sets of input variables in the current precise numerical form to the corresponding fuzzy language subsets according to the preset membership function, calculate the membership value corresponding to each language subset, and complete the conversion of precise numerical values ​​to fuzzy language quantities;

[0134] (3) Built-in preset fuzzy reasoning rule library. The rule library is built based on the experience of distribution network voltage regulation compensation experts. It covers all fuzzy subset combination working conditions of two sets of input variables. Each rule corresponds to the correction trend and correction magnitude of four types of basic compensation coefficients. For example, when the voltage is severely degraded and the load is heavily lagging, the correction amount of the two types of coefficients, voltage feedforward and line impedance, increases significantly in a positive direction.

[0135] (4) The fuzzy inference module matches all effective inference rules corresponding to the current input fuzzy subset and integrates the fuzzy correction set output by multiple rules;

[0136] (5) Perform defuzzification operation to restore the integrated set of fuzzy corrections to precise numerical form and output four independent dynamic corrections: voltage feedforward correction, load fluctuation correction, line impedance correction, and harmonic temperature rise correction. The corrections can be positively superimposed to amplify the base coefficient or negatively reduced to slightly reduce the base coefficient, adapting to various disturbance superposition conditions.

[0137] S2.7: Superimpose the initial values ​​of each basic compensation coefficient with the corresponding dynamic correction amount to generate a dynamic correction model for the linkage compensation coefficient.

[0138] S3: The total target compensation voltage is obtained by iteratively solving the four-element compensation components of power grid feedforward deviation, load dynamic fluctuation, line impedance loss, and harmonic temperature rise interference through the linkage compensation coefficient correction model.

[0139] The process of generating the total target compensation voltage includes:

[0140] S3.1: Input the current cycle's grid input voltage waveform, voltage regulator output voltage waveform, and circuit instantaneous current waveform into the linkage compensation coefficient dynamic correction model. After calculation by the linkage compensation coefficient dynamic correction model, the feedforward gain correction coefficient, fluctuation suppression correction coefficient, impedance compensation correction coefficient, and temperature rise attenuation correction coefficient are obtained respectively.

[0141] Furthermore, after each round of synchronous multi-parameter sampling is completed, the grid input voltage waveform, the regulator output voltage waveform, and the circuit instantaneous current waveform are synchronously transmitted to the input port of the linkage compensation coefficient dynamic correction model. The linkage compensation coefficient dynamic correction model first completes the three-dimensional discrimination factor update, load range determination, and fuzzy logic correction calculation based on the waveform data, and then performs the superposition operation of the basic coefficient and the correction amount, synchronously outputting four sets of real-time updated correction coefficients. After the four sets of correction coefficients are output, they are synchronously stored in the output buffer of the linkage compensation coefficient dynamic correction model. The coefficient values ​​in the buffer remain stable until the waveform data input of the next sampling cycle is completed and refreshed, ensuring that the four-element compensation sub-item calculation within a single cycle uses the same set of correction coefficients that match the current operating condition, and that the timing of the compensation sub-item calculation will not be disordered due to mid-term coefficient updates.

[0142] S3.2: The difference between the grid input voltage waveform and the regulator output voltage waveform is taken as the voltage deviation. The feedforward gain correction coefficient is multiplied by the voltage deviation to obtain the grid feedforward deviation compensation component.

[0143] Furthermore, the calculation process for the power grid feedforward deviation compensation component is as follows: at each sampling point, the instantaneous value of the power grid input voltage at the same moment is subtracted from the instantaneous value of the voltage regulator output voltage to obtain a continuous voltage deviation array for the entire cycle. Each deviation value in the array is multiplied by the feedforward gain correction coefficient to obtain the feedforward deviation compensation value at the corresponding moment, which completely offsets the static deviation of the output voltage caused by the overall offset of the power grid input voltage. This is a core component of steady-state voltage compensation.

[0144] S3.3: The difference between the current load active power and the previous load active power is taken as the power change rate. The fluctuation suppression correction coefficient is multiplied by the power change rate to obtain the load dynamic fluctuation compensation component.

[0145] Furthermore, the calculation process for the load dynamic fluctuation compensation component is as follows: retrieve the average active power of the complete load in the current cycle, retrieve the historical average active power stored in the previous synchronization cycle, and calculate the difference between the two to obtain the power change rate. A positive power change rate indicates a sudden increase in load power, while a negative number indicates a sudden decrease in load power. Multiply the power change rate value by the fluctuation suppression correction coefficient to obtain the load dynamic fluctuation compensation component, which can cope with the instantaneous power impact caused by equipment start-up and shutdown and load switching, and suppress short-term oscillations in output voltage.

[0146] S3.4: The instantaneous current waveform of the circuit is squared and then multiplied by the impedance compensation correction factor to obtain the line impedance loss compensation item;

[0147] Furthermore, the calculation process for the line impedance loss compensation sub-item is as follows: the value of each sampling point of the instantaneous current waveform of the circuit is squared separately to obtain the instantaneous current square array. All values ​​in the array are multiplied by the impedance compensation correction coefficient to generate the line impedance loss compensation sub-item. The main circuit current flowing through the conductor and winding impedance will continuously generate voltage drop loss. The larger the current, the higher the loss. This sub-item compensates for the dynamic voltage drop loss caused by the current in real time.

[0148] S3.5: Multiply the deviation between the device winding temperature value and the preset rated temperature value by the temperature rise attenuation correction coefficient to obtain the harmonic temperature rise interference compensation item;

[0149] Furthermore, the calculation process for harmonic temperature rise interference compensation is as follows: the long-term safe rated temperature of the winding is preset at the factory and stored in the program. The rated temperature value is subtracted from the average temperature reference value of the current winding to obtain the winding temperature deviation value. A positive temperature deviation indicates that the winding is overheated. The temperature deviation value is multiplied by the temperature rise attenuation correction coefficient to obtain the harmonic temperature rise interference compensation item, which offsets the loss of compensation accuracy caused by the performance degradation of the voltage regulating device due to winding overheating and harmonic losses.

[0150] S3.6: Read the weight coefficients corresponding to the current gradient load operating range from the linkage compensation coefficient dynamic correction model; the weight coefficients include feedforward weight, fluctuation weight, impedance weight and temperature rise weight;

[0151] Furthermore, the dynamic correction model for the linkage compensation coefficient pre-completes the fixed storage of a four-level gradient load interval-specific weight configuration table. The weight configuration table uses the interval level code as the primary retrieval index. Each interval level code matches an independent and non-interchangeable set of fixed weight coefficients. Each weight combination contains four independent weight parameters, named feedforward weight, fluctuation weight, impedance weight, and temperature rise weight. These four weight parameters correspond to the weighted allocation ratios of the power grid feedforward deviation compensation item, load dynamic fluctuation compensation item, line impedance loss compensation item, and harmonic temperature rise interference compensation item, respectively. The sum of all parameters within a single set of weight parameters is uniformly 1, achieving normalized configuration. The interval-specific weight parameters are calibrated through a full-condition comparative test in a residential distribution network. The specific parameter setting standards are as follows: Level 1 Zone The first level grade code corresponds to the light load operating range, with a feedforward weight set to 0.6, a fluctuation weight set to 0.1, an impedance weight set to 0.15, and a temperature rise weight set to 0.15. The second level grade code corresponds to the normal load operating range, with a feedforward weight set to 0.45, a fluctuation weight set to 0.2, an impedance weight set to 0.2, and a temperature rise weight set to 0.15. The third level grade code corresponds to the heavy load operating range, with a feedforward weight set to 0.3, a fluctuation weight set to 0.2, an impedance weight set to 0.3, and a temperature rise weight set to 0.2. The fourth level grade code corresponds to the full load operating range, with a feedforward weight set to 0.15, a fluctuation weight set to 0.15, an impedance weight set to 0.35, and a temperature rise weight set to 0.35.

[0152] Furthermore, the parameter calibration logic follows the actual disturbance distribution law of the distribution network. In the light load operation range, the power fluctuation of the grid load is small and the winding heat loss is weak. The overall voltage deviation of the grid is the main source of disturbance. Therefore, the feedforward weight setting value of the matching in the light load range is at the highest level among the four sets of parameters. In the full load operation range, the instantaneous current value of the circuit is close to the rated upper limit of the equipment. The impact of the two disturbances, line impedance voltage drop loss and winding heat loss caused by harmonic superposition, is significantly increased. Therefore, the impedance weight and temperature rise weight setting values ​​of the matching in the full load range are simultaneously and significantly increased. Each set of parameter combinations matches the dominant grid disturbance type under the corresponding gradient load operation range.

[0153] Furthermore, using the interval level code as the retrieval input, the internal retrieval process of the linkage compensation coefficient dynamic correction model receives the interval level code and matches the corresponding coded entry in the four-level gradient load interval exclusive weight configuration table. It then retrieves all four types of weight coefficients—feedforward weight, fluctuation weight, impedance weight, and temperature rise weight—under that entry in one go. After retrieval, a one-to-one binding relationship is established: the feedforward weight is bound to the power grid feedforward deviation compensation item, the fluctuation weight is bound to the load dynamic fluctuation compensation item, the impedance weight is bound to the line impedance loss compensation item, and the temperature rise weight is bound to the harmonic temperature rise interference compensation item. The bound pairing weight coefficients are used as standardized output data.

[0154] Furthermore, when the active power of the grid load changes, the operating range of the gradient load to which the load belongs is switched synchronously, the generated range level code is updated synchronously, and after receiving the updated range level code again, the weight configuration table retrieval operation is re-executed, the matching weight coefficients adapted to the new gradient load operating range are automatically retrieved, the values ​​of the four types of weight parameters are updated in real time, and the contribution distribution ratio of the four types of compensation items in the calculation of the total target compensation voltage is dynamically adjusted.

[0155] S3.7: Multiply the power grid feedforward deviation compensation item, load dynamic fluctuation compensation item, line impedance loss compensation item, and harmonic temperature rise interference compensation item by their respective weighting coefficients and add them together to obtain a weighted compensation sum. Then add the weighted compensation sum to the instantaneous sampled value of the current voltage regulator output voltage to obtain the total target compensation voltage and store it in the cache register.

[0156] Furthermore, the weighted fusion process is as follows: the four types of compensation items are multiplied by their respective matching weight coefficients to complete the weighted scaling of the items; all four sets of weighted compensation values ​​are added together to obtain the weighted compensation sum, which represents the overall voltage compensation amount that needs to be superimposed on the output terminal under the current operating condition; the instantaneous sample value of the output voltage of the regulator in the current synchronization cycle is retrieved, and the weighted compensation sum is added to the instantaneous value of the output voltage to solve for the voltage value that the regulator should output under ideal conditions, i.e., the total target compensation voltage; the total target compensation voltage is calculated synchronously point by point, and the complete array is written to the hardware cache register for locking and storage at once. The cache register has high-speed read and write performance and can quickly transmit the total target compensation voltage data to the subsequent tap voltage regulation control module. The data in the register remains unchanged until the next synchronization cycle generates a completely new total target compensation voltage and then overwrites and updates it.

[0157] S4: Divide the three-level voltage regulation deviation range according to the total target compensation voltage and match the corresponding tap voltage regulation step size. When the voltage regulation operation is performed and there is a need for cross-level tap switching, based on the real-time collected grid input voltage, analyze the voltage zero-crossing timing characteristics, use the voltage zero-crossing timing characteristics as the synchronous control reference, synchronously drive the passive compensation branch to output micro-buffer voltage, and control the conduction and cut-off of bidirectional thyristors.

[0158] The process of dividing the voltage regulation deviation range into three levels based on the total target compensation voltage and matching the corresponding tap voltage regulation step size includes:

[0159] S4.1: Read the total target compensation voltage from the cache register, and calculate the difference between the total target compensation voltage and the current regulator output voltage as the voltage regulation deviation value;

[0160] Furthermore, after the tap voltage regulation is initiated, a data reading channel is first established with the cache register to fully read the instantaneous array of the total target compensation voltage for the entire cycle stored in this round; simultaneously, the instantaneous array of the current actual output voltage of the regulator, which is collected in real time by the hardware, is retrieved, and the two arrays correspond one-to-one based on the same timestamp; at each moment, the instantaneous value of the total target compensation voltage is subtracted from the instantaneous value of the current actual output voltage to obtain the voltage regulation deviation value corresponding to each sampling point. A positive voltage regulation deviation value indicates that the current output voltage is lower than the ideal compensation voltage, and the tap level needs to be increased to raise the output voltage; a negative voltage regulation deviation value indicates that the current output voltage is too high, and the tap level needs to be decreased to lower the output voltage; the module automatically calculates the average value of the voltage regulation deviation for the entire cycle as the benchmark deviation value for determining the level switching, avoiding incorrect voltage regulation operations caused by a single instantaneous peak deviation.

[0161] S4.2: When the absolute value of the voltage regulation deviation is less than or equal to the preset first deviation threshold, it is determined to be a first-level voltage regulation deviation range and the first tap voltage regulation step size is matched.

[0162] Furthermore, the first deviation threshold is a small voltage deviation critical parameter that is uniformly calibrated by long-term operation test of residential distribution network before the equipment leaves the factory. This parameter is fixed at 2V after repeated verification under multiple stable operating conditions. The setting is based on the range of small voltage fluctuation amplitude of the power grid under daily no-load and light-load operation of the distribution network, and is specifically adapted to the normal stable operation scenario where the power grid only has small voltage deviation.

[0163] Furthermore, the average voltage regulation deviation is read, the absolute value of the average voltage regulation deviation is calculated, and the absolute value is compared with the first deviation threshold of 2V. If the absolute value of the average voltage regulation deviation is less than or equal to 2V, the system completes the interval determination operation and outputs the first-level voltage regulation deviation interval identifier.

[0164] Furthermore, the system internally stores a configuration table corresponding to the tap voltage regulation step size. The configuration table uses the voltage regulation deviation range identifier as the search index. Each type of voltage regulation deviation range identifier is bound to a unique corresponding tap voltage regulation step size parameter. The first-level voltage regulation deviation range identifier is bound to the first tap voltage regulation step size. The first tap voltage regulation step size is fixed at 1V after the whole machine voltage regulation performance test calibration. This step size is the parameter with the smallest voltage change amplitude corresponding to the adjustment of the range among all tap voltage regulation step sizes.

[0165] Furthermore, after outputting the first-level voltage regulation deviation range identifier in this step, the first tap voltage regulation step size with an output value of 1V is simultaneously retrieved from the configuration table corresponding to the tap voltage regulation step size. The first-level voltage regulation deviation range identifier and the first tap voltage regulation step size with a value of 1V are used together as paired output data.

[0166] Furthermore, the fact that the current operating condition falls within the first-level voltage regulation deviation range means that the difference between the actual output voltage of the voltage regulator and the total target compensation voltage is within a very small range. The small voltage deviation caused by the power grid can be offset by a single tap adjustment with a voltage regulation step size of 1V. A single small-amplitude adjustment will not cause a large fluctuation in the output voltage of the voltage regulator. The regulation logic corresponding to this range is suitable for light-load operation range and excellent and stable voltage quality conditions where the voltage quality degradation index is close to zero.

[0167] S4.3: When the absolute value of the voltage regulation deviation is greater than the first deviation threshold and less than or equal to the preset second deviation threshold, it is determined to be a secondary voltage regulation deviation range and the second tap voltage regulation step size is matched; the first deviation threshold is less than the second deviation threshold;

[0168] Furthermore, the second deviation threshold is a fixed critical parameter calibrated during the equipment commissioning phase in conjunction with the moderate voltage deviation conditions of the residential distribution network. The second deviation threshold is set to 5V. This parameter setting standard meets the differentiation requirements of moderate voltage deviation scenarios. The parameter value of 5V is greater than the first deviation threshold value of 2V, which satisfies the basic constraint that the first deviation threshold is less than the second deviation threshold.

[0169] Furthermore, the average voltage regulation deviation is read, and the absolute value of the average voltage regulation deviation is calculated. The calculated absolute value is compared with the first deviation threshold of 2V and the second deviation threshold of 5V in turn. If the absolute value of the average voltage regulation deviation is greater than the first deviation threshold of 2V, and the value is less than or equal to the second deviation threshold of 5V, the system completes the interval determination operation and outputs the secondary voltage regulation deviation interval identifier.

[0170] Furthermore, in the pre-stored tap voltage adjustment step size configuration table within the system, the secondary voltage adjustment deviation range identifier is bound to the second tap voltage adjustment step size. After the overall voltage adjustment performance is uniformly calibrated, the second tap voltage adjustment step size is set to 3V. The single-step voltage adjustment range of this step size, 3V, is greater than the first tap voltage adjustment step size setting value of 1V.

[0171] Furthermore, after outputting the secondary voltage regulation deviation range identifier, the corresponding configuration table of tap voltage regulation step size is retrieved simultaneously, and the second tap voltage regulation step size with a value of 3V is retrieved. The secondary voltage regulation deviation range identifier and the second tap voltage regulation step size with a value of 3V together constitute the paired output data.

[0172] Furthermore, when the absolute value of the current voltage regulation deviation falls within the middle range of the two sets of thresholds, it corresponds to an operating scenario where the power grid experiences a moderate voltage drop and the load experiences moderate power fluctuations. The corresponding operating conditions are suitable for both normal and heavy load operating ranges. The second tap voltage regulation step size of 3V is used to perform the gear adjustment, which can simultaneously take into account the voltage regulation response speed and the stability of the voltage regulator output voltage operation, and is suitable for the conventional equipment operating conditions corresponding to the normal and heavy load operating ranges.

[0173] S4.4: When the absolute value of the voltage regulation deviation is greater than the second deviation threshold, it is determined to be a third-level voltage regulation deviation range and the third tap voltage regulation step size is matched; the voltage regulation deviation range level and the corresponding tap voltage regulation step size are output to the tap switching actuator.

[0174] It is important to emphasize that the tap voltage regulation step size configuration table pre-stored within the system uses the voltage regulation deviation range identifier as the retrieval index. The first-level voltage regulation deviation range identifier is bound to the first tap voltage regulation step size with a value of 1V, the second-level voltage regulation deviation range identifier is bound to the second tap voltage regulation step size with a value of 3V, and the third-level voltage regulation deviation range identifier is bound to the third tap voltage regulation step size. The third tap voltage regulation step size is set to 5V after the overall voltage regulation performance is uniformly calibrated. The single-step voltage adjustment range corresponding to this step size is 5V, which is the parameter with the largest adjustment range among the three sets of tap voltage regulation step sizes.

[0175] Furthermore, after outputting the three-level voltage regulation deviation range identifier, the corresponding configuration table of tap voltage regulation step size is retrieved simultaneously, and the third tap voltage regulation step size with a value of 5V is retrieved. The three-level voltage regulation deviation range identifier and the third tap voltage regulation step size with a value of 5V together constitute the paired output data.

[0176] Furthermore, when the absolute value of the average voltage regulation deviation exceeds the second deviation threshold of 5V, the corresponding power grid experiences a significant voltage drop or surge, or the load experiences a full-load impact and severe disturbance. The overall voltage deviation is at a high level, and it covers extreme disturbance operation scenarios such as instantaneous switching of high-power equipment and large-scale voltage distortion of the power grid. By using the third tap voltage regulation step size of 5V to perform the gear adjustment, the difference between the current actual output voltage of the voltage regulator and the total target compensation voltage can be quickly reduced.

[0177] When performing voltage regulation operations and a tap position switching requirement occurs, the voltage zero-crossing timing characteristics are analyzed based on the real-time collected grid input voltage, including:

[0178] S4.5: After receiving the voltage regulation deviation range level and tap voltage regulation step size, the tap switching actuator determines whether the difference between the current tap position and the target tap position is greater than 1. If it is greater than 1, it is determined that there is a tap position cross-level switching requirement.

[0179] Furthermore, the tap switching actuator internally stores the actual tap position number of the current voltage regulator in real time, arranged in ascending order according to the voltage adjustment and boosting direction. After receiving the voltage adjustment step size, the actuator calculates the target tap position number to be switched to based on the current position number. Then, it calculates the numerical difference between the current position number and the target position number, and uses the absolute value of the difference to perform a comparison and judgment: if the absolute value of the difference is equal to 1, it means that only an adjacent single-stage tap switching is required, the voltage impact during the switching process is small, there is no need to start the passive buffer branch, and the conventional tap switching operation is directly performed; if the absolute value of the difference is greater than 1, it means that two or more tap positions need to be switched at once, the voltage and current change amplitude of the circuit is large at the moment of cross-stage switching, which is very easy to generate instantaneous voltage spikes and arc interference. The system determines that there is a tap position cross-stage switching requirement and starts zero-crossing synchronous buffer voltage regulation control.

[0180] S4.6: When a cross-level switching requirement is determined, the grid input voltage waveform is collected in real time. The moment when the grid input voltage waveform crosses from the negative half-cycle to the positive half-cycle is recorded as the positive zero-crossing moment, and the moment when it crosses from the positive half-cycle to the negative half-cycle is recorded as the negative zero-crossing moment. The periodic stability and frequency offset of the grid voltage are calculated based on the positive and negative zero-crossing moments of multiple consecutive power frequency cycles.

[0181] Furthermore, after the cross-level switching determination is triggered, the hardware acquisition channel immediately and continuously acquires the complete waveform of the grid input voltage. The waveform signal is synchronously sent to the hardware zero-crossing comparator. The zero-crossing comparator has a built-in voltage zero-point reference circuit, which compares the instantaneous value of the input voltage with the zero-point reference potential in real time: when the voltage value slowly rises from negative and crosses the zero-point reference potential, the comparator immediately outputs a positive zero-crossing trigger pulse and latches the current hardware clock time as the positive zero-crossing time; when the voltage value falls from positive and crosses the zero-point reference potential, the comparator outputs a negative zero-crossing trigger pulse and latches the corresponding hardware clock time as the negative zero-crossing time.

[0182] Furthermore, the program continuously records all positive and negative zero-crossing moments within the last eight complete power frequency cycles. It calculates the difference between two adjacent zero-crossing moments in the same direction to obtain the actual duration of a single cycle. The program then compares the total cycle duration with the standard rated power frequency cycle duration, statistically analyzes the distribution of deviations between each cycle duration and the standard duration, and calculates the cycle stability. A higher stability value indicates smaller power frequency cycle fluctuations and more regular voltage timing. Simultaneously, based on the actual cycle duration, the program converts the current real-time power grid frequency. The difference between the real-time frequency and the standard rated power frequency is then calculated to obtain the frequency offset. A positive or negative offset indicates a higher or lower frequency, and a larger absolute value of the offset indicates more severe power grid frequency disturbances.

[0183] S4.7: Record the nearest positive or negative zero-crossing moment after the current moment as the synchronous zero-crossing moment;

[0184] Furthermore, the current real-time clock value of the hardware is retrieved and compared with the multiple zero-crossing moments stored in the memory. The zero-crossing moments with the smallest positive difference are selected and named synchronous zero-crossing moments. The synchronous zero-crossing moment has the shortest interval between the current control command and the time of issuance, which can start the synchronous control of the buffer branch the fastest, shorten the waiting time of cross-level switching, and balance the voltage regulation response speed and the zero-crossing synchronous control accuracy.

[0185] S4.8: The timing of the synchronous zero-crossing, the periodic stability, and the frequency offset are used as the timing characteristics of the voltage zero-crossing.

[0186] Furthermore, the method of using the voltage zero-crossing timing characteristics as a synchronous control reference to synchronously drive the passive compensation branch to output a micro-buffer voltage and control the on / off state of the bidirectional thyristor includes:

[0187] (1) Read the synchronous zero-crossing time in the voltage zero-crossing timing characteristics, take the synchronous zero-crossing time as the time reference zero point, and take half a power grid frequency cycle as the driving window duration;

[0188] Furthermore, the synchronous zero-crossing point within the timing features is extracted as the reference zero point for the entire buffer drive process, and a fixed duration of half a cycle of standard power frequency is used as the basic drive window duration. At the same time, the drive window duration is slightly modified in combination with the cycle stability and frequency offset: if the cycle stability is low and the frequency offset is large, it indicates that there are fluctuations in the power grid cycle. The program fine-tunes the window duration according to the offset amplitude to ensure that the drive window fully covers the voltage zero-crossing switching interval and avoids timing misalignment of buffer branch access and disconnection due to power grid frequency fluctuations.

[0189] (2) At the start of the driving window, a turn-on driving pulse is output to the gate of the bidirectional thyristor so that the bidirectional thyristor is turned on at the zero-crossing point of the voltage, and the passive compensation branch is connected to the main circuit. The passive compensation branch outputs a micro buffer voltage to smooth out the voltage change during tap switching. The duration of the turn-on driving pulse is equal to half a power grid frequency cycle.

[0190] Furthermore, the start time of the drive window is set to be offset forward by a fixed microseconds from the synchronous zero-crossing point, thus issuing the turn-on drive pulse in advance. The bidirectional thyristor gate receives a stable level pulse lasting for half a power frequency cycle, and the device accurately completes the conduction action at the voltage synchronous zero-crossing point. The passive compensation branch includes a passive buffer circuit composed of an energy storage capacitor and a current-limiting resistor. When the circuit is connected to the main circuit, it outputs a smooth micro-buffered voltage to fill the voltage gap generated during the tap-level switching, suppress the voltage spikes and drops generated during the switching, eliminate arc and instantaneous harmonic interference, and ensure that the output voltage remains stable and continuous during the tap-level switching process, without significant jumps that would affect the normal operation of downstream electrical equipment. The duration of the turn-on pulse is strictly matched to half a power frequency cycle to ensure that the buffer branch fully covers the entire tap-level switching process.

[0191] (3) Remove the turn-on drive pulse at the end of the drive window so that the bidirectional thyristor turns off naturally at the current zero crossing point and the passive compensation branch is cut off from the main circuit.

[0192] Furthermore, when the drive window reaches the preset end time, it immediately stops outputting the turn-on drive pulse to the gate of the bidirectional thyristor, and the gate drive level returns to zero. After the bidirectional thyristor loses the gate turn-on signal, it will not immediately turn off directly, but will continue to maintain the conduction state until the main circuit alternating current naturally crosses the current zero point. The turn-off action is completed without impact at the current zero point, and the passive compensation buffer branch is completely disconnected from the main power circuit of the voltage regulator at the same time. The buffer process ends, and the tap cross-stage switch is completed synchronously.

[0193] S5: After completing this round of voltage synchronization regulation, the actual output voltage of the voltage regulator is re-acquired at an interval of half a power grid frequency cycle. The correction coefficients corresponding to the four-element compensation sub-items are iteratively corrected. Through the voltage dual closed-loop correction mechanism, the output voltage of the voltage regulator is converged and corrected to the rated operating range.

[0194] Furthermore, after completing this round of voltage synchronization regulation, the actual output voltage of the voltage regulator is re-acquired at an iteration interval of half a power grid frequency cycle. This includes: after the tap switching actuator completes the gear switching and outputs a switching completion signal, a timer is started to trigger a sampling interrupt with a period of half a power grid frequency cycle; in each sampling interrupt, the instantaneous value of the actual output voltage at the output terminal of the voltage regulator is acquired through an analog-to-digital converter; after continuously acquiring multiple sampling cycles, the multiple instantaneous values ​​of the acquired actual output voltage are filtered using a moving average filtering algorithm, and the filtering result is used as the effective value of the actual output voltage of the voltage regulator after this round of voltage regulation; the effective value of the actual output voltage of the voltage regulator is stored in a feedback register and transmitted to the iterative correction module. The moving average filtering algorithm is prior art in this field and is not an inventive solution of this application, so it will not be described in detail here.

[0195] Further, the correction coefficients corresponding to the iterative correction of the quaternary compensation sub-items include: the iterative correction module reads the effective value of the actual output voltage of the regulator from the feedback register, calculates the difference between the effective value of the actual output voltage of the regulator and the rated output voltage as the voltage tracking error; inputs the voltage tracking error to the proportional-integral-derivative (PID) controller, and outputs the feedforward gain correction step size, fluctuation suppression correction step size, impedance compensation correction step size, and temperature rise attenuation correction step size respectively after calculation by the PID controller; and superimposes the feedforward gain correction step size with the current feedforward gain correction coefficient in the dynamic correction model of the linkage compensation coefficient to obtain the updated... The feedforward gain correction coefficient is calculated as follows: the fluctuation suppression correction step size is superimposed with the current fluctuation suppression correction coefficient to obtain an updated fluctuation suppression correction coefficient; the impedance compensation correction step size is superimposed with the current impedance compensation correction coefficient to obtain an updated impedance compensation correction coefficient; the temperature rise attenuation correction step size is superimposed with the current temperature rise attenuation correction coefficient to obtain an updated temperature rise attenuation correction coefficient; the four updated correction coefficients are written back to the linkage compensation coefficient dynamic correction model for the next round of compensation sub-item calculation. Among them, the proportional-integral-derivative controller is the prior art in this field and is not an inventive solution of this application, so it will not be described in detail here.

[0196] Furthermore, the voltage dual-loop correction mechanism for converging and correcting the regulator output voltage to the rated operating range includes: using the effective value of the regulator's actual output voltage as the outer loop feedback quantity and the total target compensation voltage as the outer loop setpoint; inputting the outer loop feedback quantity and the outer loop setpoint to the voltage outer loop proportional-integral controller; the voltage outer loop proportional-integral controller outputs the setpoint reference current for the current inner loop after calculation; using the instantaneous current sampling value of the loop as the inner loop feedback quantity; inputting the inner loop feedback quantity and the setpoint reference current to the current inner loop proportional-integral controller; the current inner loop proportional-integral controller outputs a modulation signal after calculation; inputting the modulation signal to a pulse width modulation generator; the pulse width modulation generator generates a drive waveform based on the modulation signal; the drive waveform controls the power switching devices in the regulator to perform switching actions; the outer loop proportional-integral controller and the current inner loop proportional-integral controller form a cascaded structure, and the regulator output voltage is converged and corrected to the rated operating range through outer loop voltage regulation and inner loop current regulation.

[0197] Furthermore, the voltage dual-loop correction mechanism further includes: introducing a feedforward compensation branch before the given reference current of the output current inner loop of the voltage outer loop proportional-integral controller; the feedforward compensation branch processes the instantaneous sampled value of the grid input voltage through a feedforward transfer function to generate a feedforward compensation amount, and superimposes the feedforward compensation amount with the output of the voltage outer loop proportional-integral controller as the given reference current of the current inner loop; the parameters of the feedforward transfer function are dynamically adjusted by the feedforward gain correction coefficient output by the linkage compensation coefficient dynamic correction model.

[0198] Furthermore, it also includes: setting a limiting protection unit at the output of the current inner loop proportional-integral controller, the limiting protection unit limiting the amplitude of the modulation signal to a preset maximum modulation amplitude range; when the amplitude of the modulation signal exceeds the maximum modulation amplitude, the limiting protection unit clamps the amplitude of the modulation signal to the maximum modulation amplitude and generates an over-modulation alarm flag; the over-modulation alarm flag is transmitted to the linkage compensation coefficient dynamic correction model, the linkage compensation coefficient dynamic correction model decreases the impedance compensation correction coefficient by a preset step size according to the over-modulation alarm flag until the over-modulation alarm flag is eliminated.

[0199] Example 2

[0200] Please see Figure 3 Another embodiment of the present invention provides: an electronic voltage regulator voltage compensation system, comprising:

[0201] The multi-channel synchronous acquisition module 10 includes a voltage transformer, a current transformer, a distributed fiber optic temperature measurement device, a harmonic analyzer, and an embedded data acquisition terminal. Its function is to synchronously acquire the grid input voltage, the voltage regulator output voltage, and the instantaneous current waveform data of the circuit according to the preset sampling frequency, synchronously acquire the device winding temperature and the set of harmonic amplitudes, and align and package all parameters with the same timestamp to generate a synchronous multi-parameter sampling sequence.

[0202] The load intelligent identification module 20 reads the synchronous multi-parameter sampling sequence and calculates the load power factor angle, voltage quality degradation index, and harmonic thermal stress factor based on instantaneous power theory, voltage amplitude comparison method, and thermal accumulation effect model to form a three-dimensional discrimination factor. The SVM load disturbance intelligent classification and identification model, trained by the three-dimensional discrimination factor, is run and trained, outputs resistive / inductive / capacitive / nonlinear load types and generates identification codes. Then, combined with historical power data, it divides the load operation range into four levels: light load, constant load, heavy load, and full load and outputs the range level code.

[0203] The compensation voltage module 30 retrieves the initial value of the basic compensation coefficient based on the interval level code, uses a fuzzy logic control algorithm to solve the dynamic correction amount of each coefficient, and builds a dynamic correction model for the linkage compensation coefficient. Based on the model, it solves the four-element compensation items of power grid feedforward deviation, load dynamic fluctuation, line impedance loss, and harmonic temperature rise interference respectively, retrieves the corresponding weights of each item, sums them up to obtain the weighted compensation sum, superimposes the instantaneous sampled value of the output voltage to generate the total target compensation voltage and caches it, thus completing the accurate calculation of the voltage compensation amount.

[0204] The voltage regulation deviation range determination module 40 reads the total target compensation voltage in the cache register, calculates the voltage regulation deviation value and compares it with the preset high and low thresholds, divides the first, second and third level voltage regulation deviation ranges and matches the corresponding tap voltage regulation step size; determines whether there is a tap cross-level switching requirement, and directly outputs the gear adjustment command when there is no need for cross-level switching, and triggers zero-crossing synchronization control when there is cross-level switching.

[0205] The buffer voltage regulation control module 50 collects the grid input voltage in real time, analyzes the timing characteristics of the positive and negative zero-crossing points through a zero-crossing comparator, and selects the synchronous zero-crossing point as the control reference. With half a power frequency cycle as the driving window, it synchronously drives the bidirectional thyristor to conduct at the zero-crossing point and connects to the passive compensation branch to output a micro-buffered voltage. After the window ends, the pulse is removed so that the thyristor current naturally turns off at zero and cuts off the compensation branch, eliminating the voltage surge impact of cross-stage switching.

[0206] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments under the guidance of the present invention without departing from the spirit and scope of the present invention. All of these variations are within the protection scope of the present invention.

Claims

1. A voltage compensation method for an electronic voltage regulator, characterized in that, include: Acquire the synchronous multi-parameter sampling sequence of the target power grid, extract three-dimensional discriminant factors based on the synchronous multi-parameter sampling sequence, and build a smart classification and identification model of power grid load disturbance based on the three-dimensional discriminant factors; Based on the intelligent classification and identification model of power grid load disturbance, the power grid load type is identified, a four-level gradient load operation range is defined, and a dynamic correction model of linkage compensation coefficient is constructed to adapt to different load conditions. The total target compensation voltage is obtained by iteratively solving the four-element compensation components of power grid feedforward deviation, load dynamic fluctuation, line impedance loss, and harmonic temperature rise interference through the linkage compensation coefficient correction model. Based on the total target compensation voltage, the voltage regulation deviation range is divided into three levels and the corresponding tap voltage regulation step size is matched. When the voltage regulation operation is performed and there is a need for cross-level switching of tap position, the voltage zero-crossing time sequence characteristics are analyzed based on the real-time collected grid input voltage. The voltage zero-crossing time sequence characteristics are used as the synchronous control reference to synchronously drive the passive compensation branch to output micro buffer voltage and control the conduction and cutoff of bidirectional thyristors. After completing this round of voltage synchronization regulation, the actual output voltage of the voltage regulator is re-acquired at an interval of half a power grid frequency cycle. The correction coefficients corresponding to the four-element compensation sub-items are iteratively corrected. Through the voltage dual closed-loop correction mechanism, the output voltage of the voltage regulator is converged and corrected to the rated operating range.

2. The voltage compensation method for an electronic voltage regulator as described in claim 1, characterized in that, The acquisition of the synchronous multi-parameter sampling sequence of the target power grid includes: Based on the embedded data acquisition terminal, the grid input voltage waveform data and the voltage regulator output voltage waveform data output from the secondary side of the voltage transformer and the instantaneous circuit current waveform data output from the secondary side of the current transformer are synchronously acquired at a preset sampling frequency. The device winding temperature value output by the distributed optical fiber temperature measurement device is received simultaneously, as well as the set of power grid subharmonic amplitude values ​​generated by the harmonic analyzer after analyzing the voltage and current waveforms of each phase based on the fast Fourier transform algorithm. The collected power grid input voltage waveform data, voltage regulator output voltage waveform data, and circuit instantaneous current waveform data are aligned and packaged with the received device winding temperature value and power grid subharmonic amplitude set according to a unified timestamp to generate a synchronous multi-parameter sampling sequence.

3. The voltage compensation method for an electronic voltage regulator as described in claim 2, characterized in that, The process of extracting the three-dimensional discriminant factors includes: Read the grid input voltage waveform data, regulator output voltage waveform data, circuit instantaneous current waveform data, device winding temperature value, and grid subharmonic amplitude set from the synchronous multi-parameter sampling sequence; The instantaneous power theory algorithm is used to calculate the active and reactive power of the load based on the grid input voltage waveform and the instantaneous current waveform of the circuit. The first discriminant factor, namely the load power factor angle, is defined based on the ratio of active power to reactive power. The voltage amplitude comparison method is used to calculate the voltage drop depth and voltage distortion rate based on the grid input voltage waveform and the voltage regulator output voltage waveform. The second discriminant factor, namely the voltage quality degradation index, is defined based on the weighted sum of the voltage drop depth and voltage distortion rate. The thermal accumulation effect model is used to calculate the winding temperature rise rate based on the device winding temperature value. The third-dimensional discriminant factor, namely the harmonic thermal stress factor, is defined based on the product of the winding temperature rise rate and the sum of the squares of the amplitudes of each harmonic in the set of subharmonic amplitudes of the power grid. The load power factor angle, voltage quality degradation index, and harmonic thermal stress factor are combined into a three-dimensional discriminant factor.

4. The voltage compensation method for an electronic voltage regulator as described in claim 3, characterized in that, The process of building the intelligent classification and identification model for power grid load disturbances is as follows: Using the load power factor angle, voltage quality degradation index and harmonic thermal stress factor in the three-dimensional discriminant factors as input feature vectors, an initial classifier based on the support vector machine algorithm is constructed. A sample dataset labeled with load types is retrieved from the historical power grid database. The initial classifier is trained using the sample dataset. During training, a grid search algorithm is used to optimize the kernel function parameters and penalty factor of the support vector machine. The trained classifier is then denoted as the intelligent classification and identification model for power grid load disturbances.

5. The voltage compensation method for an electronic voltage regulator as described in claim 4, characterized in that, The intelligent classification and identification model based on power grid load disturbance identifies power grid load types and delineates four-level gradient load operating ranges, including: The three-dimensional discrimination factor is input into the trained intelligent classification and identification model of power grid load disturbance. After forward calculation by the intelligent classification and identification model of power grid load disturbance, the load type discrimination result is output. Based on the discrimination result, the load type of the current power grid is determined, and a load type identifier code uniquely corresponding to the load type is generated. The load types include resistive load, inductive load, capacitive load and nonlinear load. Retrieve the corresponding historical operating power dataset based on the load type identifier code, and calculate the median power and standard deviation of the historical operating power dataset. Based on the median power value, four gradient intervals were defined: light-load operation interval, normal-load operation interval, heavy-load operation interval, and full-load operation interval, respectively, using 0.5 times, 1 times, and 2 times the standard deviation of power as interval boundary thresholds. The calculated active power of the load is compared with the four gradient intervals one by one to determine the gradient load operating interval to which the current active power belongs, and an interval level code is generated.

6. The voltage compensation method for an electronic voltage regulator as described in claim 5, characterized in that, The construction of a dynamic correction model for the linkage compensation coefficient adapted to different load conditions includes: The current gradient load operating range is determined based on the range level code, and the initial value of the basic compensation coefficient matching the gradient load operating range is retrieved; the initial value of the basic compensation coefficient includes the voltage feedforward basic coefficient, the load fluctuation basic coefficient, the line impedance basic coefficient, and the harmonic temperature rise basic coefficient. A fuzzy logic control algorithm is adopted, with the load power factor angle and voltage quality degradation index as fuzzy input variables and the correction amount of each basic compensation coefficient as fuzzy output variables. After fuzzification processing, fuzzy inference and defuzzification operation, the dynamic correction amount of each basic compensation coefficient is obtained. The initial values ​​of each basic compensation coefficient are superimposed with the corresponding dynamic correction values ​​to generate a dynamic correction model for the linkage compensation coefficient.

7. The voltage compensation method for an electronic voltage regulator as described in claim 6, characterized in that, The process of generating the total target compensation voltage includes: The current cycle's grid input voltage waveform, regulator output voltage waveform, and circuit instantaneous current waveform are input into the linkage compensation coefficient dynamic correction model. After calculation by the linkage compensation coefficient dynamic correction model, the feedforward gain correction coefficient, fluctuation suppression correction coefficient, impedance compensation correction coefficient, and temperature rise attenuation correction coefficient are obtained respectively. The difference between the grid input voltage waveform and the regulator output voltage waveform is taken as the voltage deviation. The feedforward gain correction coefficient is multiplied by the voltage deviation to obtain the grid feedforward deviation compensation item. The difference between the current load active power and the previous load active power is taken as the power change rate. The fluctuation suppression correction coefficient is multiplied by the power change rate to obtain the load dynamic fluctuation compensation item. The instantaneous current waveform of the circuit is squared and multiplied by the impedance compensation correction coefficient to obtain the line impedance loss compensation item. The deviation between the device winding temperature value and the preset rated temperature value is multiplied by the temperature rise attenuation correction coefficient to obtain the harmonic temperature rise interference compensation item. The weight coefficients corresponding to the current gradient load operating range are read from the linkage compensation coefficient dynamic correction model; the weight coefficients include feedforward weight, fluctuation weight, impedance weight and temperature rise weight; The power grid feedforward deviation compensation item, load dynamic fluctuation compensation item, line impedance loss compensation item, and harmonic temperature rise interference compensation item are multiplied by their respective weighting coefficients and then added together to obtain a weighted compensation sum. The weighted compensation sum is then added to the instantaneous sampled value of the current voltage regulator output voltage to obtain the total target compensation voltage, which is then stored in the cache register.

8. The voltage compensation method for an electronic voltage regulator as described in claim 7, characterized in that, The process of dividing the voltage regulation deviation range into three levels based on the total target compensation voltage and matching the corresponding tap voltage regulation step size includes: Read the total target compensation voltage from the cache register, and calculate the difference between the total target compensation voltage and the current regulator output voltage as the voltage regulation deviation value; The absolute value of the voltage regulation deviation is compared with a preset first deviation threshold and a second deviation threshold. When the absolute value of the voltage regulation deviation is less than or equal to the first deviation threshold, it is determined to be a first-level voltage regulation deviation range and matched with a first tap voltage regulation step size. When the absolute value of the voltage regulation deviation is greater than the first deviation threshold and less than or equal to the second deviation threshold, it is determined to be a second-level voltage regulation deviation range and matched with a second tap voltage regulation step size. When the absolute value of the voltage regulation deviation is greater than the second deviation threshold, it is determined to be a third-level voltage regulation deviation range and matched with a third tap voltage regulation step size. The voltage regulation deviation range level and the corresponding tap voltage regulation step size are output to the tap switching actuator. The first deviation threshold is less than the second deviation threshold.

9. The voltage compensation method for an electronic voltage regulator as described in claim 8, characterized in that, When performing voltage regulation operations and a tap position switching requirement occurs, the voltage zero-crossing timing characteristics are analyzed based on the real-time collected grid input voltage, including: After receiving the voltage regulation deviation range level and the tap voltage regulation step size, the tap switching actuator determines whether the difference between the current tap position and the target tap position is greater than 1. If it is greater than 1, it is determined that there is a tap position cross-level switching requirement. When a cross-level switching requirement is determined, the grid input voltage waveform is collected in real time. The moment when the grid input voltage waveform crosses from the negative half cycle to the positive half cycle is recorded as the positive zero-crossing moment, and the moment when it crosses from the positive half cycle to the negative half cycle is recorded as the negative zero-crossing moment. The periodic stability and frequency offset of the grid voltage are calculated based on the positive and negative zero-crossing moments of multiple consecutive power frequency cycles. The nearest positive or negative zero-crossing moment after the current moment is recorded as the synchronous zero-crossing moment; The timing of the synchronous zero-crossing point, periodic stability, and frequency offset are used as the timing characteristics of the voltage zero-crossing point.

10. A voltage compensation system for an electronic voltage regulator, used to implement the voltage compensation method for an electronic voltage regulator according to any one of claims 1-9, characterized in that, include: A multi-channel synchronous acquisition module is used to generate synchronous multi-parameter sampling sequences; The load intelligent identification module reads the synchronous multi-parameter sampling sequence, calculates the three-dimensional discrimination factor, runs the trained intelligent classification and identification model of power grid load disturbance with the three-dimensional discrimination factor as input, outputs the load type and generates an identification code, and then combines historical power data to divide the four-level gradient load operation range and outputs the range level code. The compensation voltage module retrieves the initial value of the basic compensation coefficient based on the interval level code, uses a fuzzy logic control algorithm to solve the dynamic correction amount of each coefficient, builds a dynamic correction model of the linkage compensation coefficient, solves the four-element compensation sub-items based on the dynamic correction model of the linkage compensation coefficient, and superimposes them to generate the total target compensation voltage. The voltage regulation deviation range determination module reads the total target compensation voltage in the cache register, divides the voltage regulation deviation range and matches the corresponding tap voltage regulation step size, and determines whether there is a tap cross-stage switching requirement. The buffer voltage regulation control module collects the grid input voltage in real time, analyzes the zero-crossing timing characteristics through a zero-crossing comparator, and synchronously drives the bidirectional thyristor to conduct at the zero-crossing point to connect to the passive compensation branch and output micro-buffered voltage with half a power frequency cycle as the driving window. After the window ends, the pulse is removed to allow the thyristor current to cross zero and naturally turn off to disconnect the compensation branch.

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