A multi-point signal interlocking control method and device based on a state model
Patent Information
- Application Number
- CN202610839407.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-11
- Publication Date
- 2026-10-30
AI Technical Summary
[0003]然而,现有的闭锁控制方法中,直接采用固定阈值与“运行/非运行”两态逻辑,并没有建立多源信号加权融合的状态模型及动态迟滞比较机制
[0008]本发明的第四个目的在于提出一种非临时性计算机可读存储介质。
Smart Images

Figure CN123010626A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the automation control technology of hydropower units, and in particular to a multi-point signal interlocking control method and device based on a state model. Background Technology
[0002] Automation control of hydropower units is a core component of safe operation in the power industry and is widely used in the start-up, shutdown, and operational mode transition processes of large hydropower stations. Related technologies utilize the collaborative operation of PLC logic operations, SCADA monitoring, and relay protection devices to construct a comprehensive control system covering signal acquisition, threshold judgment, and interlocking execution. Specifically, this system includes key components such as analog signal filtering, fixed threshold alarm determination, and status identification based on a single operating indicator, aiming to ensure stable operation of the unit under complex conditions.
[0003] However, existing interlocking control methods directly employ fixed thresholds and a two-state logic of "operating / non-operating," without establishing a state model based on weighted fusion of multi-source signals or a dynamic hysteresis comparison mechanism. Due to the lack of refined identification capabilities for transitional states such as start-up and no-load conditions, the system cannot intelligently match differentiated interlocking strategies when speed fluctuates or parameters exceed limits for short periods, leading to frequent false alarms and false interlocks. This fragmented and rigid logic not only increases the difficulty of configuration and maintenance but also severely weakens the unit's response safety and operational reliability during dynamic processes. Summary of the Invention
[0004] The present invention aims to at least partially solve one of the technical problems in the related art.
[0005] Therefore, the first objective of this invention is to propose a multi-point signal interlocking control method based on a state model.
[0006] Another objective of this invention is to propose a multi-point signal interlocking control device based on a state model.
[0007] The third objective of this invention is to provide a computer device.
[0008] A fourth objective of this invention is to provide a non-transitory computer-readable storage medium.
[0009] To achieve the above objectives, a first aspect of the present invention proposes a multi-point signal interlocking control method based on a state model, comprising:
[0010] S10: Collect multiple monitoring signals during unit operation, and perform filtering, noise reduction, and normalization processing on the multiple monitoring signals to obtain standardized signal data; S20: Assign dynamic weights to the standardized signal data according to the current unit operating conditions, obtain a comprehensive state judgment value through weighted fusion calculation, and perform anti-jitter processing on the comprehensive state judgment value using hysteresis comparison logic to generate a valid state bit. S30, based on the state valid bit and the preset state transition conditions, the target operating state is determined through a priority arbitration mechanism, and the state switch is completed after the minimum dwell time constraint is met, so as to obtain the current unit operating state; S40: Query the interlocking control matrix according to the current unit operating status, obtain the interlocking enable bit corresponding to each monitoring point, and trigger an alarm or interlocking action only when the interlocking enable bit indicates that an alarm is allowed and the monitoring data exceeds the limit.
[0011] In one embodiment of the present invention, S10 includes: For each analog signal, a mean filtering operation is performed using a sliding window of length N. The original sampled values at the current time and the previous N-1 time are summed and then divided by N to obtain the filtered signal after suppressing random noise interference. Obtain the lower limit and upper limit of the engineering quantity corresponding to the filtered signal, subtract the lower limit of the engineering quantity from the filtered signal and divide it by the difference between the upper limit and the lower limit of the engineering quantity, map the calculation result to the normalized interval of 0 to 1, and obtain standardized signal data that eliminates the difference in dimensions.
[0012] In one embodiment of the present invention, the step of performing mean filtering operation on each analog signal using a sliding window of length N, and summing the original sampled values at the current time and the previous N-1 time steps and dividing by N to obtain the filtered signal after suppressing random noise interference, includes: Set the sliding window length N to 8 sampling points. Within the preset real-time scanning period of the system, read the original sampled value at time k and the historical sampled values from time k-1 to time k-N+1, using the formula:
[0013] Calculate the filtered signal value at time k, where This represents the original sampled value at time ki. This represents the filtered signal value at time k.
[0014] In one embodiment of the present invention, S20 includes: Based on the signal type and the current unit status, the dynamic weight values of the M signals participating in the status judgment are determined. The normalized standardized signal data of each signal are multiplied by the corresponding dynamic weight value and then summed to obtain the comprehensive status judgment value reflecting the joint status of multiple signals. A hysteresis comparator is constructed by setting an upper threshold for entry and a lower threshold for exit. The comprehensive state judgment value is compared with the upper threshold for entry and the lower threshold for exit. When the signal jitters, the output value of the previous moment remains unchanged, and the state valid bit of the current moment is generated.
[0015] In one embodiment of the present invention, the step of determining the dynamic weight values of the M signals participating in the state judgment based on the signal type and the current unit state, and then multiplying the normalized standardized signal data of each signal by the corresponding dynamic weight value and summing them to obtain a comprehensive state judgment value reflecting the joint state of the multiple signals includes: Based on the current operating conditions of the unit—start-up, shutdown, or fault protection—the weight values corresponding to the speed signal, excitation voltage, guide vane opening, and oil pressure signal are obtained by referring to a table. To ensure the sum of all weight values equals 1, use the formula:
[0016] Calculate the overall state judgment value S, where S is the normalized value of the i-th signal, and the value of S ranges from 0 to 1.
[0017] In one embodiment of the present invention, S30 includes: Construct a state transition matrix that includes all states and transition conditions of the unit, and determine whether all sub-conditions for transitioning from the current state to each candidate target state are simultaneously met in order to generate an enable signal; When multiple candidate target states simultaneously meet the transition conditions, the target state with the highest priority is selected as the next state according to the preset priority vector. After the state transition is completed, the minimum dwell time constraint is enforced to prevent the state from rapidly going back and forth due to brief signal jitter, and finally the current unit operating state is determined.
[0018] In one embodiment of the present invention, S40 includes: A pre-constructed offline interlocking control matrix L is constructed, where the matrix rows correspond to the steady-state, transient state, and fault protection state of the unit, and the matrix columns correspond to each signal monitoring point. When a matrix element has a value of 1, it indicates that the current state allows the alarm of that signal, and when it has a value of 0, it indicates that the current state blocks the alarm of that signal. During online operation, the system queries the data in the corresponding row of the interlocking control matrix L based on the current unit operating status to obtain the interlocking enable bit for each monitoring point.
[0019] To achieve the above objectives, a second aspect of the present invention provides a multi-point signal interlocking control device based on a state model, comprising: The signal acquisition and preprocessing module is used to acquire multiple monitoring signals during the operation of the unit, and to perform filtering, noise reduction and normalization processing on the multiple monitoring signals to obtain standardized signal data. The weighted fusion anti-jitter processing module is used to assign dynamic weights to the standardized signal data according to the current unit operating conditions, obtain a comprehensive state judgment value through weighted fusion calculation, and perform anti-jitter processing on the comprehensive state judgment value using hysteresis comparison logic to generate a valid state bit. The state priority arbitration switching module is used to determine the target operating state based on the state valid bit and the preset state transition conditions through a priority arbitration mechanism, and to complete the state switching after meeting the minimum dwell time constraint to obtain the current unit operating state. The interlocking matrix alarm interlocking module is used to query the interlocking control matrix according to the current unit operating status, obtain the interlocking enable bit corresponding to each monitoring point, and trigger an alarm or interlocking action only when the interlocking enable bit indicates that an alarm is allowed and the monitoring data exceeds the limit.
[0020] This invention discloses a multi-point signal interlocking control method and apparatus based on a state model. By constructing an improved weighted state judgment network and a finite state machine with priority arbitration, it achieves accurate identification of complex transient states of the generating unit and dynamic differentiated interlocking of alarm signals. This method effectively solves the problems of false alarms and false interlocking caused by traditional single threshold judgment, and significantly improves the safety and stability of the automatic control of hydropower units.
[0021] To achieve the above objectives, a third aspect of this application provides a computer device, including a processor and a memory; wherein the processor runs a program corresponding to the executable program code by reading executable program code stored in the memory, for implementing the method described in the first aspect embodiment.
[0022] To achieve the above objectives, a fourth aspect of this application provides a non-transitory computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the method described in the first aspect.
[0023] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0024] Figure 1 This is a flowchart of a multi-point signal interlocking control method based on a state model according to an embodiment of the present invention; Figure 2 This is a general structure diagram of a multi-point signal interlocking control network according to an embodiment of the present invention; Figure 3This is a logic diagram for determining the dual threshold value according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the improved hysteresis comparator network structure and timing according to an embodiment of the present invention; Figure 5 This is a general state model diagram of the multi-point signal interlocking control method based on a state model according to an embodiment of the present invention; Figure 6 This is a flowchart of the power-on process according to an embodiment of the present invention; Figure 7 This is a flowchart of the shutdown and fault protection process according to an embodiment of the present invention; Figure 8 This is a structural diagram of a multi-point signal interlocking control device based on a state model according to an embodiment of the present invention; Figure 9 It is a computer device according to an embodiment of the present invention. Detailed Implementation
[0025] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0027] The following description, with reference to the accompanying drawings, describes a multi-point signal interlocking control method and apparatus based on a state model according to an embodiment of the present invention.
[0028] Figure 1 This is a flowchart of a multi-point signal interlocking control method based on a state model according to an embodiment of the present invention, such as... Figure 1 As shown, it includes: S10: Collect multiple monitoring signals during unit operation, and perform filtering, noise reduction, and normalization processing on the multiple monitoring signals to obtain standardized signal data; S20: Assign dynamic weights to the standardized signal data according to the current unit operating conditions, obtain a comprehensive state judgment value through weighted fusion calculation, and perform anti-jitter processing on the comprehensive state judgment value using hysteresis comparison logic to generate a valid state bit. S30, based on the state valid bit and the preset state transition conditions, the target operating state is determined through a priority arbitration mechanism, and the state switch is completed after the minimum dwell time constraint is met, so as to obtain the current unit operating state; S40: Query the interlocking control matrix according to the current unit operating status, obtain the interlocking enable bit corresponding to each monitoring point, and trigger an alarm or interlocking action only when the interlocking enable bit indicates that an alarm is allowed and the monitoring data exceeds the limit.
[0029] This invention constructs a four-layer control network structure, with clearly defined functions for each layer and unidirectional data flow, forming a complete closed-loop processing link of "acquisition → judgment → decision → output". The overall network structure is as follows: Figure 2 As shown.
[0030] Specifically, the first layer is the signal acquisition and preprocessing layer. This layer completes the standardized acquisition and noise suppression processing of field signals, and includes the following two sub-modules: The moving average filtering module applies a moving average filter of length N to each analog signal to suppress random noise interference. The calculation formula is as follows:
[0031] in The original sampled value at time k is N, which represents 8 sampling points (configurable online). This filtering method has low computational complexity and is suitable for execution within the real-time scanning cycle of PLC / DCS.
[0032] The threshold adaptive normalization module normalizes the filtered signal to the [0,1] interval to eliminate differences in the dimensions of different engineering quantities, facilitating subsequent unified weighting processing.
[0033] Where x_min and x_max are the lower and upper limits of the engineering quantity for this signal point, respectively, and can be configured in groups according to signal type, supporting online adjustment. After normalization, all signals are in the same dimension space, laying the foundation for the second-layer weighted fusion.
[0034] Furthermore, in the second layer: the state judgment network layer, an improved weighted decision network is proposed, which has the following three improvements compared with the traditional single threshold judgment method: The signal importance weighting mechanism assigns weights to the M signals involved in the state determination. The weight values are dynamically adjusted based on the signal type and the current unit status. The weighting function is as follows:
[0035] Specifically, the weights of various signals under different states are shown in Table 1 (taking startup state Z3 as an example): Table 1
[0036] Furthermore, the multi-signal weighted fusion criterion weights and aggregates the normalized signals to obtain the state comprehensive judgment value S, calculated as follows:
[0037] The aggregated value S∈[0,1] comprehensively reflects the joint state of multiple signals, avoiding misjudgment of the state caused by a single signal triggering falsely.
[0038] Furthermore, traditional single-threshold judgments using hysteresis comparators often exhibit frequent switching (i.e., "jitter") when the signal fluctuates around the threshold. This invention introduces a hysteresis comparator, setting an upper threshold. and exit threshold ( < The dual threshold judgment logic is as follows: Figure 3 Place:
[0039] in This represents the valid state bit at the current moment. This is the output value from the previous moment. Dead zone width Δθ = A normalized value of 0.08–0.15 is recommended, and it can be configured according to signal stability groups. This mechanism maintains the state unchanged when the signal jitters near the threshold, significantly reducing the state flip frequency. Simulation verification shows that when the signal jitter amplitude is less than Δθ / 2, the number of false state flips is reduced to zero. The hysteresis comparator network structure is as follows: Figure 4 As shown.
[0040] Furthermore, the third layer: Finite State Machine Execution Layer (Improved FSM). This layer adopts an improved finite state machine, adding a priority arbitration mechanism and a state latching mechanism on the basis of the traditional FSM, which solves the conflict problem when multiple states simultaneously meet the transition conditions.
[0041] Furthermore, the state transition matrix representation organizes all states and transition conditions of the unit into a state transition matrix T, where the element T[i][j] represents the set of conditions for transitioning from state i to state j:
[0042] The transition condition is satisfied if and only if all subconditions are true simultaneously (logical AND relation):
[0043] The system achieves automatic state transitions based on the above enabling conditions. The multi-point interlocking conditions for each major state transition are shown in Table 2. Table 2
[0044] Furthermore, the priority arbitration mechanism, when multiple target states simultaneously meet the transition conditions, determines the priority based on a preset priority vector P=[ , , …, The highest priority objective is selected, and the arbitration formula is as follows:
[0045] Among them, the fault protection state G1 has the highest priority (p_G1=11), followed by the shutdown state S4, and the others decrease in priority in descending order. This mechanism ensures that when a fault signal is detected in any state, the system immediately and unconditionally jumps to the G1 state to protect the equipment.
[0046] Furthermore, the state latching mechanism introduces a minimum dwell time after the state transition is completed. Constraints are implemented to prevent rapid state recursion (glitch phenomenon) caused by brief signal jitter:
[0047] The default value is 200ms, which can be configured according to the physical characteristics of each state, effectively eliminating glitches and jitters in the control output.
[0048] Furthermore, the fourth layer: the interlocking control output layer. This layer dynamically generates the interlocking enable control word for each alarm / interlocking signal point based on the current state output from the third layer through a lookup table (LUT) mechanism. The interlocking condition lookup table is pre-built offline using an interlocking control matrix L, where rows correspond to the unit status and columns correspond to each signal monitoring point. The meanings of the matrix element values are shown in Table 3. Table 3
[0049] When running online, the locking strategy of all signal points in the current state can be obtained with only one matrix query, and the computation is O(1), which meets the requirements of real-time control.
[0050] Furthermore, dynamic enable / mask calculations are performed, ultimately outputting a valid alarm bit for the signal. From signal measurement values With threshold Limit check and latch enable bit Joint decision:
[0051] Only if the current state allows ( =1) and when the measured value exceeds the limit =1 is required to trigger an alarm or interlock action, thus fundamentally eliminating false alarms under non-operational conditions.
[0052] This invention can be integrated into PLCs, DCSs, or dedicated protection and control devices, and is implemented in the following ways: Figure 5 , Figure 6 and Figure 7 As shown: The state model includes four steady states, six transition states, and one fault protection state: steady state S1 is the generating state, S2 is the no-load state, S3 is the idling state, and S4 is the shutdown state; transition states Z1 is the start-up protection state, Z2 is the shutdown protection state, Z3 is the excitation state, Z4 is the demagnetization state, Z5 is the synchronization state, and Z6 is the disconnection state; G1 is the fault protection state. During the start-up process, the control system sequentially collects the start-up command signal, speed feedback signal, excitation command signal, excitation voltage feedback signal, synchronization closing command signal, and output circuit breaker position feedback signal (i.e., steps S101-S106). Only when the previous signal is confirmed and no blocking signal is issued by any protection group is the switch from the current state to the next state allowed; otherwise, the current state is maintained or the system switches to fault protection state G1. During shutdown, the control system sequentially collects shutdown commands, circuit breaker position feedback, demagnetization commands, excitation voltage reset feedback, guide vane closing commands, and speed reset feedback signals (i.e., steps S201-S206), and switches states according to the same multi-point signal interlocking rules. In any steady-state or transient state, if the protection output signal activates, the system directly switches from the current state to fault protection state G1, and via the emergency shutdown output signal (S207), the unit sequentially enters shutdown protection state Z2 and shutdown state S4, achieving safe interlocking shutdown of the unit. Thus, through the joint determination of three types of multi-point signals—command signals, feedback signals, and protection signals—multi-point signal interlocking control of the entire unit start-up and shutdown process is achieved.
[0053] The embodiments of this invention also have the following technical effects: Improved operational safety: By modeling key operational states as a finite set of states and implementing multi-point signal interlocking for state transition processes, this invention can effectively prevent illegal, out-of-level, or erroneous control operations, avoiding risk scenarios such as mis-excitation, mis-grid connection, and shutdown under load, significantly reducing the possibility of equipment damage or personnel injury. Enhanced automated control capabilities: This invention clarifies the state boundaries and transition paths of each operating stage of the hydropower unit. The control system can autonomously complete state judgment and transition operations based on real-time signals without manual intervention, achieving fully automated start-stop control, especially effective in unattended, small hydropower stations, or remote centralized control scenarios. Improved fault response speed: The system embeds a unified fault protection state (such as G1 fault protection state). When a key fault signal is detected, it can quickly trigger corresponding protection linkage actions (such as disconnecting the circuit breaker, shutting down, and starting the emergency oil pump), which is more coordinated and consistent in response than traditional independent protection relay systems, greatly improving the unit's emergency response capabilities. Enhanced visualization and traceability of control logic: Leveraging the clear structure of the state model, the operating status can be graphically presented in the Human-Machine Interface (HMI), allowing operators to intuitively grasp the equipment's current stage and control process. Simultaneously, state transitions and interlocking judgments have data recording capabilities, facilitating subsequent event tracking, accident analysis, and operational optimization. Improved scalability and maintainability of control strategies: The state model possesses a naturally modular structure, allowing for easy addition of new states or modification of transition paths based on system expansion or equipment upgrades, maintaining the continuous adaptability of the control strategy. Compared to hard-wired logic or flowchart programs, it offers better maintainability and engineering efficiency. Compatible with existing control platforms, low implementation cost: The state model and interlocking mechanism of this invention can be deployed in software within existing PLCs, DCSs, or embedded controllers, without requiring numerous new hardware interfaces. The control logic is clear, highly portable, and has low implementation and modification costs, making it suitable for intelligent upgrades of old power plants or standardized applications in new projects. This invention facilitates the digital transformation of hydropower stations by providing a high-quality data foundation and state semantic system for building digital twin systems and intelligent operation and maintenance platforms for hydropower stations through standardized modeling and unified control of unit operating status. It has significant strategic importance and promotional value.
[0054] To achieve the above embodiments, such as Figure 8 As shown, this embodiment also provides a multi-point signal interlocking control device 10 based on a state model, including: The signal acquisition and preprocessing module 100 is used to acquire multiple monitoring signals during the operation of the unit, and to perform filtering, noise reduction and normalization processing on the multiple monitoring signals to obtain standardized signal data. The weighted fusion anti-jitter processing module 200 is used to assign dynamic weights to the standardized signal data according to the current unit operating conditions, obtain a comprehensive state judgment value through weighted fusion calculation, and perform anti-jitter processing on the comprehensive state judgment value using hysteresis comparison logic to generate a valid state bit. The state priority arbitration switching module 300 is used to determine the target operating state based on the state valid bit and the preset state transition conditions through a priority arbitration mechanism, and to complete the state switching after meeting the minimum dwell time constraint to obtain the current unit operating state. The interlocking matrix alarm interlocking module 400 is used to query the interlocking control matrix according to the current unit operating status, obtain the interlocking enable bit corresponding to each monitoring point, and trigger an alarm or interlocking action only when the interlocking enable bit indicates that an alarm is allowed and the monitoring data exceeds the limit.
[0055] This invention discloses a multi-point signal interlocking control device based on a state model. By constructing an improved weighted state judgment network and a finite state machine with priority arbitration, it achieves accurate identification of complex transient states of the generating unit and dynamic differentiated interlocking of alarm signals. This method effectively solves the problems of false alarms and false interlocking caused by traditional single threshold judgment, and significantly improves the safety and stability of the automatic control of hydropower units.
[0056] To implement the methods of the above embodiments, the present invention also provides a computer device, such as... Figure 9 As shown, the computer device 600 includes a memory 601 and a processor 602; wherein, the processor 602 reads executable program code stored in the memory 601 to run a program corresponding to the executable program code, so as to implement the various steps of the method described above.
[0057] To implement the above embodiments, this application also proposes a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the method described in the foregoing embodiments.
[0058] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0059] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
Claims
1. A multi-point signal interlocking control method based on a state model, characterized in that, include: S10: Collect multiple monitoring signals during unit operation, and perform filtering, noise reduction, and normalization processing on the multiple monitoring signals to obtain standardized signal data; S20: Assign dynamic weights to the standardized signal data according to the current unit operating conditions, obtain a comprehensive state judgment value through weighted fusion calculation, and perform anti-jitter processing on the comprehensive state judgment value using hysteresis comparison logic to generate a valid state bit. S30, based on the state valid bit and the preset state transition conditions, the target operating state is determined through a priority arbitration mechanism, and the state switch is completed after the minimum dwell time constraint is met, so as to obtain the current unit operating state; S40: Query the interlocking control matrix according to the current unit operating status, obtain the interlocking enable bit corresponding to each monitoring point, and trigger an alarm or interlocking action only when the interlocking enable bit indicates that an alarm is allowed and the monitoring data exceeds the limit.
2. The method as described in claim 1, characterized in that, S10 includes: For each analog signal, a mean filtering operation is performed using a sliding window of length N. The original sampled values at the current time and the previous N-1 time are summed and then divided by N to obtain the filtered signal after suppressing random noise interference. Obtain the lower limit and upper limit of the engineering quantity corresponding to the filtered signal, subtract the lower limit of the engineering quantity from the filtered signal and divide it by the difference between the upper limit and the lower limit of the engineering quantity, map the calculation result to the normalized interval of 0 to 1, and obtain standardized signal data that eliminates the difference in dimensions.
3. The method as described in claim 2, characterized in that, The step of performing mean filtering on each analog signal using a sliding window of length N involves summing the original sampled values from the current time and the previous N-1 time steps, then dividing by N to obtain the filtered signal after suppressing random noise interference. This includes: Set the sliding window length N to 8 sampling points. Within the preset real-time scanning period of the system, read the original sampled value at time k and the historical sampled values from time k-1 to time k-N+1, using the formula: Calculate the filtered signal value at time k, where This represents the original sampled value at time ki. This represents the filtered signal value at time k.
4. The method as described in claim 1, characterized in that, S20 includes: Based on the signal type and the current unit status, the dynamic weight values of the M signals participating in the status judgment are determined. The normalized standardized signal data of each signal are multiplied by the corresponding dynamic weight value and then summed to obtain the comprehensive status judgment value reflecting the joint status of multiple signals. A hysteresis comparator is constructed by setting an upper threshold for entry and a lower threshold for exit. The comprehensive state judgment value is compared with the upper threshold for entry and the lower threshold for exit. When the signal jitters, the output value of the previous moment remains unchanged, and the state valid bit of the current moment is generated.
5. The method as described in claim 4, characterized in that, The dynamic weight values of the M signals participating in the state judgment are determined based on the signal type and the current unit status. The normalized standardized signal data of each signal are multiplied by their corresponding dynamic weight values and then summed to obtain a comprehensive state judgment value reflecting the joint state of the multiple signals, including: Based on the current operating conditions of the unit—start-up, shutdown, or fault protection—the weight values corresponding to the speed signal, excitation voltage, guide vane opening, and oil pressure signal are obtained by referring to a table. To ensure the sum of all weight values equals 1, use the formula: Calculate the overall state judgment value S, where S is the normalized value of the i-th signal, and the value of S ranges from 0 to 1.
6. The method as described in claim 1, characterized in that, S30 includes: Construct a state transition matrix that includes all states and transition conditions of the unit, and determine whether all sub-conditions for transitioning from the current state to each candidate target state are simultaneously met in order to generate an enable signal. When multiple candidate target states simultaneously meet the transition conditions, the target state with the highest priority is selected as the next state according to the preset priority vector. After the state transition is completed, the minimum dwell time constraint is enforced to prevent the state from rapidly going back and forth due to brief signal jitter, and finally the current unit operating state is determined.
7. The method as described in claim 1, characterized in that, S40 includes: A pre-constructed offline interlocking control matrix L is constructed, where the matrix rows correspond to the steady-state, transient state, and fault protection state of the unit, and the matrix columns correspond to each signal monitoring point. When a matrix element has a value of 1, it indicates that the current state allows the alarm of that signal, and when it has a value of 0, it indicates that the current state blocks the alarm of that signal. During online operation, the system queries the data in the corresponding row of the interlocking control matrix L based on the current unit operating status to obtain the interlocking enable bit for each monitoring point.
8. A multi-point signal interlocking control device based on a state model, characterized in that, include: The signal acquisition and preprocessing module is used to acquire multiple monitoring signals during the operation of the unit, and to perform filtering, noise reduction and normalization processing on the multiple monitoring signals to obtain standardized signal data. The weighted fusion anti-jitter processing module is used to assign dynamic weights to the standardized signal data according to the current unit operating conditions, obtain a comprehensive state judgment value through weighted fusion calculation, and perform anti-jitter processing on the comprehensive state judgment value using hysteresis comparison logic to generate a valid state bit. The state priority arbitration switching module is used to determine the target operating state based on the state valid bit and the preset state transition conditions through a priority arbitration mechanism, and to complete the state switching after meeting the minimum dwell time constraint to obtain the current unit operating state. The interlocking matrix alarm interlocking module is used to query the interlocking control matrix according to the current unit operating status, obtain the interlocking enable bit corresponding to each monitoring point, and trigger an alarm or interlocking action only when the interlocking enable bit indicates that an alarm is allowed and the monitoring data exceeds the limit.
9. A computer device, characterized in that, Including processor and memory; The processor reads executable program code stored in the memory to run a program corresponding to the executable program code, so as to implement a multi-point signal interlocking control method based on a state model as described in any one of claims 1-7.
10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements a multi-point signal interlocking control method based on a state model as described in any one of claims 1-7.
