Fault processing method and device, computer device, readable storage medium and program product

Abstract

The application relates to a fault processing method and device, computer equipment, a computer readable storage medium and a computer program product. The method is applied to a fault processing unit, the fault processing unit is electrically connected with a fault collection unit, the fault collection unit is electrically connected with a plurality of fault sources of a target chip, the fault collection unit is used for collecting fault trigger signals of the plurality of fault sources, the method comprises the following steps: acquiring a fault trigger signal sent by the fault collection unit; wherein the fault trigger signal is used for indicating that a target fault source in the plurality of fault sources has a fault; according to the fault trigger signal and preset response configuration information, a target response mode is determined from at least two fault response modes, and a corresponding fault processing operation is performed. The method can improve the flexibility and scalability of fault processing.

Description

Technical Field

[0001] This application relates to the field of fault handling technology, and in particular to a fault handling method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Technology

[0002] In the field of automotive electronics, the microcontroller (MCU) is a core control component, and its fault handling capability is directly related to driving safety and system reliability. As the functional safety requirements of automobiles continue to increase, MCUs need to detect and respond to various types and levels of fault sources to ensure that the system can enter a safe state in a timely and reliable manner when a fault occurs.

[0003] In traditional technologies, MCU fault handling adopts a hardware direct connection architecture, that is, the correspondence between fault sources and response methods is fixed through hardware connections, resulting in poor flexibility in fault handling. Summary of the Invention

[0004] Therefore, it is necessary to provide a fault handling method, apparatus, computer equipment, computer-readable storage medium, and computer program product that can improve the flexibility and scalability of fault handling in response to the above-mentioned technical problems.

[0005] In a first aspect, this application provides a fault handling method applied to a fault handling unit, wherein the fault handling unit is electrically connected to a fault collection unit, the fault collection unit is electrically connected to multiple fault sources of a target chip, and the fault collection unit is used to collect fault trigger signals of the multiple fault sources. The method includes:

[0006] Acquire the fault trigger signal sent by the fault collection unit; wherein the fault trigger signal is used to indicate that a target fault source among the plurality of fault sources has failed;

[0007] Based on the fault trigger signal and the preset response configuration information, the target response mode is determined from at least two fault response modes, and the corresponding fault handling operation is executed.

[0008] In one embodiment, determining the target response mode from at least two fault response modes based on the fault trigger signal and preset response configuration information, and performing the corresponding fault handling operation includes:

[0009] When the preset response configuration information corresponding to the fault trigger signal indicates that the target fault source is a recoverable fault category, an interrupt output signal is generated, and a hardware counter is triggered to start counting.

[0010] When the count value of the hardware counter reaches a preset time threshold, the fault status information of the target fault source is obtained;

[0011] If the fault status information indicates that the target fault source has not been cleared, a timeout flag is generated, and the target fault source is marked as an unrecoverable fault category;

[0012] Based on the preset response configuration information corresponding to the unrecoverable fault category, perform a reset operation or a fault output signal operation.

[0013] In one embodiment, after acquiring the fault trigger signal sent by the fault collection unit, the process includes:

[0014] When the preset response configuration information corresponding to the fault trigger signal indicates that the target fault source is an unrecoverable fault category or a timeout flag is detected, the fault output generator is driven to generate an output signal with preset signal characteristics; wherein, the output signal is used to allow external monitoring equipment to obtain the internal safety status of the chip.

[0015] In one embodiment, prior to acquiring the fault trigger signal sent by the fault collection unit, the process includes:

[0016] Receive a fault injection instruction, wherein the fault injection instruction is used to specify the target fault source to be simulated;

[0017] By operating the fault injection register corresponding to the target fault source to be simulated via the bus, the fault collection unit is instructed to generate a fault trigger signal according to the configuration of the fault injection register.

[0018] In one embodiment, prior to acquiring the fault trigger signal sent by the fault collection unit, the process includes:

[0019] Based on the risk level of each fault source, the fault enable switch and fault response type corresponding to each fault source are pre-configured through software.

[0020] In one embodiment, the fault handling unit includes a master control state machine and an interrupt counter. The step of determining a target response mode from at least two fault response modes based on the fault trigger signal and preset response configuration information, and executing the corresponding fault handling operation, includes:

[0021] The main control state machine responds to the fault trigger signal and performs fault priority adjustment, controls the generation of interrupt output signals, controls the generation of reset output signals, and / or records status according to the corresponding preset response configuration information.

[0022] The interrupt counter responds to the interrupt trigger to start counting and feeds back the timeout status to the master control state machine, so that the master control state machine can perform the corresponding fault handling operation according to the timeout status.

[0023] Secondly, this application also provides a fault handling device applied to a fault handling unit, wherein the fault handling unit is electrically connected to a fault collection unit, the fault collection unit is electrically connected to multiple fault sources of a target chip, and the fault collection unit is used to collect fault trigger signals of the multiple fault sources. The device includes:

[0024] The acquisition module is used to acquire the fault trigger signal sent by the fault collection unit; wherein the fault trigger signal is used to indicate that a target fault source among the plurality of fault sources has failed;

[0025] The processing module is used to determine the target response mode from at least two fault response modes based on the fault trigger signal and preset response configuration information, and to perform the corresponding fault processing operation.

[0026] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in any of the above-mentioned embodiments.

[0027] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the preceding claims.

[0028] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in any of the above claims.

[0029] The aforementioned fault handling methods, devices, computer equipment, computer-readable storage media, and computer program products, by adding a fault collection unit to uniformly collect fault trigger signals from multiple fault sources of the target chip, replace the dedicated hardware lines between the fault source and the response controller in the traditional hardware direct connection architecture, and realize unified monitoring of multiple fault sources; at the same time, by dynamically matching and executing fault response methods based on preset response configuration information through the fault handling unit, there is no need to rely on hardware connections to fix the correspondence between faults and responses, which solves the problems of fixed fault response methods, poor flexibility, and high difficulty in expanding multiple fault sources in the traditional hardware direct connection architecture, and improves the flexibility and scalability of fault handling. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the hardware architecture for fault handling in related technologies;

[0032] Figure 2 This is an application environment diagram of a fault handling method in one embodiment;

[0033] Figure 3 This is a flowchart illustrating a fault handling method in one embodiment;

[0034] Figure 4 This is a schematic diagram illustrating the connection relationship between the fault collection unit and the fault source in one embodiment.

[0035] Figure 5 This is a flowchart illustrating step S120 in one embodiment;

[0036] Figure 6 This is a flowchart illustrating step S120 in another embodiment;

[0037] Figure 7 This is a schematic diagram of the fault handling unit in one embodiment;

[0038] Figure 8 This is a schematic diagram of the fault handling unit in another embodiment;

[0039] Figure 9 This is a structural block diagram of a fault handling device in one embodiment;

[0040] Figure 10 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0042] It should be noted that the terms "comprising" and "having," and any variations thereof, as used in this application, are intended to cover non-exclusive inclusion. The term "multiple" as used in this application refers to two or more. The term "and / or" as used in this application refers to one of the solutions, or any combination of multiple solutions.

[0043] In related technologies, different fault sources are directly connected to their corresponding response controllers via dedicated hardware lines. For example, for unrecoverable faults that threaten driving safety, such as abnormal temperature or power failure, the fault is directly connected to the reset controller via hardware lines, triggering a full MCU reset when the fault occurs. For recoverable faults, such as single-bit memory errors, the fault is directly connected to the interrupt controller, triggering a CPU interrupt when the fault occurs, with software handling the error query. Please refer to [reference needed]. Figure 1 , Figure 1 This is a schematic diagram of the hardware architecture for fault handling in related technologies. Because the fault types and response methods are fixed through hardware connections, the flexibility is poor. For example, each new fault type requires an additional hardware connection to the corresponding controller, increasing the difficulty of chip design and making it difficult to adapt to the needs of expanding with multiple fault sources.

[0044] This application provides a fault handling method that can be applied to, for example... Figure 2 The fault handling unit 01 shown is electrically connected to the fault collection unit 02. The fault collection unit 02 is connected to multiple fault sources of the target chip ( Figure 2 Electrical connections (not shown) are used to acquire fault trigger signals from multiple fault sources. Here, the target chip can be an automotive-grade MCU. In this embodiment, as... Figure 3 As shown, the method includes the following steps:

[0045] S110, acquire the fault trigger signal sent by the fault collection unit; wherein, the fault trigger signal is used to indicate that the target fault source among multiple fault sources has failed.

[0046] For example, please continue to refer to Figure 2 The fault collection unit 02 can uniformly collect fault trigger signals from multiple fault sources of the target chip. These fault trigger signals can be directly generated by abnormal states of hardware modules such as temperature sensors, voltage monitors, and memory controllers, or they can be actively generated by software injection to support fault simulation verification. Specifically, temperature faults can be triggered by the temperature sensor detecting a temperature exceeding a preset threshold, voltage faults can be triggered by the voltage monitor detecting a voltage exceeding a preset threshold, and memory faults can be triggered by the memory controller detecting multi-bit ECC errors.

[0047] In one possible implementation, please refer to Figure 4The fault collection unit 02 is configured to receive and summarize trigger signals of multiple different fault sources and software-injected faults within the target chip. The fault signal corresponding to each fault source can be selected and controlled by an independent enable switch (such as switch 1 to switch n). Only when the enable switch is turned on will the fault trigger signal of the corresponding fault source be summarized by the fault collection unit and output to the fault processing unit.

[0048] S120: Based on the fault trigger signal and the preset response configuration information, determine the target response mode from at least two fault response modes and execute the corresponding fault handling operation.

[0049] At least two fault response methods are included, but are not limited to, interrupt, reset, and fault pin output. Each fault source has corresponding preset response configuration information. In one possible implementation, a corresponding response strategy can be configured in response to fault enabling to obtain the response configuration information. The response configuration information may include the correspondence between fault level and response method; for example, a high-risk fault corresponds to a reset operation, and a low-risk fault corresponds to an interrupt operation.

[0050] For example, please continue to refer to Figure 2 The fault handling unit 01 is configured to receive the fault trigger signal output by the fault collection unit 02, and based on the pre-configured response configuration information, match the corresponding fault response mode for different fault trigger signals, and drive the generation of the corresponding response signal to complete the fault handling operation.

[0051] Optionally, prior to step S120 above, the software can pre-configure the response configuration information corresponding to each fault source based on the risk level of each fault source, and determine the target response method corresponding to different fault sources. The response configuration information can be dynamically updated according to the system status during chip operation without modifying the hardware connections.

[0052] In the above-mentioned fault handling method, a fault collection unit is added to collect fault trigger signals from multiple fault sources of the target chip in a unified manner, replacing the dedicated hardware lines between the fault source and the response controller in the traditional hardware direct connection architecture, thus realizing unified monitoring of multiple fault sources. At the same time, the fault handling unit dynamically matches and executes the fault response mode based on the preset response configuration information, without relying on hardware connections to fix the correspondence between faults and responses. This solves the problems of fixed fault response modes, poor flexibility, and high difficulty in expanding multiple fault sources in the traditional hardware direct connection architecture, thereby improving the flexibility and scalability of fault handling.

[0053] In one exemplary embodiment, such as Figure 5 As shown, step S120 above may include:

[0054] A1 generates an interrupt output signal and triggers the hardware counter to start counting when the preset response configuration information corresponding to the fault trigger signal indicates that the target fault source is a recoverable fault category.

[0055] The hardware counter can be an interrupt counter inside the fault handling unit.

[0056] For example, after receiving a fault trigger signal corresponding to a recoverable fault category sent by the fault collection unit, the fault handling unit can drive the generation of an interrupt output signal and send it to the CPU of the target chip according to the preset response configuration information, and at the same time send a start command to the internal interrupt counter to trigger the interrupt counter to start counting.

[0057] A2: When the count value of the hardware counter reaches the preset time threshold, obtain the fault status information of the target fault source.

[0058] For example, when the count value of the interrupt counter inside the fault handling unit reaches the preset time threshold pre-configured by the software, the fault handling unit can send a status query instruction to the fault collection unit to obtain the current fault status information of the target fault source.

[0059] A3 generates a timeout flag and marks the target fault source as an unrecoverable fault category if the fault status information indicates that the target fault source has not been cleared.

[0060] For example, if the fault status information obtained by query shows that the fault signal of the target fault source is still in a valid state (i.e. the fault has not been cleared), the fault processing unit can generate a timeout flag signal and update the temporary fault category mark of the target fault source to an unrecoverable fault category. The updated category mark is stored in the status register inside the fault processing unit.

[0061] Optionally, if the fault is cleared during the counting period, the master state machine sends a clear command to the interrupt counter, and the interrupt counter performs the clear operation and stops counting.

[0062] A4, based on the preset response configuration information corresponding to the unrecoverable fault category, execute a reset operation or a fault output signal operation.

[0063] For example, the fault handling unit can match the corresponding preset response configuration information according to the updated unrecoverable fault category. If the configuration is a reset operation, it drives the generation of a reset signal and sends it to the reset controller of the target chip to trigger the overall reset of the MCU. If the configuration is a fault output signal operation, it sends a control command to the fault output generator to drive the generation of the corresponding fault output signal.

[0064] In this embodiment, by using a hardware counter to monitor the timeout of recoverable fault interruptions and automatically escalate the fault level to execute corresponding processing, the processing chaos caused by CPU failures or software processing failures can be reduced, CPU load can be reduced, and the reliability and stability of fault handling can be improved.

[0065] In one exemplary embodiment, the above-described fault handling method may further include:

[0066] S130, when the preset response configuration information corresponding to the fault trigger signal indicates that the target fault source is an unrecoverable fault category or a timeout flag is detected, the fault output generator is driven to generate an output signal with preset signal characteristics; wherein, the output signal is used to allow external monitoring equipment to obtain the internal safety status of the chip.

[0067] The output frequency of the fault output generator can be controlled by software through the configuration of a dedicated register.

[0068] For example, the fault handling unit can send a drive command to the internal fault output generator upon receiving a fault trigger signal corresponding to an unrecoverable fault category, or upon detecting a timeout flag signal. The fault output generator can generate and output a PWM signal with a 50% duty cycle based on pre-configured frequency parameters in the software. This signal is output to an external monitoring device through a dedicated fault pin on the target chip. Furthermore, the external monitoring device can obtain the internal safety status of the chip through the signal output from this fault pin, enabling safe collaborative monitoring between the chip and the external system.

[0069] In this embodiment, a fault output signal with specific characteristics is generated by a fault output generator for external devices to collect, which enables real-time external monitoring of the internal safety status of the chip.

[0070] In one exemplary embodiment, the above-described fault handling method may further include:

[0071] S1401, Receive fault injection command, the fault injection command is used to specify the target fault source to be simulated.

[0072] For example, the software can generate fault injection instructions based on fault testing and verification requirements, which are used to specify the target fault source to be simulated.

[0073] S1402, through bus operation of the fault injection register corresponding to the target fault source to be simulated, instructs the fault collection unit to generate a fault trigger signal according to the configuration of the fault injection register.

[0074] For example, a configuration operation can be performed on the fault injection register corresponding to the target fault source to be simulated through the chip's internal bus. After the fault collection unit detects the configuration status of the fault injection register, it generates a fault trigger signal for the corresponding target fault source according to the configuration and sends the fault trigger signal to the fault processing unit.

[0075] In this embodiment, the software can actively, accurately, and repeatedly inject specified faults by operating the fault injection register via the bus, thereby improving the flexibility and controllability of fault testing.

[0076] In one exemplary embodiment, the above-described fault handling method may further include:

[0077] S150, based on the risk level of each fault source, pre-configures the fault enable switch and fault response type corresponding to each fault source through software.

[0078] The fault enable switch can be used to control whether the fault signal of the corresponding fault source is collected and transmitted by the fault collection unit. The fault response type can be used to define the fault handling method executed by the fault handling unit after the fault source is triggered.

[0079] For example, the software can configure the on / off state of the corresponding fault enable switch and a fault response type for each fault source according to the risk level of the fault source; the fault collection unit filters fault source signals according to the configuration of the fault enable switch, and the fault processing unit performs corresponding fault processing according to the pre-configured fault response type.

[0080] In this embodiment, by pre-configuring fault enable switches and fault response types according to the fault source risk level through software, flexible software configuration of fault acquisition and response can be achieved without modifying hardware wiring, reducing chip design difficulty and adapting to the expansion needs of multiple fault sources.

[0081] In one exemplary embodiment, such as Figure 6 As shown, the fault handling unit includes a master control state machine and an interrupt counter. In this embodiment, step S120 may include:

[0082] B1 responds to the fault trigger signal through the main control state machine, and performs fault priority adjustment, control interrupt output signal generation, control reset output signal generation, and / or status recording according to the corresponding preset response configuration information.

[0083] B2 responds to interrupt triggers to start counting and feeds back the timeout status to the master control state machine, so that the master control state machine can perform the corresponding fault handling operation according to the timeout status.

[0084] For example, please refer to Figure 7The fault trigger signal (i.e., "fault n" in the diagram) output by the fault collection unit is input to the main control state machine of the fault handling unit 01. After receiving the fault trigger signal, the main control state machine reads the preset response configuration information corresponding to the fault source and performs priority adjustment on multiple simultaneously triggered faults according to the configuration information. When configured as an interrupt response mode, the main control state machine controls the generation of an interrupt output signal; when configured as a reset response mode, the main control state machine controls the generation of a reset output signal. At the same time, the main control state machine records information such as the fault source identifier, fault trigger time, and current processing status in its internal status register. The interrupt counter in the fault handling unit 01 is bidirectionally connected to the main control state machine, receives the start command from the main control state machine, and feeds back the counting status.

[0085] Optionally, the fault handling unit further includes a fault output generator, which is used to generate a fault pin output signal according to the instructions of the master control state machine.

[0086] In one possible implementation, please refer to Figure 8 When a fault source triggers a fault trigger signal, this signal is input to the main control state machine. The main control state machine, in conjunction with the preset fault response configuration information, makes a judgment. If the target fault source is configured as a recoverable fault type, it controls the generation of an interrupt output signal and sends it to the interrupt controller. At the same time, it sends a start command to the interrupt counter, triggering the interrupt counter to start counting. During the counting process, if the interrupt counter receives a fault clearing signal from the main control state machine, it performs a counter clearing operation. If the count reaches a preset time threshold and no fault clearing signal is received, it reports a timeout status to the main control state machine. After receiving the timeout status, the main control state machine, based on the fault response configuration information, if configured for a reset operation, controls the generation of a reset output signal and sends it to the reset controller. If configured for a fault pin output operation, it sends a control command to the fault output generator, controlling it to generate a fault pin output signal and send it to the PAD pin. The main control state machine also records and manages information such as the priority, response configuration, and current processing status of each fault source.

[0087] In this embodiment, by using a master control state machine to uniformly schedule and prioritize the fault handling process, orderly responses can be achieved in scenarios with multiple concurrent faults, ensuring the consistency and traceability of fault handling logic. Furthermore, by using an interrupt counter to monitor and feedback the timeout status of fault interrupts in hardware, automatic detection and escalation of fault handling status can be achieved without continuous software polling. Therefore, hardware-based control of the fault handling process can be realized, reducing software load and improving the reliability and efficiency of fault response.

[0088] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0089] Based on the same inventive concept, this application also provides a fault handling apparatus for implementing the fault handling method described above. The solution provided by this apparatus is similar to the solution described in the above method; therefore, the specific limitations in one or more fault handling apparatus embodiments provided below can be found in the limitations of the fault handling method described above, and will not be repeated here.

[0090] In one exemplary embodiment, such as Figure 9 As shown, a fault handling device 600 is provided, including: an acquisition module 601 and a processing module 602, wherein:

[0091] The acquisition module 601 is used to acquire the fault trigger signal sent by the fault collection unit; wherein the fault trigger signal is used to indicate that a target fault source among multiple fault sources has failed.

[0092] The processing module 602 is used to determine the target response mode from at least two fault response modes based on the fault trigger signal and preset response configuration information, and to perform the corresponding fault handling operation.

[0093] In one embodiment, the processing module 602 is further configured to:

[0094] When the preset response configuration information corresponding to the fault trigger signal indicates that the target fault source is a recoverable fault category, an interrupt output signal is generated, and the hardware counter is triggered to start counting.

[0095] When the count value of the hardware counter reaches a preset time threshold, the fault status information of the target fault source is obtained;

[0096] If the fault status information indicates that the target fault source has not been cleared, a timeout flag is generated and the target fault source is marked as an unrecoverable fault category;

[0097] Based on the preset response configuration information corresponding to the unrecoverable fault category, perform a reset operation or a fault output signal operation.

[0098] In one embodiment, the processing module 602 is further configured to:

[0099] When the preset response configuration information corresponding to the fault trigger signal indicates that the target fault source is an unrecoverable fault category or a timeout flag is detected, the fault output generator is driven to generate an output signal with preset signal characteristics; wherein, the output signal is used to allow external monitoring equipment to obtain the internal safety status of the chip.

[0100] In one embodiment, the fault handling device 600 further includes a fault injection module, used for:

[0101] Receive fault injection instructions, which specify the target fault source to be simulated;

[0102] By operating the fault injection register corresponding to the target fault source to be simulated via the bus, the fault collection unit is instructed to generate a fault trigger signal according to the configuration of the fault injection register.

[0103] In one embodiment, the fault handling device 600 further includes a software configuration module, used for:

[0104] Based on the risk level of each fault source, the fault enable switch and fault response type corresponding to each fault source are pre-configured through software.

[0105] In one embodiment, the fault handling unit includes a master control state machine and an interrupt counter, and the processing module 602 is further configured to:

[0106] The main control state machine responds to the fault trigger signal and performs fault priority adjustment, controls the generation of interrupt output signals, controls the generation of reset output signals, and / or records the status according to the corresponding preset response configuration information.

[0107] The interrupt counter is activated in response to an interrupt trigger to start counting and feeds back the timeout status to the master control state machine, so that the master control state machine can perform the corresponding fault handling operation based on the timeout status.

[0108] Each module in the aforementioned fault handling device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0109] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 10 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a fault handling method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0110] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0111] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0112] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.

[0113] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0114] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0115] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0116] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A fault handling method, characterized in that, An application is made in a fault handling unit, which is electrically connected to a fault collection unit. The fault collection unit is electrically connected to multiple fault sources of the target chip. The fault collection unit is used to collect fault trigger signals from the multiple fault sources. The method includes: Acquire the fault trigger signal sent by the fault collection unit; wherein the fault trigger signal is used to indicate that a target fault source among the plurality of fault sources has failed; Based on the fault trigger signal and the preset response configuration information, the target response mode is determined from at least two fault response modes, and the corresponding fault handling operation is executed.

2. The method according to claim 1, characterized in that, The step of determining the target response mode from at least two fault response modes based on the fault trigger signal and preset response configuration information, and performing the corresponding fault handling operation, includes: When the preset response configuration information corresponding to the fault trigger signal indicates that the target fault source is a recoverable fault category, an interrupt output signal is generated, and a hardware counter is triggered to start counting. When the count value of the hardware counter reaches a preset time threshold, the fault status information of the target fault source is obtained; If the fault status information indicates that the target fault source has not been cleared, a timeout flag is generated, and the target fault source is marked as an unrecoverable fault category; Based on the preset response configuration information corresponding to the unrecoverable fault category, perform a reset operation or a fault output signal operation.

3. The method according to claim 2, characterized in that, After acquiring the fault trigger signal sent by the fault collection unit, the process includes: When the preset response configuration information corresponding to the fault trigger signal indicates that the target fault source is an unrecoverable fault category or a timeout flag is detected, the fault output generator is driven to generate an output signal with preset signal characteristics; wherein, the output signal is used to allow external monitoring equipment to obtain the internal safety status of the chip.

4. The method according to claim 1, characterized in that, Before acquiring the fault trigger signal sent by the fault collection unit, the process includes: Receive a fault injection instruction, wherein the fault injection instruction is used to specify the target fault source to be simulated; By operating the fault injection register corresponding to the target fault source to be simulated via the bus, the fault collection unit is instructed to generate a fault trigger signal according to the configuration of the fault injection register.

5. The method according to claim 1, characterized in that, Before acquiring the fault trigger signal sent by the fault collection unit, the following steps are included: Based on the risk level of each fault source, the fault enable switch and fault response type corresponding to each fault source are pre-configured through software.

6. The method according to claim 1, characterized in that, The fault handling unit includes a master control state machine and an interrupt counter. The step of determining the target response mode from at least two fault response modes based on the fault trigger signal and preset response configuration information, and executing the corresponding fault handling operation, includes: The main control state machine responds to the fault trigger signal and performs fault priority adjustment, controls the generation of interrupt output signals, controls the generation of reset output signals, and / or records status according to the corresponding preset response configuration information. The interrupt counter responds to the interrupt trigger to start counting and feeds back the timeout status to the master control state machine, so that the master control state machine can perform the corresponding fault handling operation according to the timeout status.

7. A fault handling device, characterized in that, An apparatus is applied to a fault handling unit, which is electrically connected to a fault collection unit. The fault collection unit is electrically connected to multiple fault sources of the target chip. The fault collection unit is used to collect fault trigger signals from the multiple fault sources. The apparatus includes: The acquisition module is used to acquire the fault trigger signal sent by the fault collection unit; wherein the fault trigger signal is used to indicate that a target fault source among the plurality of fault sources has failed; The processing module is used to determine the target response mode from at least two fault response modes based on the fault trigger signal and preset response configuration information, and to perform the corresponding fault processing operation.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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