A three-redundancy control system for an aircraft landing gear system and an aircraft landing gear system

Abstract

The application discloses a three-redundancy control system for an aircraft take-off and landing system and the aircraft take-off and landing system, wherein a take-off and landing management processor, a brake control processor and a front wheel turning control processor are arranged in each channel, the three processors are connected to the same programmable logic device to interact with main information, meanwhile, the programmable logic devices of the channels are connected with each other through cross transmission link interfaces to realize data interaction among the three channels, shorten the information transmission path among the systems, reduce data interaction delay, improve system response speed, and the take-off and landing management processor, the brake control processor and the front wheel turning control processor are connected with the programmable logic device to interact with the main information, and the brake control processor and the front wheel turning control processor are also directly connected with the take-off and landing management processor, thereby providing two communication paths of main and backup inside the channel for control and management of the three safety critical systems.

Description

Technical Field

[0001] This invention belongs to the field of airborne computers and relates to a triple redundancy control system for aircraft take-off and landing systems and the aircraft take-off and landing system. Background Technology

[0002] The takeoff and landing system comprises the landing gear retraction and extension subsystem, braking subsystem, nose wheel steering subsystem, and takeoff and landing control subsystem, corresponding to the landing gear system in civil aircraft, and is a safety-critical system. In the past, aircraft used separate controllers for landing gear retraction and extension, braking, and nose wheel steering, with each controller performing only a single control function for one system. However, multiple separate controllers increase the number of aircraft components, leading to increased overall weight. Furthermore, the need for external buses or hardwired cables for communication between controllers results in long communication paths, data exchange delays, and limitations on system response speed and control accuracy. Summary of the Invention

[0003] The purpose of this invention is to solve the problem that in the prior art, the three safety-critical systems of aircraft landing gear retraction, braking, and nose wheel steering are implemented by separate controllers, which leads to low system integration, large equipment weight, long interaction paths between systems, communication delays, and reliability bottlenecks. The invention provides a triple-redundant control system for aircraft take-off and landing systems and an aircraft take-off and landing system.

[0004] To achieve the above objectives, the present invention employs the following technical solution: A triple-redundant control system for an aircraft takeoff and landing system includes mutually independent and electrically isolated channels A, B, and C. Each of channels A, B, and C includes a takeoff and landing management processor, a programmable logic device, a brake control processor, a front wheel steering control processor, a cross-transmission link interface, and an input / output interface. The takeoff and landing management processor, brake control processor and front wheel steering control processor are all connected to a programmable logic device and interact with the main information through the programmable logic device. Both the brake control processor and the front wheel steering control processor are connected to the takeoff and landing management processor. The programmable logic devices corresponding to channels A, B, and C are interconnected through a cross-transmission link interface. The programmable logic device is connected to an input / output interface, which is connected to the signal interfaces of the external landing gear retraction mechanism, braking mechanism, and front wheel steering mechanism.

[0005] A further improvement of the present invention is that: The takeoff and landing management processor, brake control processor, and front wheel steering control processor are all connected to non-volatile memory via peripheral interfaces.

[0006] The takeoff and landing management processor communicates with the aircraft's aerospace system via a 1394 bus.

[0007] The takeoff and landing management processor, brake control processor, and front wheel steering control processor are all digital processors.

[0008] The input / output interfaces of channels B and C are connected to the control terminals of the emergency landing gear deployment solenoid valve. Channel B is a backup control channel, and channel C is the main control channel.

[0009] When controlling the retraction and extension of the landing gear, channel A is the main channel, channel B is the backup channel, and channel C is the emergency channel; When braking is controlled, channel A is the main channel, channel B is the backup channel, and channel C is the emergency channel; When controlling the front wheels to turn, channel A is the primary channel and channel C is the backup channel.

[0010] The cross-transmission link interface includes an SPI bus and an RS422 bus. The SPI bus is used for automatic forwarding of acquired data between programmable logic devices in each channel. The RS422 bus is used to forward application layer data between programmable logic devices in each channel.

[0011] The programmable logic device is a field-programmable gate array (FPGA).

[0012] The field-programmable gate array integrates a channel fault logic module, which is used to realize mutual monitoring between the processor and programmable logic device in the channel and the switching control between channels.

[0013] An aircraft takeoff and landing system, comprising any of the triple-redundant control systems described in the preceding claims.

[0014] Compared with the prior art, the present invention has the following beneficial effects: This invention discloses a triple-redundant control system for aircraft takeoff and landing systems. It comprises three independent and electrically isolated channels: A, B, and C. Each channel houses a takeoff and landing management processor, a brake control processor, and a nose wheel steering control processor. These three processors are connected to the same programmable logic device (PLC) for master information exchange. Simultaneously, the PLCs of each channel are interconnected via a cross-link interface, enabling data exchange between the three channels. Compared to traditional discrete controllers communicating via an external bus, this significantly shortens the information transmission path between systems, reduces data exchange latency, and improves system response speed. Furthermore, the takeoff and landing management processor, brake control processor, and nose wheel steering control processor... All processors are connected to programmable logic devices for master information exchange. The brake control processor and the front wheel steering control processor are also directly connected to the takeoff and landing management processor, providing two communication paths within the channel for the control and management of the three safety-critical systems: a primary path and a backup path. The interconnection between the three channels through programmable logic devices and cross-transmission link interfaces enables each processor in any channel to obtain data from its own channel and other channels. Channels A, B, and C are independent and electrically isolated from each other. This achieves integrated control of the three safety-critical systems with a single device while ensuring that each system can operate independently and reliably, thus meeting the dual requirements of high integration and high safety of the aircraft takeoff and landing system. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This invention discloses a triple redundancy control system for an aircraft takeoff and landing system, and a diagram of the aircraft takeoff and landing system. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0018] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0019] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0020] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0022] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0023] The present invention will now be described in further detail with reference to the accompanying drawings: First, the abbreviations used in this embodiment will be explained: DSP: Digital Signal Processor; in this embodiment, the takeoff and landing DSP is the landing management processor, responsible for landing gear retraction and extension control, communication with the flight control computer, command distribution and status summary; the brake DSP is the brake control processor, which performs real-time closed-loop calculation and control of brake pressure; the front wheel steering DSP is the front wheel steering control processor, which performs real-time closed-loop calculation and control of the front wheel steering angle.

[0024] NVM: Non-Volatile Memory. In this embodiment, NVM is used to store fault information and calibration information.

[0025] FPGA: Field-Programmable Gate Array. In this embodiment, the FPGA is mainly used for input / output interface management, for inter-channel cross-transmission, channel synchronization, and channel fault logic.

[0026] CCDL: Cross-Channel Data Link. In redundant avionics systems, it is a general term for communication links used for data exchange, status synchronization, and cross-comparison between multiple redundant channels. In this embodiment, the main functions of CCDL include transmitting sensor data, calculation results, and status information collected by each channel to other channels, and providing a physical communication basis for redundancy management, data voting, and fault isolation between the three channels, so as to avoid the entire system entering an unsafe state due to data abnormality of a single channel or failure of the communication link.

[0027] LGCIU: Landing Gear Control Interface Unit. The triple-redundant integrated architecture disclosed in this embodiment is a specific implementation of LGCIU.

[0028] SPI-CCDL: Cross-channel data link implemented based on SPI bus. SPI bus is a synchronous serial communication bus. In this embodiment, SPI-CCDL is the first link in the dual CCDL. It is mainly used to realize the automatic forwarding of acquired data. Specifically, after the FPGA in the channel acquires all input and output interface data, it automatically sends the data to the FPGA of other channels according to a fixed period without DSP intervention. It is mainly used for low-level real-time data.

[0029] RS422-CCDL: A cross-channel data link implemented based on the RS422 bus. RS422 is a differential signal serial communication standard. RS422-CCDL is the second link in a dual CCDL system, used to implement application layer data forwarding initiated by the DSP. Specifically, it is mainly used to transmit application layer data, such as channel status information, redundancy management instructions, channel switching instructions, and system health monitoring results. RS422-CCDL and SPI-CCDL complement each other: SPI-CCDL is responsible for the automatic distribution of low-level acquired data, while RS422-CCDL is responsible for the on-demand forwarding of high-level application data. The two links are physically independent, and if either one fails, the other can still maintain basic communication between the three channels, avoiding system paralysis due to the failure of a single CCDL link.

[0030] See Figure 1 This invention discloses a triple-redundant control system for aircraft take-off and landing systems, which helps to improve the integration level of airborne computers and enhance system safety. The controller is a homogeneous triple-redundant design with three independent and electrically isolated channels. Each channel includes an independent 1394 bus, DSP processor, power supply, and interface circuit.

[0031] In this system, the landing gear retraction and deployment subsystem, the braking subsystem, and the front wheel steering subsystem are all high-safety-critical systems. Both the braking and front wheel steering subsystems require short-cycle closed-loop control. To ensure maximum decoupling between systems, shorten product startup time, and improve mission reliability, three DSP processors are configured within each channel: a landing DSP, a braking DSP, and a front wheel DSP. These three DSPs share FPGA resources and acquire I / O interface data from their respective systems through the FPGA to complete CCDL and synchronization functions between channels. The landing DSP, acting as a comprehensive management DSP, not only performs control and management functions for the landing gear retraction and deployment subsystem but also communicates with the VMC via a 1394 bus. It distributes bus commands to the braking and front wheel DSPs through the product's internal interface and simultaneously receives system status information from the braking and front wheel DSPs, uploading this status information to the VMC via the 1394 bus. Based on the received bus commands and the acquired system I / O data, the braking and front wheel DSPs perform data processing and real-time closed-loop control locally.

[0032] This embodiment specifically includes: The A, B, and C channels are independent and electrically isolated from each other. Each of the A, B, and C channels includes a power conversion circuit, a take-off and landing DSP, a braking DSP, a front wheel steering DSP, an FPGA, an NVM, and input / output interfaces.

[0033] The takeoff and landing DSP, serving as the integrated management DSP, communicates with the flight control computer via a 1394 bus. It interacts with the braking DSP and the front wheel steering DSP via an FPGA for primary information exchange, and with the braking DSP and the front wheel steering DSP for backup information exchange via its built-in SCI interface. It connects to the NVM via a peripheral interface and obtains landing gear interface information through the FPGA to control the landing gear deployment and recovery subsystem. The relationship between channels A, B, and C in the landing gear deployment and recovery subsystem is as follows: channel A is the primary channel, channel B is the backup channel, and channel C is the emergency channel.

[0034] Furthermore, the braking DSP interacts with the takeoff and landing DSP via the FPGA to exchange primary information, and with the takeoff and landing DSP via the DSP's built-in SCI interface to exchange backup information. It connects to the NVM via a peripheral interface and obtains braking interface information through the FPGA to control the braking subsystem. The relationship between channels A, B, and C in the braking subsystem is as follows: channel A is the primary channel, channel B is the backup channel, and channel C is the emergency channel.

[0035] Furthermore, the front wheel steering DSP interacts with the take-off and landing DSP via the FPGA for primary information exchange, and with the take-off and landing DSP via the DSP's built-in SCI interface for backup information exchange. It connects to the NVM via a peripheral interface and obtains front wheel steering interface information through the FPGA to control the front wheel steering subsystem. The relationship between channels A and C in the front wheel steering subsystem is as follows: channel A is the primary channel, and channel C is the backup channel. Channel B does not participate in control.

[0036] Furthermore, the input / output interface circuit channels are independent of each other. For the emergency landing gear deployment solenoid valve control, a dual-redundant electrical control system is designed for channels B and C. Specifically, the emergency landing gear deployment control function is achieved by energizing the pneumatic-electric valve. Under normal circumstances, channel C is the emergency channel. The pneumatic-electric valve is designed with dual-redundant electrical control; channel B has a pneumatic-electric valve control interface. When channel C fails, the emergency landing gear deployment function can be achieved through the channel B interface.

[0037] Furthermore, FPGAs can implement input / output interface management, cross-channel transmission (CCDL), synchronization, and channel fault logic. Specifically, the channel fault logic is designed in three sets within the entire machine for each channel: fault logic for the landing gear retraction subsystem, fault logic for the braking subsystem, and fault logic for the front wheel steering subsystem. The landing system controller uses the channel fault logic to achieve mutual monitoring of hardware and software within each channel and to switch between channels. For the braking system and front wheel steering system, which require mutual exclusion control of the servo valves between the primary and backup channels, the channel fault logic implements hardware mutual exclusion, ensuring that the interface output can only be controlled when the current channel control is effective; otherwise, even if the software writes an output command, the hardware will not respond, thus improving system safety.

[0038] Specifically, the channel fault logic includes: (1) CHV indicates that the channel is valid; "1" indicates that the channel is valid, and "0" indicates that the channel is invalid. This signal is determined by the WDV, PSV, DSPV, LGCV, and DONE signals. CHV is valid when all five signals are valid. Valid; otherwise, CHV is invalid.

[0039] (2) CHCV indicates that channel control is valid; "1" indicates that channel control is valid, and "0" indicates that channel control is invalid. This signal is determined by WDV, DSPV, NOCV, and SWITCH. In master mode, the channel is effectively controlled as long as channel CHV is valid. In master / standby mode, the channel is effectively controlled only when both CHV and CHCV are valid.

[0040] (3) WDV is the watchdog valid signal, which is an internal signal of the FPGA and is valid by default. The logic watchdog is set in the FPGA, and the software accesses the FPGA through the local bus to perform the watchdog feeding operation. If the software malfunctions and fails to perform the watchdog feeding operation on the FPGA within the specified time, the WDV signal will be invalid and low level. After passing through an AND gate, the CHV and CHCV signals of this channel will be invalidated.

[0041] (4) PSV is the power supply valid signal, which is the GPIO output signal of the DSP and is valid by default. After the ±15V power supply is divided by resistors (-15V needs to be reversed by the circuit) to a suitable range, the DSP's built-in AD is used to collect and monitor the ±15V power supply. If an abnormal power supply voltage is detected, the software writes to the GPIO port to set the PSV signal to invalid and low level, and then sets the CHV signal of this channel to invalid after passing through an AND gate.

[0042] (5) DSPV is the valid signal of the DSP, which belongs to the GPIO output signal of the DSP and is valid by default. The software performs a self-test on the internal resources of the DSP in the periodic task. When an error is detected, the software writes to the GPIO port to invalidate the DSP signal to a low level, and then invalidates the CHV and CHCV signals of this channel through an AND gate.

[0043] (6) LGCV is a logic valid signal, belonging to the GPIO output signal of the DSP, and is valid by default. During the periodic task, the software accesses the FPGA through the local bus to perform read and write tests. If the test fails, the software writes to the GPIO port to invalidate the LGCV signal to a low level, and then invalidates the CHV signal of this channel through an AND gate.

[0044] (7) The DONE signal indicates the logic loading status. A high level indicates successful logic loading, and a low level indicates failure. After the FPGA establishes a 3.3V power supply, it begins the logic loading operation, transferring the bitstream file from the PROM to the FPGA for execution. The DONE signal is low by default after power-on. After successful logic loading, the DONE signal becomes high and remains high until power-off. If logic loading fails, the DONE signal is low and invalid, and the CHV signal of this channel is invalidated after passing through an AND gate.

[0045] (8) NOCV is a software-initiated handover signal, which is a GPIO output signal of the DSP and is valid by default. The software can write to the GPIO port to set the NOCV signal low, and then use an AND gate to invalidate the CHCV signal of this channel, thereby releasing the channel control.

[0046] (9) Power-on reset state In reset state, PSV, LGCV, DONE, WDV, and DSPV are all valid by default, and CHV is valid. 120ms after reset, #SWITCH of channel A becomes valid, therefore CHCV of channel A is valid, and channel A has control. Both CHV and CHCV of channel A are valid. The AND operation of these two signals is used as the #SWITCH signal input for channel B. 500ms after reset, channel B checks the #SWITCH signal. If the #SWITCH signal is invalid at this time, it indicates that control does not switch. After internal logic operations within the FPGA, CHCV of channel B is ultimately invalid, and channel B does not have control.

[0047] (10) Normal working status During normal operation, when WDV, PSV, DSPV, LGCV or NOCV are invalid in channel A, CHCV becomes invalid. After the AND operation of CHCV and CHV is connected to #SWITCH of channel B, #SWITCH of channel B becomes valid, indicating a switch in control and channel A loses control.

[0048] If #SWITCH of channel B is valid and WDV, PSV, DSPV, LGCV, and NOCV are valid, then CHCV of channel B becomes valid, and channel B has control; if #SWITCH of channel B is valid and any of WDV, PSV, DSPV, LGCV, and NOCV are invalid, CHCV of channel B becomes invalid, and channel B loses control. If both CHCVs in channels A and B are invalid, it indicates that the main channel and backup channel functions have been lost, the takeoff and landing control unit has a dual-channel failure, the takeoff and landing control unit remains silent, and the cockpit pilot controls the system through the emergency switch.

[0049] Furthermore, channels A and B are the primary and backup channels for braking, while channels A and C are the primary and backup channels for nose wheel steering. Normal nose wheel steering relies on the solenoid valves and servo valves in channels A and C to achieve forward and reverse rotation of the nose wheels. Channels A and B rely on solenoid valves and servo valves to achieve closed-loop control of braking pressure. When channels A and B fail, the aircraft can correct its course through nose wheel steering in channel C. When channels A and C fail simultaneously, the aircraft can correct its course through the differential braking function in channel B. This architecture ensures that the aircraft retains its corrective function even if any two channels fail.

[0050] Furthermore, in this embodiment, the three DSPs within the channel communicate serially via the FPGA's internal RS422 interface. When the FPGA fails, direct communication between the DSPs can be achieved through their built-in SCI serial interfaces. This dual serial communication design between processors enhances system security and task reliability. Each DSP within the channel is equipped with an NVM (Network Virtual Machine) to record its own system's fault and calibration information; the NVMs between systems are independent of each other.

[0051] A schematic diagram of a terminal device according to an embodiment of the present invention. The terminal device of this embodiment includes: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps in the various method embodiments described above. Alternatively, when the processor executes the computer program, it implements the functions of each module / unit in the various device embodiments described above.

[0052] The computer program can be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present invention.

[0053] The terminal device can be a desktop computer, laptop computer, cloud server, or other device with strong computing power. The terminal device may include, but is not limited to, a processor and memory.

[0054] The optimal choice for the processor is a multi-core high-speed central processing unit (CPU).

[0055] The memory can be used to store the computer program and / or module. The processor implements various functions of the terminal device by running or executing the computer program and / or module stored in the memory and calling the data stored in the memory.

[0056] If the modules / units integrated into the terminal device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0057] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A triple-redundant control system for aircraft takeoff and landing systems, characterized in that, It includes independent and electrically isolated channels A, B, and C, each of which includes a takeoff and landing management processor, a programmable logic device, a brake control processor, a front wheel steering control processor, a cross-transmission link interface, and an input / output interface; The takeoff and landing management processor, brake control processor and front wheel steering control processor are all connected to a programmable logic device and interact with the main information through the programmable logic device. Both the brake control processor and the front wheel steering control processor are connected to the takeoff and landing management processor. The programmable logic devices corresponding to channels A, B, and C are interconnected through a cross-transmission link interface. The programmable logic device is connected to an input / output interface, which is connected to the signal interfaces of the external landing gear retraction mechanism, braking mechanism, and front wheel steering mechanism.

2. A triple-redundant control system for an aircraft takeoff and landing system according to claim 1, characterized in that, The takeoff and landing management processor, brake control processor, and front wheel steering control processor are all connected to non-volatile memory via peripheral interfaces.

3. A triple-redundant control system for an aircraft takeoff and landing system according to claim 1, characterized in that, The takeoff and landing management processor communicates with the aircraft's aerospace system via a 1394 bus.

4. A triple-redundant control system for an aircraft takeoff and landing system according to claim 1, characterized in that, The takeoff and landing management processor, brake control processor, and front wheel steering control processor are all digital processors.

5. A triple-redundant control system for an aircraft takeoff and landing system according to claim 1, characterized in that, The input / output interfaces of channels B and C are connected to the control terminals of the emergency landing gear deployment solenoid valve. Channel B is a backup control channel, and channel C is the main control channel.

6. A triple-redundant control system for an aircraft takeoff and landing system according to claim 1, characterized in that, When controlling the retraction and extension of the landing gear, channel A is the main channel, channel B is the backup channel, and channel C is the emergency channel; When braking is controlled, channel A is the main channel, channel B is the backup channel, and channel C is the emergency channel; When controlling the front wheels to turn, channel A is the primary channel and channel C is the backup channel.

7. A triple-redundant control system for an aircraft takeoff and landing system according to claim 1, characterized in that, The cross-transmission link interface includes an SPI bus and an RS422 bus. The SPI bus is used for automatic forwarding of acquired data between programmable logic devices in each channel. The RS422 bus is used to forward application layer data between programmable logic devices in each channel.

8. A triple-redundant control system for an aircraft takeoff and landing system according to claim 1, characterized in that, The programmable logic device is a field-programmable gate array (FPGA).

9. A triple-redundant control system for an aircraft takeoff and landing system according to claim 8, characterized in that, The field-programmable gate array integrates a channel fault logic module, which is used to realize mutual monitoring between the processor and programmable logic device in the channel and the switching control between channels.

10. An aircraft takeoff and landing system, characterized in that, Includes the triple redundancy control system as described in any one of claims 1-8.

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