Can communication method of electronic speed regulator and electronic speed regulator

Abstract

Embodiments of the present application relate to the technical field of unmanned aerial vehicles, and disclose a CAN communication method of an electronic governor, the electronic governor and a computer readable storage medium. The electronic governor comprises a plurality of microcontrollers and a CAN transceiver, and the sending pin of each microcontroller is directly and in parallel connected to the sending input pin of the CAN transceiver. The method is executed by a target microcontroller and comprises the following steps: configuring the sending pin of the target microcontroller as a high-impedance state; synchronizing to a common timing reference while maintaining the high-impedance state, and determining the sending period corresponding to the target microcontroller based on the timing reference; switching the sending pin to an output state and sending a message via the CAN transceiver when entering the sending period; and restoring the sending pin to the high-impedance state after the message is sent. In the above manner, the plurality of microcontrollers can share one CAN transceiver without setting a gating circuit, thereby reducing the volume and weight of the electronic governor.

Description

Technical Field

[0001] This application relates to the field of unmanned aerial vehicle (UAV) technology, and in particular to a CAN communication method for an electronic speed controller and an electronic speed controller. Background Technology

[0002] The electronic speed controller (ESC) is a core component of the UAV's power system. It receives control commands from the flight controller, drives the brushless motor to operate at a specified speed, and transmits operating status information such as motor speed, current, and temperature back to the flight controller. As UAVs develop towards larger payloads, longer endurance, and higher reliability, the functions that the ESC needs to undertake are constantly increasing. Its internal architecture has also evolved from an early single-microcontroller architecture to a multi-microcontroller architecture, with different microcontrollers handling tasks such as motor drive and commutation control, operating status acquisition and monitoring, and external communication. Simultaneously, the communication method between the ESC and the flight controller and other airborne equipment has been upgraded from analog signals and unidirectional serial communication to CAN bus communication to meet the requirements of multi-device networking, bidirectional real-time transmission, and strong anti-interference. Since the microcontroller itself cannot directly drive the differential signals of the CAN bus, the ESC also needs to incorporate a CAN transceiver to convert between the microcontroller's logic level and the bus differential level.

[0003] In implementing the embodiments of this application, the inventors discovered that: currently, when multi-microcontroller architecture ESCs implement CAN communication, they either set up a separate CAN transceiver for each microcontroller, or add hardware switching structures such as hardware gate lines, analog switches, and interlocking circuits between multiple microcontrollers and a single CAN transceiver to achieve time-sharing of the transceiver. Both of these methods require the introduction of additional components and wiring, occupying a large printed circuit board area, resulting in a large size and weight of the ESC, which is difficult to adapt to the increasing miniaturization and lightweight installation requirements of UAVs. Summary of the Invention

[0004] The main technical problem solved by the embodiments of this application is to provide a CAN communication method for an electronic speed controller, an electronic speed controller and a computer-readable storage medium, which enables multiple microcontrollers to share a CAN transceiver without setting a gating circuit.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application embodiment is: providing a CAN communication method for an electronic speed controller, wherein the electronic speed controller includes multiple microcontrollers and a CAN transceiver, the CAN transceiver is connected between the CAN bus and the multiple microcontrollers and has a transmit input pin, the transmit pins of each microcontroller are directly connected in parallel to the transmit input pin, the method is executed by a target microcontroller among the multiple microcontrollers, and no gating circuit is provided between each transmit pin and the transmit input pin for selecting one of the multiple microcontrollers to be connected to the transmit input pin, the method includes: configuring the transmit pin of the target microcontroller to a high-impedance state, in the... In a high-impedance state, the transmit pin does not output a drive level to the transmit input pin. While maintaining the high-impedance state, it is synchronized to a common timing reference of the multiple microcontrollers, and the transmission period corresponding to the target microcontroller is determined based on the timing reference. The transmission period does not overlap with the transmission periods corresponding to the other microcontrollers among the multiple microcontrollers except the target microcontroller. When entering the transmission period, the transmit pin is switched from the high-impedance state to the output state, and a message is sent to the CAN bus via the CAN transceiver. After the message is sent, the transmit pin is restored to the high-impedance state and waits for the next entry into the transmission period.

[0006] Optionally, the electronic speed controller further includes an arbitration signal line, wherein the arbitration pins of each microcontroller are connected to the arbitration signal line in an open-drain manner. The arbitration signal line maintains a first level when not driven by any of the microcontrollers, and presents a second level different from the first level when driven by any of the microcontrollers. The step of switching the transmit pin from the high-impedance state to the output state and transmitting a message to the CAN bus via the CAN transceiver when entering the transmission period includes: detecting the level of the arbitration signal line when entering the transmission period; driving the arbitration signal line to the second level via the arbitration pin of the target microcontroller when the arbitration signal line is at the first level, switching the transmit pin from the high-impedance state to the output state, transmitting the message to the CAN bus via the CAN transceiver, and stopping driving the arbitration signal line after the message transmission is completed; and maintaining the transmit pin in the high-impedance state when the arbitration signal line is at the second level and waiting for the next transmission period to begin.

[0007] Optionally, the CAN transceiver further includes a standby control pin, and the arbitration signal line is the connection line between the arbitration pin of each microcontroller and the standby control pin; the CAN transceiver is in operating mode when the standby control pin is at the first level, and switches from operating mode to standby mode when the duration of the standby control pin being at the second level reaches the mode switching determination time; the target microcontroller drives the arbitration signal line to the second level for a duration shorter than the mode switching determination time.

[0008] Optionally, the CAN transceiver further includes a receive output pin, and the receive pins of each microcontroller are connected to the receive output pin. Before switching the transmit pin from the high-impedance state to the output state when the arbitration signal line is at the first level, the method further includes: detecting the level of the CAN bus through the receive pin of the target microcontroller to obtain a detection result; if the detection result indicates that at least 11 consecutive recessive bits appear on the CAN bus, performing the step of switching the transmit pin from the high-impedance state to the output state; if the detection result indicates that no consecutive recessive bits appear on the CAN bus, keeping the transmit pin in the high-impedance state, stopping the driving of the arbitration signal line, and waiting for the next transmission period.

[0009] Optionally, each of the microcontrollers is equipped with a CAN controller, which has a listen-only mode and a transmit mode. In the listen-only mode, the CAN controller receives messages transmitted on the CAN bus and does not output any level to the CAN bus; in the transmit mode, the CAN controller transmits messages to the CAN bus. The method further includes: configuring the CAN controller of the target microcontroller to the listen-only mode during the period when the transmit pin is in the high-impedance state; configuring the CAN controller to the transmit mode during the period when the transmit pin is in the output state; and clearing the error count value accumulated by the CAN controller in the transmit mode when the CAN controller is configured from the transmit mode to the listen-only mode.

[0010] Optionally, the plurality of microcontrollers includes a reference microcontroller, which is used to periodically send synchronization messages to the CAN bus via the CAN transceiver. Each microcontroller is equipped with a local timer. The synchronization to a common timing reference of the plurality of microcontrollers includes: when the target microcontroller receives the synchronization message, calibrating the local timer of the target microcontroller according to the synchronization message, and using the timing result of the calibrated local timer as the timing reference; when the duration for which the target microcontroller does not receive the synchronization message reaches a preset failure duration, using the timing result of the local timer as the timing reference, wherein the preset failure duration is longer than the period during which the reference microcontroller sends the synchronization message.

[0011] Optionally, each microcontroller is equipped with a local clock, and the local timer of each microcontroller is driven by its own local clock. A protection interval is set between two adjacent transmission periods, and each microcontroller does not send a message to the CAN bus during the protection interval. The duration of the protection interval is not less than the maximum time deviation, which is the maximum value of the accumulated time deviation caused by the frequency difference between the local clocks of each microcontroller within one cycle of the synchronization message.

[0012] Optionally, the method further includes: restoring the transmit pin to the high-impedance state and stopping driving the arbitration signal line when the duration of the transmit pin being in the output state reaches the maximum drive duration; the maximum drive duration is not less than the longest duration required for the target microcontroller to transmit a single message via the CAN transceiver.

[0013] To solve the above-mentioned technical problems, another technical solution adopted in this application embodiment is: providing an electronic speed controller, including multiple microcontrollers and a CAN transceiver, wherein the CAN transceiver is connected between the CAN bus and the multiple microcontrollers and is provided with a transmit input pin, wherein the transmit pins of each microcontroller are directly connected in parallel to the transmit input pin, and no gating circuit is provided between each transmit pin and the transmit input pin for selecting one of the multiple microcontrollers to be connected to the transmit input pin; each microcontroller includes a memory and a processing unit, wherein the memory stores a computer program, and the computer program is executed by the processing unit to implement the method described in any of the above-mentioned embodiments.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of this application is: providing a computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and the computer program, when executed by a processor, implements the method described in any of the above-mentioned embodiments.

[0015] This application provides a CAN communication method for an electronic speed controller. By configuring the transmit pins of each microcontroller to a high-impedance state outside their corresponding transmit time period and switching them to an output state during their corresponding transmit time period, and ensuring that the transmit time periods of each microcontroller do not overlap in time, the transmit time period determines which microcontroller should occupy the CAN transceiver at a certain moment. The high-impedance state electrically disconnects the unoccupied microcontroller from the transmit input pin, thereby allowing the transmit pins of multiple microcontrollers to be directly connected in parallel to the same transmit input pin. This eliminates the need for gating circuits and their associated wiring, reducing the printed circuit board area, volume, and weight of the electronic speed controller. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0017] Figure 1 This is a schematic diagram of the electronic speed controller provided in the embodiments of this application; Figure 2 A schematic flowchart of the CAN communication method for an electronic speed controller provided in an embodiment of this application; Figure 3 A schematic diagram of an electronic speed controller with an arbitration signal line provided in an embodiment of this application; Figure 4 A schematic diagram illustrating the arbitration signal line preemption and backoff process provided in an embodiment of this application; Figure 5 A schematic diagram of the electronic speed controller that uses a standby control pin multiplexed for arbitration signal lines, as provided in an embodiment of this application. Figure 6 A schematic diagram of the CAN bus idle detection process provided in an embodiment of this application; Figure 7 This is a schematic diagram of the CAN controller mode setting process provided in the embodiments of this application; Figure 8 A schematic diagram illustrating the process of establishing a timing reference provided in an embodiment of this application; Figure 9 A timing diagram illustrating the transmission period and protection interval provided for embodiments of this application; Figure 10 A schematic diagram of the maximum drive duration control provided in the embodiments of this application.

[0018] The reference numerals in the detailed embodiments are as follows: 100, Electronic speed controller; 11, First microcontroller; 12, Second microcontroller; 13, Third microcontroller; 101, Transmit pin; 102, Arbitration pin; 103, Receive pin; 104, CAN controller; 105, Local timer; 106, Local clock; 107, Memory; 108, Processing unit; 20, CAN transceiver; 21, Transmit input pin; 22, Standby control pin; 23, Receive output pin; 30, CAN bus; 40, Arbitration signal line; 41, Second pull-up element; 51, Transmit time period; 52, Guard interval; 53, Synchronization message; 54, Period of synchronization message. Detailed Implementation

[0019] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed" to another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "vertical," "horizontal," etc., used in this specification to indicate orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing this application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0021] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0022] The CAN communication method for an electronic speed controller provided in this application embodiment is applied to an electronic speed controller 100 of an unmanned aerial vehicle (UAV). The electronic speed controller 100 has multiple microcontrollers and is connected to a CAN bus 30 via a CAN transceiver 20 to complete message interaction with airborne equipment such as flight controllers.

[0023] Please see Figure 1The electronic speed controller 100 includes a first microcontroller 11, a second microcontroller 12, and a CAN transceiver 20. The CAN transceiver 20 is connected between the CAN bus 30 and the plurality of microcontrollers, and is used to convert between the logic level of the microcontrollers and the differential level of the CAN bus 30. It has a transmit input pin 21. The transmit pins 101 of the first microcontroller 11 and the second microcontroller 12 are directly connected in parallel to the same transmit input pin 21 by wires. No selection circuit is provided between each transmit pin 101 and the transmit input pin 21 to select one of the plurality of microcontrollers to be connected to the transmit input pin 21. Each microcontroller includes a CAN controller 104, a local timer 105, a local clock 106, a memory 107, and a processing unit 108. The CAN controller 104 is used in the following embodiment four; the local timer 105 and the local clock 106 are used in the following embodiment five; and the memory 107 and the processing unit 108 are used in the following embodiment seven. It should be noted that the number of microcontrollers is not limited. Figure 1 The two shown can also be three or more, for example... Figure 3 The first microcontroller 11, the second microcontroller 12, and the third microcontroller 13 shown are connected in the same way as... Figure 1 same.

[0024] To facilitate understanding of the embodiments of this application, several terms used in the claims and specification of this application will be explained here first.

[0025] The target microcontroller refers to any one of the plurality of microcontrollers currently executing this method. In the embodiments of this application, the method flow executed by each microcontroller is exactly the same, and any microcontroller executing this flow is the target microcontroller. This application does not limit the target microcontroller by the microcontroller's number, master-slave relationship, or specific task it undertakes.

[0026] The gating circuit refers to a circuit located between each transmit pin 101 and transmit input pin 21, used to enable one of the multiple microcontrollers to conduct through the transmit input pin 21 at a certain time, while disconnecting the other microcontrollers from the transmit input pin 21. Examples include analog switches, multiplexers, tri-state buffers, and hardware interlock circuits. In this embodiment, none of the above circuits are provided; each transmit pin 101 is directly connected in parallel to the transmit input pin 21.

[0027] The high-impedance state refers to a state where the transmit pin 101 neither outputs a high level nor a low level to the transmit input pin 21. In this embodiment, this state is achieved by remapping the transmit pin 101 from the CAN multiplexing function to a general-purpose input / output high-impedance input function. At this time, the push-pull drive circuit connected to this pin inside the microcontroller chip is completely disconnected. In other embodiments, the transmit pin 101 can also be configured in analog input mode, or other configuration methods that can disconnect the push-pull drive circuit connected to this pin inside the microcontroller chip can be used, as long as the configuration can ensure that the pin neither outputs a high level nor a low level. It should be noted that simply disabling the transmit enable of the CAN peripheral is not sufficient to form a high-impedance state, because most microcontrollers' CAN peripherals still maintain the transmit pin 101 as a recessive high level in push-pull output when idle. If multiple transmit pins 101 are directly connected in parallel, once one of them outputs a dominant low level, a level collision will occur between the two push-pull outputs.

[0028] The output state refers to the state in which the transmit pin 101 can output a drive level to the transmit input pin 21. In this embodiment, this state is achieved by remapping the transmit pin 101 to a CAN multiplexed push-pull output.

[0029] The timing reference refers to the timing start point or timing value that the multiple microcontrollers refer to together, used to ensure that the timing judgments of each microcontroller are consistent. For the specific method of obtaining it, please refer to Implementation Method Five below. The transmission period refers to the time interval allocated to each microcontroller based on the timing reference, allowing it to occupy the CAN transceiver 20 to send messages to the CAN bus 30. The transmission periods corresponding to each microcontroller do not overlap in time.

[0030] Please see Figure 2 The CAN communication method of the electronic speed controller provided in this embodiment is executed by the target microcontroller and includes the following steps.

[0031] S101: Set the transmit pin of the target microcontroller to a high-impedance state, and the transmit pin in the high-impedance state does not output a drive level to the transmit input pin; The target microcontroller's transmit pin is configured to a high-impedance state. After power-on initialization, the target microcontroller sets its transmit pin 101 to a high-impedance state, and the transmit pin 101 in this high-impedance state does not output a drive level to the transmit input pin 21. Since all the microcontrollers use the high-impedance state as their default state, at most only one microcontroller's transmit pin 101 can drive the transmit input pin 21 at any given time, thus avoiding level collisions between multiple push-pull outputs at the electrical level.

[0032] Optionally, a first pull-up element (not shown in the figure) is connected between the transmit input pin 21 and the power supply. In this way, during the period when all transmit pins 101 are in a high-impedance state, the transmit input pin 21 is pulled up and kept at a recessive level, preventing the CAN bus 30 from being continuously pulled to a dominant level during the microcontroller's reset due to the pin state being undefined.

[0033] S102: While maintaining the high impedance state, synchronize to the common timing reference of the multiple microcontrollers, and determine the transmission period corresponding to the target microcontroller based on the timing reference, wherein the transmission period does not overlap with the transmission periods corresponding to the other microcontrollers among the multiple microcontrollers except the target microcontroller in time. While maintaining the high-impedance state, synchronization is performed to a common timing reference shared by the multiple microcontrollers. The target microcontroller acquires this timing reference while its transmit pin 101 remains in a high-impedance state. Since this step is completed in a high-impedance state, the synchronization process itself will not affect the transmit input pin 21 or the CAN bus 30, and will not interfere with each other even if multiple microcontrollers execute this step simultaneously.

[0034] S103: When entering the transmission period, switch the transmission pin from the high-impedance state to the output state, and send a message to the CAN bus via the CAN transceiver; Based on the timing reference, the transmission period corresponding to the target microcontroller is determined. The target microcontroller, according to a preset time period division rule, determines its own corresponding transmission period based on the timing reference. This transmission period does not overlap with the transmission periods corresponding to the other microcontrollers among the plurality of microcontrollers (excluding the target microcontroller). For example, in an electronic speed controller 100 containing three microcontrollers, a cycle can be divided into three time periods, which are then assigned to the first microcontroller 11, the second microcontroller 12, and the third microcontroller 13, respectively. The duration of each transmission period can be equal, or it can be set differently depending on the message volume of the task undertaken by each microcontroller; this application does not impose any limitation on this.

[0035] S104: After the message is sent, restore the sending pin to the high-impedance state and wait for the next sending period.

[0036] When entering the transmission period, the transmission pin is switched from the high-impedance state to the output state. After entering its corresponding transmission period, the target microcontroller remaps the transmission pin 101 from the general-purpose input / output high-impedance input function to the CAN multiplexing function push-pull output, thereby obtaining the driving capability of the transmission input pin 21.

[0037] S105: When the arbitration signal line is at the first level, drive the arbitration signal line to the second level through the arbitration pin of the target microcontroller, switch the transmit pin from the high impedance state to the output state, send the message to the CAN bus through the CAN transceiver, and stop driving the arbitration signal line after the message is sent. The target microcontroller sends messages to the CAN bus via the CAN transceiver 20, and sends messages to the CAN bus 30 via the CAN transceiver 20 according to the CAN protocol. Optionally, the target microcontroller adopts a single-transmission mode during this transmission period, that is, it prohibits its CAN controller 104 from automatically retransmitting messages that fail to be transmitted. In this way, it can avoid messages being repeatedly retransmitted due to arbitration failure on the CAN bus 30, thereby crossing the boundary of this transmission period and encroaching on the transmission period of other microcontrollers.

[0038] S106: When the arbitration signal line is at the second level, keep the transmit pin in the high-impedance state and wait for the next transmission period.

[0039] After the message transmission is completed, the transmit pin is restored to the high-impedance state, and the system waits for the next transmission period. After the message transmission is completed, the target microcontroller resets the transmit pin 101 to the high-impedance state, exits the drive of the transmit input pin 21, and then waits for the next transmission period corresponding to itself, and executes steps S104 to S106 again, and so on. Thus, the multiple microcontrollers sequentially occupy the same CAN transceiver 20 according to their respective transmission periods, achieving time-division sharing of the CAN transceiver 20.

[0040] In other embodiments, the transmit pin 101 can also be configured in analog input mode, or other configurations that disconnect the push-pull drive loop connected to the pin within the microcontroller chip can be used, as long as the configuration ensures that the pin neither outputs a high level nor a low level. It should be noted that simply disabling the transmit enable of the CAN peripheral is insufficient to create a high-impedance state, because most microcontrollers' CAN peripherals maintain the transmit pin 101 as a recessive high level in a push-pull output when idle. If multiple transmit pins 101 are directly connected in parallel, a level collision will occur between the two push-pull outputs if one of them outputs a dominant low level.

[0041] This embodiment replaces the channel selection and channel disconnection functions performed by the gating circuit in the traditional scheme by cyclically switching the transmit pin 101 between a high-impedance state and an output state, in conjunction with non-overlapping transmit periods defined based on a common timing reference. The non-overlapping transmit periods determine which microcontroller should occupy the CAN transceiver 20 at a certain moment, while the high-impedance state ensures that the unoccupied microcontroller is electrically disconnected from the transmit input pin 21. Through the above settings, the transmit pins 101 of the multiple microcontrollers can be directly connected in parallel to the same transmit input pin 21, eliminating the need for analog switches, multiplexers, hardware interlock circuits, and other devices and their corresponding wiring, thereby reducing the printed circuit board area of ​​the electronic speed controller 100 and lowering its size and weight.

[0042] In the above embodiment, each microcontroller occupies the CAN transceiver 20 sequentially according to non-overlapping transmission time periods. However, each microcontroller determines whether to enter its corresponding transmission time period based on its own timing result. If there is a discrepancy between the timing result of one microcontroller and the other microcontrollers, two adjacent transmission time periods may actually overlap at the boundary. In this case, two microcontrollers may simultaneously switch their respective transmission pins 101 to the output state. Therefore, this embodiment adds an occupation confirmation step at the electrical level on the basis of time period division.

[0043] Please see Figure 3 The electronic speed controller 100 also includes an arbitration signal line 40. The arbitration pins 102 of the first microcontroller 11, the second microcontroller 12, and the third microcontroller 13 are all connected to the arbitration signal line 40 in an open-drain manner. The arbitration signal line 40 is connected to the power supply via a second pull-up element 41.

[0044] The arbitration signal line refers to a signal line shared by the multiple microcontrollers, used to indicate whether the CAN transceiver 20 is currently occupied by one of the microcontrollers. The open-drain configuration means that the arbitration pin 102 can only actively pull the arbitration signal line 40 to a low level, and cannot actively pull it to a high level; when no drive is applied to the arbitration pin 102, the pin is in a high-impedance state. Since the arbitration pins 102 of the multiple microcontrollers are all connected to the same arbitration signal line 40 in an open-drain configuration, as long as any one of the arbitration pins 102 is driven, the arbitration signal line 40 will be pulled low; this is the wired-AND characteristic.

[0045] The first level refers to the level presented by the arbitration signal line 40 when it is not driven by any microcontroller, and the second level refers to the level presented by the arbitration signal line 40 when it is driven by any microcontroller, which is different from the first level. Figure 3In the illustrated embodiment, the first level is a high level formed by the pull-up element, and the second level is a low level pulled out by the arbitration pin 102. It should be noted that this application uses "first level" and "second level" instead of "high level" and "low level" because, as described below... Figure 5 In the embodiment shown, the high-low relationship between the two depends on the pin level definition of the selected CAN transceiver 20. This application does not limit the specific high-low of the first level and the second level, as long as they are different from each other.

[0046] The second pull-up element 41 can be a pull-up resistor connected between the arbitration signal line 40 and the power supply, or it can be a pull-up structure set inside the microcontroller or the CAN transceiver 20, as long as it can keep the arbitration signal line 40 at the first level when it is not driven.

[0047] Please see Figure 4 In this embodiment, the step of "switching the transmission pin from the high-impedance state to the output state and sending a message to the CAN bus via the CAN transceiver" described in the above embodiment further includes the following steps.

[0048] S201: When entering the transmission period, detect the level of the arbitration signal line; After entering its corresponding transmission period, the target microcontroller does not immediately switch the transmission pin 101 to the output state, but first reads the current level of the arbitration signal line 40 through its arbitration pin 102.

[0049] It should be noted here that the target microcontroller has not yet applied any drive to the arbitration signal line 40 in this step, so the level it reads only reflects the driving situation of the other microcontrollers on this line, that is, detection first, then driving.

[0050] In some embodiments, after entering their corresponding transmission period and before executing step S201, each microcontroller may wait for a different detection delay, so that the detection of the arbitration signal line 40 by each microcontroller is staggered in time. The microcontroller that detects first has priority to gain access, and the microcontroller that detects later reads the second level and backs off, thereby forming a definite access order. The duration of this detection delay is greater than the sum of the signal transmission time on the arbitration signal line 40 and the level sampling time of the arbitration pin 102.

[0051] S202: Determine whether the arbitration signal line is at the first level.

[0052] If the arbitration signal line 40 is at the first level, it indicates that none of the microcontrollers are currently occupying the CAN transceiver 20, and the target microcontroller executes step S203; if the arbitration signal line 40 is at the second level, it indicates that the remaining microcontrollers are occupying the CAN transceiver 20, and the target microcontroller executes step S206.

[0053] S203: Drive the arbitration signal line to the second level via the arbitration pin of the target microcontroller.

[0054] The target microcontroller pulls the arbitration signal line 40 to the second level via its arbitration pin 102 to indicate to the other microcontrollers that the CAN transceiver 20 has been occupied. Thereafter, even if the other microcontrollers enter their transmission periods at the same time due to timing discrepancies, they will still read the second level in step S201, thus preventing them from switching their respective transmit pins 101 to the output state.

[0055] Optionally, to further reduce the possibility that both microcontrollers read the first level at the same time, each microcontroller, after entering its corresponding transmission period and before executing step S201, may wait for a different detection delay. The duration of this detection delay is greater than the sum of the signal transmission time on the arbitration signal line 40 and the level sampling time of the arbitration pin 102. In this way, the detection of the arbitration signal line 40 by each microcontroller is staggered in time, with the first detector gaining priority in access, and the subsequent detector inevitably reading the second level and retreating, thus forming a definite access order.

[0056] S204: Switch the transmit pin from the high-impedance state to the output state, and send a message to the CAN bus via the CAN transceiver.

[0057] After obtaining the right to use the device, the target microcontroller switches the transmit pin 101 from the high impedance state to the output state and sends a message to the CAN bus 30 via the CAN transceiver 20 according to the CAN protocol. The specific process is the same as steps S104 and S105 in the first specific implementation method.

[0058] S205: After the message is sent, stop driving the arbitration signal line.

[0059] After the message is sent, the target microcontroller restores its transmit pin 101 to a high-impedance state and simultaneously stops driving the arbitration signal line 40 via its arbitration pin 102. The arbitration signal line 40 is then restored to its first level by the pull-up element 41, allowing other microcontrollers to acquire access during its transmission period. It should be noted that this step is indispensable; otherwise, the arbitration signal line 40 will remain at the second level, and other microcontrollers will never be able to acquire access.

[0060] S206: Keep the transmit pin in the high-impedance state and wait for the next transmission period.

[0061] Upon reading the second level, the target microcontroller determines that the CAN transceiver 20 is already occupied by another microcontroller. Therefore, it abandons the current transmission, keeping the transmit pin 101 in a high-impedance state, and waits for the next transmission period before re-executing step S201. It should be noted that since the target microcontroller did not drive the arbitration signal line 40 during steps S201 to S202, no release action is required in this step.

[0062] The above Figure 3 In the illustrated embodiment, the arbitration signal line 40 is an open-drain signal line independently located within the electronic speed controller 100. As a preferred embodiment, the arbitration signal line 40 can also be multiplexed from the existing pins of the CAN transceiver 20, thus eliminating the need for any additional wiring.

[0063] Please see Figure 5 The CAN transceiver 20 also has a standby control pin 22, and the arbitration signal line 40 is the connection line between the arbitration pin 102 of each microcontroller and the standby control pin 22. The CAN transceiver 20 is in the working mode when the standby control pin 22 is at the first level, and switches from the working mode to the standby mode when the standby control pin 22 is at the second level for a duration that reaches the mode switching determination time.

[0064] The mode switching determination duration refers to the shortest duration of the level required for the CAN transceiver 20 to determine that the level on its standby control pin 22 constitutes a valid mode switching command. This value can be determined by the device parameters of the CAN transceiver 20. Level changes shorter than this duration are considered interference and filtered out by the CAN transceiver 20, and will not cause a change in its operating mode.

[0065] Accordingly, the target microcontroller drives the arbitration signal line 40 to the second level for a duration shorter than the mode switching determination duration. Thus, this drive constitutes a valid occupancy flag for the multiple microcontrollers, but is filtered out for the CAN transceiver 20. The CAN transceiver 20 remains in operating mode throughout the entire message transmission process of the target microcontroller, and its original standby control function does not interfere with the occupancy flag function added in this application.

[0066] It should be noted here that the first level should be the level that keeps the CAN transceiver 20 in operating mode. Different models of CAN transceivers 20 define different level polarities for their standby control pin 22; some use a high level to represent standby, while others use a low level. In implementation, the model that keeps the CAN transceiver 20 in operating mode when the arbitration signal line 40 is not driven should be selected, and the high and low levels of the first and second levels should be determined accordingly.

[0067] As an example, if the minimum mode switching determination time of a certain CAN transceiver 20 is 20 microseconds, then the duration of the target microcontroller driving the arbitration signal line 40 can be 5 microseconds. This duration is sufficient for the other microcontrollers to complete level sampling, and is much shorter than the mode switching determination time.

[0068] This embodiment adds an arbitration signal line 40 shared by the multiple microcontrollers. After entering its transmission period, the target microcontroller first detects the level of this line. Only when it is at the first level will the line be driven to the second level and the transmission pin 101 be switched. After the message is sent, the line is released. Even if two adjacent transmission periods overlap at the boundary due to timing deviation, only one microcontroller can obtain the right to occupy the line. The other microcontrollers will retreat to their next transmission period. This avoids multiple transmission pins 101 being in the output state at the same time and forming a level collision on the transmission input pin 21. Furthermore, the arbitration signal line 40 is multiplexed as the connection line of the standby control pin 22 of the CAN transceiver 20, and the driving time is limited to within the mode switching determination time. This allows the above-mentioned occupancy confirmation mechanism to be implemented without adding any wiring in the electronic speed controller 100.

[0069] The target microcontroller confirms that no other microcontroller among the plurality of microcontrollers is currently occupying the CAN transceiver 20 by detecting the level of the arbitration signal line 40. However, the arbitration signal line 40 is located inside the electronic speed controller 100, and its level only reflects the occupancy status of the CAN transceiver 20 by the plurality of microcontrollers, not the transmission and reception status of other nodes on the CAN bus 30. In addition to the electronic speed controller 100, the CAN bus 30 is usually connected to nodes such as flight controllers and other electronic speed controllers. If the target microcontroller switches its transmit pin 101 to the output state and sends a message while these nodes are sending messages, it will destroy the data frame being transmitted on the CAN bus 30. Therefore, this embodiment adds an idle confirmation to the CAN bus 30 in addition to the internal occupancy confirmation provided by the arbitration signal line 40.

[0070] Please see Figure 5The CAN transceiver 20 also has a receive output pin 23, to which the receive pins 103 of the first microcontroller 11 and the second microcontroller 12 are connected. The CAN transceiver 20 converts the differential signals received from the CAN bus 30 into logic levels and outputs them through the receive output pin 23. Thus, each of the multiple microcontrollers can read the current level of the CAN bus 30 through its respective receive pin 103. It should be noted that the receive output pin 23 is the output terminal of the CAN transceiver 20, while each receive pin 103 is an input terminal of the microcontroller. Therefore, connecting all receive pins 103 in parallel to the same receive output pin 23 will not cause level collisions and does not require state switching as with the transmit pin 101.

[0071] The recessive bit refers to the bit level corresponding to the CAN bus 30 when it is not driven by any node. After conversion by the CAN transceiver 20, it is output as a high level by the receive output pin 23. Conversely, the dominant bit refers to the bit level corresponding to the CAN bus 30 when it is driven by a node. After conversion, it is output as a low level. The CAN protocol stipulates that the bus is considered idle after any node detects 11 consecutive recessive bits on the bus. The length of these 11 bits corresponds to the standard length of the inter-frame space. This embodiment uses this length as the basis for determining that the CAN bus 30 is completely idle.

[0072] The detection result refers to the result obtained by the target microcontroller through its receiving pin 103 to continuously sample the level of the CAN bus 30, which is used to characterize whether there are no less than 11 consecutive recessive bits on the CAN bus 30.

[0073] Please see Figure 6 In this embodiment, before switching the transmit pin 101 from a high-impedance state to an output state when the arbitration signal line 40 is at a first level, the following steps are also included.

[0074] S301: Detect the level of the CAN bus via the receive pin of the target microcontroller.

[0075] After the target microcontroller drives the arbitration signal line 40 to the second level in step S203, it does not immediately switch its transmit pin 101. Instead, it continuously samples the level output by the receive output pin 23 through its receive pin 103. The sampling time interval can be the duration of one bit on the CAN bus 30, or it can be a value less than the duration of one bit. This application does not limit this, as long as it can distinguish continuous bit levels.

[0076] S302: The test results are obtained.

[0077] The target microcontroller performs statistical analysis on the sampled levels to obtain a detection result that characterizes whether at least 11 consecutive recessive bits appear on the CAN bus 30.

[0078] S303: Determine whether the detection result indicates that there are no fewer than 11 consecutive recessive bits on the CAN bus.

[0079] If the detection result indicates that there are no fewer than 11 consecutive recessive bits on the CAN bus 30, it means that there are no data frames being transmitted on the CAN bus 30, nor are there any residual interference signals. The target microcontroller then executes step S304. If the detection result indicates that no less than 11 consecutive recessive bits appear on the CAN bus 30, it means that there are still other nodes on the CAN bus 30 transmitting data frames, and the target microcontroller executes step S305.

[0080] S304: Perform the step of switching the transmit pin from the high-impedance state to the output state.

[0081] After confirming that the CAN bus 30 is in an idle state, the target microcontroller executes step S204 in the second specific implementation method, that is, switches its transmit pin 101 from a high-impedance state to an output state and sends a message.

[0082] The target microcontroller needs to meet two conditions simultaneously to switch transmit pin 101: Firstly, the arbitration signal line 40 is at the first level, indicating that no other microcontrollers inside the electronic speed controller 100 are occupying the CAN transceiver 20; Secondly, the presence of at least 11 consecutive recessive bits on the CAN bus 30 indicates that no other nodes outside the electronic speed controller 100 are occupying the CAN bus 30. Both conditions are indispensable.

[0083] S305: Keep the transmit pin in the high-impedance state, stop driving the arbitration signal line, and wait for the next transmission period.

[0084] If the target microcontroller does not confirm that the CAN bus 30 is idle, it will abandon the transmission, keeping its transmit pin 101 in a high-impedance state. It is important to note that this step also requires stopping the drive of its arbitration pin 102 to the arbitration signal line 40.

[0085] This is because the target microcontroller had already driven the arbitration signal line 40 to the second level through step S203 before executing step S301. If this step only backs off without releasing the line, the arbitration signal line 40 will continue to maintain the second level, and the other microcontrollers will read the second level during their respective transmission periods and will not be able to obtain the right to occupy the line.

[0086] After release, the target microcontroller waits for the next transmission period corresponding to itself and re-executes step S201 in the second specific implementation method.

[0087] In some embodiments, after executing step S305, the target microcontroller may not need to wait until the next transmission period, but may instead re-execute steps S201 to S303 for the remaining duration of the current transmission period until the current transmission period ends. This can improve the utilization rate of the current transmission period and is suitable for situations where the messages from other nodes on the CAN bus 30 are relatively dense.

[0088] In some embodiments, before executing step S304, the target microcontroller may also determine whether the remaining duration of the current transmission period is not less than the maximum duration required to transmit a single message, and only switch its transmission pin 101 if the remaining duration is sufficient. This prevents the message transmission process from exceeding the boundary of the current transmission period.

[0089] Based on the internal occupancy confirmation described in Specific Implementation 2, this implementation adds a CAN bus 30 idle confirmation based on 11 consecutive recessive bits. Both are used as the admission conditions for the target microcontroller to switch its transmit pin 101. The arbitration signal line 40 resolves the occupancy conflict between the multiple microcontrollers inside the electronic speed controller 100, while the detection of consecutive recessive bits resolves the occupancy conflict between the electronic speed controller 100 and other nodes on the CAN bus 30. The two address different objects and together ensure that the target microcontroller only sends messages when both the CAN transceiver 20 and the CAN bus 30 are in an idle state, avoiding damage to the data frames being transmitted on the CAN bus 30. In this implementation, the arbitration signal line 40 is released synchronously when the detection fails, ensuring that the other microcontrollers can still normally obtain occupancy rights during their respective transmission periods.

[0090] In the above embodiments, the target microcontroller keeps the transmit pin 101 in a high-impedance state outside its corresponding transmission period, thereby disconnecting it from the transmit input pin 21 at the electrical level. However, the state switching of the transmit pin 101 only changes the connection relationship between the pin and the internal drive circuit of the chip, and does not change the working state of the CAN controller 104 inside the microcontroller itself.

[0091] If the CAN controller 104 remains in a transmittable state during this period, the following situation may occur: The CAN controller 104 believes that it is sending a certain bit level to the CAN bus 30, and compares the level read back through the receive pin 103 with the bit level according to the bit monitoring mechanism specified by the CAN protocol. Since the transmit pin 101 is in a high-impedance state at this time, the level output by the CAN controller 104 does not actually reach the transmit input pin 21. Instead, it reads back the level transmitted by other nodes on the CAN bus 30. The two are inevitably inconsistent, and the CAN controller 104 determines that a bit error has occurred, and its error count is incremented accordingly.

[0092] The above process repeats itself. After the error count accumulates to the threshold, the CAN controller 104 will enter the bus shutdown state and stop transmitting and receiving. The microcontroller loses its transmitting capability before its corresponding transmitting period arrives. Therefore, this embodiment makes the working mode of the CAN controller 104 switch synchronously with the state of the transmitting pin 101.

[0093] Please refer to the following: Figure 1 Both the first microcontroller 11 and the second microcontroller 12 are equipped with a CAN controller 104. The CAN controller 104 is used to encapsulate, send, receive and parse messages according to the CAN protocol.

[0094] The listen-only mode refers to the operating mode in which the CAN controller 104 receives messages transmitted on the CAN bus 30 but does not output any level to the CAN bus 30. In this mode, the CAN controller 104 neither actively sends messages nor sends acknowledge bits or error flags, and therefore does not perform bit monitoring. Its error count will not accumulate even when the transmit pin 101 is in a high-impedance state.

[0095] The transmission mode refers to the working mode in which the CAN controller 104 sends messages to the CAN bus 30. In this mode, the CAN controller 104 executes all transmission and reception processes, including bit monitoring, according to the CAN protocol.

[0096] The error count value refers to the cumulative value obtained by the CAN controller 104 according to the CAN protocol for detecting errors. When the value reaches the threshold specified by the CAN protocol, the CAN controller 104 enters the bus shutdown state.

[0097] Please see Figure 7 The method provided in this embodiment also includes the following steps.

[0098] S401: During the period when the transmit pin is in the high impedance state, configure the CAN controller of the target microcontroller to the listen-only mode.

[0099] During the period when the target microcontroller's transmit pin 101 is in a high-impedance state, its CAN controller 104 is configured to listen-only mode. During this period, the CAN controller 104 does not output any level to the CAN bus 30, nor does it perform bit monitoring, so that the error count value will not be accumulated because the transmit pin 101 has been disconnected. At the same time, the CAN controller 104 can still receive the messages transmitted on the CAN bus 30 normally through the receive pin 103 in this mode. Therefore, the target microcontroller can still receive the control commands issued by the flight controller and the synchronization messages sent by the reference microcontroller in the following specific implementation method five during this period.

[0100] S402: During the period when the transmit pin is in the output state, configure the CAN controller to the transmit mode.

[0101] When the target microcontroller switches its transmit pin 101 from high-impedance to output mode, it simultaneously configures its CAN controller 104 from listen-only mode to transmit mode, restoring the CAN controller 104's full transmit and receive capabilities to complete message transmission. Since the transmit pin 101 is now in output mode, the level output by the CAN controller 104 can reach the CAN bus 30 via the transmit input pin 21. The level read back by its bit monitor is consistent with the bit level it transmitted, and no bit error occurs.

[0102] As can be seen from the above steps S401 and S402, the working mode of the CAN controller 104 always corresponds to the state of the transmit pin 101: when the transmit pin 101 is in a high impedance state, the CAN controller 104 is in a listen-only mode; when the transmit pin 101 is in an output state, the CAN controller 104 is in a transmit mode.

[0103] The two modes are switched synchronously to avoid a mismatch where the CAN controller 104 is in transmit mode while the transmit pin 101 is in a high-impedance state.

[0104] S403: When the CAN controller is configured from the transmit mode to the listen-only mode, clear the error count value accumulated by the CAN controller in the transmit mode.

[0105] When the target microcontroller completes message transmission, restores its transmit pin 101 to a high-impedance state, and configures its CAN controller 104 from transmit mode back to listen-only mode, it also clears the error count value accumulated by the CAN controller 104 during this transmit mode. Even if a small number of error counts are generated due to interference on the CAN bus 30 during this transmission, the count will not continue to accumulate across the transmission period, ensuring that the CAN controller 104 enters the transmit mode with no residual errors when the next transmission period arrives.

[0106] In some embodiments, in addition to the case where message transmission is completed, the target microcontroller may also perform the above-mentioned clearing operation in the following two cases: one is when the target microcontroller abandons the transmission in step S206 of specific embodiment two or step S305 of specific embodiment three. The second is when the transmission period corresponding to the target microcontroller ends. The clearing operation can be achieved by performing a soft reset on the CAN controller 104, or by directly writing to its error count register; this application does not limit this to either.

[0107] It should be noted that, according to the CAN protocol, the sender of a message needs to receive an acknowledgment from the other nodes on the CAN bus 30 in the acknowledgment bit in order to determine that the message was successfully sent.

[0108] In this embodiment of the application, all microcontrollers except the target microcontroller are in listen-only mode during this period, and their transmit pins 101 are in a high-impedance state, thus not providing a response.

[0109] This application embodiment is applicable to situations where a flight controller or other electronic speed controllers are connected to the CAN bus 30, and these nodes provide responses. When the electronic speed controller 100 is being bench-tested alone and there are no other nodes on the CAN bus 30, the CAN controller 104 of the target microcontroller can be configured in self-response mode, or a judgment of response errors can be added in addition to the detection results described in Specific Embodiment Three; this application does not limit this.

[0110] This implementation synchronizes the switching of the CAN controller 104's operating mode with the state of the transmit pin 101. During the period when the transmit pin 101 is in a high-impedance state, the CAN controller 104 is configured in listen-only mode, thereby stopping its transmission behavior at the protocol level. This prevents the accumulation of error counts due to inconsistencies between the bit monitoring readback level and the transmitted bit level, and thus prevents the microcontroller from entering a bus-off state before its transmission period arrives due to the error count reaching a threshold. Since the CAN controller 104's receiving function is unaffected in listen-only mode, each microcontroller can still normally receive messages transmitted on the CAN bus 30 outside its transmission period. The error count is cleared each time the transmission mode is exited, ensuring that each transmission period is independent and that the error count does not accumulate across transmission periods.

[0111] The target microcontroller determines its corresponding transmission period based on a common timing reference shared by the multiple microcontrollers. This embodiment further explains the method for establishing this timing reference and the problem of overlapping time period boundaries caused by timing errors among the microcontrollers.

[0112] Please refer to the following: Figure 1Each microcontroller is equipped with a local timer 105 and a local clock 106. The local timer 105 is driven by the local clock 106 to keep time, and its timing result is the basis for the microcontroller to determine whether it has entered its corresponding transmission period.

[0113] The plurality of microcontrollers includes a reference microcontroller, which is used to periodically send synchronization messages to the CAN bus 30 via the CAN transceiver 20. The reference microcontroller can be any one of the first microcontroller 11, the second microcontroller 12, or the third microcontroller 13.

[0114] It should be noted that the synchronization message is transmitted via the existing CAN bus 30. Its transmission process is the same as that of other messages. That is, the reference microcontroller also switches its transmit pin 101 to the output state and sends the synchronization message during its corresponding transmission period. Therefore, there is no need to set up a separate synchronization line for timing synchronization and no additional wiring is required in the electronic speed controller 100.

[0115] The synchronization message refers to the message sent by the reference microcontroller for other microcontrollers to calibrate their local timers 105. Other microcontrollers can distinguish it from other messages using a message identifier. The preset failure duration is a threshold duration used to determine when the reference microcontroller can no longer send synchronization messages. The maximum time deviation is the maximum cumulative time deviation caused by the frequency difference between the local clocks 106 of each microcontroller within one cycle of the synchronization message. The protection interval is the time interval set between two adjacent transmission periods during which none of the microcontrollers send messages to the CAN bus 30.

[0116] Please see Figure 8 In this embodiment, the step of "synchronizing to the common timing reference of the multiple microcontrollers" described in the above embodiments further includes the following steps.

[0117] S501: Receives synchronization messages periodically sent by the reference microcontroller.

[0118] The target microcontroller receives messages transmitted on the CAN bus 30 via its receive pin 103 and identifies the synchronization message sent by the reference microcontroller based on the message identifier. As described in Specific Implementation Four, the target microcontroller is in a listen-only mode outside of its transmission period. In this mode, its receiving function is unaffected, and therefore it can receive synchronization messages normally.

[0119] S502, determine whether the duration of the time during which the synchronization message has not been received has reached the preset expiration time.

[0120] The target microcontroller keeps track of the elapsed time since it last received a synchronization message and compares that time with a preset failure time.

[0121] If the timeout period does not reach the preset failure timeout period, it indicates that the reference microcontroller is still sending synchronization messages normally, and the target microcontroller executes step S503.

[0122] If the timeout period reaches the preset failure timeout, it indicates that the reference microcontroller can no longer send synchronization messages, and the target microcontroller executes step S505.

[0123] The preset failure duration is longer than the period during which the reference microcontroller sends synchronization messages. If the preset failure duration is less than or equal to this period, the target microcontroller will also mistakenly judge the reference microcontroller as failed due to the normal interval between two synchronization messages during normal operation, causing it to repeatedly switch between the two timing modes.

[0124] For example, the preset failure duration can be three to five times the period of the synchronization message, in order to strike a balance between timeliness and the ability to resist occasional packet loss.

[0125] S503: Calibrate the local timer of the target microcontroller according to the synchronization message.

[0126] The target microcontroller calibrates its local timer 105 based on the received synchronization message, for example, by clearing the local timer 105 or setting it to the timing value carried by the synchronization message.

[0127] S504: Use the timing result of the calibrated local timer as the timing reference.

[0128] The target microcontroller uses the timing result of the calibrated local timer 105 as a timing reference and determines its corresponding transmission period accordingly. Since the multiple microcontrollers all complete the calibration based on the same synchronization message, the local timers 105 of each microcontroller thus obtain a consistent timing starting point.

[0129] S505: Use the timing result of the local timer as the timing reference.

[0130] If the reference microcontroller is determined to be faulty, the target microcontroller will no longer wait for the synchronization message. Instead, it will directly use the current timing result of its local timer 105 as the timing reference, maintain timing independently according to its own local clock 106, and continue to determine its corresponding transmission period accordingly.

[0131] Since the multiple microcontrollers had been calibrated before the reference microcontroller failed, and each continued to time according to the same time period division rules, the multiple microcontrollers could still maintain non-overlapping transmission periods for a period of time after the reference microcontroller failed, and CAN communication would not be interrupted.

[0132] Please see Figure 9 In this embodiment, a protection interval 52 is set between two adjacent transmission periods 51, and each microcontroller does not send messages to the CAN bus 30 within the protection interval 52. Figure 9 The diagram shows a period 54 between two transmissions of the synchronization message 53, in which a first transmission period 51, a guard interval 52, a second transmission period 51, a guard interval 52, and a third transmission period 51 are arranged sequentially.

[0133] The reason for setting the guard interval 52 is that there is a frequency difference between the local clocks 106 of each microcontroller. Since the last calibration, the deviation between the timing results of the local timers 105 of each microcontroller has accumulated over time. If two adjacent transmission periods 51 are directly connected, this deviation will cause the start of the transmission period as perceived by one microcontroller to be earlier than the end of the transmission period as perceived by the preceding microcontroller, thus causing the two transmission periods to overlap at the boundary. After setting the guard interval 52, as long as the deviation does not exceed the duration of the guard interval 52, the above overlap will not occur.

[0134] Therefore, the duration of the protection interval 52 is not less than the maximum time deviation. For example, this maximum time deviation can be determined by the following formula: Maximum time deviation 2 Maximum relative frequency deviation of local clock Synchronization message period jitter in the reception time of synchronization messages The first term represents the cumulative deviation caused by the local clocks 106 of the two microcontrollers deviating from their nominal frequencies in opposite directions, while the second term represents the difference in the timing of each microcontroller's recognition of the synchronization message due to factors such as interrupt response.

[0135] As an example, if the local clock 106 uses an oscillator with a relative frequency deviation of one percent, the period of the synchronization message is ten milliseconds, and the jitter of the receiving time of the synchronization message is twenty microseconds, then the maximum time deviation is two hundred and twenty microseconds, and the duration of the guard interval 52 can be taken as two hundred and fifty microseconds.

[0136] As another example, if the local clock 106 uses a crystal oscillator with a relative frequency deviation of 50 parts per million, and all other conditions remain unchanged, then the maximum time deviation is 20.5 microseconds, and the duration of the guard interval 52 can be taken as 30 microseconds.

[0137] Therefore, it can be seen that by selecting a local clock 106 with a smaller frequency deviation, or by shortening the period of the synchronization message, the duration of the protection interval 52 can be shortened, thereby improving the time utilization of the CAN bus 30.

[0138] In some embodiments, the duration of each transmission period 51 and the duration of each protection interval 52 may be equal, or may be set to be unequal according to the message volume of the task undertaken by each microcontroller. This application does not limit this.

[0139] In some embodiments, to reduce the transmission delay of fault messages such as motor stall, over-temperature, and over-current, as well as emergency throttle control commands, a preemption period can be set separately within a cycle 54. When any microcontroller detects an event of the aforementioned preset type, it does not need to wait for its corresponding transmission period 51, but can initiate preemption according to the steps in the above embodiments within the next preemption period. Regular operating parameters and status log messages are still transmitted within their respective transmission periods 51.

[0140] This implementation establishes a common timing reference for the multiple microcontrollers by periodically sending synchronization messages via the existing CAN bus 30, without the need to set up a separate synchronization line. In the event of failure of the reference microcontroller, each microcontroller switches to independent timing based on its own local clock 106, avoiding CAN communication interruption due to the single point of failure of the reference microcontroller.

[0141] Based on this, a protection interval 52 with a duration not less than the maximum time deviation is set between two adjacent transmission periods 51, so that the accumulated deviation of the frequency difference between the local clocks 106 of each microcontroller is absorbed within the protection interval 52, ensuring that the transmission periods 51 do not overlap in actual operation.

[0142] In the above embodiments, after acquiring the occupancy permission, the target microcontroller switches its transmit pin 101 to the output state, and actively restores it to the high-impedance state and stops driving the arbitration signal line 40 after the message is sent. The above release action depends on the normal operation of the target microcontroller's program. If the target microcontroller cannot execute the release step due to a program abnormality during this period, its transmit pin 101 will remain in the output state, and the arbitration signal line 40 will also remain driven to the second level.

[0143] The following consequences will occur at this time: the other microcontrollers will all read the second level during their respective transmission periods and will be unable to obtain the right to use the device, and the CAN communication in the electronic speed controller 100 will be terminated; if the transmission pin 101 happens to be at the dominant level, the CAN bus 30 will be continuously pulled to the dominant level, and the other nodes such as the flight controller on the CAN bus 30 will also be unable to complete communication.

[0144] Therefore, this embodiment adds a forced release step that does not depend on the normal execution of the above-mentioned release steps.

[0145] The maximum drive duration refers to the upper limit of the duration during which the transmit pin 101 can remain in the output state continuously. This upper limit is not less than the maximum duration required for the target microcontroller to transmit a single message via the CAN transceiver 20. If this upper limit is less than the maximum duration required to transmit a single message, the normal message transmission process will be interrupted midway, resulting in incomplete data frames on the CAN bus 30.

[0146] The maximum duration required to send a single message can be determined based on the communication rate of the CAN bus 30 and the maximum length of the message. As an example, with a communication rate of one megabit per second, using a standard frame format and a data field length of eight bytes, the number of bits in a single message after bit stuffing is approximately 130 bits, and its transmission time is approximately 130 microseconds. Therefore, the maximum drive time can be taken as 500 microseconds.

[0147] Please see Figure 10 The method provided in this embodiment also includes the following steps.

[0148] S601: Detect the duration for which the transmit pin is in the output state.

[0149] The target microcontroller starts timing the duration of the output state of the transmit pin 101 from the high-impedance state to the output state.

[0150] This timing can be accomplished by a timing unit independent of the main program flow, so that it can still proceed normally in the event of an exception in the main program.

[0151] S602: Determine whether the duration has reached the maximum driving duration.

[0152] The target microcontroller compares the above duration with the maximum drive duration. If the duration reaches the maximum drive duration, it indicates that the transmission failed to be completed within the expected duration, and the target microcontroller executes step S603. If the transmission is not completed, it indicates that the transmission is still in progress and the target microcontroller will execute step S605.

[0153] S603: Restore the transmit pin to the high-impedance state.

[0154] The target microcontroller forces its transmit pin 101 to return to a high-impedance state from an output state, causing it to stop driving the transmit input pin 21. Even though the pin was originally at a dominant level, the CAN bus 30 immediately returns to a recessive level, allowing the remaining nodes on the CAN bus 30 to continue communicating.

[0155] S604: Stop driving the arbitration signal line.

[0156] The target microcontroller simultaneously stops driving the arbitration signal line 40 via its arbitration pin 102, thus restoring the arbitration signal line 40 to its first level. The remaining microcontrollers can then regain access during their respective transmission periods, allowing CAN communication within the electronic speed controller 100 to continue.

[0157] It should be noted that this step and step S603 must be performed together. If only the transmit pin 101 is restored without releasing the arbitration signal line 40, the other microcontrollers will still be unable to obtain the right to use the device because they read the second level.

[0158] S605: Keep the transmit pin in the output state.

[0159] If the duration does not reach the maximum drive duration, the target microcontroller keeps its transmit pin 101 in the output state, completes the message transmission according to step S105, and actively restores it to the high impedance state after the transmission is completed according to step S106.

[0160] The forced release described in this embodiment is only triggered when the active release fails to complete on time, and the normal sending process is not affected.

[0161] In some embodiments, the CAN transceiver 20 may also have a dominant timeout protection function, that is, when the duration for which its transmit input pin 21 is held at a dominant level reaches the upper limit specified by the device, its drive to the CAN bus 30 is automatically shut down. This function and the forced release mechanism described in this embodiment can be configured in parallel, acting on the microcontroller side and the CAN transceiver 20 side respectively, with mutual redundancy. In this case, the maximum drive duration should preferably be less than the aforementioned upper limit specified by the CAN transceiver 20, so that the CAN bus 30 is preferentially released by the microcontroller side.

[0162] In some embodiments, after executing steps S603 and S604, the target microcontroller may further configure its CAN controller 104 to a listening mode and clear its error count value according to step S403 of the fourth embodiment, so that the microcontroller can enter the transmission mode with no residual errors when the next transmission period arrives.

[0163] This embodiment uses the duration of the transmit pin 101 in the output state as the criterion. When this duration reaches the maximum drive duration, the transmit pin 101 is forcibly restored to a high-impedance state and the arbitration signal line 40 is released. This embodiment does not rely on the normal execution of the target microcontroller's main program flow. Therefore, it can still be triggered in the event of a program malfunction in the target microcontroller. This avoids a single microcontroller occupying the CAN transceiver 20 for a long time, preventing other microcontrollers in the electronic speed controller 100 from communicating. It also avoids the microcontroller continuously pulling the CAN bus 30 to a dominant level, affecting other nodes on the CAN bus 30. Since the maximum drive duration is not less than the longest duration required to send a single message, the normal message transmission process will not be interrupted midway.

[0164] Please refer to the following: Figure 1 This application provides an electronic speed controller 100, including the plurality of microcontrollers and a CAN transceiver 20. The CAN transceiver 20 is connected between the CAN bus 30 and the plurality of microcontrollers and is provided with a transmit input pin 21. The plurality of microcontrollers are, for example, Figure 1 The first microcontroller 11 and the second microcontroller 12 shown can also be Figure 3 The number of the first microcontroller 11, the second microcontroller 12, and the third microcontroller 13 shown is not limited. The transmit pins 101 of each microcontroller are directly connected in parallel to the transmit input pin 21, and there is no gating circuit between each transmit pin 101 and the transmit input pin 21 for selecting one of the plurality of microcontrollers to be connected to the transmit input pin 21.

[0165] Each microcontroller includes a memory 107 and a processing unit 108. The memory 107 stores a computer program, which, when executed by the processing unit 108, implements the CAN communication method of the electronic speed controller described in any of the above specific embodiments.

[0166] The memory 107 can be flash memory, read-only memory, programmable read-only memory, or random access memory, etc. It can be integrated inside the microcontroller chip or it can be a memory chip that is independently set outside the microcontroller chip and connected to it. This application does not limit this. The processing unit 108 can be the processor core inside the microcontroller chip or it can be other computing units with program execution capabilities. This application does not limit this.

[0167] In some embodiments, the electronic speed controller 100 further includes an arbitration signal line 40 and a second pull-up element 41. The arbitration pins 102 of each microcontroller are connected to the arbitration signal line 40 in an open-drain manner, as shown in the diagram. Figure 3As shown; or, the CAN transceiver 20 has a standby control pin 22, and the arbitration signal line 40 is the connection line between the arbitration pin 102 of each microcontroller and the standby control pin 22, and its connection method is as follows. Figure 5 As shown.

[0168] In some embodiments, the CAN transceiver 20 further includes a receive output pin 23, and the receive pins 103 of each microcontroller are connected to the receive output pin 23, as shown in the following connection method. Figure 5 As shown.

[0169] In some embodiments, each microcontroller further includes a CAN controller 104, a local timer 105, and a local clock 106, configured as follows: Figure 1 As shown.

[0170] Furthermore, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the CAN communication method of the electronic speed controller described above.

[0171] The computer-readable storage medium can be a flash memory, read-only memory, programmable read-only memory, random access memory, magnetic disk, or optical disk, or any other medium capable of storing program code. This computer-readable storage medium can be located within the electronic speed controller 100 or can be a separate medium used for programming or upgrading the electronic speed controller 100. Therefore, even without altering the hardware structure of the electronic speed controller 100, the existing electronic speed controller 100 can possess the functions described in the CAN communication method for electronic speed controllers by writing the aforementioned computer program to each microcontroller.

[0172] Those skilled in the art will understand that all or part of the CAN communication method of the electronic speed controller described in the above specific embodiments can be implemented by hardware related to computer program instructions. The computer program can be stored in the above computer-readable storage medium, and when the computer program is executed, it can include the process of the method described in each of the above specific embodiments.

[0173] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A CAN communication method for an electronic speed controller, the electronic speed controller comprising multiple microcontrollers and a CAN transceiver, the CAN transceiver being connected between a CAN bus and the multiple microcontrollers and having a transmit input pin, the transmit pins of each microcontroller being directly connected in parallel to the transmit input pin, the method being executed by a target microcontroller among the multiple microcontrollers, characterized in that, The method includes the following: No gating circuit is provided between each of the transmit pins and the transmit input pins for selecting one of the plurality of microcontrollers to be connected to the transmit input pin. The transmit pin of the target microcontroller is set to a high-impedance state, and the transmit pin in the high-impedance state does not output a drive level to the transmit input pin; While maintaining the high-impedance state, the system is synchronized to a common timing reference of the multiple microcontrollers, and the transmission period corresponding to the target microcontroller is determined based on the timing reference. The transmission period does not overlap with the transmission periods corresponding to the other microcontrollers among the multiple microcontrollers except the target microcontroller in time. When entering the transmission period, the transmission pin is switched from the high-impedance state to the output state, and a message is sent to the CAN bus via the CAN transceiver; After the message is sent, the sending pin is restored to the high-impedance state and waits for the next sending period.

2. The CAN communication method for the electronic speed controller according to claim 1, characterized in that, The electronic speed controller also includes an arbitration signal line. The arbitration pins of each microcontroller are connected to the arbitration signal line in an open-drain manner. The arbitration signal line maintains a first level when not driven by any of the microcontrollers, and presents a second level different from the first level when driven by any of the microcontrollers. During the transmission period, the transmission pin is switched from a high-impedance state to an output state, and a message is sent to the CAN bus via the CAN transceiver, including: When the transmission period begins, the level of the arbitration signal line is detected; When the arbitration signal line is at the first level, the arbitration signal line is driven to the second level through the arbitration pin of the target microcontroller, the transmit pin is switched from the high impedance state to the output state, the message is sent to the CAN bus via the CAN transceiver, and the driving of the arbitration signal line is stopped after the message is sent. When the arbitration signal line is at the second level, the transmit pin remains in the high-impedance state and waits for the next transmission period.

3. The CAN communication method for the electronic speed controller according to claim 2, characterized in that, The CAN transceiver also has a standby control pin, and the arbitration signal line is the connection line between the arbitration pin of each microcontroller and the standby control pin; The CAN transceiver is in operating mode when the standby control pin is at the first level, and switches from operating mode to standby mode when the duration of the standby control pin being at the second level reaches the mode switching determination time. The duration for which the target microcontroller drives the arbitration signal line to the second level is less than the mode switching determination duration.

4. The CAN communication method for the electronic speed controller according to claim 2 or 3, characterized in that, The CAN transceiver also has a receive output pin, and the receive pins of each microcontroller are connected to the receive output pin. Before switching the transmit pin from the high-impedance state to the output state when the arbitration signal line is at the first level, the method further includes: The detection result is obtained by detecting the level of the CAN bus through the receive pin of the target microcontroller; If the detection result indicates that there are no fewer than 11 consecutive recessive bits on the CAN bus, then the step of switching the transmit pin from the high-impedance state to the output state is performed. If the detection result indicates that no consecutive recessive bits appear on the CAN bus, the transmit pin is kept in the high-impedance state, the arbitration signal line is stopped from being driven, and the system waits for the next transmission period.

5. The CAN communication method for the electronic speed controller according to claim 1, characterized in that, Each of the microcontrollers is equipped with a CAN controller, which has a listen-only mode and a transmit mode. In listen-only mode, the CAN controller receives messages transmitted on the CAN bus and does not output any level signal to the CAN bus. In transmit mode, the CAN controller transmits messages to the CAN bus. The method further includes: During the period when the transmit pin is in the high-impedance state, the CAN controller of the target microcontroller is set to the listen-only mode; During the period when the transmit pin is in the output state, the CAN controller is set to the transmit mode; When the CAN controller is set from the transmit mode to the listen-only mode, the error count value accumulated by the CAN controller in the transmit mode is cleared.

6. The CAN communication method for the electronic speed controller according to claim 1, characterized in that, The plurality of microcontrollers includes a reference microcontroller, which is used to periodically send synchronization messages to the CAN bus via the CAN transceiver, and each of the microcontrollers is equipped with a local timer; The synchronization to the common timing reference of the multiple microcontrollers includes: When the target microcontroller receives the synchronization message, the local timer of the target microcontroller is calibrated according to the synchronization message, and the timing result of the calibrated local timer is used as the timing reference; If the duration during which the target microcontroller does not receive the synchronization message reaches a preset failure duration, the timing result of the local timer is used as the timing reference, and the preset failure duration is longer than the period during which the reference microcontroller sends the synchronization message.

7. The CAN communication method for the electronic speed controller according to claim 6, characterized in that, Each of the microcontrollers is equipped with a local clock, and the local timer of each microcontroller is driven by its own local clock. A protection interval is set between two adjacent transmission periods, and each microcontroller does not send messages to the CAN bus during the protection interval. The duration of the protection interval is not less than the maximum time deviation, which is the maximum value of the cumulative time deviation generated by each microcontroller within one cycle of the synchronization message due to the frequency difference between their respective local clocks.

8. The CAN communication method for the electronic speed controller according to claim 2, characterized in that, The method further includes: If the duration of the transmitting pin being in the output state reaches the maximum driving duration, the transmitting pin is restored to the high-impedance state, and the driving of the arbitration signal line is stopped. The maximum drive duration is not less than the longest duration required for the target microcontroller to send a single message via the CAN transceiver.

9. An electronic speed controller, comprising multiple microcontrollers and a CAN transceiver, wherein the CAN transceiver is connected between a CAN bus and the multiple microcontrollers and has a transmit input pin, and the transmit pins of each microcontroller are directly connected in parallel to the transmit input pin, characterized in that, No gating circuit is provided between each of the transmit pins and the transmit input pins for selecting one of the plurality of microcontrollers to be connected to the transmit input pin; Each of the microcontrollers includes a memory and a processing unit, the memory storing a computer program that, when executed by the processing unit, implements the method as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 8.

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