A reference voltage buffer applied to a pipelined analog-to-digital converter

Abstract

The application discloses a reference voltage buffer applied to a pipeline analog-to-digital converter, comprising a reference voltage bias stage circuit and a reference voltage output stage circuit. The reference voltage bias stage circuit comprises a first operational amplifier, a second operational amplifier and a replica resistor. The output end of the first operational amplifier outputs a negative reference voltage clamp output voltage signal; the output end of the second operational amplifier outputs a positive reference voltage clamp output voltage signal; one end of the replica resistor is connected with a positive feedback voltage, and the other end is connected with a negative feedback voltage. The reference voltage output stage circuit comprises a first PMOS tube, a first NMOS tube, a first resistor, a second PMOS tube, a second NMOS tube and a reduced overshoot capacitor network. The gate of the first PMOS tube is connected with the positive reference voltage clamp output voltage signal, and the gate of the first NMOS tube is connected with the negative reference voltage clamp output voltage signal. Through the above structure, the technical effect of improving the comprehensive performance of the reference voltage buffer in the high-speed high-precision scene is realized.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit technology, specifically relating to a reference voltage buffer applied to a pipelined analog-to-digital converter. Background Technology

[0002] With the rapid development of next-generation wireless communications (such as 5G or 6G), high-precision radar systems, medical imaging, and high-speed instrumentation, digital signal processing systems are placing higher demands on the sampling rate and resolution of the core component of the front-end data acquisition module: the analog-to-digital converter (ADC). Among various high-speed ADC architectures, the pipelined ADC has become the preferred architecture for these applications due to its ability to effectively balance ultra-high sampling rates and high conversion accuracy. In the overall architecture of a high-speed, high-precision pipelined ADC, the reference voltage buffer plays a crucial role.

[0003] Currently, reference voltage buffers are typically designed based on an open-loop source follower topology with a master-slave replication architecture. This traditional architecture is structurally divided into a reference voltage bias stage circuit and a reference voltage output stage circuit. In the bias stage, a high-gain closed-loop error amplifier is typically used to construct a deep negative feedback network, clamping the DC reference level provided by the external bandgap reference source with the voltage of the internal feedback node with high precision, generating a high-precision drive control voltage. In the output drive stage, the output stage MOSFETs are configured in a fixed ratio (e.g., 1: N The corresponding transistor in the bias stage circuit is copied.

[0004] However, the above technologies have the following problems in high-speed and high-precision application scenarios: high output impedance, large voltage overshoot, and slow voltage recovery; static replication mismatch introduces voltage error, resulting in the technical problem of low overall performance of the reference voltage buffer in high-speed and high-precision scenarios. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a reference voltage buffer for pipelined analog-to-digital converters. In a first aspect, the present invention provides a reference voltage buffer for a pipelined analog-to-digital converter, comprising: a reference voltage bias stage circuit and a reference voltage output stage circuit, wherein the current of the reference voltage output stage circuit is equal to the current of the reference voltage bias stage circuit. N times, NThe reference voltage bias stage circuit includes a first operational amplifier, a second operational amplifier, and a replication resistor. The non-inverting input of the first operational amplifier is connected to a negative reference voltage, the inverting input is connected to a negative feedback voltage, and the output of the first operational amplifier outputs a negative reference voltage clamping output voltage signal. The non-inverting input of the second operational amplifier is connected to a positive reference voltage, the inverting input is connected to a positive feedback voltage, and the output of the second operational amplifier outputs a positive reference voltage clamping output voltage signal. One end of the replication resistor is connected to the positive feedback voltage, and the other end is connected to the negative feedback voltage. The reference voltage output stage circuit includes a first PMOS transistor, a first NMOS transistor, a first resistor, a second PMOS transistor, a second NMOS transistor, and an overshoot reduction capacitor network. The gate of the first PMOS transistor is connected to the positive reference voltage clamping output voltage signal, and the source of the first PMOS transistor outputs a positive reference voltage. The output signal is achieved as follows: the drain of the first PMOS transistor is connected to one end of the first resistor; the gate of the first NMOS transistor is connected to the negative reference voltage to clamp the output voltage signal, the source of the first NMOS transistor outputs the negative reference voltage output signal, and the drain of the first NMOS transistor is connected to the other end of the first resistor; the drain of the second NMOS transistor is connected to the source of the first NMOS transistor, and the gate of the second NMOS transistor is connected to the drain of the first NMOS transistor; the source of the second PMOS transistor is connected to the positive reference voltage output signal, the drain of the second PMOS transistor is connected to the negative reference voltage output signal, and the gate of the second PMOS transistor is connected to the drain of the first NMOS transistor; the overshoot reduction capacitor network includes a first capacitor and a second capacitor; one end of the first capacitor is connected to the positive reference voltage to clamp the output voltage signal, and the other end of the first capacitor is connected to the negative reference voltage output signal; one end of the second capacitor is connected to the negative reference voltage to clamp the output voltage signal, and the other end of the second capacitor is connected to the positive reference voltage output signal.

[0006] In one embodiment of the present invention, the reference voltage bias stage circuit further includes a second resistor, a third PMOS transistor, and a third NMOS transistor; the drain of the third PMOS transistor is connected to one end of the second resistor, the gate of the third PMOS transistor is connected to the positive reference voltage clamping output voltage signal, and the source of the third PMOS transistor is connected to the positive feedback voltage; the drain of the third NMOS transistor is connected to the other end of the second resistor, the gate of the third NMOS transistor is connected to the negative reference voltage clamping output voltage signal, and the source of the third NMOS transistor is connected to the negative feedback voltage.

[0007] In one embodiment of the present invention, the reference voltage bias stage circuit further includes a fourth PMOS transistor, a fourth NMOS transistor, and a first tail current transistor; the source of the fourth PMOS transistor is connected to the power supply, the drain of the fourth PMOS transistor is connected to the source of the third PMOS transistor, and the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor; the drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor, the gate of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, and the source of the fourth NMOS transistor is connected to the drain of the first tail current transistor; the source of the first tail current transistor is connected to ground, and the gate of the first tail current transistor is connected to the tail current transistor gate bias voltage signal.

[0008] In one embodiment of the present invention, the reference voltage bias stage circuit further includes a fifth PMOS transistor and a fifth NMOS transistor; the source of the fifth PMOS transistor is connected to the positive feedback voltage, the drain of the fifth PMOS transistor is connected to the negative feedback voltage, and the gate of the fifth PMOS transistor is connected to the drain of the third NMOS transistor; the source of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor, the drain of the fifth NMOS transistor is connected to the source of the fifth PMOS transistor, and the gate of the fifth NMOS transistor is connected to the drain of the third PMOS transistor.

[0009] In one embodiment of the present invention, the bias circuit module further includes a bias current source and a sixth NMOS transistor; one end of the bias current source is connected to a power supply, and the other end of the bias current source is connected to the drain and gate of the sixth NMOS transistor; the source of the sixth NMOS transistor is connected to ground.

[0010] In one embodiment of the present invention, the reference voltage output stage circuit further includes a sixth PMOS transistor and a second tail current transistor; the source of the sixth PMOS transistor is connected to the power supply, the drain of the sixth PMOS transistor is connected to the source of the first PMOS transistor, and the gate of the sixth PMOS transistor is connected to the drain of the first PMOS transistor; the source of the second tail current transistor is connected to ground, the gate of the second tail current transistor is connected to the tail current transistor gate bias voltage signal, and the drain of the second tail current transistor is connected to the source of the second NMOS transistor.

[0011] In one embodiment of the present invention, the reference voltage output stage circuit further includes a seventh NMOS transistor; the source of the seventh NMOS transistor is connected to the drain of the second PMOS transistor, the drain of the seventh NMOS transistor is connected to the source of the second PMOS transistor, and the gate of the seventh NMOS transistor is connected to the drain of the first PMOS transistor.

[0012] Compared with the prior art, the beneficial effects of this invention are as follows: A reference voltage buffer for high-speed, high-precision pipelined ADCs is proposed, comprising a reference voltage bias stage circuit and a reference voltage output stage circuit. The reference voltage bias stage circuit includes a first operational amplifier, a second operational amplifier, and a replication resistor. The non-inverting input of the first operational amplifier is connected to a negative reference voltage, the inverting input is connected to a negative feedback voltage, and the output outputs a negative reference voltage clamping output voltage signal. The non-inverting input of the second operational amplifier is connected to a positive reference voltage, the inverting input is connected to a positive feedback voltage, and the output outputs a positive reference voltage clamping output voltage signal. One end of the replication resistor is connected to the positive feedback voltage, and the other end is connected to the negative feedback voltage. The replication resistor in the above structure can eliminate the static offset introduced by the resistive load at the reference voltage output terminal.

[0013] The reference voltage output stage circuit includes a first PMOS transistor, a first NMOS transistor, a first resistor, a second PMOS transistor, a second NMOS transistor, and an overshoot reduction capacitor network. The gate of the first PMOS transistor is connected to the positive reference voltage clamping output voltage signal, its source outputs the positive reference voltage output signal, and its drain is connected to one end of the first resistor. The gate of the first NMOS transistor is connected to the negative reference voltage clamping output voltage signal, its source outputs the negative reference voltage output signal, and its drain is connected to the other end of the first resistor. The drain of the second NMOS transistor is connected to the source of the first NMOS transistor, and its gate is connected to the drain of the first NMOS transistor. The source of the second PMOS transistor is connected to the positive reference voltage output signal, its drain is connected to the negative reference voltage output signal, and its gate is connected to the drain of the first NMOS transistor. The overshoot reduction capacitor network includes a first capacitor and a second capacitor. One end of the first capacitor is connected to the positive reference voltage clamping output voltage signal, and the other end is connected to the negative reference voltage output signal. One end of the second capacitor is connected to the negative reference voltage clamping output voltage signal, and the other end is connected to the positive reference voltage output signal. The above structure can reduce the overshoot of the reference voltage and accelerate the recovery speed of the reference voltage, thereby achieving the technical effect of improving the overall performance of the reference voltage buffer in high-speed and high-precision scenarios.

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a reference voltage buffer applied to a pipelined analog-to-digital converter provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of a reference voltage bias stage circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a reference voltage output stage circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a waveform comparison for establishing a positive reference voltage transient, provided by an embodiment of the present invention. Figure 5 This is a schematic diagram of a waveform comparison for establishing a negative reference voltage transient, provided by an embodiment of the present invention. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0017] In the overall architecture of a high-speed, high-precision pipelined ADC, the reference voltage buffer faces a complex load environment. On one hand, the core module of the pipelined ADC, the Multiplying Digital-to-Analog Converter (MDAC), internally employs a switched-capacitor network. Within each extremely short clock cycle, the high-speed switching generates a huge high-frequency transient current draw at the output of the reference voltage buffer. This requires the reference voltage buffer to have extremely low dynamic output impedance, capable of periodically providing large transient currents to the massive switched capacitors for extremely high-speed charging and discharging. On the other hand, the reference voltage buffer also needs to continuously provide a stable DC reference voltage to the resistor string network in the Flash ADC sub-section within the ADC.

[0018] Therefore, the mixed load conditions described above, which simultaneously involve large-signal transient AC load extraction (switched capacitor) and continuous DC current extraction (resistor string), pose extremely high design challenges to the reference voltage buffer. The transient settling speed, large-signal driving capability, and anti-interference capability of the reference voltage buffer directly determine the highest clock sampling rate and effective bit depth achievable by the entire ADC. If the reference voltage fails to establish up to the required target accuracy within a given time after a transient load drop, it will directly deteriorate the residual voltage transfer between stages, leading to severe nonlinear distortion and causing a sharp deterioration in the signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) of the entire ADC system.

[0019] Traditional source followers, when faced with the massive current drawn from the reference voltage buffer during sampling by a capacitive digital-to-analog converter (CDAC), suffer from a prolonged recovery time of the reference voltage (VREF) to the required accuracy due to the insufficiently low output impedance of their output stage. Simultaneously, significant voltage overshoot further prolongs this recovery time, resulting in problems such as high output impedance, large voltage overshoot, and slow voltage recovery. Furthermore, the reference resistor string at the load end of the Flash ADC draws a fixed quiescent current from the output branch, while the master bias branch lacks this drawdown path. This disrupts the ideal proportional replication relationship between the master and slave branches, leading to a significant static offset error in the output reference voltage—a phenomenon known as static replication mismatch introducing voltage error.

[0020] In summary, traditional architectures generally suffer from high output impedance, large voltage overshoot, and slow settling. Furthermore, the static offset error introduced by the resistive load at the output also affects ADC performance. Therefore, there is an urgent need to design a reference voltage buffer that combines low output impedance, fast transient settling speed, and zero static offset error.

[0021] In a first aspect, embodiments of the present invention provide a reference voltage buffer for use in a pipelined analog-to-digital converter.

[0022] Please see Figure 1 , Figure 1 This is a schematic diagram of a reference voltage buffer applied to a pipelined analog-to-digital converter according to an embodiment of the present invention. The reference voltage buffer applied to the pipelined analog-to-digital converter may include: a reference voltage bias stage circuit and a reference voltage output stage circuit.

[0023] The current in the reference voltage output stage circuit is equal to the current in the reference voltage bias stage circuit. N times, N It is a positive integer greater than 1.

[0024] Optionally, the transistor size in the reference voltage output stage circuit is also the same as the transistor size in the reference voltage bias stage circuit. N times.

[0025] In this embodiment, the reference voltage bias stage circuit includes a first operational amplifier, a second operational amplifier, and a replication resistor. The reference voltage output stage circuit includes a first PMOS transistor, a first NMOS transistor, a first resistor, a second PMOS transistor, a second NMOS transistor, and an overshoot reduction capacitor network. The gate of the first PMOS transistor is connected to the positive reference voltage clamping output voltage signal output from the output terminal of the second operational amplifier, the source outputs a positive reference voltage output signal, and the drain is connected to one end of the first resistor. The gate of the first NMOS transistor is connected to the negative reference voltage clamping output voltage signal output from the output terminal of the first operational amplifier, the source outputs a negative reference voltage output signal, and the drain is connected to the other end of the first resistor.

[0026] Figure 2 This is a schematic diagram of a reference voltage bias stage circuit provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the non-inverting input of the first operational amplifier AMP1 is connected to the negative reference voltage VREFN, the inverting input of the first operational amplifier AMP1 is connected to the negative feedback voltage VREFN_FB, and the output of the first operational amplifier AMP1 outputs the negative reference voltage clamping output voltage signal VREFN_IN.

[0027] The non-inverting input of the second operational amplifier AMP2 is connected to the positive reference voltage VREFP, the inverting input of the second operational amplifier AMP2 is connected to the positive feedback voltage VREFP_FB, and the output of the second operational amplifier AMP2 outputs the positive reference voltage clamping output voltage signal VREFP_IN.

[0028] One end of the replication resistor R2 is connected to the positive feedback voltage VREFP_FB, and the other end of the replication resistor R2 is connected to the negative feedback voltage VREFN_FB, in order to maintain the circuit replication relationship and avoid the output reference voltage deviation.

[0029] Figure 3 This is a schematic diagram of a reference voltage output stage circuit provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the gate of the first PMOS transistor MP4 is connected to the positive reference voltage clamping output voltage signal VREFP_IN, the source of the first PMOS transistor MP4 outputs the positive reference voltage output signal VREFP_OUT, and the drain of the first PMOS transistor MP4 is connected to one end of the first resistor R3.

[0030] The gate of the first NMOS transistor MN8 is connected to the negative reference voltage clamping output voltage signal VREFN_IN, the source of the first NMOS transistor MN8 outputs the negative reference voltage output signal VREFN_OUT, and the drain of the first NMOS transistor MN8 is connected to the other end of the first resistor R3.

[0031] The drain of the second NMOS transistor MN7 is connected to the source of the first NMOS transistor MN8, and the gate of the second NMOS transistor MN7 is connected to the drain of the first NMOS transistor MN8.

[0032] The source of the second PMOS transistor MP6 is connected to the positive reference voltage output signal VREFP_OUT, the drain of the second PMOS transistor MP6 is connected to the negative reference voltage output signal VREFN_OUT, and the gate of the second PMOS transistor MP6 is connected to the drain of the first NMOS transistor MN8.

[0033] The overshoot reduction capacitor network includes a first capacitor C1 and a second capacitor C2. One end of the first capacitor C1 is connected to the positive reference voltage clamping output voltage signal VREFP_IN, and the other end is connected to the negative reference voltage output signal VREFN_OUT. One end of the second capacitor C2 is connected to the negative reference voltage clamping output voltage signal VREFN_IN, and the other end is connected to the positive reference voltage output signal VREFP_OUT.

[0034] In one embodiment of the present invention, such as Figure 2 As shown, the reference voltage bias stage circuit also includes a second resistor R1, a third PMOS transistor MP1, and a third NMOS transistor MN4.

[0035] In this configuration, the drain of the third PMOS transistor MP1 is connected to one end of the second resistor R1, the gate of the third PMOS transistor MP1 is connected to the positive reference voltage clamping output voltage signal VREFP_IN, and the source of the third PMOS transistor MP1 is connected to the positive feedback voltage VREFP_FB.

[0036] The drain of the third NMOS transistor MN4 is connected to the other end of the second resistor R1, the gate of the third NMOS transistor MN4 is connected to the negative reference voltage clamping output voltage signal VREFN_IN, and the source of the third NMOS transistor MN4 is connected to the negative feedback voltage VREFN_FB.

[0037] In this embodiment, the first operational amplifier AMP1 and the third NMOS transistor MN4 clamp together to generate a negative reference voltage clamping output voltage signal VREFN_IN, which is connected to the gate of the first NMOS transistor MN8 in the reference voltage output stage circuit. The second operational amplifier AMP2 and the third PMOS transistor MP1 clamp together to generate a positive reference voltage clamping output voltage signal VREFP_IN, which is connected to the gate of the first PMOS transistor MP4 in the reference voltage output stage circuit.

[0038] In one embodiment of the present invention, such as Figure 2 As shown, the reference voltage bias stage circuit also includes a fourth PMOS transistor MP2, a fourth NMOS transistor MN3, and a first tail current transistor MN2.

[0039] In this configuration, the source of the fourth PMOS transistor MP2 is connected to the power supply VDD, the drain of the fourth PMOS transistor MP2 is connected to the source of the third PMOS transistor MP1, and the gate of the fourth PMOS transistor MP2 is connected to the drain of the third PMOS transistor MP1.

[0040] The drain of the fourth NMOS transistor MN3 is connected to the source of the third NMOS transistor MN4, the gate of the fourth NMOS transistor MN3 is connected to the drain of the third NMOS transistor MN4, and the source of the fourth NMOS transistor MN3 is connected to the drain of the first tail current transistor MN2.

[0041] The source of the first tail current transistor MN2 is connected to ground, and the gate of the first tail current transistor MN2 is connected to the tail current transistor gate bias voltage signal VBIAS.

[0042] In one embodiment of the present invention, such as Figure 2 As shown, the reference voltage bias stage circuit also includes a fifth PMOS transistor MP3 and a fifth NMOS transistor MN5.

[0043] The source of the fifth PMOS transistor MP3 is connected to the positive feedback voltage VREFP_FB, the drain of the fifth PMOS transistor MP3 is connected to the negative feedback voltage VREFN_FB, and the gate of the fifth PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN4.

[0044] The source of the fifth NMOS transistor MN5 is connected to the drain of the fifth PMOS transistor MP3, the drain of the fifth NMOS transistor MN5 is connected to the source of the fifth PMOS transistor MP3, and the gate of the fifth NMOS transistor MN5 is connected to the drain of the third PMOS transistor MP1.

[0045] It should be noted that the fourth NMOS transistor MN3, the third NMOS transistor MN4, and the fifth PMOS transistor MP3 form a flipped voltage follower (FVF) + super source follower (SSF) structure. The third PMOS transistor MP1, the fourth PMOS transistor MP2, and the fifth NMOS transistor MN5 form an FVF + SSF structure.

[0046] In one embodiment of the present invention, such as Figure 2 As shown, the bias circuit module also includes a bias current source I1 and a sixth NMOS transistor MN1.

[0047] One end of the bias current source I1 is connected to the power supply VDD, and the other end of the bias current source I1 is connected to the drain and gate of the sixth NMOS transistor MN1.

[0048] The source of the sixth NMOS transistor MN1 is connected to ground.

[0049] It should be noted that the gate of the sixth NMOS transistor MN1 is connected to the gate of the first tail current transistor MN2 to form a current mirror structure.

[0050] Because the resistor string in the Flash ADC draws static current between the positive and negative reference voltage output terminals, causing a mismatch, a replica resistor R2 of appropriate value was added between the positive feedback voltage VREFP_FB and the negative feedback voltage VREFN_FB in the reference voltage bias stage circuit. This eliminates the static offset of the reference voltage and reduces the mismatch between the reference voltage bias stage circuit and the reference voltage output stage circuit. Since the current in the reference voltage output stage circuit is a fraction of the current in the reference voltage bias stage circuit... N Therefore, the resistance of the replication resistor R2 in the reference voltage bias stage circuit is equal to the total resistance of the resistor series in the FlashADC. N times.

[0051] In one embodiment of the present invention, such as Figure 3 As shown, the reference voltage output stage circuit also includes a sixth PMOS transistor MP5 and a second tail current transistor MN6.

[0052] The source of the sixth PMOS transistor MP5 is connected to the power supply VDD, the drain of the sixth PMOS transistor MP5 is connected to the source of the first PMOS transistor MP4, and the gate of the sixth PMOS transistor MP5 is connected to the drain of the first PMOS transistor MP4.

[0053] The source of the second tail current transistor MN6 is connected to ground, the gate of the second tail current transistor MN6 is connected to the tail current transistor gate bias voltage signal VBIAS, and the drain of the second tail current transistor MN6 is connected to the source of the second NMOS transistor MN7. The second tail current transistor MN6 is the tail current source transistor.

[0054] In one embodiment of the present invention, such as Figure 3 As shown, the reference voltage output stage circuit also includes a seventh NMOS transistor MN9.

[0055] The source of the seventh NMOS transistor MN9 is connected to the drain of the second PMOS transistor MP6, the drain of the seventh NMOS transistor MN9 is connected to the source of the second PMOS transistor MP6, and the gate of the seventh NMOS transistor MN9 is connected to the drain of the first PMOS transistor MP4.

[0056] It should be noted that the second NMOS transistor MN7 and the first NMOS transistor MN8 form an FVF structure, and the first NMOS transistor MN8 and the second PMOS transistor MP6 form an SSF structure. The first NMOS transistor MN8, the second NMOS transistor MN7, and the second PMOS transistor MP6 together form an FVF+SSF structure. The output impedance of this structure is... The order of magnitude is significantly larger than that of a stage with only the first NMOS transistor MN8 as the output stage, where the output impedance is [missing information]. The aforementioned FVF+SSF structure significantly reduces output impedance and shortens the reference voltage recovery time, which is beneficial for the extremely rapid recovery of the N-terminal reference voltage. Among these features, Used to indicate the transconductance of a MOSFET. This is used to represent the output resistance of the MOSFET. Similarly, the first PMOS transistor MP4, the sixth PMOS transistor MP5, and the seventh NMOS transistor MN9 also form an FVF+SSF structure, which is beneficial for the extremely fast recovery of the P-terminal reference voltage.

[0057] This embodiment connects a first capacitor C1 between the positive reference voltage clamping output voltage signal VREFP_IN and the negative reference voltage output signal VREFN_OUT, and a second capacitor C2 between the negative reference voltage clamping output voltage signal VREFN_IN and the positive reference voltage output signal VREFP_OUT. During the instantaneous charging and discharging of the load, the capacitive path provides transient charge to complement each other, suppressing voltage overshoot, effectively reducing the voltage overshoot amplitude, and shortening the time for VREF to establish to the required accuracy.

[0058] When the ADC samples, the positive reference voltage output signal VREFP_OUT will momentarily overshoot downwards, and the negative reference voltage output signal VREFN_OUT will momentarily overshoot upwards. The downward overshoot voltage of the positive reference voltage output signal VREFP_OUT is coupled to the negative reference voltage clamp output voltage signal VREFN_IN through the second capacitor C2. However, due to the source follower effect of the first NMOS transistor MN8, the source of the first NMOS transistor MN8 (i.e., the negative reference voltage output signal VREFN_OUT) will follow the gate of the first NMOS transistor MN8 (i.e., the node of the negative reference voltage clamp output voltage signal VREFN_IN), and will tend to overshoot downwards. This tendency will offset part of the original upward overshoot of the negative reference voltage output signal VREFN_OUT. Therefore, the upward overshoot amplitude of the negative reference voltage output signal VREFN_OUT due to sampling will be reduced, which is beneficial for the N-terminal reference voltage to recover to the required voltage more quickly. The same applies to the P-terminal, which will not be elaborated here.

[0059] Combining the two methods above, the FVF+SSF structure accelerates the recovery speed, allowing the reference voltage to quickly return to the required accuracy. Adding an overshoot-reducing capacitor further accelerates this process by minimizing the overshoot amplitude of the reference voltage. The combination of these two methods enables the reference voltage to recover to the required accuracy even faster.

[0060] In summary, this invention proposes a reference voltage buffer for high-speed, high-precision pipelined ADCs. Specifically, the reference voltage output stage circuit adopts an FVF+SSF structure, with an overshoot-reducing capacitor connected between the reference voltage output terminal and the internal nodes; the reference voltage bias stage circuit includes a proportionally replicated resistor.

[0061] In this invention, the reference voltage output stage circuit adopts an FVF+SSF structure, providing extremely low output impedance, which can... The output impedance of a traditional NMOS-based output stage is on the order of magnitude. Furthermore, the low output impedance of the FVF+SSF structure in this invention greatly accelerates the reference voltage establishment speed, enabling the reference voltage fluctuating at GHz frequency to still recover to the required accuracy.

[0062] During ADC sampling, the capacitor array generates a large high-frequency transient current drawdown at the output of the reference voltage buffer, causing a significant overshoot in the reference voltage. This results in a downward overshoot at the P output and an upward overshoot at the N output. Therefore, connecting a small capacitor between the P output and the circuit nodes related to the N output can partially cancel out the overshoot at both outputs, reducing the magnitude of the voltage overshoot. Combined with the FVF+SSF structure, this further accelerates the reference voltage recovery speed. The same principle applies to the N output, and will not be elaborated further here.

[0063] When a reference voltage buffer is applied to a pipelined ADC, a resistor string is connected between the reference voltage P output terminal and the N output terminal, with a resistance value of Therefore, a resistor string is also connected between the P and N terminals in the reference voltage bias stage circuit, with a resistance value of [value missing]. .in, It is the ratio of the current in the reference voltage output stage circuit to the current in the reference voltage bias stage circuit.

[0064] Figure 4 This is a schematic diagram illustrating a waveform comparison for establishing a positive reference voltage transient, provided by an embodiment of the present invention. Figure 5 This is a schematic diagram of a negative reference voltage transient waveform comparison provided in an embodiment of the present invention, as shown below. Figure 4 and Figure 5 As shown, the horizontal axis represents time, in nanoseconds (ns), and the vertical axis represents voltage, in volts (V). From Figure 4 and Figure 5 As can be seen, compared with the traditional structure, the above-described structure of the present invention has a smaller reference voltage output overshoot and a faster recovery speed, which is more conducive to the establishment of the reference voltage for high-speed, high-precision ADCs. In other words, the reference voltage of the present invention is established to the required accuracy in a shorter time with a faster recovery speed and smaller voltage overshoot.

[0065] This embodiment discloses a reference voltage buffer for a high-speed, high-precision pipeline ADC. The reference voltage output stage circuit of the reference voltage buffer adopts an FVF+SSF structure, which greatly reduces the output impedance. It also reduces the overshoot of the output reference voltage by reducing the overshoot capacitor. The combination of the two can greatly accelerate the recovery speed of the reference voltage. The reference voltage bias stage circuit of the reference voltage adopts a resistor with equal proportional replication, which can eliminate the static offset of the reference voltage.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0067] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0068] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A reference voltage buffer for use in a pipelined analog-to-digital converter, characterized in that, include: A reference voltage bias stage circuit and a reference voltage output stage circuit are provided, wherein the current of the reference voltage output stage circuit is equal to the current of the reference voltage bias stage circuit. N times, N It is a positive integer greater than 1; The reference voltage bias stage circuit includes a first operational amplifier, a second operational amplifier, and a replication resistor; The non-inverting input of the first operational amplifier is connected to a negative reference voltage, the inverting input of the first operational amplifier is connected to a negative feedback voltage, and the output of the first operational amplifier outputs a negative reference voltage clamping output voltage signal. The non-inverting input of the second operational amplifier is connected to a positive reference voltage, the inverting input of the second operational amplifier is connected to a positive feedback voltage, and the output of the second operational amplifier outputs a positive reference voltage clamping output voltage signal. One end of the replication resistor is connected to the positive feedback voltage, and the other end of the replication resistor is connected to the negative feedback voltage; The reference voltage output stage circuit includes a first PMOS transistor, a first NMOS transistor, a first resistor, a second NMOS transistor, a second PMOS transistor, and an overshoot reduction capacitor network; The gate of the first PMOS transistor is connected to the positive reference voltage clamping output voltage signal, the source of the first PMOS transistor outputs the positive reference voltage output signal, and the drain of the first PMOS transistor is connected to one end of the first resistor. The gate of the first NMOS transistor is connected to the negative reference voltage clamping output voltage signal, the source of the first NMOS transistor outputs the negative reference voltage output signal, and the drain of the first NMOS transistor is connected to the other end of the first resistor. The drain of the second NMOS transistor is connected to the source of the first NMOS transistor, and the gate of the second NMOS transistor is connected to the drain of the first NMOS transistor. The source of the second PMOS transistor is connected to the positive reference voltage output signal, the drain of the second PMOS transistor is connected to the negative reference voltage output signal, and the gate of the second PMOS transistor is connected to the drain of the first NMOS transistor. The overshoot reduction capacitor network includes a first capacitor and a second capacitor; One end of the first capacitor is connected to the positive reference voltage clamping output voltage signal, and the other end of the first capacitor is connected to the negative reference voltage output signal; One end of the second capacitor is connected to the negative reference voltage clamping output voltage signal, and the other end of the second capacitor is connected to the positive reference voltage output signal.

2. The reference voltage buffer for a pipelined analog-to-digital converter according to claim 1, characterized in that, The reference voltage bias stage circuit also includes a second resistor, a third PMOS transistor, and a third NMOS transistor; The drain of the third PMOS transistor is connected to one end of the second resistor, the gate of the third PMOS transistor is connected to the positive reference voltage clamping output voltage signal, and the source of the third PMOS transistor is connected to the positive feedback voltage. The drain of the third NMOS transistor is connected to the other end of the second resistor, the gate of the third NMOS transistor is connected to the negative reference voltage clamping output voltage signal, and the source of the third NMOS transistor is connected to the negative feedback voltage.

3. The reference voltage buffer for a pipelined analog-to-digital converter according to claim 2, characterized in that, The reference voltage bias stage circuit also includes a fourth PMOS transistor, a fourth NMOS transistor, and a first tail current transistor; The source of the fourth PMOS transistor is connected to the power supply, the drain of the fourth PMOS transistor is connected to the source of the third PMOS transistor, and the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor. The drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor, the gate of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, and the source of the fourth NMOS transistor is connected to the drain of the first tail current transistor. The source of the first tail current transistor is connected to ground, and the gate of the first tail current transistor is connected to the tail current transistor gate bias voltage signal.

4. The reference voltage buffer for a pipelined analog-to-digital converter according to claim 2, characterized in that, The reference voltage bias stage circuit also includes a fifth PMOS transistor and a fifth NMOS transistor; The source of the fifth PMOS transistor is connected to the positive feedback voltage, the drain of the fifth PMOS transistor is connected to the negative feedback voltage, and the gate of the fifth PMOS transistor is connected to the drain of the third NMOS transistor. The source of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor, the drain of the fifth NMOS transistor is connected to the source of the fifth PMOS transistor, and the gate of the fifth NMOS transistor is connected to the drain of the third PMOS transistor.

5. The reference voltage buffer for a pipelined analog-to-digital converter according to claim 1, characterized in that, The reference voltage bias stage circuit also includes a bias current source and a sixth NMOS transistor; One end of the bias current source is connected to the power supply, and the other end of the bias current source is connected to the drain of the sixth NMOS transistor and the gate of the sixth NMOS transistor. The source of the sixth NMOS transistor is connected to ground.

6. The reference voltage buffer for a pipelined analog-to-digital converter according to claim 1, characterized in that, The reference voltage output stage circuit also includes a sixth PMOS transistor and a second tail current transistor; The source of the sixth PMOS transistor is connected to the power supply, the drain of the sixth PMOS transistor is connected to the source of the first PMOS transistor, and the gate of the sixth PMOS transistor is connected to the drain of the first PMOS transistor. The source of the second tail current transistor is connected to ground, the gate of the second tail current transistor is connected to the gate bias voltage signal of the tail current transistor, and the drain of the second tail current transistor is connected to the source of the second NMOS transistor.

7. The reference voltage buffer for a pipelined analog-to-digital converter according to claim 1, characterized in that, The reference voltage output stage circuit also includes a seventh NMOS transistor; The source of the seventh NMOS transistor is connected to the drain of the second PMOS transistor, the drain of the seventh NMOS transistor is connected to the source of the second PMOS transistor, and the gate of the seventh NMOS transistor is connected to the drain of the first PMOS transistor.

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