LDO circuit

Abstract

The specification relates to the technical field of circuit, and particularly relates to an LDO circuit. The LDO circuit comprises a main circuit, a comparison circuit and a control circuit. The main circuit comprises a power tube, which is used to provide an output voltage of the LDO circuit; the comparison circuit is used to compare the output voltage with a lower limit voltage, generate a charge adjustment signal according to a comparison result of the output voltage and the lower limit voltage, and transmit the charge adjustment signal to the control circuit; the control circuit comprises a first capacitor, a first end of the first capacitor is connected to a control end of the power tube, and a second end of the first capacitor is connected to a low-voltage end; the control circuit is used to charge adjust the first capacitor according to the charge adjustment signal, so as to increase the output voltage when the output voltage is lower than the lower limit voltage. The embodiment of the specification can improve the transient response performance of the LDO circuit, and control the drop amplitude of the output voltage of the LDO circuit.

Description

Technical Field

[0001] This specification relates to the field of circuit technology, and in particular to an LDO circuit. Background Technology

[0002] With the rapid development of electronic technology, LDO (Low Dropout Regulator) circuits have been widely used. For example, LDO circuits can be applied to power management chips to achieve voltage regulation.

[0003] To enable LDO circuits to achieve both high gain and fast transient response, LDO circuits based on the FVF (Flipped Voltage Follower) topology have been proposed. This type of FVF LDO combines a high-gain, slow loop with a lower-gain, but faster-responding, fast-response loop to achieve both high gain and fast transient response.

[0004] However, existing FVF-type LDO circuits still suffer from insufficient transient response performance under low quiescent current conditions. Summary of the Invention

[0005] This specification provides an LDO circuit to improve the transient response performance of LDO circuits.

[0006] This specification provides an LDO circuit, including a main circuit, a comparator circuit, and a control circuit. The main circuit includes a power transistor, which is used to provide the output voltage of the LDO circuit; The comparison circuit is used to compare the output voltage with the lower limit voltage, generate a charge adjustment signal based on the comparison result of the output voltage and the lower limit voltage, and transmit the charge adjustment signal to the control circuit. The control circuit includes a first capacitor, a first terminal of which is connected to the control terminal of the power transistor, and a second terminal of which is connected to the low-voltage terminal. The control circuit is used to adjust the charge of the first capacitor according to the charge adjustment signal, so as to increase the output voltage when the output voltage is lower than the lower limit voltage.

[0007] In some embodiments, the power transistor is a P-type switching transistor; the control circuit is used to transfer charge from the first capacitor according to the charge adjustment signal to reduce the control terminal voltage of the power transistor.

[0008] In some embodiments, the comparator circuit includes a comparator and an inverter circuit. The positive input terminal of the comparator circuit is connected to the lower limit voltage, the negative input terminal of the comparator circuit is connected to the output terminal of the power transistor, the output terminal of the power transistor is used to provide an output voltage, the output terminal of the comparator circuit is connected to the input terminal of the inverter circuit, and the output terminal of the inverter circuit is used to provide the charge adjustment signal.

[0009] In some embodiments, the inverter circuit includes N cascaded inverters, where N is an even number, and the charge adjustment signal includes a charge transfer signal output by the Nth inverter and a charge reset signal output by the (N-1)th inverter.

[0010] In some embodiments, the control circuit further includes a second capacitor; The charge adjustment signal includes a charge transfer signal and a charge reset signal; The control circuit is used to perform charge transfer between the first capacitor and the second capacitor according to the charge transfer signal, and to perform charge reset on the second capacitor according to the charge reset signal.

[0011] In some embodiments, the control circuit further includes a first switch and a second switch, wherein a first terminal of the first switch is connected to the control terminal of the power transistor, a second terminal of the first switch is connected to the first terminal of the second switch, and a second terminal of the second switch is connected to a low-voltage terminal; a first terminal of the second capacitor is connected to the second terminal of the first switch and the first terminal of the second switch, and a second terminal of the second capacitor is connected to a low-voltage terminal. The charge transfer signal is used to control the first switch to perform charge transfer between the first capacitor and the second capacitor, and the charge reset signal is used to control the second switch to perform charge reset on the second capacitor.

[0012] In some embodiments, the main circuit further includes a third capacitor; The first terminal of the third capacitor is connected to the control terminal of the power transistor, and the second terminal of the third capacitor is connected to the output terminal of the power transistor. The output terminal of the power transistor is used to provide the output voltage.

[0013] In some embodiments, the main circuit is an FVF type LDO circuit.

[0014] In some embodiments, the main circuit includes an operational amplifier, a buffer circuit, an FVF circuit, and a power circuit. The negative input terminal of the operational amplifier is connected to the output terminal of the FVF circuit, the positive input terminal of the operational amplifier is connected to a reference voltage, the output terminal of the operational amplifier is connected to the buffer circuit, the buffer circuit is connected to the FVF circuit and the power circuit, and the power circuit includes the power transistor.

[0015] In some embodiments, the operational amplifier includes a differential amplifier circuit, the negative input terminal of which is connected to the output terminal of the FVF circuit, the positive input terminal of which is connected to a reference voltage, and the output terminal of which is connected to the buffer circuit.

[0016] In some embodiments, the differential amplifier circuit includes a first load transistor, a second load transistor, a first compensation transistor, a second compensation transistor, a first input transistor, a second input transistor, and a bias transistor; The input terminals of the first load transistor and the second load transistor are connected to the high voltage terminal. The control terminal of the first load transistor is connected to the control terminal of the second load transistor. The output terminal of the first load transistor is connected to the input terminal of the first compensation transistor. The output terminal of the second load transistor is connected to the input terminal of the second compensation transistor. The control terminal of the first compensation transistor is connected to the control terminal of the second compensation transistor. The control terminals of the first compensation transistor and the control terminals of the second compensation transistor are connected to the bias voltage. The output terminal of the first compensation tube is connected to the input terminal of the first input tube, the output terminal of the second compensation tube is connected to the input terminal of the second input tube, the output terminals of the first input tube and the second input tube are connected to the input terminal of the bias tube, and the output terminal of the bias tube is connected to the low voltage terminal. The negative input terminal of the differential amplifier circuit is the control terminal of the first input transistor, and the positive input terminal of the differential amplifier circuit is the control terminal of the second input transistor.

[0017] The LDO circuit of this embodiment includes a main circuit, a comparator circuit, and a control circuit. The main circuit includes a power transistor (PTZ) that provides the output voltage of the LDO circuit. The comparator circuit compares the output voltage with a lower limit voltage, generates a charge adjustment signal based on the comparison result, and transmits the charge adjustment signal to the control circuit. The control circuit includes a first capacitor, with a first terminal connected to the control terminal of the PTR and a second terminal connected to a low-voltage terminal. The control circuit adjusts the charge of the first capacitor according to the charge adjustment signal to increase the output voltage when it is below the lower limit voltage. Therefore, this embodiment can quickly adjust the control terminal voltage of the PTR by the comparator circuit and the control circuit carrying the first capacitor when the output voltage is below the lower limit voltage, rapidly raising the output voltage and improving the problem of the output voltage dropping below the lower limit voltage. Furthermore, because the control terminal voltage of the PTR can be quickly adjusted, the output voltage of the LDO circuit can quickly recover to the reference voltage, thereby shortening the output voltage recovery time and improving the transient response speed of the LDO circuit under load fluctuations. In addition, the ability to quickly adjust the control terminal voltage of the power transistor reduces the quiescent current of the main circuit (e.g., the quiescent current of the power circuit in the main circuit), thereby reducing the power consumption of the LDO circuit. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. The drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a functional structure diagram of an FVF-type LDO circuit in related technologies; Figure 2 This is a functional structure diagram of the LDO circuit in the embodiments of this specification; Figure 3 This is a schematic diagram illustrating the response of an LDO circuit in related technologies and an LDO circuit in the embodiments of this specification to an I / O load.

[0020] The following are some of the figure labels: 1. Operational amplifier; 2. Source follower; 3. FVF circuit; 4. Output stage circuit; 41. Switching transistor; 42. Switching transistor; 43. Switching transistor; 44. Switching transistor; 45. Switching transistor; 21. Main circuit; 211. Operational amplifier; 212. Buffer circuit; 213. FVF circuit; 214. Power circuit; 2141. Switching transistor; 2142. Switching transistor; 2143. Switching transistor; 2144. Switching transistor; 2145. Switching transistor; 22. Comparator circuit; 221. Comparator; 222. Inverter circuit; 23. Control circuit; 231. First capacitor; 232. Second capacitor; 233. First switch; 234. Second switch. Detailed Implementation

[0021] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. The specific embodiments described herein are only used to explain this disclosure, and not to limit this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure are within the scope of protection of this disclosure. In addition, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0022] Figure 1 A functional structure diagram of the aforementioned FVF-type LDO circuit is shown. The FVF-type LDO circuit may include an operational amplifier 1, a source follower 2, an FVF circuit 3, and an output stage circuit 4. The negative input terminal VN of operational amplifier 1 is connected to the output terminal of FVF circuit 3, and the output terminal of FVF circuit 3 is used to provide the sampling voltage VOUT0. Thus, the negative input terminal VN of operational amplifier 1 is connected to the sampling voltage VOUT0. The positive input terminal VP of operational amplifier 1 is connected to a reference voltage. Operational amplifier 1 amplifies the voltage difference between the positive input terminal VP and the negative input terminal VN, outputting an error amplification voltage VAMP. The output terminal of operational amplifier 1 is connected to the input terminal of source follower 2. Source follower 2 generates and outputs a control voltage VSET based on the error amplification voltage VAMP. The output terminal of source follower 2 is connected to the input terminal of FVF circuit 3 and the input terminal of output stage circuit 4. Output stage circuit 4 provides the output voltage VOUT of the LDO circuit. Depending on the load capacity, output stage circuit 4 may include one or more FVF circuits. Figure 1 The output stage circuit 4 includes an FVF circuit. The topology of the FVF circuit in output stage circuit 4 is the same as that of FVF circuit 3. The output voltage VOUT provided by output stage circuit 4 is equal to the sampling voltage VOUT0 provided by FVF circuit 3. The capacitance value of capacitor C4 can be designed according to the actual circuit requirements, for example, it can be designed to be between several hundred pF and 1 nF. Figure 1In the diagram, VB, VB1, VB2, and VC are the bias voltages of the LDO circuit.

[0023] Depend on Figure 1 As shown in the LDO circuit, operational amplifier 1, source follower 2, and FVF circuit 3 form a main feedback loop, enabling the sampling voltage VOUT0 provided by FVF circuit 3 to follow the reference voltage. The output voltage VOUT provided by output stage circuit 4 also follows the reference voltage. Output stage circuit 4 is not within the main feedback loop. The stabilization process of output stage circuit 4 does not require passing through the main feedback loop, but only through its own local feedback loop, resulting in a faster transient response. For example, output stage circuit 4 may include switches 41, 42, 43, 44, and 45. Switches 43 and 45 are NMOS transistors. Switches 41, 42, and 44 are PMOS transistors. Switch 42 is a power transistor used to provide the output voltage VOUT. The local feedback loop may include, for example, output voltage VOUT → the potential of the VS node → the potential of the VG node → output voltage VOUT. The VS node is the connection point between the drain of switch 44 and the drain of switch 45. The VG node is the connection point between the drain of switching transistor 41, the drain of switching transistor 43, and the gate of switching transistor 42. For example, when the output voltage VOUT is pulled low by the load, the current flowing into the VS node decreases, and the potential of the VS node drops. After the potential of the VS node decreases, a positive potential difference is formed between the VG node and the VS node, causing the VG node to discharge and further lower its potential. The decrease in the potential of the VG node increases the conduction capability of switching transistor 42, and the output voltage VOUT increases.

[0024] The response speed of an LDO circuit is related to the quiescent current of output stage circuit 4. A larger quiescent current in output stage circuit 4 results in a faster response speed, while a smaller quiescent current leads to a slower response speed. In practice, to reduce static power consumption, the quiescent current of output stage circuit 4 is often designed to be relatively small. This results in a smaller charging and discharging current at the VG node, a slower potential change at the VG node, and a slower adjustment speed for the output voltage VOUT. Consequently, after the output voltage VOUT is pulled low by the load, it often takes a long time to recover, resulting in insufficient transient response performance.

[0025] Additionally, operational amplifier 1 is a cascode operational amplifier. Operational amplifier 1 may include a differential amplifier circuit and a cascode bias circuit 11. The negative input terminal VN of the differential amplifier circuit is connected to the output terminal of the FVF circuit 3, and the positive input terminal VP of the differential amplifier circuit is connected to the reference voltage. The differential amplifier circuit outputs an error amplification voltage VAMP through the cascode bias circuit 11, and the error amplification voltage VAMP is connected to the input terminal of the source follower 2. The cascode bias circuit 11 can improve the DC open-loop gain of operational amplifier 1 and reduce the steady-state voltage regulation deviation of the LDO circuit. Combined with the internal compensation capacitor Cc, the cascode bias circuit 11 can achieve better pole splitting, improve the phase margin of the main feedback loop, and thus improve the overall stability of the LDO circuit. However, the cascode bias circuit 11 introduces additional static circuitry, further increasing the power consumption of the LDO circuit.

[0026] Please see Figure 2 This specification provides an LDO (Low Dropout Regulator) circuit. The LDO circuit can provide a relatively stable output voltage VOUT. The LDO circuit is an FVF type LDO circuit. The FVF type LDO circuit includes an FVF (Flipped Voltage Follower), which is an LDO circuit based on an FVF topology. The LDO circuit may include a main circuit 21, a comparator circuit 22, and a control circuit 23. The main circuit 21 is connected to the comparator circuit 22 and the control circuit 23; the comparator circuit 22 is connected to the main circuit 21 and the control circuit 23; and the control circuit 23 is connected to the main circuit 21 and the comparator circuit 22. The main circuit 21 is used to provide the output voltage VOUT of the LDO circuit.

[0027] The main circuit 21 may include a switching transistor 2142. The switching transistor 2142 may be a power transistor, used to provide the output voltage VOUT of the LDO circuit. The comparator circuit 22 compares the output voltage VOUT with the lower limit voltage VTH, generates a charge adjustment signal based on the comparison result, and transmits the charge adjustment signal to the control circuit 23. The control circuit 23 includes a first capacitor 231. The first terminal of the first capacitor 231 is connected to the control terminal of the switching transistor 2142. The second terminal of the first capacitor 231 is connected to a low-voltage terminal, which may be ground, for example. The control circuit 23 adjusts the charge of the first capacitor 231 according to the charge adjustment signal to increase the output voltage VOUT when it is lower than the lower limit voltage VTH.

[0028] Therefore, this embodiment of the specification can quickly adjust the control terminal voltage of the switching transistor 2142 by means of the comparator circuit 22 and the control circuit 23 carrying the first capacitor 231 when the output voltage VOUT is lower than the lower limit voltage VTH, thereby rapidly increasing the output voltage VOUT and improving the problem of the output voltage VOUT falling below the lower limit voltage VTH. In addition, this embodiment of the specification can enable the output voltage VOUT of the LDO circuit to quickly recover to the reference voltage VREF, shortening the recovery time of the output voltage VOUT and improving the transient response speed of the LDO circuit under load fluctuations. Furthermore, since the control terminal voltage of the switching transistor 2142 can be quickly adjusted by means of the comparator circuit 22 and the control circuit 23 carrying the first capacitor 231, the quiescent current of the power circuit 214 can be reduced, thereby reducing the power consumption of the LDO circuit.

[0029] In some embodiments, the main circuit 21 can be an FVF-type LDO circuit. The FVF-type LDO circuit includes an FVF (Flipped Voltage Follower), which is an LDO circuit based on an FVF topology. The main circuit 21 includes an operational amplifier 211, a buffer circuit 212, an FVF circuit 213, and a power circuit 214. The negative input terminal VN of the operational amplifier 211 is connected to the output terminal of the FVF circuit 213. The output terminal of the FVF circuit 213 is used to provide a sampling voltage VOUT0. Thus, the negative input terminal VN of the operational amplifier 211 is connected to the sampling voltage VOUT0. The positive input terminal VP of the operational amplifier 211 is connected to the reference voltage VREF. The operational amplifier 211 amplifies the voltage difference between the positive input terminal VP and the negative input terminal VN, outputting an error amplified voltage VAMP; the error amplified voltage VAMP can be provided to the buffer circuit 212. The buffer circuit 212 can be, for example, a source follower. The buffer circuit 212 can be a source follower used to generate and output a control voltage VSET based on the error amplified voltage VAMP. The output of buffer circuit 212 is connected to the input of FVF circuit 213 and the input of power circuit 214. Power circuit 214 provides the output voltage VOUT of LDO circuit. Power circuit 214 can be an FVF output stage circuit. Depending on the load capacity, power circuit 214 may include one or more FVF circuits. Figure 2 The medium power circuit 214 includes an FVF circuit.

[0030] The power circuit 214 may include switching transistors 2141, 2142, 2143, 2144, and 2145. Switches 2143 and 2145 are N-type switching transistors. Switches 2141, 2142, and 2144 are P-type switching transistors. The N-type switching transistors may be, for example, N-type field-effect transistors (NMOS). The P-type switching transistors may be, for example, P-type field-effect transistors (PMOS). Switch 2142 is a power transistor used to provide the output voltage VOUT. The input terminal (e.g., source) of switch 2141 is connected to a high-voltage terminal, which may be, for example, the power supply voltage. The output terminal (e.g., drain) of switch 2141, the input terminal (e.g., drain) of switch 2143, and the control terminal (e.g., gate) of switch 2142 are connected together. The output terminal (e.g., source) of switch 2143, the input terminal (e.g., drain) of switch 2145, and the output terminal (e.g., drain) of switch 2144 are connected together. The output terminal (e.g., source) of switch 2145 is connected to a low-voltage terminal, which can be ground, for example. The input terminal (e.g., source) of switch 2142 is connected to a high-voltage terminal, which can be a power supply, for example. The output terminal (e.g., drain) of switch 2142 is connected to the input terminal (e.g., source) of switch 2144. The output terminal (e.g., drain) of switch 2142 is used to provide the output voltage VOUT. The control terminal (e.g., gate) of switch 2141 is connected to a first bias voltage VBP1. The control terminal (e.g., gate) of switch 2143 is connected to a second bias voltage VBN2. The control terminal (e.g., gate) of switch 2144 is connected to a control voltage VSET. The control terminal (e.g., gate) of switch 2145 is connected to a third bias voltage VBN1. The first bias voltage VBP1, the second bias voltage VBN2, and the third bias voltage VBN1 can be generated by a bias circuit, for example.

[0031] In the main circuit 21 described above, the operational amplifier 211, buffer circuit 212, and FVF circuit 213 form a main feedback loop, enabling the sampling voltage VOUT0 provided by the FVF circuit 213 to follow the reference voltage VREF. The output voltage VOUT of the power circuit 214 follows the sampling voltage VOUT0 provided by the FVF circuit 213, and thus also follows the reference voltage VREF. The power circuit 214 is not within the main feedback loop. The stabilization process of the power circuit 214 does not need to go through the main feedback loop, but only through its own local feedback loop, thus the transient response speed of the LDO circuit is relatively fast. The local feedback loop can include the output voltage VOUT → the potential of the VS node → the potential of the VG node → the output voltage VOUT. The VS node is the connection point between the output terminal of the switch 2144 and the input terminal of the switch 2145. The VG node is the connection point between the output terminal of the switch 2141, the input terminal of the switch 2143, and the control terminal of the switch 2142. For example, when the output voltage VOUT is pulled low by the load, the current flowing into the VS node decreases, and the potential of the VS node drops. After the potential of the VS node decreases, a positive potential difference is formed between the VG node and the VS node, causing the VG node to discharge and further lower its potential. This decrease in the potential of the VG node increases the conduction capability of the 2142 switching transistor, thus increasing the output voltage VOUT.

[0032] In some embodiments, operational amplifier 211 can be a common-source, common-gate operational amplifier. Operational amplifier 211 may include a differential amplifier circuit and a common-source, common-gate bias circuit. The negative input terminal VN of the differential amplifier circuit is connected to the output terminal of the FVF circuit 213, and the positive input terminal VP of the differential amplifier circuit is connected to the reference voltage VREF. The differential amplifier circuit outputs an error amplification voltage VAMP through the common-source, common-gate bias circuit, which is connected to the input terminal of the buffer circuit 212. The common-source, common-gate bias circuit is used to improve the DC open-loop gain of operational amplifier 211 and reduce the steady-state voltage regulation deviation of the LDO circuit. Combined with the internal compensation capacitor Cc, the common-source, common-gate bias circuit can achieve better pole splitting, improve the phase margin of the main feedback loop, and thus improve the overall stability of the LDO circuit.

[0033] In some embodiments, operational amplifier 211 may also be a non-cascode operational amplifier. Operational amplifier 211 may include a differential amplifier circuit but not a cascode bias circuit. The negative input terminal VN of the differential amplifier circuit is connected to the output terminal of FVF circuit 213. The positive input terminal VP of the differential amplifier circuit is connected to the reference voltage VREF. The output terminal of the differential amplifier circuit is connected to buffer circuit 212. The differential amplifier circuit can amplify the voltage difference between the positive input terminal VP and the negative input terminal VN, and directly output the error amplification voltage VAMP without passing through the cascode bias circuit. Since operational amplifier 211 does not include a cascode bias circuit, the power consumption of operational amplifier 211 can be reduced, and the power consumption of LDO circuit can be reduced.

[0034] exist Figure 2 In this context, operational amplifier 211 is a non-cascode operational amplifier.

[0035] The differential amplifier circuit in a non-cascode operational amplifier may include a first load transistor 2111, a second load transistor 2112, a first compensation transistor 2113, a second compensation transistor 2114, a first input transistor 2115, a second input transistor 2116, and a bias transistor 2117.

[0036] The input terminals of the first load transistor 2111 and the second load transistor 2112 are connected to the high-voltage terminal. The control terminal of the first load transistor 2111 is connected to the control terminal of the second load transistor 2112. The control terminal of the first load transistor 2111 is connected to the output terminal of the first load transistor 2111. Thus, the first load transistor 2111 is in diode connection mode. The output terminal of the first load transistor 2111 is connected to the input terminal of the first compensation transistor 2113. The output terminal of the second load transistor 2112 is connected to the input terminal of the second compensation transistor 2114. The control terminal of the first compensation transistor 2113 is connected to the control terminal of the second compensation transistor 2114. The control terminals of the first compensation transistor 2113 and the second compensation transistor 2114 are connected to the bias voltage VC. The output terminal of the first compensation transistor 2113 is connected to the input terminal of the first input transistor 2115. The output terminal of the second compensation transistor 2114 is connected to the input terminal of the second input transistor 2116. The output terminals of the first input transistor 2115 and the second input transistor 2116 are connected to the input terminal of the bias transistor 2117. The output terminal of bias transistor 2117 is connected to the low-voltage side. The control terminal of bias transistor 2117 is connected to the third bias voltage VBN1. The negative input terminal VN of the differential amplifier circuit is the control terminal of the first input transistor 2115, and thus the control terminal of the first input transistor 2115 is connected to the sampling voltage VOUT0. The positive input terminal VP of the differential amplifier circuit is the control terminal of the second input transistor 2116. Thus, the control terminal of the second input transistor 2116 is connected to the reference voltage VREF.

[0037] The first input transistor 2115 and the second input transistor 2116 can form a differential input pair. The first load transistor 2111 and the second load transistor 2112 can form a current mirror. The current mirror provides a proportional load current to the differential input pair, matching the quiescent operating points of the two branches in the differential input pair. The first compensation transistor 2113 and the second compensation transistor 2114 can form a pair of common-control compensation transistors. The differential input pair and the common-control compensation transistors together constitute a cascode structure. Thus, by adding the first compensation transistor 2113 and the second compensation transistor 2114, cascode compensation can be achieved without a cascode bias circuit, improving the equivalent output impedance of the differential amplifier circuit and enabling the differential amplifier circuit to achieve higher gain.

[0038] The first load transistor 2111, the second load transistor 2112, the first compensation transistor 2113, the second compensation transistor 2114, the first input transistor 2115, the second input transistor 2116, and the bias transistor 2117 are switching transistors. The first load transistor 2111 and the second load transistor 2112 are P-type switching transistors. The first compensation transistor 2113, the second compensation transistor 2114, the first input transistor 2115, the second input transistor 2116, and the bias transistor 2117 are N-type switching transistors. The input terminal of the P-type switching transistor is the source, the output terminal is the drain, and the control terminal is the gate. The input terminal of the N-type switching transistor is the drain, the output terminal is the source, and the control terminal is the gate.

[0039] In some embodiments, the comparator circuit 22 may include a comparator 221 and an inverter circuit 222. The positive input terminal of the comparator 221 is connected to the lower limit voltage VTH, and the negative input terminal of the comparator 221 is connected to the output terminal of the switching transistor 2142. The output terminal of the comparator 221 is connected to the input terminal of the inverter circuit 222. The inverter circuit 222 is used to provide a charge adjustment signal. The inverter circuit 222 is used to shape the waveform of the signal generated by the comparator 221 and improve the driving capability of the comparator 221. The inverter circuit 222 includes N cascaded inverters, where N is an integer and even number. The charge adjustment signal includes a charge transfer signal output by the Nth inverter and a charge reset signal output by the (N-1)th inverter. The phase difference between the charge transfer signal and the charge reset signal is set by a predetermined value. The predetermined value can be 180°. Figure 2 In this case, N=4.

[0040] Comparator 221 can be a static comparator. A static comparator does not require a clock signal and is a comparator that can operate continuously. Comparator 221 can also be other types of comparators, such as a dynamic comparator. A dynamic comparator can perform comparisons based on a clock signal.

[0041] The switching transistor 2142 can be a P-type switching transistor, such as a P-type field-effect transistor (PMOS), and its output terminal can be the drain of the switching transistor 2142. Alternatively, the switching transistor 2142 can also be an N-type switching transistor, such as an N-type field-effect transistor (NMOS), and its output terminal can be the source of the switching transistor 2142.

[0042] The comparator circuit 22 is merely an example. In practical applications, the comparator circuit 22 can also be implemented using other circuit structures. For example, the comparator circuit 22 may consist only of a comparator. Or, for instance, the comparator circuit 22 may include a comparator and an inverter. The comparator is used to output a charge transfer signal, and the inverter is used to output a charge reset signal.

[0043] In some embodiments, comparator 221 can compare the output voltage VOUT with the lower limit voltage VTH, generate a signal Q based on the comparison result, and transmit the signal Q to inverter circuit 222. Inverter circuit 222 can generate a charge adjustment signal based on signal Q. The charge adjustment signal includes a charge transfer signal and a charge reset signal.

[0044] The charge reset signal switches between a first level and a second level. The charge transfer signal also switches between a first level and a second level. When the output voltage VOUT is lower than the lower limit voltage VTH, the signal Q generated by comparator 221 is at the first level, the charge transfer signal in the charge adjustment signal is at the first level, and the charge reset signal in the charge adjustment signal is at the second level. When the output voltage VOUT is higher than the lower limit voltage VTH, the signal Q generated by comparator 221 is at the second level, the charge transfer signal in the charge adjustment signal is at the second level, and the charge reset signal in the charge adjustment signal is at the first level. The first level is an active level, which can be, for example, a high level; the second level is an inactive level, which can be, for example, a low level.

[0045] In some embodiments, the first capacitor 231 is used to adjust the control terminal voltage of the switch 2142, thereby adjusting the output voltage Vout of the switch 2142. The charge of the first capacitor 231 is positively correlated with the control terminal voltage of the switch 2142. When the first capacitor 231 stores a large amount of charge, the control terminal voltage of the switch 2142 is higher. When the first capacitor 231 stores a small amount of charge, the control terminal voltage of the switch 2142 is lower. When the charge stored in the first capacitor 231 remains constant, the control terminal voltage of the switch 2142 can remain constant. The control terminal voltage of the switch 2142 can be adjusted by adjusting the charge of the first capacitor 231.

[0046] Switch 2142 can be a P-type switch. For example, a P-type field-effect transistor (PMOS) can be used. Therefore, the control terminal voltage of switch 2142 can be negatively correlated with its output voltage VOUT. By reducing the control terminal voltage of switch 2142, the output voltage VOUT of switch 2142 can be increased. For example, control circuit 23 can transfer charge from first capacitor 231 according to a charge adjustment signal to reduce the control terminal voltage of switch 2142, thereby increasing the output voltage VOUT of switch 2142. Alternatively, control circuit 23 can maintain a constant amount of charge stored in first capacitor 231 according to the charge adjustment signal, thereby keeping the control terminal voltage of switch 2142 constant, and consequently, keeping the output voltage VOUT of switch 2142 constant.

[0047] Of course, the switching transistor 2142 can also be an N-type switching transistor. An N-type switching transistor can be an N-type field-effect transistor (NMOS). Therefore, the control terminal voltage of the switching transistor 2142 can be positively correlated with its output voltage VOUT. By increasing the control terminal voltage of the switching transistor 2142, the output voltage VOUT of the switching transistor 2142 can be increased. For example, the control circuit 23 can increase the charge of the first capacitor 231 according to the charge adjustment signal to increase the control terminal voltage of the switching transistor 2142, thereby increasing its output voltage VOUT. Alternatively, the control circuit 23 can keep the amount of charge stored in the first capacitor 231 constant according to the charge adjustment signal, thus keeping the control terminal voltage of the switching transistor 2142 constant, and consequently, keeping its output voltage VOUT constant.

[0048] In some embodiments, the control circuit 23 may further include a second capacitor 232. The second capacitor 232 is used to adjust the charge of the first capacitor 231. The control circuit 23 can perform charge transfer between the first capacitor 231 and the second capacitor 232 according to a charge transfer signal; and can perform charge reset on the second capacitor 232 according to a charge reset signal. Thus, the amount of charge in the first capacitor 231 can be adjusted by the second capacitor 232, thereby adjusting the voltage at the control terminal of the switching transistor 2142, and further adjusting the output voltage VOUT.

[0049] The control circuit 23 can be a switched capacitor circuit. The control circuit may also include a first switch 233 and a second switch 234. The first terminal of the first switch 233 is connected to the control terminal of the switching transistor 2142. The second terminal of the first switch 233 is connected to the first terminal of the second switch 234. The second terminal of the second switch 234 is connected to the low-voltage terminal. The first terminal of the second capacitor 232 is connected to the second terminal of both the first switch 233 and the first terminal of the second switch 234. The second terminal of the second capacitor 232 is connected to the low-voltage terminal.

[0050] The first switch 233 and the second switch 234 can simulate switches. The simulated switches can be controlled to close and open.

[0051] A charge transfer signal is used to control a first switch 233 to perform a charge transfer between a first capacitor 231 and a second capacitor 232. A charge reset signal is used to control a second switch 234 to perform a charge reset on the second capacitor 232.

[0052] In some embodiments, the switching transistor 2142 can be a P-type switching transistor. When the output voltage VOUT is lower than the lower limit voltage VTH, the charge transfer signal is at a first level, the first switch 233 is closed, and the charge reset signal is at a second level, the second switch 234 is open. Thus, the first terminal of the first capacitor 231 and the first terminal of the second capacitor 232 are both connected to the control terminal of the switching transistor 2142, and the second terminals of both capacitors 231 and 232 are both connected to the low-voltage terminal. The first capacitor 231 and the second capacitor 232 are connected in parallel, causing charge to transfer from the first capacitor 231 to the second capacitor 232. The control terminal voltage of the switching transistor 2142 decreases, and the output voltage VOUT of the switching transistor 2142 increases. When the output voltage VOUT is higher than the lower limit voltage VTH, the charge transfer signal is at the second level, the first switch 233 is open, and the charge reset signal is at the first level, the second switch 234 is closed. Thus, the first terminal of the first capacitor 231 is connected to the control terminal of the switching transistor 2142, and the second terminal of the first capacitor 231 is connected to the low-voltage terminal. The voltage across the first capacitor 231 remains constant, as does the voltage at the control terminal of the switching transistor 2142. Furthermore, both the first and second terminals of the second capacitor 232 are connected to a low-voltage terminal. The second capacitor 232 performs a charge reset, reducing the amount of charge on it.

[0053] In some embodiments, an output voltage Vout being lower than the lower limit voltage VTH can mean that the output voltage Vout is less than the lower limit voltage VTH, or that the output voltage Vout is less than or equal to the lower limit voltage VTH. An output voltage Vout being higher than the lower limit voltage VTH can mean that the output voltage Vout is greater than the lower limit voltage VTH, or that the output voltage Vout is greater than or equal to the lower limit voltage VTH. The magnitudes of the lower limit voltage VTH and the reference voltage VREF can be preset. The lower limit voltage VTH can be less than the reference voltage VREF. For example, the lower limit voltage VTH can be 1.18V, and the reference voltage VREF can be 1.22V. The LDO circuit can stabilize the output voltage VOUT near the reference voltage VREF and improve the problem of the output voltage VOUT falling below the lower limit voltage VTH.

[0054] The difference between the lower limit voltage VTH and the reference voltage VREF can be understood as the voltage sag of the LDO circuit. By setting the relationship between the lower limit voltage VTH and the reference voltage VREF, the allowable voltage sag of the LDO circuit can be configured.

[0055] In some embodiments, the capacitance values ​​of the first capacitor 231 and the second capacitor 232 are related to the response speed of the LDO circuit. By adjusting the capacitance values ​​of the first capacitor 231 and the second capacitor 232, the response speed of the LDO circuit can be adjusted, thereby adjusting the response speed of the output voltage VOUT. For example, the capacitance values ​​of the first capacitor 231 and the second capacitor 232 are negatively correlated with the response speed of the LDO circuit.

[0056] In some embodiments, the topology of the FVF circuit in power circuit 214 can be the same as that of FVF circuit 213. Alternatively, the topology of the FVF circuit in power circuit 214 can be different from that of FVF circuit 213. For example, the FVF circuit in power circuit 214 may also include a third capacitor C2. The first end of the third capacitor C2 is connected to the control terminal of the switching transistor 2142, and the second end of the third capacitor C2 is connected to the output terminal of the switching transistor 2142. The output terminal of the switching transistor 2142 is used to provide the output voltage VOUT. Thus, by coupling the third capacitor C2 between the control terminal and the output terminal of the switching transistor 2142, the third capacitor C2 provides a capacitive coupling path between the control terminal and the output terminal of the switching transistor 2142. In this way, changes in the output voltage VOUT can be transmitted to the control terminal of the switching transistor 2142, causing a change in the control terminal voltage of the switching transistor 2142, thereby improving the transient response speed of the LDO circuit. For example, the switching transistor 2142 can be a P-type switching transistor. When the output voltage VOUT is pulled down by the load, the control terminal voltage of the switching transistor 2142 also decreases, causing the output voltage VOUT to increase.

[0057] In some embodiments, the LDO circuit may further include a fourth capacitor C4.

[0058] The first terminal of the fourth capacitor C4 is connected to the output terminal of the 2142 switching transistor, and the second terminal of the fourth capacitor C4 is connected to the low-voltage terminal. The fourth capacitor C4 can be an external capacitor used to provide transient current to the load and reduce the ripple of the LDO's output voltage Vout.

[0059] In some embodiments, the load of the LDO circuit may include a capacitive load and / or a resistive load.

[0060] exist Figure 2 In this diagram, VBP1, VBP2, VBN1, VBN2, and VC are the bias voltages of the LDO circuit. The bias voltages can be generated by the bias circuit.

[0061] In some embodiments, Figure 3 This diagram illustrates the response of an LDO circuit in related technologies and the LDO circuit in the embodiments of this specification to a pulsed load. The pulsed load can be an I / O load, such as a chip pin, a passive crystal oscillator, or an LED indicator. The I / O load generates a periodic pulsed current during high-speed switching. The period of the pulsed current is T.

[0062] In related technologies, LDO circuits often require a long time (much longer than the period T) for their output voltage VOUT to recover to the reference voltage VREF after being pulled low by the load. Due to this slow recovery, when the next pulse cycle arrives, VOUT has not yet risen back to the reference voltage VREF, and the new pulse cycle will further pull VOUT down. This cycle repeats, causing VOUT to decrease periodically in a stepped manner. Eventually, VOUT will stabilize at a low voltage value far below the reference voltage VREF, which may lead to abnormal operation of the I / O load.

[0063] Unlike LDO circuits in related technologies, the LDO circuit in this embodiment closes the first switch 233 and opens the second switch 234 when the output voltage VOUT is pulled down by the load and falls below the lower limit voltage VTH. The first capacitor 231 and the second capacitor 232 are connected in parallel, utilizing charge transfer to quickly pull down the control terminal voltage of the switching transistor 2142, causing the output voltage VOUT to rise rapidly. The output voltage VOUT can recover within a single pulse cycle T, effectively avoiding the problem of the output voltage VOUT dropping cycle by cycle. Furthermore, the quiescent current of the power circuit 214 is reduced, thereby further reducing the overall power consumption of the LDO circuit.

[0064] The functional units in the embodiments of this specification can be integrated into one processing unit, or each functional unit can exist physically separately, or two or more functional units can be integrated into one processing unit.

[0065] Those skilled in the art will understand that the descriptions of the various embodiments in this specification have different focuses, and parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, it is understood that those skilled in the art, after reading this specification, can conceive of any combination of some or all of the embodiments listed in this specification without creative effort, and such combinations are also within the scope of disclosure and protection of this specification.

[0066] Although this specification has been described through embodiments, those skilled in the art will understand that the above embodiments are merely illustrative of the core ideas of this specification. Those skilled in the art will appreciate that many variations and modifications are possible with this specification. It is intended that the appended claims encompass these variations and modifications without departing from the spirit of this specification.

Claims

1. An LDO circuit, characterized in that, It includes the main circuit, the comparator circuit, and the control circuit; The main circuit includes a power transistor, which is used to provide the output voltage of the LDO circuit; The comparison circuit is used to compare the output voltage with the lower limit voltage, generate a charge adjustment signal based on the comparison result of the output voltage and the lower limit voltage, and transmit the charge adjustment signal to the control circuit. The control circuit includes a first capacitor, a first terminal of which is connected to the control terminal of the power transistor, and a second terminal of which is connected to the low-voltage terminal. The control circuit is used to adjust the charge of the first capacitor according to the charge adjustment signal, so as to increase the output voltage when the output voltage is lower than the lower limit voltage.

2. The LDO circuit according to claim 1, characterized in that, The power transistor is a P-type switching transistor; the control circuit is used to transfer charge from the first capacitor according to the charge adjustment signal to adjust the control terminal voltage of the power transistor.

3. The LDO circuit according to claim 1, characterized in that, The comparison circuit includes a comparator and an inverter circuit. The positive input terminal of the comparator is connected to the lower limit voltage, and the negative input terminal of the comparator is connected to the output terminal of the power transistor. The output terminal of the power transistor is used to provide the output voltage. The output terminal of the comparator is connected to the input terminal of the inverter circuit, and the output terminal of the inverter circuit is used to provide the charge adjustment signal.

4. The LDO circuit according to claim 3, characterized in that, The inverter circuit includes N cascaded inverters, where N is an even number. The charge adjustment signal includes the charge transfer signal output by the Nth inverter and the charge reset signal output by the (N-1)th inverter.

5. The LDO circuit according to claim 1, characterized in that, The control circuit also includes a second capacitor; The charge adjustment signal includes a charge transfer signal and a charge reset signal; The control circuit is used to perform charge transfer between the first capacitor and the second capacitor according to the charge transfer signal, and to perform charge reset on the second capacitor according to the charge reset signal.

6. The LDO circuit according to claim 5, characterized in that, The control circuit further includes a first switch and a second switch. The first end of the first switch is connected to the control terminal of the power transistor, the second end of the first switch is connected to the first end of the second switch, and the second end of the second switch is connected to the low-voltage terminal. The first end of the second capacitor is connected to the second end of the first switch and the first end of the second switch, and the second end of the second capacitor is connected to the low-voltage terminal. The charge transfer signal is used to control the first switch to perform charge transfer between the first capacitor and the second capacitor, and the charge reset signal is used to control the second switch to perform charge reset on the second capacitor.

7. The LDO circuit according to claim 1, characterized in that, The main circuit also includes a third capacitor; The first terminal of the third capacitor is connected to the control terminal of the power transistor, and the second terminal of the third capacitor is connected to the output terminal of the power transistor. The output terminal of the power transistor is used to provide the output voltage.

8. The LDO circuit according to claim 1, characterized in that, The main circuit is an FVF type LDO circuit.

9. The LDO circuit according to claim 1 or 8, characterized in that, The main circuit includes an operational amplifier, a buffer circuit, an FVF circuit, and a power circuit. The negative input terminal of the operational amplifier is connected to the output terminal of the FVF circuit, the positive input terminal of the operational amplifier is connected to a reference voltage, the output terminal of the operational amplifier is connected to the buffer circuit, the buffer circuit is connected to the FVF circuit and the power circuit, and the power circuit includes the power transistor.

10. The LDO circuit according to claim 9, characterized in that, The operational amplifier includes a differential amplifier circuit, the negative input terminal of which is connected to the output terminal of the FVF circuit, the positive input terminal of which is connected to a reference voltage, and the output terminal of which is connected to the buffer circuit.

11. The LDO circuit according to claim 10, characterized in that, The differential amplifier circuit includes a first load transistor, a second load transistor, a first compensation transistor, a second compensation transistor, a first input transistor, a second input transistor, and a bias transistor; The input terminals of the first load transistor and the second load transistor are connected to the high voltage terminal. The control terminal of the first load transistor is connected to the control terminal of the second load transistor. The output terminal of the first load transistor is connected to the input terminal of the first compensation transistor. The output terminal of the second load transistor is connected to the input terminal of the second compensation transistor. The control terminal of the first compensation transistor is connected to the control terminal of the second compensation transistor. The control terminals of the first compensation transistor and the control terminals of the second compensation transistor are connected to the bias voltage. The output terminal of the first compensation tube is connected to the input terminal of the first input tube, the output terminal of the second compensation tube is connected to the input terminal of the second input tube, the output terminals of the first input tube and the second input tube are connected to the input terminal of the bias tube, and the output terminal of the bias tube is connected to the low voltage terminal. The negative input terminal of the differential amplifier circuit is the control terminal of the first input transistor, and the positive input terminal of the differential amplifier circuit is the control terminal of the second input transistor.

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