A digitally assisted analog LDO circuit

Abstract

The application discloses a kind of digital auxiliary analog LDO circuit, belong to power management analog integrated circuit technical field, including band gap reference module, parallelly arranged analog voltage regulation loop and digital auxiliary loop, binary weighting power tube array, feedback voltage division network, band gap reference provides multiple reference voltage and bias current, analog loop sets independent auxiliary power tube fast passage, responsible for steady-state high-precision linear fine adjustment, digital loop adopts three-way dynamic comparator to demarcate output voltage dead zone, steady-state latching control code word reduces digital dynamic power consumption.The application fuses the advantages of low ripple, high power suppression of analog loop and the advantages of transient high-speed regulation of digital loop, simplifies the complex architecture of traditional multi-loop hybrid LDO, the system stability is high, without large capacity compensation capacitor outside the chip, with fast transient response, low static power consumption, high output voltage precision characteristics, suitable for internet of things, portable low-power chip power supply scene.

Description

Technical Field

[0001] This invention belongs to the field of power management analog integrated circuit technology, specifically relating to a digital-assisted analog LDO circuit, which is particularly suitable for power supply scenarios that require high transient response speed, output voltage accuracy, and low static power consumption, such as IoT terminals, portable electronic devices, and low-power on-chip systems. Background Technology

[0002] With the rapid development of portable electronic devices and IoT terminals, electronic systems are placing increasingly higher demands on high-performance, low-power, and highly integrated power management solutions. The performance of power management chips directly determines the system's efficiency and battery life. Low-dropout linear regulators (LDOs), due to their simple structure, small size, high integration, low noise, fast response, and low electromagnetic interference, have become key units for achieving fine power management in on-chip systems and are widely used in various miniaturized electronic devices. Existing LDOs are divided into two categories: purely analog LDOs and purely digital LDOs (DLDOs), both of which have inherent performance limitations. Traditional analog LDOs consist of a bandgap reference, an error amplifier, a feedback resistor, a main power transistor, and a compensation capacitor forming a continuous negative feedback loop. To ensure loop stability and improve transient response performance, large-capacity on-chip / off-chip compensation capacitors must be configured, which is not conducive to full chip integration. Under advanced low-voltage processes, the design difficulty of error amplifier gain and bandwidth increases significantly. When the load current changes rapidly, the loop bandwidth is limited, resulting in large output voltage overshoot / undershoot amplitudes, long voltage recovery times, and poor transient response performance. The process portability is weak, and the amplifier and compensation network need to be completely redesigned after changing the manufacturing process.

[0003] Digital LDOs rely on clock-driven digital logic and binary power transistor arrays to achieve discrete step voltage regulation. They require no compensation circuits, have fast transient adjustment speeds, and are easy to port to other technologies. However, they have significant drawbacks: discrete switching control introduces fixed quantization ripple and limit cycle oscillations, resulting in insufficient output voltage accuracy; high-frequency power supply rejection performance is poor, and noise levels are high; the clock and comparator operate continuously throughout the entire process, leading to relatively high static power consumption under light loads; and the overall area of ​​the power transistor array is larger than that of analog LDOs of the same specifications.

[0004] The following problems still exist with existing technologies: Existing hybrid synchronous-asynchronous digital LDOs employ multi-loop, multi-group shift register hierarchical control, and improve transient undershoot through multi-level auxiliary loops. However, the system loop architecture is complex, and the collaborative control of multiple logic controllers increases the difficulty of circuit analysis. Multi-loop coupling can easily lead to system stability risks, and the hardware logic resources are consumed in large quantities with limited room for static power consumption optimization.

[0005] Current low-power portable chips and IoT SoCs simultaneously present three hard requirements: no external large-capacity capacitors, fast transient recovery from load jumps, and low steady-state output ripple and low static power consumption. Single analog or digital architectures and traditional multi-loop mixed-signal architectures cannot meet these requirements at the same time. Summary of the Invention

[0006] This invention addresses the shortcomings of existing pure analog LDOs, such as slow transient response and complex compensation circuits; pure digital LDOs, such as large quantization ripple and low steady-state accuracy; and traditional multi-loop hybrid DLDO architectures, such as complex architectures and poor stability. It provides a digital-assisted analog LDO circuit that combines the advantages of high steady-state accuracy and low ripple of analog loops with the advantages of fast transient coarse adjustment of digital loops. This simplifies the overall circuit architecture and achieves fast transient response, extremely low output ripple, low static power consumption, and high system stability without the need for large external capacitors.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: In a first aspect, the present invention provides a digital-assisted analog LDO circuit, comprising a bandgap reference module, an analog voltage regulator loop, a digital auxiliary loop, a power transistor array, and a feedback voltage divider network; The bandgap reference module outputs a reference voltage VREF and a preset reference voltage VREF0 to the analog voltage regulation loop and the digital auxiliary loop, respectively, and outputs multiple bias currents. The analog voltage regulator loop and the digital auxiliary loop are connected in parallel to the output terminal VOUT of the power transistor array. The analog voltage regulator loop regulates the auxiliary power transistor M1 and the analog main power transistor M2, while the digital auxiliary loop regulates the output current of the power transistor array. The feedback voltage divider network is connected to VOUT at one end and grounded at the other end, and the voltage divider node feeds back the voltage divider voltage to the analog voltage regulator loop; The analog voltage regulation loop includes an error amplifier EA, a buffer, an auxiliary voltage comparator CMP, an auxiliary power transistor M1, and an analog main power transistor M2. The digital auxiliary loop includes three dynamic voltage comparators COMP1, COMP2, and COMP3, a digital logic controller, and a multi-channel inverting buffer.

[0008] Preferably, the error amplifier adopts a common source cascode structure, rather than a simple five-transistor operational amplifier. The non-inverting input is connected to VREF, the inverting input is connected to the feedback voltage divider, the output of the error amplifier is connected to the buffer input, the output of the buffer drives the gate of the analog main power transistor M2, and an on-chip compensation capacitor C1 is connected in parallel between the error amplifier and the buffer. The non-inverting input of the auxiliary voltage comparator CMP is connected to VREF0, and the inverting input is connected to VOUT. The comparator output drives the gate of the auxiliary power transistor M1. The sources of the auxiliary power transistor M1 and the analog main power transistor M2 are connected to the power supply VDD, and their drains are connected to VOUT.

[0009] Preferably, COMP1 outputs a lower limit detection signal VOL, COMP2 outputs an upper limit detection signal VOH, and VOL and VOH are connected to a digital logic controller to define the output voltage dead zone range; COMP3 outputs a COUT signal to provide feedback on the high / low relationship between VOUT and VREF0; The digital logic controller has a built-in 6-bit successive approximation binary search control logic. The input signals include VOL, VOH, COUT, system clock CLK, and reset signal RST_N. The output is a 6-bit control codeword. Each control codeword drives the gate of a single power transistor in the power transistor array through an inverting buffer.

[0010] Preferably, the power transistor array is a 6-channel binary weighted PMOS transistor array, with all PMOS sources connected to VDD and drains connected in parallel to output VOUT; the 6 PMOS transistors have the same channel length and a conduction width ratio of 1:2:4:8:16:32; the PMOS transistors are turned on at low level and the on / off state is controlled by the output level of the inverting buffer.

[0011] Preferably, the bandgap reference module is a PTAT bandgap reference circuit of a multi-stage common-source cascode current mirror coupled differential amplifier, which outputs two reference signals VREF and VREF0, and simultaneously outputs independent bias currents IB_EA and IB_CMP to the error amplifier, three dynamic voltage comparators, and auxiliary voltage comparator, respectively.

[0012] Preferably, the feedback voltage divider network is composed of series resistors R0 and R1, with the upper end of R0 connected to VOUT and the lower end of R1 grounded. The feedback voltage output from the voltage divider node between R0 and R1 is connected to the inverting input terminal of the error amplifier.

[0013] Preferably, the working logic of the digital logic controller is as follows: after reset, all control codewords are cleared to zero, the analog loop enable is turned off, VOL and VOH are continuously monitored on the rising edge of the clock, and when VOUT jumps out of the dead zone range, the binary search method is started for coarse adjustment, the optimal conduction codeword is obtained by traversing the 6-bit binary weights, the analog loop enable is pulled high after the coarse adjustment is completed, the digital loop latch control codeword stops dynamic adjustment, and the analog loop steady-state fine adjustment mode is switched.

[0014] Secondly, based on the first aspect above, the present invention also provides a digitally assisted fast transient response simulation LDO design method, comprising the following steps: S1. Building a reference generation unit: A multi-stage PTAT bandgap reference circuit with cascode current mirror coupling differential amplification is used to generate a steady-state reference voltage VREF and an output target reference voltage VREF0, and to output independent bias currents IB_EA and IB_CMP to supply the active devices of the analog loop and digital loop respectively. S2. Construct a parallel dual-control loop architecture, wherein the parallel dual-control loop includes an analog voltage regulation loop and a digital auxiliary loop, which are connected in parallel to the output terminal VOUT, and together with a binary weighted power transistor array and a feedback voltage divider network, constitute the complete LDO body; S3, Analog Loop Steady-State Fine-Tuning Control: The difference between the VOUT voltage divider feedback voltage and VREF is acquired by the Cascode structure error amplifier, and the analog main power transistor M2 is driven by the buffer to achieve continuous linear voltage regulation; an independent voltage comparator CMP is added at the same time to form an instantaneous current auxiliary path with the auxiliary power transistor M1, and the output current is supplemented synchronously when the load changes transiently; only the analog loop works continuously in the steady-state range to eliminate discrete quantization error; S4. Digital loop dead-zone triggered binary search coarse adjustment control: Three dynamic voltage comparators are set to generate the output voltage dead zone interval [VREFL,VREFH]. Only when VOUT exceeds the dead zone threshold, the digital logic controller triggers the successive approximation binary search method to quickly solve the optimal conduction control codeword by traversing the weight bits of the binary power transistor array. After coarse adjustment, the digital control codeword is latched, the digital dynamic toggle behavior is turned off, and the analog loop is enabled to complete fine voltage regulation independently. S5. Power transistor coordinated voltage regulation control: During the transient load transition phase, the digital loop outputs control codewords to drive the binary PMOS power transistor array to provide a large-span coarse adjustment current; during the steady-state phase, the digital array maintains a fixed on state, and the auxiliary power transistor M1 and the analog main power transistor M2 in the analog loop provide a continuously adjustable micro current. The two work together to achieve high-precision voltage regulation over a wide load range.

[0015] Due to the adoption of the above technical solution, the technical progress achieved by this invention compared to the prior art is as follows: 1. This invention abandons the traditional multi-group shift register and multi-auxiliary loop superposition architecture, and only sets up two control paths: a single analog loop and a single digital auxiliary loop. The circuit topology is simple, the loop coupling interference is less, the circuit simulation and debugging after tape-out are less difficult, and the risk of multi-loop coupling oscillation is avoided.

[0016] 2. The digital loop of this invention uses a 6-bit binary power transistor array with a successive approximation binary search method. When the load jump exceeds the dead zone, only 6 clock cycles are needed to complete the coarse adjustment. The analog loop adds an independent auxiliary power transistor fast path, and the digital and analog paths synchronously and instantaneously supplement the output current, significantly reducing the overshoot and undershoot of the output voltage. Fast transient recovery can be achieved without external large-capacity compensation capacitors.

[0017] 3. After the transient coarse adjustment is completed, the digital loop latch control code stops the switching action, eliminating digital quantization ripple; the analog loop continuously and linearly fine-tunes the output voltage, inheriting the advantages of high power supply rejection and low noise of analog LDOs, and the steady-state output has no limit loop oscillation, with voltage accuracy far superior to pure digital LDOs.

[0018] 4. During the steady-state operation phase of this invention, the digital loop only has static latching and no dynamic clock flipping power consumption, and only the analog loop operates continuously at low power. The error amplifier adopts a low-power Cascode operational amplifier structure, and the multi-stage common source and common gate structure of the bandgap reference reduces bias current consumption. The overall light-load static current is much lower than that of traditional DLDO solutions. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the overall architecture of an embodiment of the present invention; Figure 2 This is a schematic diagram of the independent structure of the simulated voltage regulator loop in an embodiment of the present invention; Figure 3 This is a circuit of a bandgap reference module according to an embodiment of the present invention; Figure 4 This is a flowchart of the state transition process of the digital logic controller using the binary search method according to an embodiment of the present invention. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to embodiments: Example 1 like Figure 1 As shown, this invention provides a digital-assisted analog LDO circuit, comprising a bandgap reference module (Bandgap), an analog voltage regulation loop (EA, Buffer, CMP, auxiliary power transistor M1, analog main power transistor M2, compensation capacitor C1), a digital auxiliary loop (COMP1, COMP2, COMP3, digital logic controller, inverting buffer (...)...) Figure 1 The device located between the power transistor array and the digital logic controller includes a 6-bit binary PMOS power transistor array, feedback voltage divider resistors R0=25kΩ and R1=100kΩ.

[0021] The bandgap reference simultaneously outputs VREF, VREF0, bias current IB_EA, IB_CMP, and bias voltage VBP; the analog loop and digital auxiliary loop are connected in parallel to the VOUT node, and the feedback voltage divider network collects the VOUT voltage and sends it to the error amplifier to form analog negative feedback.

[0022] The system clock CLK frequency is configured to 50MHz, and the voltage dead zone threshold Δ is set to 20mV, i.e., VREFH=VREF0+20mV, VREFL=VREF0-20mV; the digital loop starts coarse adjustment only when VOUT deviates from the target voltage by more than 20mV, and only the analog loop works when the voltage fluctuation is less than 20mV.

[0023] Example 2 like Figure 2 As shown, based on Embodiment 1, the present invention provides a technical solution: the preferred error amplifier adopts a two-stage Cascode five-transistor OTA (comprising five transistors, commonly used in low-power, high-linearity analog circuits), with an open-loop gain ≥80dB, improving the low-frequency power supply rejection ratio; the auxiliary voltage comparator CMP independently monitors VOUT and VREF0, and drives the auxiliary power transistor M1 to conduct when the load suddenly drops, instantaneously injecting a large current into VOUT to compensate for the response delay caused by insufficient bandwidth of the analog main loop; the compensation capacitor C1 is only an on-chip miniature capacitor, which can ensure the stability of the analog loop without the need for an external large-capacity load capacitor.

[0024] In steady state, the auxiliary comparator outputs a constant level, the auxiliary power transistor M1 provides only a small amount of static fine-tuning current, the analog main power transistor M2 serves as the main current output transistor, and the output DC error is eliminated by relying on the closed loop of the error amplifier.

[0025] Example 3 like Figure 3 As shown, based on Embodiments 1 and 2, the present invention provides a technical solution: Preferably, the bandgap reference adopts a multi-stage common-source cascode current mirror coupled differential amplifier architecture, with a built-in PTAT current (wherein, PTAT current is a current source that increases linearly with absolute temperature, widely used in temperature compensation and bandgap reference circuits, providing stable bias in operational amplifiers or bandgap reference circuits, ensuring that circuit performance is not affected by temperature) generation branch, with a temperature coefficient ≤10ppm / ℃; multiple independent bias outputs are respectively supplied to analog operational amplifiers, analog comparators, and three digital dynamic comparators, and the bias currents of each channel do not interfere with each other, ensuring that the voltage and current references of the entire module are unified, reducing the output error caused by reference mismatch between modules.

[0026] Example 4 like Figure 4 As shown, based on Embodiments 1, 2, and 3, the present invention provides a technical solution: Preferably, the power-on reset signal RST_N is active low, and after reset, the 6-bit control code C<5:0>=000000, all power transistors are turned off, ALDO_EN=0, and the analog loop is temporarily closed; At each rising edge of CLK, the VOL and VOH signals are sampled. If VOL=1 or VOH=1, it is determined that VOUT has exited the dead zone, and the binary search method is started. 1) The temporary register temp is initialized to 000000, and the current operation bit is set to 5 (the highest weight bit); 2) Set temp[bit] to 1 and output it to the power transistor array, then wait for half a clock cycle for the VOUT voltage to stabilize; 3) Read COMP3 output COUT: COUT=1 means VOUT>VREF0, the current number of weighted transistors is too many, so temp[bit] is cleared to zero; COUT=0 means VOUT<VREF0, so temp[bit]=1 is retained; 4) Decrement the bit by 1, repeat steps 2-3 until the bit < 0, thus completing the solution for the optimal 6-bit binary codeword; 5) Assign temp to the output control codeword C<5:0>, pull ALDO_EN=1 high, the digital loop stops dynamic search, only latches the current codeword, and the analog loop continues to finely adjust; The digital coarse adjustment process is triggered again only when a change in the VOL or VOH level is detected again.

[0027] Example 5 This embodiment provides power transistor array drive logic: the width ratio of the 6 PMOS power transistors is 1:2:4:8:16:32, and the minimum transistor width of a single channel is set according to the 40nm standard CMOS process; the high level of the digital logic output is converted to a low level by an inverter, corresponding to the PMOS transistor being turned on; the low level of the output is converted to a high level by an inverter, corresponding to the PMOS transistor being turned off. When there is a high current demand from a transient load, the binary division method quickly turns on the multi-weighted power transistors, providing coarse adjustment current for a short time; in steady state, only the auxiliary power transistor M1 and the analog main power transistor M2 provide continuously adjustable current, and the digital array only maintains a fixed on state, with no switching power consumption.

[0028] Example 6 This embodiment provides a digitally assisted fast transient response analog LDO design method, applied to the digitally assisted analog LDO circuits as shown in Embodiments 1 to 5, including the following steps: S1. Building a reference generation unit: A multi-stage PTAT bandgap reference circuit with cascode current mirror coupling differential amplification is used to generate a steady-state reference voltage VREF and an output target reference voltage VREF0, and to output independent bias currents IB_EA and IB_CMP to supply the active devices of the analog loop and digital loop respectively. Specifically, this step involves building a multi-level common-source cascode PTAT bandgap reference generation unit to uniformly output two reference voltages: steady-state fine-tuning reference VREF and output target voltage VREF0; at the same time, it generates multiple mutually isolated constant bias currents IB_EA and IB_CMP, which are respectively supplied to the error amplifier of the analog loop, the auxiliary comparator, and the three dynamic comparators of the digital loop, ensuring the uniformity of the reference for the entire circuit and reducing device mismatch errors.

[0029] S2. Construct a parallel dual-control loop architecture. The parallel dual-control loop includes an analog voltage regulation loop and a digital auxiliary loop. The two are connected in parallel to the output terminal VOUT. Combined with a binary weighted power transistor array and a feedback voltage divider network, it forms the complete LDO body. Specifically, this step establishes a parallel dual-loop collaborative control architecture, consisting of an analog voltage regulation loop and a digital auxiliary loop connected in parallel to the output node VOUT. Together with a 6-bit binary weighted PMOS power transistor array and a resistor voltage divider feedback network, it forms the complete LDO hardware body. The analog loop is responsible for steady-state continuous fine voltage regulation, while the digital loop only starts coarse regulation when the load transient exceeds the voltage dead zone.

[0030] S3, Analog Loop Steady-State Fine-Tuning Control: The difference between the VOUT voltage divider feedback voltage and VREF is acquired by the Cascode structure error amplifier, and the analog main power transistor M2 is driven by the buffer to achieve continuous linear voltage regulation; an independent voltage comparator CMP is added at the same time to form an instantaneous current auxiliary path with the auxiliary power transistor M1, and the output current is supplemented synchronously when the load changes transiently; only the analog loop works continuously in the steady-state range to eliminate discrete quantization error; The Cascode structure is a common-source, common-gate structure consisting of two transistors connected in series, typically a common-source amplifier and a common-gate amplifier. The main purpose of this structure is to improve the circuit's gain and output impedance while reducing the mutual interference between the input and output.

[0031] Specifically, this step involves fine-tuning the steady-state simulation loop and constructing an instantaneous auxiliary current path: a Cascode high-gain error amplifier is used to acquire the difference between the output voltage divider feedback voltage and the reference VREF, which is then driven by a buffer to form a continuous linear negative feedback voltage regulation path for the analog main power transistor M2; an independent auxiliary voltage comparator CMP and an auxiliary power transistor M1 are added to form an instantaneous current auxiliary branch, which synchronously draws a large current to the output terminal when the load current changes abruptly, compensating for the response delay caused by insufficient bandwidth of the simulation loop; when the output voltage is stable within the dead zone, only the simulation loop continues to work, eliminating the quantization error introduced by digital discrete control.

[0032] S4. Digital loop dead-zone triggered binary search coarse adjustment control: Three dynamic voltage comparators are set to generate the output voltage dead zone interval [VREFL,VREFH]. Only when VOUT exceeds the dead zone threshold, the digital logic controller triggers the successive approximation binary search method to quickly solve the optimal conduction control codeword by traversing the weight bits of the binary power transistor array. After coarse adjustment, the digital control codeword is latched, the digital dynamic toggle behavior is turned off, and the analog loop is enabled to complete fine voltage regulation independently. Specifically, in this step, the digital loop dead-time triggered successive approximation binary search coarse adjustment control is implemented: three dynamic latch voltage comparators are configured to define the output voltage dead-time range [VREFL, VREF0-Δ, VREF0+Δ]; COMP1 outputs the lower limit overflow signal VOL, and COMP2 outputs the upper limit overflow signal VOH, which serve as the digital loop start-up trigger conditions; COMP3 outputs the COUT level signal, used to determine the conduction quantity of each bit weight in the binary search method; only when VOUT jumps out of the dead-time threshold, the digital logic controller starts the successive approximation binary search iteration, requiring only 6 clock cycles to solve for the optimal power transistor conduction control codeword; after the iteration is completed, all digital control codewords are latched, the dynamic flipping of the digital logic clock is stopped, and the analog loop is enabled to regulate voltage independently, significantly reducing the digital dynamic power consumption.

[0033] S5. Power transistor coordinated voltage regulation control: During the transient load transition phase, the digital loop outputs control codewords to drive the binary PMOS power transistor array to provide a large-span coarse adjustment current; during the steady-state phase, the digital array maintains a fixed on state, and the auxiliary power transistor M1 and the analog main power transistor M2 in the analog loop provide a continuously adjustable micro current. The two work together to achieve high-precision voltage regulation over a wide load range.

[0034] Specifically, in this step, the power transistor array coordinates voltage regulation control: during the transient phase of load step change, the digital loop outputs binary control codewords to drive the power transistor array, rapidly increasing or decreasing the number of conducting power transistors, providing a large-span coarse adjustment current, and quickly pulling the output voltage back to the dead zone; in the steady-state range, the digital array maintains a fixed conducting state, and the analog auxiliary power transistor M1 and the analog main power transistor M2 provide continuously adjustable micro-currents. The two work together to achieve high-precision, low-ripple voltage regulation across the entire load range.

[0035] The present invention has been described in detail above. However, modifications or improvements can be made to it, which will be obvious to those skilled in the art. Therefore, any modifications or improvements that do not depart from the spirit of the present invention are within the scope of protection of the present invention.

Claims

1. A digital-assisted analog LDO circuit, characterized in that: It includes a bandgap reference module, an analog voltage regulator loop, a digital auxiliary loop, a power transistor array, and a feedback voltage divider network; The bandgap reference module outputs a reference voltage VREF and a preset reference voltage VREF0 to the analog voltage regulation loop and the digital auxiliary loop, respectively, and outputs multiple bias currents. The analog voltage regulator loop and the digital auxiliary loop are connected in parallel to the output terminal VOUT of the power transistor array. The analog voltage regulator loop regulates the auxiliary power transistor M1 and the analog main power transistor M2, while the digital auxiliary loop regulates the output current of the power transistor array. The feedback voltage divider network is connected to VOUT at one end and grounded at the other end, and the voltage divider node feeds back the voltage divider voltage to the analog voltage regulator loop; The analog voltage regulation loop includes an error amplifier EA, a buffer, an auxiliary voltage comparator CMP, an auxiliary power transistor M1, and an analog main power transistor M2. The digital auxiliary loop includes three dynamic voltage comparators COMP1, COMP2, and COMP3, a digital logic controller, and a multi-channel inverting buffer.

2. The digital-assisted analog LDO circuit according to claim 1, characterized in that: The error amplifier adopts a common source cascode structure, rather than a simple five-transistor operational amplifier. The non-inverting input is connected to VREF, the inverting input is connected to the feedback voltage divider, the output of the error amplifier is connected to the input of the buffer, the output of the buffer drives the gate of the analog main power transistor M2, and an on-chip compensation capacitor C1 is connected in parallel between the error amplifier and the buffer. The non-inverting input of the auxiliary voltage comparator CMP is connected to VREF0, and the inverting input is connected to VOUT. The comparator output drives the gate of the auxiliary power transistor M1. The sources of the auxiliary power transistor M1 and the analog main power transistor M2 are connected to the power supply VDD, and their drains are connected to VOUT.

3. The digital-assisted analog LDO circuit according to claim 1, characterized in that: COMP1 outputs the lower limit detection signal VOL, COMP2 outputs the upper limit detection signal VOH, and VOL and VOH are connected to the digital logic controller to define the output voltage dead zone range; COMP3 outputs the COUT signal to provide feedback on the high / low relationship between VOUT and VREF0. The digital logic controller has a built-in 6-bit successive approximation binary search control logic. The input signals include VOL, VOH, COUT, system clock CLK, and reset signal RST_N. The output is a 6-bit control codeword. Each control codeword drives the gate of a single power transistor in the power transistor array through an inverting buffer.

4. The digital-assisted analog LDO circuit according to claim 3, characterized in that: The power transistor array is a 6-channel binary weighted PMOS transistor array. All PMOS sources are connected to VDD and the drains are connected in parallel to output VOUT. The 6 PMOS transistors have the same channel length and the conduction width ratio is 1:2:4:8:16:

32. The PMOS transistors are turned on when the level is low and the on and off are controlled by the output level of the inverting buffer.

5. The digital-assisted analog LDO circuit according to claim 1, characterized in that: The bandgap reference module is a PTAT bandgap reference circuit with a multi-stage common-source cascode current mirror coupled differential amplifier. It outputs two reference signals VREF and VREF0, and simultaneously outputs independent bias currents IB_EA and IB_CMP to the error amplifier, three dynamic voltage comparators, and auxiliary voltage comparator, respectively.

6. The digital-assisted analog LDO circuit according to claim 1, characterized in that: The feedback voltage divider network consists of series resistors R0 and R1. The upper end of R0 is connected to VOUT, and the lower end of R1 is grounded. The feedback voltage output from the voltage divider node between R0 and R1 is connected to the inverting input of the error amplifier.

7. A digital-assisted analog LDO circuit according to claim 3, characterized in that: The working logic of the digital logic controller is as follows: after reset, all control codewords are cleared to zero, the analog loop enable is turned off, VOL and VOH are continuously monitored on the rising edge of the clock, and when VOUT jumps out of the dead zone range, the binary search method is started for coarse adjustment. The optimal conduction codeword is obtained by traversing the 6-bit binary weight. After the coarse adjustment is completed, the analog loop enable is pulled high, the digital loop latch control codeword stops dynamic adjustment, and the analog loop steady-state fine adjustment mode is switched.

8. A digitally assisted fast transient response analog LDO design method, used in any one of the digitally assisted analog LDO circuits described in claims 1-7, characterized in that: Includes the following steps: S1. Building a reference generation unit: A multi-stage PTAT bandgap reference circuit with cascode current mirror coupling differential amplification is used to generate a steady-state reference voltage VREF and an output target reference voltage VREF0, and to output independent bias currents IB_EA and IB_CMP to supply the active devices of the analog loop and digital loop respectively. S2. Construct a parallel dual-control loop architecture, wherein the parallel dual-control loop includes an analog voltage regulation loop and a digital auxiliary loop, which are connected in parallel to the output terminal VOUT, and together with a binary weighted power transistor array and a feedback voltage divider network, constitute the complete LDO body; S3. Analog Loop Steady-State Fine-Tuning Control: The difference between the VOUT voltage divider feedback voltage and VREF is acquired by the Cascode structure error amplifier, and the analog main power transistor M2 is driven by the buffer to achieve continuous linear voltage regulation; an independent voltage comparator CMP is added at the same time to form an instantaneous current auxiliary path with the auxiliary power transistor M1, and the output current is supplemented synchronously when the load changes transiently; only the analog loop works continuously in the steady-state range to eliminate discrete quantization error. S4. Digital loop dead-zone triggered binary search coarse adjustment control: Three dynamic voltage comparators are set to generate the output voltage dead zone interval [VREFL,VREFH]. Only when VOUT exceeds the dead zone threshold, the digital logic controller triggers the successive approximation binary search method to quickly solve the optimal conduction control codeword by traversing the weight bits of the binary power transistor array. After coarse adjustment, the digital control codeword is latched, the digital dynamic toggle behavior is turned off, and the analog loop is enabled to complete fine voltage regulation independently. S5. Power transistor coordinated voltage regulation control: During the transient load transition phase, the digital loop outputs control codewords to drive the binary PMOS power transistor array to provide a large-span coarse adjustment current; during the steady-state phase, the digital array maintains a fixed on state, and the auxiliary power transistor M1 and the analog main power transistor M2 in the analog loop provide a continuously adjustable micro current. The two work together to achieve high-precision voltage regulation over a wide load range.

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