A high voltage LDO regulator with output short protection

Abstract

The application relates to the field of voltage stabilizers, in particular to a high-voltage LDO voltage stabilizer with output short-circuit protection. After an internal power supply is established in a pre-stabilization module, an upper power reset module, an enable module, a band gap reference and an error amplifier U0 are sequentially driven, so that time sequence competition in the starting process is avoided. A power tube gate control node is shared by an over-temperature protection module and a short-circuit protection module. When the chip temperature exceeds a threshold value or the output occurs short-circuit, the power tube is limited or turned off through the same control path, so that protection action conflicts are avoided. The short-circuit protection module suppresses output peak surge current through clamping of the power tube gate pull-down amplitude.

Description

Technical Field

[0001] This invention relates to the field of voltage regulators, and more specifically to a high-voltage LDO voltage regulator with output short-circuit protection. Background Technology

[0002] High-voltage LDO regulators are a type of low-dropout linear regulator specifically designed for wide-range, high-input-voltage applications. They significantly increase the input voltage withstand capability compared to conventional LDOs. While ordinary LDOs typically support input voltages of only a few tens of volts, high-voltage LDOs can generally withstand tens or even hundreds of volts. Some industrial-grade and automotive-grade models can even withstand higher transient voltage surges, preventing chip breakdown damage during large input voltage fluctuations. They also rely on an internal negative feedback closed-loop mechanism, using an error amplifier to compare the difference between the output sampling voltage and the reference voltage in real time, dynamically adjusting the conduction state of the internal regulating transistor to convert fluctuating high-voltage inputs into stable low-voltage outputs. This process retains the advantages of traditional LDOs, such as extremely low output ripple, no switching noise, high power supply rejection ratio, and simple peripheral circuitry.

[0003] High-voltage LDO regulators typically control the power transistor by comparing the sampled output current with a fixed threshold. In constant-current limiting mode, the power transistor experiences significant voltage stress and power dissipation, easily leading to thermal failure, latch-up shutdown or hiccup mode requiring external reset or power-on, poor sampling accuracy, and susceptibility to false triggering at high temperatures or during power-on. Conventional solutions employ clamping schemes to prevent latch-up or suppress high-temperature drift. However, the clamping target is the false trigger signal itself, rather than directly clamping the pull-down amplitude of the power transistor gate to limit the peak current, thus failing to achieve the goal of limiting the peak current. Summary of the Invention

[0004] The purpose of this invention is to provide a high-voltage LDO regulator with output short-circuit protection, which aims to improve the problem that existing clamping schemes target the false trigger signal itself rather than directly clamp the pull-down amplitude of the power transistor gate to limit the peak current, thus failing to limit the peak current.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A high-voltage LDO regulator with output short-circuit protection includes a pre-regulation module, a reference module, an enable module, a power-on reset module, an over-temperature protection module, a short-circuit protection module, an error amplifier U0, a high-voltage MOSFET HP100, a high-voltage MOSFET HN100, and resistors R100, R101, and R102. An external power supply VIN is input to one end of the pre-regulator module, the short-circuit protection module, and the resistor R100. The pre-regulator module outputs VDD to the power input terminals of the reference module, the over-temperature protection module, the power-on reset module, and the error amplifier U0. The output terminals of the pre-regulator module and the power-on reset module respectively output bias voltage VNG and control signal POR_SET to the enable module. The enable module outputs enable signals ENL and ENLB to the pre-regulator module. The pre-regulator module outputs enable signal ENH to the short-circuit protection module. The reference module outputs reference voltage VREF and reference voltage VREF1 to the over-temperature protection module and the inverting input terminal of error amplifier U0 respectively. The over-temperature protection module outputs bias voltage BIAS2 to the gate of high-voltage MOSFET HN100. The over-temperature protection module outputs bias voltage BIAS1 and voltage OTP to the short-circuit protection module. The output terminal of the short-circuit protection module is electrically connected to the gate and drain of high-voltage MOSFET HP100 and high-voltage MOSFET HN100. The other end of resistor R100 is electrically connected to the source of high-voltage MOSFET HP100. The drain of high-voltage MOSFET HP100 is electrically connected to one end of resistor R101 and serves as the output terminal OUT connected to the outside. The other end of resistor R101 is electrically connected to the non-inverting input terminal of error amplifier U0 and one end of resistor R102. The output terminal of error amplifier U0 is electrically connected to the source of high-voltage MOSFET HN100. The other end of resistor R102 is grounded.

[0006] Furthermore, the pre-regulator module includes MOSFETs P0, P1, P2, P3, P4, P5, P6, P7, N0, N3, N4, HP1, HP2, HP3, HP4, HN1, HN2, HN3, HN4, resistors R0, R1, R2, R3, R4, and capacitor C0; An external power supply VIN is input to one end of resistor R0, the source of MOSFET P1, the source of MOSFET P2, the source of MOSFET P3, the source of MOSFET P4, the source of MOSFET P5, the source of MOSFET P6, the source of MOSFET P7, the source of MOSFET HP4, one end of capacitor C0, and one end of resistor R4; the enable signal ENLB is input to the gate of MOSFET HN2, the enable signal ENL is input to the gate of MOSFET HN3, and the external IN1 signal is input to the gate of MOSFET P0; The other end of resistor R0 is electrically connected to the drain of MOSFET N0 and the gate of MOSFET HN1; the gate and drain of MOSFET P1 are electrically connected to the gates of MOSFET P2, MOSFET P5, MOSFET P6, and MOSFET P7 and one end of resistor R2; the other end of resistor R2 is electrically connected to the drain of MOSFET HN1, the gate of MOSFET HP1, the gate of MOSFET HP2, and the gate of MOSFET HP3; the source of MOSFET HN1 is electrically connected to one end of resistor R1 and the gate of MOSFET N0. The drain of MOS transistor P2 is electrically connected to the source of MOS transistor HP1, the drain of MOS transistor P3, and the gate of MOS transistor P4. The drain of MOS transistor HP1 is electrically connected to the drain of MOS transistor HN2. The gate of MOSFET P3 is electrically connected to the drain of MOSFET P4, the drain of MOSFET P5, and the source of MOSFET HP2, and outputs an enable signal ENH to the short-circuit protection module as an output terminal. The drain of MOSFET HP2 is electrically connected to the drain of MOSFET HN3. The drain of MOSFET P6 is electrically connected to the source of MOSFET HP3. The drain of MOSFET HP3 is electrically connected to the gate of MOSFET HN4, the gate and drain of MOSFET N3, and the gate of MOSFET N4, and serves as the output terminal to output the bias voltage VNG to the enable module. The drain of MOSFET P7 is electrically connected to one end of resistor R3, the source of MOSFET N2, the gate of MOSFET HP4, and the drain of MOSFET HN4. The source of MOSFET HN4 is electrically connected to the drain of MOSFET N4 and the drain of MOSFET P0. The other end of capacitor C0 is electrically connected to the other end of resistor R3 and the gate of MOSFET N2. The drain of MOSFET N2 is electrically connected to the other end of resistor R4. The drain of MOSFET HP2 is electrically connected to the source of MOSFET P0 and outputs VDD to the power input terminals of the reference module, over-temperature protection module, power-on reset module and error amplifier U0. The source terminals of MOSFET N0, MOSFET HN2, MOSFET HN3, MOSFET N3, MOSFET N4, and the other end of resistor R1 are all grounded.

[0007] Furthermore, the reference module includes MOSFETs P8, P9, and P10, transistors Q5 and Q6, resistors R8, R9, R10, R11, R12, R5, R6, and R7, and capacitor C1. The pre-regulated voltage module outputs VDD to one end of resistor R8, one end of resistor R5, one end of resistor R6, and one end of resistor R7; The other end of resistor R8 is electrically connected to one end of resistor R1, the base of transistor Q5, and the base of transistor Q6, and serves as the output terminal to output the reference voltage VREF to the over-temperature protection module. The other end of resistor R9 is electrically connected to one end of resistor R10, and serves as the output terminal to output the reference voltage VREF1 to the inverting input terminal of error amplifier U0. The other end of resistor R5 is electrically connected to the source of MOSFET P8. The gate and drain of MOSFET P8 are electrically connected to the collector of transistor Q5, the gate of MOSFET P1, and the gate of MOSFET P2. The emitter of transistor Q5 is electrically connected to one end of resistor R11. The other end of resistor R11 is electrically connected to the emitter of transistor Q6 and one end of resistor R12. The other end of resistor R6 is electrically connected to the source of MOSFET P9. The drain of MOSFET P1 is electrically connected to the collector of transistor Q6 and one end of capacitor C1, and is connected to the external circuit as output terminal OUT1. The other end of resistor R7 is electrically connected to the source of MOSFET P10. The drain of MOSFET P10 outputs current PTAT to the over-temperature protection module. The other ends of resistor R10, resistor R12, and capacitor C1 are all grounded.

[0008] Furthermore, the following condition must be satisfied: (W / L) P8 (W / L) P9 =1:1, Among them, (W / L) P8 and (W / L) P9 These are the width-to-length ratios of MOSFETs P8 and P9, respectively. The resistance values ​​of resistors R5, R6, and R7 are equal.

[0009] Furthermore, the over-temperature protection module includes transistors Q0, Q1, Q2, Q3, and Q4; MOSFETs P11, P12, P13, P14, P15, P16, P17, P18, and P19; MOSFETs N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, HP5, HP6, HP7, HP8, HP9, HP10, HN5, HN6, HN7, HN8, HN9, and HN10; and resistors R13, R14, R15, and R16. An external power supply VIN is input to the source of MOSFETs P11, P13, P14, P15, P16, P17, P18, P19, and HP8, and one end of resistor R16; the pre-regulator module outputs VDD to one end of resistor R13, the reference module outputs a reference voltage VREF to one end of resistor R14, and the reference module outputs a current PTAT to the gate and drain of MOSFET N5, the gate of MOSFET N6, and the gate of MOSFET N7; The gate and drain of MOSFET P11 are electrically connected to the source of MOSFET P12. The gate and drain of MOSFET P12 are electrically connected to the gates of MOSFETs HP5, HP6, HP7, HP9, HP10, and HN5. The other end of resistor R13 is electrically connected to the gates of MOSFETs HN5, HN6, HN7, HN8, and HN9. The source of MOSFET HN5 is electrically connected to the drain of MOSFET N6. The other end of resistor R14 is electrically connected to the base of transistor Q0. The gate of MOSFET P13 is electrically connected to the gates of MOSFETs P14, P15, P18, and P19, as well as the drain of MOSFET HP5 and the drain of MOSFET HN6, and serves as the output terminal to output the bias voltage BIAS1 to the short-circuit protection module; the drain of MOSFET P13 is electrically connected to the source of MOSFET HP5, and the source of MOSFET HN6 is electrically connected to the drain of MOSFET N7. The drain of MOSFET P14 is electrically connected to the source of MOSFET HP6, and the drain of MOSFET HP6 is electrically connected to the gate and drain of MOSFET N8, the gate of MOSFET N10, the gate of MOSFET N11, and the gate of MOSFET N12. The drain of MOSFET P15 is electrically connected to the drain of MOSFET HN7, the gate of MOSFET P16, and the gate of MOSFET P17. The source of MOSFET HN7 is electrically connected to the collector of transistor Q0. The emitter of transistor Q0 is electrically connected to the base and collector of transistor Q1. The emitter of transistor Q1 is electrically connected to the base and collector of transistor Q2. The emitter of transistor Q2 is electrically connected to the base and collector of transistor Q3. The emitter of transistor Q3 is electrically connected to one end of resistor R15. The other end of resistor R15 is electrically connected to the base and collector of transistor Q4 and the drain of transistor N9. The drain of MOSFET P15 is electrically connected to the source of MOSFET HP7; the drain of MOSFET HP7 is electrically connected to the gate of transistor N9 and the drain of MOSFET N10; the drain of MOSFET P17 is electrically connected to the gate of MOSFET HP8 and the drain of MOSFET HN8; the source of MOSFET HN8 is electrically connected to the drain of MOSFET N11; the drain of MOSFET HP8 is electrically connected to the drain of MOSFET HN9 and serves as the output terminal, outputting voltage OTP to the short-circuit protection module; the source of MOSFET HN9 is electrically connected to the drain of MOSFET N12. The drain of MOSFET P18 is electrically connected to the source of MOSFET HP9. The drain of MOSFET HP9 is electrically connected to the gate and drain of MOSFET N13 and the gate of MOSFET N14, and serves as the output terminal to output VG to the outside. The drain of MOSFET P19 is electrically connected to the source of MOSFET HP10. The drain of MOSFET HP10 is electrically connected to the drain of MOSFET N15 and the gate of MOSFET HN10, and serves as the output terminal to output the bias voltage BIAS2 to the gate of high-voltage MOSFET HN100. The other end of resistor R16 is electrically connected to the drain of MOSFET HN10. The source of MOSFET HN10 is electrically connected to the gate of MOSFET N15 and the drain of MOSFET N14. The sources of MOSFETs N5, N6, N7, N8, N9, N10, N11, N12, N13, and N14, as well as the emitter of transistor Q4, are all grounded.

[0010] Furthermore, the enabling module includes a Schmitt trigger U100, an inverter U101, an inverter U102, an inverter U105, a NAND gate U103, a NAND gate U104, and a MOSFET N21; The output terminal of the pre-regulator module outputs a bias voltage VNG to the gate of the MOS transistor N21. The drain of the MOS transistor N21 is electrically connected to the input terminal of the Schmitt trigger U100. The inverters U101 and U102 are connected in series between the output terminal of the Schmitt trigger U100 and the first input terminal of the NAND gate U103. The source of the MOS transistor N21 and the second input terminal of the NAND gate U103 are both grounded. The output terminal of the NAND gate and the first input terminal of the NAND gate U104 are electrically connected. The output control signal POR_SET of the power-on reset module is sent to the second input terminal of the NAND gate U104. The output terminal of the NAND gate U104 is electrically connected to the input terminal of the inverter U105 and outputs an enable signal ENL to the pre-regulation module. The output terminal of the inverter U105 outputs an enable signal ENLB to the pre-regulation module.

[0011] Furthermore, the power-on reset module includes MOSFETs P20, P21, P22, P23, P24, P25, P26, P27, P28, N16, N17, N18, N19, and N20, capacitors C2 and C3, and resistor R17. The pre-regulator module outputs VDD to the sources of MOSFETs P20, P21, P22, P23, P24, P25, P26, P27, and P28. The gate and drain of MOSFET P20 are electrically connected to the gate of MOSFET N16 and the drain of MOSFET P21. The gate of MOSFET P21 is electrically connected to the gate of MOSFET P22 and the drain of MOSFET N16. The drain of MOSFET P22 is electrically connected to one end of resistor R17, one end of capacitor C2, the drain of MOSFET P23, the gate of MOSFET P24, and the gate of MOSFET N17. The gate of MOSFET P23 is electrically connected to the drain of MOSFET P24, the drain of MOSFET N17, the gate of MOSFET P25, and the drain of MOSFET P26. The gate of S-channel transistor N18 is electrically connected; the drains of MOSFET P25 and MOSFET N18 are both electrically connected to the drain of MOSFET P26, one end of capacitor C3, the gate of MOSFET P27, and the gate of MOSFET N19; the drain of MOSFET P27 is electrically connected to the gate of MOSFET P26, the drain of MOSFET N19, the gate of MOSFET P28, and the gate of MOSFET N20; the drain of MOSFET P28 is electrically connected to the drain of MOSFET N20, and outputs the control signal POR_SET to the enable module as the output terminal; The sources of MOSFETs N16, N17, N18, N19, and N20, as well as the other end of resistor R17, capacitor C2, and capacitor C3, are all grounded.

[0012] Furthermore, the short-circuit protection module includes MOSFETs P29, P30, P31, P32, P33, and P34, and diode D0; An external power supply VIN is input to the source of MOSFET P29, the source of MOSFET P30, the source of MOSFET P31, the source of MOSFET P32, and the cathode of diode D0; the pre-regulation module outputs an enable signal ENH to the gate of MOSFET P29; the over-temperature protection module outputs voltage OTP to the gate of MOSFET P30; and the over-temperature protection module outputs bias voltage BIAS1 to the gate of MOSFET P31. The gate and drain of the MOS transistor P32 are electrically connected to the source of the MOS transistor P33, and the gate and drain of the MOS transistor P33 are electrically connected to the source of the MOS transistor P34. The drain of MOSFET P29 is electrically connected to the drain of MOSFET P30, the drain of MOSFET P31, the gate and drain of MOSFET P34, and the diode D0, and is also electrically connected as the output terminal to the gate of high-voltage MOSFET HP100 and the drain of high-voltage MOSFET HN100.

[0013] Furthermore, the error amplifier U0 includes MOSFETs P35, P36, P37, P39, N21, N22, N23, and N24. The pre-regulator module outputs VDD to the source of MOSFET P35, the source of MOSFET P36, the source of MOSFET P37, and the source of MOSFET P39. The reference module outputs reference voltage VREF1 to the gate of MOSFET N21. The other end of the resistor R101 is electrically connected to the gate of MOSFET N22. The external signal VG is input to the gates of MOSFET N23 and MOSFET N24. The gate and drain of MOSFET P35 are electrically connected to the gate of MOSFET P36 and the drain of MOSFET N21. The source of MOSFET N21 is electrically connected to the drain of MOSFET N23 and the source of MOSFET N22. The drain of MOSFET P36 is electrically connected to the gate and drain of MOSFET P37, the gate of MOSFET P38, and the drain of MOSFET N22. The drain of MOSFET P38 is electrically connected to the drain of MOSFET N24 and serves as the output terminal, electrically connected to the source of high-voltage MOSFET HN100. The sources of both MOS transistor N23 and MOS transistor N24 are grounded.

[0014] By adopting the above technical solution, the present invention has the following advantages compared with the prior art: After the pre-regulator module establishes its internal power supply, it sequentially drives the power-on reset module, enable module, bandgap reference, and error amplifier U0 to avoid timing races during startup. The over-temperature protection module and the short-circuit protection module share the power transistor gate control node. When the chip temperature exceeds the threshold or a short circuit occurs at the output, both modules limit or turn off the power transistor through the same control path to avoid conflicting protection actions. The short-circuit protection module suppresses the output peak surge current by clamping the power transistor gate pull-down amplitude. At the same time, the power transistor remains in the conducting state throughout the short circuit and automatically recovers after the fault is cleared. Attached Figure Description

[0015] Figure 1 This is a circuit diagram of the high-voltage LDO regulator with output short-circuit protection described in this invention; Figure 2 This is a circuit diagram of the pre-regulator module of the high-voltage LDO regulator with output short-circuit protection described in this invention; Figure 3 This is a circuit diagram of the reference module of the high-voltage LDO regulator with output short-circuit protection described in this invention; Figure 4 This is a circuit diagram of the over-temperature protection module for a high-voltage LDO regulator with output short-circuit protection as described in this invention. Figure 5 This is a circuit diagram of the enable module of the high-voltage LDO regulator with output short-circuit protection described in this invention; Figure 6 This is a circuit diagram of the power-on reset module of the high-voltage LDO regulator with output short-circuit protection described in this invention; Figure 7 This is a circuit diagram of the short-circuit protection module of the high-voltage LDO regulator with output short-circuit protection described in this invention; Figure 8 The circuit diagram of the error amplifier U0 of the high-voltage LDO regulator with output short-circuit protection described in this invention is shown below. Figure 9 This is a circuit function simulation diagram of the high-voltage LDO regulator with output short-circuit protection described in this invention as the input VIN rises from 14V to 36V. Figure 10 This is a simulation diagram of the current limiting effect of the circuit when the OUT of the high-voltage LDO regulator with output short-circuit protection described in this invention is pulled down from 12V to ground. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0017] Additionally, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are all based on the orientation or positional relationship shown in the accompanying drawings. They are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element of the present invention must have a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0018] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.

[0019] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example

[0020] Please refer to Figure 1-10 As shown, this embodiment provides a high-voltage LDO regulator with output short-circuit protection. Please refer to... Figure 1 As shown, the system includes a pre-regulator module, a reference module, an enable module, a power-on reset module, an over-temperature protection module, a short-circuit protection module, an error amplifier U0, high-voltage MOSFETs HP100 and HN100, and resistors R100, R101, and R102. An external power supply VIN is input to one end of the pre-regulator module, the short-circuit protection module, and resistor R100. The pre-regulator module outputs VDD to the power input terminals of the reference module, the over-temperature protection module, the power-on reset module, and the error amplifier U0. The output terminals of the pre-regulator module and the power-on reset module output a bias voltage VNG and a control signal POR_SET to the enable module, respectively. The enable module outputs enable signals ENL and ENLB to the pre-regulator module, and an enable signal ENH to the short-circuit protection module. The reference module outputs reference voltages VREF and VREF1 to the inverting input terminals of the over-temperature protection module and the error amplifier U0, respectively. The over-temperature protection module outputs a bias voltage BIAS2 to the gate of the high-voltage MOSFET HN100. It also outputs a bias voltage BIAS1 and a voltage OTP to the short-circuit protection module. The output of the short-circuit protection module is electrically connected to the gate and drain of the high-voltage MOSFET HP100 and HN100, respectively. The other end of resistor R100 is electrically connected to the source of the high-voltage MOSFET HP100. The drain of the high-voltage MOSFET HP100 is electrically connected to one end of resistor R101, which serves as the output terminal OUT connected to an external circuit. The other end of resistor R101 is electrically connected to the non-inverting input of error amplifier U0 and one end of resistor R102. The output of error amplifier U0 is electrically connected to the source of the high-voltage MOSFET HN100. The other end of resistor R102 is grounded.

[0021] Resistor R100 is the input resistor, resistors R101 and R102 are the output voltage divider resistors, and high-voltage MOSFET HP100 is the main power adjustment transistor. The high-voltage MOSFET isolates the low-voltage output of the error amplifier from the gate of the main power transistor to prevent high-voltage breakdown and damage to the error amplifier.

[0022] After the pre-regulator module establishes its internal power supply, it sequentially drives the power-on reset module, enable module, bandgap reference, and error amplifier U0 to avoid timing races during startup. The over-temperature protection module and the short-circuit protection module share the power transistor gate control node. When the chip temperature exceeds the threshold or a short circuit occurs at the output, both modules limit or turn off the power transistor through the same control path to avoid conflicting protection actions. The short-circuit protection module suppresses the output peak surge current by clamping the power transistor gate pull-down amplitude. At the same time, the power transistor remains in the conducting state throughout the short circuit and automatically recovers after the fault is cleared.

[0023] Please refer to the appendix. Figure 2 Specifically, the pre-regulator module includes MOSFETs P0, P1, P2, P3, P4, P5, P6, P7, N0, N3, N4, HP1, HP2, HP3, HP4, HN1, HN2, HN3, and HN4, resistors R0, R1, R2, R3, and R4, and capacitor C0.

[0024] External power supply VIN is input to one end of resistor R0, the source of MOSFET P1, the source of MOSFET P2, the source of MOSFET P3, the source of MOSFET P4, the source of MOSFET P5, the source of MOSFET P6, the source of MOSFET P7, the source of MOSFET HP4, one end of capacitor C0, and one end of resistor R4; enable signal ENLB is input to the gate of MOSFET HN2, enable signal ENL is input to the gate of MOSFET HN3, and external signal IN1 is input to the gate of MOSFET P0.

[0025] The other end of resistor R0 is electrically connected to the drain of MOSFET N0 and the gate of MOSFET HN1; the gate and drain of MOSFET P1 are electrically connected to the gates of MOSFET P2, MOSFET P5, MOSFET P6, MOSFET P7 and one end of resistor R2; the other end of resistor R2 is electrically connected to the drain of MOSFET HN1, the gate of MOSFET HP1, MOSFET HP2 and MOSFET HP3; the source of MOSFET HN1 is electrically connected to one end of resistor R1 and the gate of MOSFET N0.

[0026] The drain of MOSFET P2 is electrically connected to the source of MOSFET HP1, the drain of MOSFET P3, and the gate of MOSFET P4. The drain of MOSFET HP1 is electrically connected to the drain of MOSFET HN2. The gate of MOSFET P3 is electrically connected to the drain of MOSFET P4, the drain of MOSFET P5, and the source of MOSFET HP2, and outputs the enable signal ENH to the short-circuit protection module as the output terminal. The drain of MOSFET HP2 is electrically connected to the drain of MOSFET HN3.

[0027] The drain of MOSFET P6 is electrically connected to the source of MOSFET HP3. The drain of MOSFET HP3 is electrically connected to the gate of MOSFET HN4, the gate and drain of MOSFET N3, and the gate of MOSFET N4, and serves as the output terminal to output the bias voltage VNG to the enable module. The drain of MOSFET P7 is electrically connected to one end of resistor R3, the source of MOSFET N2, the gate of MOSFET HP4, and the drain of MOSFET HN4. The source of MOSFET HN4 is electrically connected to the drain of MOSFET N4 and the drain of MOSFET P0.

[0028] The other end of capacitor C0 is electrically connected to the other end of resistor R3 and the gate of MOSFET N2. The drain of MOSFET N2 is electrically connected to the other end of resistor R4. The drain of MOSFET HP2 is electrically connected to the source of MOSFET P0, and outputs VDD to the power input terminals of the reference module, over-temperature protection module, power-on reset module and error amplifier U0.

[0029] The sources of MOSFET N0, MOSFET HN2, MOSFET HN3, MOSFET N3, MOSFET N4, and the other end of resistor R1 are all grounded.

[0030] In the pre-regulation module, resistors R0 and R1, MOSFETs P1, N0, and HN1 form a VGS / R type bias circuit. VIN is the external input power supply. The bias circuit automatically starts after VIN is powered on, providing a startup voltage for the PMOS current mirror and generating a stable PMOS self-bias. The current flowing through MOSFET N0 can be obtained from the bias circuit: ; The current flowing through MOSFET HN1 is: ; Where VIN is the external power supply voltage, VGS1 is the gate-source voltage of MOSFET N0, VGS2 is the gate-source voltage of MOSFET HN1, Δ is the overdrive voltage of the MOSFET, and Vthn is the NMOS threshold voltage.

[0031] MOSFETs P0, P1, P2, P5, P6, and P7 form a current mirror structure to mirror the I0 current to each branch. MOSFETs P2, P5, P6, and P7 form a common-source, common-gate structure with MOSFETs HP1, HP2, HP3, and HN4, respectively, and are responsible for handling the high voltage VIN. MOSFETs HN2 and HN3 receive the enable signal from the enable module and output a high-level enable signal ENH through the common-source, common-gate structure. MOSFETs P3 and P4 are hysteresis transistors, responsible for the hysteresis of the ENH signal.

[0032] Resistor R3, resistor R4, capacitor C0, and MOSFET N2 form a surge suppression structure that stabilizes the gate voltage of MOSFET HP2. If the VIN voltage changes abruptly for a short time, since the voltage across capacitor C0 cannot change abruptly, the gate-source voltage of MOSFET N2 will follow suit, and MOSFET N2 will enter the saturation region. The current flowing through MOSFET N2 will be automatically limited to its maximum current due to the square law characteristic of NMOS.

[0033] MOSFETs N3 and N4 form an NMOS current mirror. MOSFET N3 is connected as a diode, and MOSFET N4 mirrors its current, adjusting the pull-down current of MOSFET P0 based on error feedback. The pull-up current of MOSFET P0 and the pull-down current of MOSFET N3 are superimposed at the drain of MOSFET P3, jointly determining the source potential of MOSFET HN4. If the VDD output increases, MOSFET P0 conducts more strongly, its pull-up current increases, the pull-down current of MOSFET P0 weakens, the gate voltage of MOSFET HP2 increases, and its conduction weakens, thus pulling VDD back to the set value, and vice versa.

[0034] Please refer to the appendix. Figure 3 Specifically, the reference module includes MOSFETs P8, P9, and P10, transistors Q5 and Q6, resistors R8, R9, R10, R11, R12, R5, R6, and R7, and capacitor C1.

[0035] The pre-regulator module outputs VDD to one end of resistor R8, one end of resistor R5, one end of resistor R6, and one end of resistor R7. The other end of resistor R8 is electrically connected to one end of resistor R1, the base of transistor Q5, and the base of transistor Q6, and serves as the output terminal to output the reference voltage VREF to the over-temperature protection module. The other end of resistor R9 is electrically connected to one end of resistor R10, and serves as the output terminal to output the reference voltage VREF1 to the inverting input terminal of error amplifier U0.

[0036] The other end of resistor R5 is electrically connected to the source of MOSFET P8. The gate and drain of MOSFET P8 are electrically connected to the collector of transistor Q5, the gate of MOSFET P1, and the gate of MOSFET P2. The emitter of transistor Q5 is electrically connected to one end of resistor R11. The other end of resistor R11 is electrically connected to the emitter of transistor Q6 and one end of resistor R12.

[0037] The other end of resistor R6 is electrically connected to the source of MOSFET P9. The drain of MOSFET P1 is electrically connected to the collector of transistor Q6 and one end of capacitor C1, and serves as the output terminal OUT1, electrically connected to the external circuit. The other end of resistor R7 is electrically connected to the source of MOSFET P10, and the drain of MOSFET P10 outputs current PTAT to the over-temperature protection module. The other ends of resistors R10, R12, and C1 are all grounded.

[0038] VDD is a constant internal power supply generated by the pre-regulator. Resistors R8, R9, and R10 are the VDD voltage divider resistors. The BJT differential pair transistors Q5 and Q6, along with MOSFETs P8, P9, and P10, form an op-amp-less error amplification structure. The BJT differential pair receives the sampled voltage and converts voltage fluctuations into current changes, while MOSFET P10 outputs the PTAT current. Resistors R5, R6, and R7 are the source load resistors for MOSFETs P8, P9, and P10; capacitor C1 is the output compensation capacitor.

[0039] Furthermore, the reference module satisfies the following condition: (W / L) P8 (W / L) P9 =1:1, Among them, (W / L) P8 and (W / L) P9 These are the width-to-length ratios of MOSFETs P8 and P9, respectively. The resistance values ​​of resistors R5, R6, and R7 are equal.

[0040] Therefore, the current flowing through resistor R3 is: ; Among them, V BE5 and V BE6 Let ln be the base-emitter voltage of transistors Q5 and Q6 respectively, where ln is the logarithm of n to the base e, and n is the ratio of the number of transistors Q5 and Q6 connected in parallel. T It is thermal voltage.

[0041] VREF is the base voltage of transistors Q5 and Q6, specifically: ; Because VBE is a negative temperature coefficient voltage in terms of process parameters, V T Since it's a positive temperature coefficient voltage, adjusting the ratio of resistors R12 to R11 can adjust the magnitude of the positive temperature coefficient, thus canceling out the negative temperature coefficient and allowing V to... REF It becomes a zero temperature coefficient voltage, and V REF The resistors divide VDD, thus simultaneously increasing the output reference V. REF Stability with internal power supply VDD.

[0042] Please refer to the appendix. Figure 4 Specifically, the over-temperature protection module includes transistors Q0, Q1, Q2, Q3, and Q4; MOSFETs P11, P12, P13, P14, P15, P16, P17, P18, and P19; MOSFETs N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, HP5, HP6, HP7, HP8, HP9, HP10; MOSFETs HN5, HN6, HN7, HN8, HN9, and HN10; and resistors R13, R14, R15, and R16.

[0043] External power supply VIN is input to the source of MOSFET P11, the source of MOSFET P13, the source of MOSFET P14, the source of MOSFET P15, the source of MOSFET P16, the source of MOSFET P17, the source of MOSFET P18, the source of MOSFET P19, the source of MOSFET HP8, and one end of resistor R16; the pre-regulator module outputs VDD to one end of resistor R13, the reference module outputs reference voltage VREF to one end of resistor R14, and the reference module outputs current PTAT to the gate and drain of MOSFET N5, the gate of MOSFET N6, and the gate of MOSFET N7.

[0044] The gate and drain of MOSFET P11 are electrically connected to the source of MOSFET P12. The gate and drain of MOSFET P12 are electrically connected to the gates of MOSFETs HP5, HP6, HP7, HP9, HP10, and HN5. The other end of resistor R13 is electrically connected to the gates of MOSFETs HN5, HN6, HN7, HN8, and HN9. The source of MOSFET HN5 is electrically connected to the drain of MOSFET N6. The other end of resistor R14 is electrically connected to the base of transistor Q0.

[0045] The gate of MOSFET P13 is electrically connected to the gates of MOSFETs P14, P15, P18, and P19, and the drains of MOSFETs HP5 and HN6, serving as the output terminal to provide a bias voltage BIAS1 to the short-circuit protection module. The drain of MOSFET P13 is electrically connected to the source of MOSFET HP5, and the source of MOSFET HN6 is electrically connected to the drain of MOSFET N7.

[0046] The drain of MOSFET P14 is electrically connected to the source of MOSFET HP6. The drain of MOSFET HP6 is electrically connected to the gate and drain of MOSFET N8, the gate of MOSFET N10, the gate of MOSFET N11, and the gate of MOSFET N12.

[0047] The drain of MOSFET P15 is electrically connected to the drain of MOSFET HN7, the gate of MOSFET P16, and the gate of MOSFET P17. The source of MOSFET HN7 is electrically connected to the collector of transistor Q0. The emitter of transistor Q0 is electrically connected to the base and collector of transistor Q1. The emitter of transistor Q1 is electrically connected to the base and collector of transistor Q2. The emitter of transistor Q2 is electrically connected to the base and collector of transistor Q3. The emitter of transistor Q3 is electrically connected to one end of resistor R15. The other end of resistor R15 is electrically connected to the base and collector of transistor Q4 and the drain of transistor N9.

[0048] The drain of MOSFET P15 is electrically connected to the source of MOSFET HP7. The drain of MOSFET HP7 is electrically connected to the gate of transistor N9 and the drain of MOSFET N10. The drain of MOSFET P17 is electrically connected to the gate of MOSFET HP8 and the drain of MOSFET HN8. The source of MOSFET HN8 is electrically connected to the drain of MOSFET N11. The drain of MOSFET HP8 is electrically connected to the drain of MOSFET HN9 and serves as the output terminal, providing the OTP voltage to the short-circuit protection module. The source of MOSFET HN9 is electrically connected to the drain of MOSFET N12.

[0049] The drain of MOSFET P18 is electrically connected to the source of MOSFET HP9. The drain of MOSFET HP9 is electrically connected to the gate and drain of MOSFET N13 and the gate of MOSFET N14, and serves as the output terminal, outputting VG to the outside. The drain of MOSFET P19 is electrically connected to the source of MOSFET HP10. The drain of MOSFET HP10 is electrically connected to the drain of MOSFET N15 and the gate of MOSFET HN10, and serves as the output terminal, outputting the bias voltage BIAS2 to the gate of high-voltage MOSFET HN100. The other end of resistor R16 is electrically connected to the drain of MOSFET HN10. The source of MOSFET HN10 is electrically connected to the gate of MOSFET N15 and the drain of MOSFET N14.

[0050] The sources of MOSFETs N5, N6, N7, N8, N9, N10, N11, N12, N13, and N14, as well as the emitter of transistor Q4, are all grounded.

[0051] Transistors Q0, HN5, HN6, HN7, HN8, and HN9 are bias transistors, using zero-temperature coefficient voltages VDD and V... REF As a bias input, errors are avoided. MOSFETs N5, N6, and N7, along with MOSFETs N8, N11, and N12, form two pairs of NMOS current mirror structures to replicate the PTAT current. MOSFETs P13, P14, P15, P18, and P19 form a PMOS current mirror structure to replicate the PTAT current to the enhancement-mode CTAT voltage sensing branch composed of transistors Q1, Q2, Q3, Q4, and resistor R15. Resistor R15 is only used to raise the VZ potential. MOSFETs P11 and P12 control the conduction state of MOSFETs HP5, HP6, HP7, HP8, and HP9 through the gate-source voltage difference formed by diode connection, setting the operating point of MOSFET P13 and controlling the magnitude of the bias voltage Bias1.

[0052] The voltage drop V generated by shorting the base and collector of transistors Q1, Q2, Q3, and Q4 in series is as follows: BE As the sensing voltage, since the temperature coefficient of a single VBE at T=300K is: ; The connection of four transistors in series amplifies this slope to approximately -6mV / K. A larger slope means that near the critical temperature point, a small temperature change can produce a sufficiently large voltage change, thus giving the sensed voltage a strong CTAT characteristic.

[0053] Furthermore, the transconductance of the transistor gm = I C / V T , where I C It is the collector current, V T It is thermal voltage. If I C Since I is a constant, gm decreases as temperature increases. However, if I... C It refers to the PTAT current. Since the PTAT current is directly proportional to the absolute temperature, it increases with increasing temperature. Therefore, gm = I. C / V T ∝T / T, where ∝ indicates a direct proportional relationship between the two quantities. In this case, gm is a constant, thus remaining constant with temperature changes. The constancy of gm stabilizes the transistor's gain and sensitivity, reducing the impact of temperature fluctuations on circuit performance. In other words, the PTAT current can compensate for the decreasing trend of the transistor's transconductance gm with increasing temperature.

[0054] When I C When V is constant, the transistor's V BE The first and second derivatives with respect to temperature T are: ; ; When I C When it is the PTAT current, i.e., I C When V = N*T (where N is a constant), BE The first and second derivatives with respect to temperature T are: ; ; Where m≈-3 / 2, V T It is thermal voltage, E g q is the band gap energy of silicon, k is the Boltzmann constant, and q is the charge of the electron.

[0055] Therefore, under the influence of PTAT current, V BE The rate of change of the first-order temperature coefficient with temperature, i.e., the second-order temperature derivative, is smaller. In other words, V BE The curvature of the first-order temperature coefficient curve decreases. V... BE The change is closer to linear, reducing the drift of the trigger point and improving the accuracy and consistency of temperature detection.

[0056] As the circuit's operating temperature rises, the PTAT current increases with temperature, and the current flowing through MOSFETs N6 and N7 also increases accordingly. Therefore, the gate potentials of MOSFETs P13 and P15 through the current mirror structure are also raised. Ignoring the slight voltage drop generated when transistors Q0 and HN7 are turned on, the VZ voltage can be considered approximately equal to the sensing voltage. Before the temperature rises to the critical point, VZ = 4 * V. BE +I Z *R15; Where IZ is the PTAT current replicated by the current mirror of MOSFET P15. Since V BE Due to its negative temperature characteristic, VZ will slowly decrease as the temperature rises. When the temperature reaches the critical point, MOSFET P16 will turn on instantaneously, the drain potential of MOSFET N10 will change from low to high, turning on MOSFET N9. Transistor Q4 will be short-circuited, pulling VZ down to a lower potential. At this point, VZ = 3 * V BE +I Z *R15. To restore the VZ potential during cooling, the circuit must lower the temperature to an even lower level to raise V. BE This allows VZ to return to its original level, thus creating a wider hysteresis range.

[0057] OTP is the over-temperature protection output voltage. When the VZ voltage rises to the critical point potential, MOSFET P17 turns on and pulls up VCC, turning off MOSFET HP8. The OTP potential flips to output a low-level over-temperature signal. After the circuit temperature drops to the safe point, MOSFET P17 turns off again, MOSFET HP8 turns on and pulls up VCC, and the OTP potential returns to a high level.

[0058] MOSFETs P19, HP10, R16, HN10, and N15 form a VGS / R type bias to generate the bias voltage Bias2. MOSFETs P19 and HP10 are active loads, and MOSFET N14 is the tail current source controlled by MOSFET N13.

[0059] Please refer to the appendix. Figure 5 Specifically, the enable module includes Schmitt trigger U100, inverter U101, inverter U102, inverter U105, NAND gate U103, NAND gate U104 and MOSFET N21.

[0060] The output of the pre-regulator module outputs a bias voltage VNG to the gate of MOSFET N21. The drain of MOSFET N21 is electrically connected to the input of Schmitt trigger U100. Inverters U101 and U102 are connected in series between the output of Schmitt trigger U100 and the first input of NAND gate U103. The source of MOSFET N21 and the second input of NAND gate U103 are both grounded.

[0061] The output terminal of the NAND gate is electrically connected to the first input terminal of the NAND gate U104. The output control signal POR_SET of the power-on reset module is sent to the second input terminal of the NAND gate U104. The output terminal of the NAND gate U104 is electrically connected to the input terminal of the inverter U105 and outputs the enable signal ENL to the pre-regulator module. The output terminal of the inverter U105 outputs the enable signal ENLB to the pre-regulator module.

[0062] VNG is the bias voltage generated by the pre-regulator module. When MOSFET N21 receives the VNG signal, it turns on and pulls the input of Schmitt trigger U100 to ground. The NAND gate U103 outputs a high level. When the internal power supply VDD of the pre-regulator module is generated normally, the signal POR_SET outputs a high level signal, enabling ENL to output a low level signal and enabling ENLB to output a high level signal.

[0063] Please refer to the appendix. Figure 6 Specifically, the power-on reset module includes MOSFETs P20, P21, P22, P23, P24, P25, P26, P27, P28, N16, N17, N18, N19, and N20, capacitors C2 and C3, and resistor R17.

[0064] The pre-regulator module outputs VDD to the sources of MOSFETs P20, P21, P22, P23, P24, P25, P26, P27, and P28.

[0065] The gate and drain of MOSFET P20 are electrically connected to the gate of MOSFET N16 and the drain of MOSFET P21. The gate of MOSFET P21 is electrically connected to the gate of MOSFET P22 and the drain of MOSFET N16. The drain of MOSFET P22 is electrically connected to one end of resistor R17, one end of capacitor C2, the drain of MOSFET P23, the gate of MOSFET P24, and the gate of MOSFET N17. The gate of MOSFET P23 is electrically connected to the drain of MOSFET P24, the drain of MOSFET N17, the gate of MOSFET P25, and the gate of MOSFET N18. The drains of MOSFET P25 and MOSFET N18 are both electrically connected to the drain of MOSFET P26, one end of capacitor C3, the gate of MOSFET P27, and the gate of MOSFET N19. The drain of MOSFET P27 is electrically connected to the gate of MOSFET P26, the drain of MOSFET N19, the gate of MOSFET P28, and the gate of MOSFET N20. The drain of MOSFET P28 is electrically connected to the drain of MOSFET N20, and the control signal POR_SET is output to the enable module as the output terminal.

[0066] The sources of MOSFETs N16, N17, N18, N19, and N20, as well as the other end of resistor R17, capacitor C2, and capacitor C3, are all grounded.

[0067] VDD is the internal power supply generated by the pre-regulator. During the power-up phase, the power supply VDD starts to rise from 0V. When it is at a low voltage, VT1 follows VDD's rise through the self-biasing of MOSFET P20. MOSFET N16 gradually turns on, pulling VT2 low. Subsequently, MOSFET P21 turns on, pulling up VT1 and strengthening the conduction of MOSFET N16, which strongly pulls VT2 low, forming positive feedback to accelerate the switching. MOSFET P22 turns on, causing VT3 to be raised to VDD. MOSFETs P23, P24, P25, N17, and N18, along with MOSFETs P26, P27, P28, N19, and N20, form two sets of Schmitt triggers. VT3 outputs a high-level signal POR_SET through these two sets of Schmitt triggers. After VDD is de-energized, VT1 decreases with VDD, VT2 remains low, VT3 is pulled to ground by resistor R17, and POR_SET outputs a low-level signal; capacitors C2 and C3 are delay capacitors.

[0068] Please refer to the appendix. Figure 7 Specifically, the short-circuit protection module includes MOSFETs P29, P30, P31, P32, P33, and P34, and diode D0.

[0069] External power supply VIN is input to the source of MOSFET P29, the source of MOSFET P30, the source of MOSFET P31, the source of MOSFET P32, and the cathode of diode D0; the pre-regulation module outputs an enable signal ENH to the gate of MOSFET P29; the over-temperature protection module outputs voltage OTP to the gate of MOSFET P30; and the over-temperature protection module outputs bias voltage BIAS1 to the gate of MOSFET P31.

[0070] The gate and drain of MOSFET P32 are electrically connected to the source of MOSFET P33, and the gate and drain of MOSFET P33 are electrically connected to the source of MOSFET P34.

[0071] The drain of MOSFET P29 is electrically connected to the drain of MOSFET P30, the drain of MOSFET P31, the gate and drain of MOSFET P34, and the diode D0. It is also electrically connected as the output terminal to the gate of high-voltage MOSFET HP100 and the drain of high-voltage MOSFET HN100.

[0072] The output Y of the short-circuit protection module is connected to the gate of the power transistor HP100 and is jointly controlled by the short-circuit protection module and the over-temperature protection module. When BIAS1 is working normally, the gate of the power transistor HP100 is biased by the constant pull-up current of the pull-up MOSFET P31. When the over-temperature protection is triggered, the OTP signal flips from high to low, the MOSFET P30 is fully turned on, the gate of the power transistor HP100 is pulled up to VIN, and the power transistor is turned off. When the enable signal ENH is low, the MOSFET P29 is fully turned on, the gate of the power transistor HP100 is pulled up to VIN, and the power transistor is turned off.

[0073] MOSFETs P32, P33, and P34 are clamping PMOS transistors, with a total clamping voltage V. clamp ≈3*(|V thp |+Δ), where V thp Δ is the PMOS threshold voltage, and Δ is the MOS overdrive voltage. Diode D0 is a Zener diode. The output short-circuit protection in this embodiment is not a traditional fixed constant current limiting protection, but rather serves to limit the peak current.

[0074] When OUT is short-circuited, the error amplifier U0 strongly pulls down the gate voltage of the power transistor HP100. At this time, the soft clamp formed by the three PMOS transistors with their gates and drains shorted in series initially limits the rise slope of the short-circuit current. If the gate voltage of the power transistor HP100 continues to be pulled down until the voltage difference between it and VIN exceeds the breakdown voltage of the Zener diode, the Zener diode will immediately conduct, precisely clamping the gate voltage across VIN-VZENER, where VZENER is the Zener breakdown voltage. At this point, the gate voltage cannot be pulled down further, and the peak current is thus limited. Because the power transistor is not turned off during the short circuit, the clamping mechanism itself is passive, voltage-dependent, and independent of current sampling. Therefore, when the short-circuit event disappears, this circuit can automatically resume normal operation.

[0075] Please refer to the appendix. Figure 8 Specifically, the error amplifier U0 includes MOSFETs P35, P36, P37, P39, N21, N22, N23, and N24.

[0076] The pre-regulator module outputs VDD to the source of MOSFET P35, the source of MOSFET P36, the source of MOSFET P37, and the source of MOSFET P39. The reference module outputs reference voltage VREF1 to the gate of MOSFET N21. The other end of resistor R101 is electrically connected to the gate of MOSFET N22. The external signal VG is input to the gates of MOSFET N23 and MOSFET N24.

[0077] The gate and drain of MOSFET P35 are electrically connected to the gate of MOSFET P36 and the drain of MOSFET N21. The source of MOSFET N21 is electrically connected to the drain of MOSFET N23 and the source of MOSFET N22. The drain of MOSFET P36 is electrically connected to the gate and drain of MOSFET P37, the gate of MOSFET P38, and the drain of MOSFET N22. The drain of MOSFET P38 is electrically connected to the drain of MOSFET N24 and serves as the output terminal, electrically connected to the source of high-voltage MOSFET HN100. The sources of MOSFETs N23 and N24 are both grounded.

[0078] MOSFETs P35, P36, N21, N22, and N23 form a five-transistor OTA (Over-The-Air) structure. MOSFET P38 is the output pull-up transistor, MOSFET N24 is the output pull-down transistor, and MOSFET P37 is the auxiliary pull-up transistor. When VIN is less than the minimum operating voltage, the LDO (Low-Density Logic Controller) cannot operate normally. MOSFET P37 provides a pull-up to ensure that MOSFET P38 is turned off. When VIN is greater than the operating voltage, MOSFET P38 is turned on, and the error amplifier U0 operates normally.

[0079] Please refer to the appendix. Figure 9 , attached Figure 9 The circuit function simulation diagram for the process of input VIN rising from 14V to 36V is attached. Figure 9 It can be seen that when VIN rises steadily to a level greater than the minimum operating voltage, Vdd outputs a stable 2.56V, enabling the high signal to follow VIN, the reference voltage outputs a stable 1.19V, and the output voltage stabilizes at 12.1V; that is, the circuit can be directly connected to a high voltage input and can work directly under a wide range of high voltage VIN, the internal power supply and reference voltage are stable, and the LDO function is normal.

[0080] Please refer to the appendix. Figure 10 , attached Figure 10 The simulation diagram shows the current limiting effect of the circuit when OUT is pulled down from 12V to ground. (See attached diagram.) Figure 10 As can be seen, with the pull-down of the OUT voltage, the rate of change of the short-circuit current gradually decreases, and the current eventually stabilizes at around 450mA.

[0081] The high-voltage LDO regulator disclosed in this embodiment limits the short-circuit current to a safe peak value of approximately 450mA, and the power transistor remains on throughout the entire VOUT pull-down process without being turned off. This current limiting effect is not a traditional constant current limiting, but rather a peak current limiting achieved through gate voltage clamping.

[0082] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A high-voltage LDO regulator with output short-circuit protection, characterized in that, It includes a pre-regulator module, a reference module, an enable module, a power-on reset module, an over-temperature protection module, a short-circuit protection module, an error amplifier U0, a high-voltage MOSFET HP100, a high-voltage MOSFET HN100, and resistors R100, R101, and R102. An external power supply VIN is input to one end of the pre-regulator module, the short-circuit protection module, and the resistor R100. The pre-regulator module outputs VDD to the power input terminals of the reference module, the over-temperature protection module, the power-on reset module, and the error amplifier U0. The output terminals of the pre-regulator module and the power-on reset module respectively output bias voltage VNG and control signal POR_SET to the enable module. The enable module outputs enable signals ENL and ENLB to the pre-regulator module. The pre-regulator module outputs enable signal ENH to the short-circuit protection module. The reference module outputs reference voltage VREF and reference voltage VREF1 to the over-temperature protection module and the inverting input terminal of error amplifier U0 respectively. The over-temperature protection module outputs bias voltage BIAS2 to the gate of high-voltage MOSFET HN100. The over-temperature protection module outputs bias voltage BIAS1 and voltage OTP to the short-circuit protection module. The output terminal of the short-circuit protection module is electrically connected to the gate and drain of high-voltage MOSFET HP100 and high-voltage MOSFET HN100. The other end of resistor R100 is electrically connected to the source of high-voltage MOSFET HP100. The drain of high-voltage MOSFET HP100 is electrically connected to one end of resistor R101 and serves as the output terminal OUT connected to the outside. The other end of resistor R101 is electrically connected to the non-inverting input terminal of error amplifier U0 and one end of resistor R102. The output terminal of error amplifier U0 is electrically connected to the source of high-voltage MOSFET HN100. The other end of resistor R102 is grounded. The short-circuit protection module includes MOSFETs P29, P30, P31, P32, P33, and P34, and diode D0; An external power supply VIN is input to the source of MOSFET P29, the source of MOSFET P30, the source of MOSFET P31, the source of MOSFET P32, and the cathode of diode D0; the pre-regulation module outputs an enable signal ENH to the gate of MOSFET P29; the over-temperature protection module outputs voltage OTP to the gate of MOSFET P30; and the over-temperature protection module outputs bias voltage BIAS1 to the gate of MOSFET P31. The gate and drain of the MOS transistor P32 are electrically connected to the source of the MOS transistor P33, and the gate and drain of the MOS transistor P33 are electrically connected to the source of the MOS transistor P34. The drain of MOSFET P29 is electrically connected to the drain of MOSFET P30, the drain of MOSFET P31, the gate and drain of MOSFET P34, and the diode D0, and is also electrically connected as the output terminal to the gate of high-voltage MOSFET HP100 and the drain of high-voltage MOSFET HN100.

2. The high-voltage LDO regulator with output short-circuit protection according to claim 1, characterized in that, The pre-regulator module includes MOSFETs P0, P1, P2, P3, P4, P5, P6, P7, N0, N3, N4, HP1, HP2, HP3, HP4, HN1, HN2, HN3, HN4, resistors R0, R1, R2, R3, R4, and capacitor C0. An external power supply VIN is input to one end of resistor R0, the source of MOSFET P1, the source of MOSFET P2, the source of MOSFET P3, the source of MOSFET P4, the source of MOSFET P5, the source of MOSFET P6, the source of MOSFET P7, the source of MOSFET HP4, one end of capacitor C0, and one end of resistor R4; the enable signal ENLB is input to the gate of MOSFET HN2, the enable signal ENL is input to the gate of MOSFET HN3, and the external IN1 signal is input to the gate of MOSFET P0; The other end of resistor R0 is electrically connected to the drain of MOSFET N0 and the gate of MOSFET HN1; the gate and drain of MOSFET P1 are electrically connected to the gates of MOSFET P2, MOSFET P5, MOSFET P6, and MOSFET P7 and one end of resistor R2; the other end of resistor R2 is electrically connected to the drain of MOSFET HN1, the gate of MOSFET HP1, the gate of MOSFET HP2, and the gate of MOSFET HP3; the source of MOSFET HN1 is electrically connected to one end of resistor R1 and the gate of MOSFET N0. The drain of MOS transistor P2 is electrically connected to the source of MOS transistor HP1, the drain of MOS transistor P3, and the gate of MOS transistor P4. The drain of MOS transistor HP1 is electrically connected to the drain of MOS transistor HN2. The gate of MOSFET P3 is electrically connected to the drain of MOSFET P4, the drain of MOSFET P5, and the source of MOSFET HP2, and outputs an enable signal ENH to the short-circuit protection module as an output terminal. The drain of MOSFET HP2 is electrically connected to the drain of MOSFET HN3. The drain of MOSFET P6 is electrically connected to the source of MOSFET HP3. The drain of MOSFET HP3 is electrically connected to the gate of MOSFET HN4, the gate and drain of MOSFET N3, and the gate of MOSFET N4, and serves as the output terminal to output the bias voltage VNG to the enable module. The drain of MOSFET P7 is electrically connected to one end of resistor R3, the source of MOSFET N2, the gate of MOSFET HP4, and the drain of MOSFET HN4. The source of MOSFET HN4 is electrically connected to the drain of MOSFET N4 and the drain of MOSFET P0. The other end of capacitor C0 is electrically connected to the other end of resistor R3 and the gate of MOSFET N2. The drain of MOSFET N2 is electrically connected to the other end of resistor R4. The drain of MOSFET HP2 is electrically connected to the source of MOSFET P0 and outputs VDD to the power input terminals of the reference module, over-temperature protection module, power-on reset module and error amplifier U0. The source terminals of MOSFET N0, MOSFET HN2, MOSFET HN3, MOSFET N3, MOSFET N4, and the other end of resistor R1 are all grounded.

3. The high-voltage LDO regulator with output short-circuit protection according to claim 1, characterized in that, The reference module includes MOSFETs P8, P9, and P10, transistors Q5 and Q6, resistors R8, R9, R10, R11, R12, R5, R6, and R7, and capacitor C1. The pre-regulated voltage module outputs VDD to one end of resistor R8, one end of resistor R5, one end of resistor R6, and one end of resistor R7; The other end of resistor R8 is electrically connected to one end of resistor R1, the base of transistor Q5, and the base of transistor Q6, and serves as the output terminal to output the reference voltage VREF to the over-temperature protection module. The other end of resistor R9 is electrically connected to one end of resistor R10, and serves as the output terminal to output the reference voltage VREF1 to the inverting input terminal of error amplifier U0. The other end of resistor R5 is electrically connected to the source of MOSFET P8. The gate and drain of MOSFET P8 are electrically connected to the collector of transistor Q5, the gate of MOSFET P1, and the gate of MOSFET P2. The emitter of transistor Q5 is electrically connected to one end of resistor R11. The other end of resistor R11 is electrically connected to the emitter of transistor Q6 and one end of resistor R12. The other end of resistor R6 is electrically connected to the source of MOSFET P9. The drain of MOSFET P1 is electrically connected to the collector of transistor Q6 and one end of capacitor C1, and is connected to the external circuit as output terminal OUT1. The other end of resistor R7 is electrically connected to the source of MOSFET P10. The drain of MOSFET P10 outputs current PTAT to the over-temperature protection module. The other ends of resistor R10, resistor R12, and capacitor C1 are all grounded.

4. The high-voltage LDO regulator with output short-circuit protection according to claim 3, characterized in that, The following conditions must be met: (W / L) P8 :(W / L) P9 =1:1, Among them, (W / L) P8 and (W / L) P9 These are the width-to-length ratios of MOSFETs P8 and P9, respectively. The resistance values ​​of resistors R5, R6, and R7 are equal.

5. The high-voltage LDO regulator with output short-circuit protection according to claim 1, characterized in that, The over-temperature protection module includes transistors Q0, Q1, Q2, Q3, Q4, MOSFETs P11, P12, P13, P14, P15, P16, P17, P18, P19, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, HP5, HP6, HP7, HP8, HP9, HP10, HN5, HN6, HN7, HN8, HN9, HN10, and resistors R13, R14, R15, and R16. An external power supply VIN is input to the source of MOSFETs P11, P13, P14, P15, P16, P17, P18, P19, and HP8, and one end of resistor R16; the pre-regulator module outputs VDD to one end of resistor R13, the reference module outputs a reference voltage VREF to one end of resistor R14, and the reference module outputs a current PTAT to the gate and drain of MOSFET N5, the gate of MOSFET N6, and the gate of MOSFET N7; The gate and drain of MOSFET P11 are electrically connected to the source of MOSFET P12. The gate and drain of MOSFET P12 are electrically connected to the gates of MOSFETs HP5, HP6, HP7, HP9, HP10, and HN5. The other end of resistor R13 is electrically connected to the gates of MOSFETs HN5, HN6, HN7, HN8, and HN9. The source of MOSFET HN5 is electrically connected to the drain of MOSFET N6. The other end of resistor R14 is electrically connected to the base of transistor Q0. The gate of MOSFET P13 is electrically connected to the gates of MOSFETs P14, P15, P18, and P19, as well as the drain of MOSFET HP5 and the drain of MOSFET HN6, and serves as the output terminal to output the bias voltage BIAS1 to the short-circuit protection module; the drain of MOSFET P13 is electrically connected to the source of MOSFET HP5, and the source of MOSFET HN6 is electrically connected to the drain of MOSFET N7. The drain of MOSFET P14 is electrically connected to the source of MOSFET HP6, and the drain of MOSFET HP6 is electrically connected to the gate and drain of MOSFET N8, the gate of MOSFET N10, the gate of MOSFET N11, and the gate of MOSFET N12. The drain of MOSFET P15 is electrically connected to the drain of MOSFET HN7, the gate of MOSFET P16, and the gate of MOSFET P17. The source of MOSFET HN7 is electrically connected to the collector of transistor Q0. The emitter of transistor Q0 is electrically connected to the base and collector of transistor Q1. The emitter of transistor Q1 is electrically connected to the base and collector of transistor Q2. The emitter of transistor Q2 is electrically connected to the base and collector of transistor Q3. The emitter of transistor Q3 is electrically connected to one end of resistor R15. The other end of resistor R15 is electrically connected to the base and collector of transistor Q4 and the drain of transistor N9. The drain of MOSFET P15 is electrically connected to the source of MOSFET HP7; the drain of MOSFET HP7 is electrically connected to the gate of transistor N9 and the drain of MOSFET N10; the drain of MOSFET P17 is electrically connected to the gate of MOSFET HP8 and the drain of MOSFET HN8; the source of MOSFET HN8 is electrically connected to the drain of MOSFET N11; the drain of MOSFET HP8 is electrically connected to the drain of MOSFET HN9 and serves as the output terminal, outputting voltage OTP to the short-circuit protection module; the source of MOSFET HN9 is electrically connected to the drain of MOSFET N12. The drain of MOSFET P18 is electrically connected to the source of MOSFET HP9. The drain of MOSFET HP9 is electrically connected to the gate and drain of MOSFET N13 and the gate of MOSFET N14, and serves as the output terminal to output VG to the outside. The drain of MOSFET P19 is electrically connected to the source of MOSFET HP10. The drain of MOSFET HP10 is electrically connected to the drain of MOSFET N15 and the gate of MOSFET HN10, and serves as the output terminal to output the bias voltage BIAS2 to the gate of high-voltage MOSFET HN100. The other end of resistor R16 is electrically connected to the drain of MOSFET HN10. The source of MOSFET HN10 is electrically connected to the gate of MOSFET N15 and the drain of MOSFET N14. The sources of MOSFETs N5, N6, N7, N8, N9, N10, N11, N12, N13, and N14, as well as the emitter of transistor Q4, are all grounded.

6. The high-voltage LDO regulator with output short-circuit protection according to claim 1, characterized in that, The enabling module includes a Schmitt trigger U100, an inverter U101, an inverter U102, an inverter U105, a NAND gate U103, a NAND gate U104, and a MOSFET N21; The output terminal of the pre-regulator module outputs a bias voltage VNG to the gate of the MOS transistor N21. The drain of the MOS transistor N21 is electrically connected to the input terminal of the Schmitt trigger U100. The inverters U101 and U102 are connected in series between the output terminal of the Schmitt trigger U100 and the first input terminal of the NAND gate U103. The source of the MOS transistor N21 and the second input terminal of the NAND gate U103 are both grounded. The output terminal of the NAND gate and the first input terminal of the NAND gate U104 are electrically connected. The output control signal POR_SET of the power-on reset module is sent to the second input terminal of the NAND gate U104. The output terminal of the NAND gate U104 is electrically connected to the input terminal of the inverter U105 and outputs an enable signal ENL to the pre-regulation module. The output terminal of the inverter U105 outputs an enable signal ENLB to the pre-regulation module.

7. The high-voltage LDO regulator with output short-circuit protection according to claim 1, characterized in that, The power-on reset module includes MOSFETs P20, P21, P22, P23, P24, P25, P26, P27, P28, N16, N17, N18, N19, and N20, capacitors C2 and C3, and resistor R17. The pre-regulator module outputs VDD to the sources of MOSFETs P20, P21, P22, P23, P24, P25, P26, P27, and P28. The gate and drain of MOSFET P20 are electrically connected to the gate of MOSFET N16 and the drain of MOSFET P21. The gate of MOSFET P21 is electrically connected to the gate of MOSFET P22 and the drain of MOSFET N16. The drain of MOSFET P22 is electrically connected to one end of resistor R17, one end of capacitor C2, the drain of MOSFET P23, the gate of MOSFET P24, and the gate of MOSFET N17. The gate of MOSFET P23 is electrically connected to the drain of MOSFET P24, the drain of MOSFET N17, the gate of MOSFET P25, and the drain of MOSFET P26. The gate of S-channel transistor N18 is electrically connected; the drains of MOSFET P25 and MOSFET N18 are both electrically connected to the drain of MOSFET P26, one end of capacitor C3, the gate of MOSFET P27, and the gate of MOSFET N19; the drain of MOSFET P27 is electrically connected to the gate of MOSFET P26, the drain of MOSFET N19, the gate of MOSFET P28, and the gate of MOSFET N20; the drain of MOSFET P28 is electrically connected to the drain of MOSFET N20, and outputs the control signal POR_SET to the enable module as the output terminal; The sources of MOSFETs N16, N17, N18, N19, and N20, as well as the other end of resistor R17, capacitor C2, and capacitor C3, are all grounded.

8. The high-voltage LDO regulator with output short-circuit protection according to claim 1, characterized in that, The error amplifier U0 includes MOSFETs P35, P36, P37, P39, N21, N22, N23, and N24. The pre-regulator module outputs VDD to the source of MOSFET P35, the source of MOSFET P36, the source of MOSFET P37, and the source of MOSFET P39. The reference module outputs reference voltage VREF1 to the gate of MOSFET N21. The other end of the resistor R101 is electrically connected to the gate of MOSFET N22. The external signal VG is input to the gates of MOSFET N23 and MOSFET N24. The gate and drain of MOSFET P35 are electrically connected to the gate of MOSFET P36 and the drain of MOSFET N21. The source of MOSFET N21 is electrically connected to the drain of MOSFET N23 and the source of MOSFET N22. The drain of MOSFET P36 is electrically connected to the gate and drain of MOSFET P37, the gate of MOSFET P38, and the drain of MOSFET N22. The drain of MOSFET P38 is electrically connected to the drain of MOSFET N24 and serves as the output terminal, electrically connected to the source of high-voltage MOSFET HN100. The sources of both MOS transistor N23 and MOS transistor N24 are grounded.

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