A bandgap reference voltage source with segmented compensation and high power supply rejection ratio

Abstract

The application discloses a band gap reference voltage source with segmented compensation and high power supply rejection ratio, and belongs to the field of integrated circuits, and particularly relates to application in a system on chip. The band gap reference voltage source comprises a band gap reference core circuit, a segmented compensation circuit and a starting circuit. The band gap reference core circuit generates a reference voltage independent of temperature and voltage; a switch is used to select the segmented compensation circuit to be connected, so that a negative temperature coefficient current generated by the segmented compensation circuit flows into the band gap reference core circuit, and the accuracy of the reference voltage is further improved; wherein the band gap reference core circuit uses a three-stage operational amplifier to improve loop gain, and greatly improves the power supply rejection ratio at low frequency. A transistor is used as an input pair of the first-stage operational amplifier, so that the offset voltage is effectively reduced, the accuracy of the reference voltage is higher, and the temperature drift is lower, so that the band gap reference voltage source with segmented compensation, high accuracy and high power supply rejection ratio is realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a segmented compensated bandgap reference voltage source with a high power supply rejection ratio. Background Technology

[0002] With the continuous advancement of modern integrated circuit technology, bandgap reference voltage sources, as a key voltage reference source, have been widely used in many integrated circuit systems, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and power management circuits.

[0003] Traditional bandgap reference voltage sources often employ a single current source and the forward voltage drop principle of a diode. While they can provide a stable voltage under certain conditions, the accuracy of temperature compensation is often limited due to process variations and environmental factors, especially over a wide temperature range. Therefore, segmented compensation is required.

[0004] Traditional bandgap voltage references may experience output voltage stability issues when exposed to power supply voltage fluctuations, especially in the presence of significant power supply noise or ripple. A low power supply rejection ratio (PSRR) can lead to instability in the reference voltage, thereby impacting overall system performance, particularly in low-noise, high-precision applications. Summary of the Invention

[0005] The purpose of this invention is to provide a segmented compensated bandgap reference voltage source with a high power supply rejection ratio, so as to provide a high-precision on-chip reference voltage source that is not affected by power supply noise.

[0006] To solve the above-mentioned technical problems, the present invention provides a bandgap reference voltage source with segmented compensation and high power supply rejection ratio, comprising: a bandgap reference core circuit, a segmented compensation circuit, and a startup circuit;

[0007] The bandgap reference core circuit is used to generate a reference voltage that is independent of temperature and power supply voltage, while using high loop gain to achieve a high power supply rejection ratio.

[0008] The segmented compensation circuit generates a negative temperature coefficient current and transmits it to the bandgap reference core circuit for compensation, thereby achieving fine adjustment of the reference voltage, further improving the accuracy of the voltage output, and ensuring high-precision reference voltage output under different operating conditions.

[0009] The startup circuit is used to provide appropriate current during the power-on process of the circuit, so that the bandgap reference core circuit can quickly jump out of the degenerate state and enter a stable working state, ensuring the reliability of the circuit during startup.

[0010] In one embodiment, the bandgap reference core circuit includes a first operational amplifier to a third operational amplifier, a first resistor to a fifth resistor, a first MOS transistor, a first NPN bipolar transistor, a second NPN bipolar transistor, a first capacitor, a second capacitor, and a first trimming resistor.

[0011] The non-inverting input of the first operational amplifier is simultaneously connected to the first terminal of the first resistor and the collector of the first NPN bipolar transistor; the inverting input of the first operational amplifier is simultaneously connected to the first terminal of the second resistor and the collector of the second NPN bipolar transistor; the non-inverting output of the first operational amplifier is connected to the non-inverting input of the second operational amplifier, and the inverting output of the first operational amplifier is connected to the inverting input of the second operational amplifier; the non-inverting input of the third operational amplifier is simultaneously connected to the non-inverting output of the second operational amplifier and the first terminal of the fourth resistor, the second terminal of the fourth resistor is connected to the first terminal of the first capacitor, the inverting input of the third operational amplifier is connected to the inverting output of the second operational amplifier, and the output terminal is simultaneously connected to the second terminal of the first capacitor, the first terminal of the fifth resistor, and the gate of the first MOSFET; the source of the first MOSFET is connected to the power supply VDD, and the drain is connected to the second terminal of the second capacitor; the second terminal of the fifth resistor is connected to the first terminal of the second capacitor; the base of the first NPN bipolar transistor is simultaneously connected to the base of the second NPN bipolar transistor, the second terminal of the first resistor, the second terminal of the second resistor, and the bandgap reference voltage V generated by the bandgap reference voltage source. BG The emitter of the first NPN bipolar transistor is connected to the first terminal of the third resistor; the second terminal of the third resistor is connected to both the emitter of the second NPN bipolar transistor and the first terminal of the first adjustment resistor; the second terminal of the first adjustment resistor is grounded; the second terminal of the second capacitor and the drain of the first MOSFET are both connected to the bandgap reference voltage V generated by the bandgap reference voltage source. BG .

[0012] In one embodiment, the first operational amplifier includes a seventh NPN bipolar transistor to a tenth NPN bipolar transistor, a tenth resistor to a fourteenth resistor, and a third capacitor;

[0013] The emitter of the seventh NPN transistor is grounded, and its base is connected to both its own collector and the base of the eighth NPN transistor. The collector is connected to the power supply VDD through the tenth resistor. The emitter of the eighth NPN transistor is grounded through the eleventh resistor, and its collector is connected to both the emitters of the ninth and tenth NPN transistors. The base of the ninth NPN transistor is connected to the non-inverting input terminal INP1, and its collector is connected to the inverting output terminal OUTN1, the first terminal of the third capacitor, and the second terminal of the twelfth resistor. The base of the tenth NPN transistor is connected to the inverting input terminal INP1, and its collector is connected to the non-inverting output terminal OUTP1, the second terminal of the fourteenth resistor, and the second terminal of the thirteenth resistor. The second terminal of the third capacitor is connected to the first terminal of the fourteenth resistor. The first terminals of the twelfth and thirteenth resistors are both connected to the power supply VDD.

[0014] In one embodiment, the second operational amplifier includes an eleventh to thirteenth NPN bipolar transistor, a second MOSFET and a third MOSFET, a fifteenth to a sixteenth resistor, and a fourth capacitor. The base of the eleventh NPN transistor is connected to a bias voltage, its emitter is grounded through the sixteenth resistor, and its collector is connected to the emitters of both the twelfth and thirteenth NPN transistors. The base of the twelfth NPN transistor is connected to the non-inverting input terminal INP2, and its collector is connected to the inverting output terminal OUTN2, the first terminal of the fourth capacitor, the drain of the second MOSFET, the gate of the second MOSFET, and the gate of the third MOSFET. The base of the thirteenth NPN transistor is connected to the inverting input terminal INP2, and its collector is connected to the non-inverting output terminal OUTP2, the second terminal of the fifteenth resistor, and the drain of the third MOSFET. The second terminal of the fourth capacitor is connected to the first terminal of the fifteenth resistor. The sources of the second and third MOSFETs are connected to the power supply VDD.

[0015] In one embodiment, the third operational amplifier includes a fourth to an eleventh MOS transistor; the gate of the fourth MOS transistor is connected to the non-inverting output terminal INP3, and its drain is simultaneously connected to the drain, gate, and gate of the sixth MOS transistor; the sources of the sixth and eighth MOS transistors are simultaneously grounded; the drain of the eighth MOS transistor is connected to the drain of the tenth MOS transistor; the source of the tenth MOS transistor is connected to the power supply VDD; the gate of the fifth MOS transistor is connected to the inverting input terminal INN3, and its drain is simultaneously connected to the drain, gate, and gate of the seventh and ninth MOS transistors; the sources of the seventh and ninth MOS transistors are simultaneously grounded; the drains of the ninth and eleventh MOS transistors are simultaneously connected to the output terminal OUT3; the source of the eleventh MOS transistor is connected to VDD, and its gate is connected to the gate of the tenth MOS transistor.

[0016] In one embodiment, the first trimming resistor is used to generate a voltage with a low temperature drift coefficient by adjusting the resistance value of the first trimming resistor after a temperature and power supply-independent voltage is generated in the bandgap.

[0017] In one embodiment, the segmented compensation circuit includes a third NPN bipolar transistor, a sixth to eighth resistor, a second adjustment resistor, a first switch, and a second switch; the second terminals of the sixth and seventh resistors are grounded; the emitter of the third NPN bipolar transistor is connected to the first terminal of the sixth resistor, the base is connected to the first terminal of the seventh resistor and the second terminal of the eighth resistor, and the collector is connected to the second terminal of the second adjustment resistor; the first terminal of the second adjustment resistor is connected to the second terminal of the first switch; the first terminal of the eighth resistor is connected to the second terminal of the second switch; the first terminals of both the first and second switches are connected to the bandgap reference voltage V generated by the bandgap reference voltage source. BG .

[0018] In one embodiment, the startup circuit includes a fourth NPN bipolar transistor to a sixth NPN bipolar transistor and a ninth resistor; the emitters of the fourth, fifth, and sixth NPN bipolar transistors are simultaneously grounded; the base of the fourth NPN bipolar transistor is simultaneously connected to the bases of the fifth and sixth NPN bipolar transistors and the second terminal of the ninth resistor; the first terminal of the ninth resistor is connected to the power supply VDD.

[0019] The present invention provides a segmented compensated bandgap reference voltage source with a high power supply rejection ratio, which has the following beneficial effects:

[0020] (1) The high power supply rejection ratio bandgap reference voltage source with segmented compensation in this invention is optional. The segmented compensation circuit can be selected by the ports of the first switch and the second switch to improve the accuracy of the bandgap reference voltage and facilitate its application.

[0021] (2) The use of a three-stage operational amplifier structure improves the low-frequency loop gain, thereby improving the power supply rejection ratio of the bandgap voltage: the first operational amplifier uses a transistor as the input pair, which effectively reduces the offset voltage and improves the accuracy of the bandgap voltage; the series resistor and capacitor between the positive and negative output terminals of the first and second operational amplifiers introduce additional zeros and poles, increasing the phase margin and improving the loop stability.

[0022] (3) The typical value of the temperature drift coefficient of the present invention is 17.3ppm / ℃, and the typical value of the low frequency power supply rejection ratio is -132dB. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of the segmented compensated high power supply rejection ratio bandgap reference voltage source provided by the present invention;

[0024] Figure 2 This is a circuit diagram of the first operational amplifier in the bandgap core circuit;

[0025] Figure 3 This is a circuit diagram of the second operational amplifier in the bandgap core circuit;

[0026] Figure 4 This is a circuit diagram of the third operational amplifier in the bandgap core circuit;

[0027] Figure 5 This is a schematic diagram of the output voltage of a bandgap reference voltage source;

[0028] Figure 6 This is a schematic diagram of the power supply rejection ratio of a bandgap reference voltage source. Detailed Implementation

[0029] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a segmented compensated bandgap reference voltage source with a high power supply rejection ratio, as proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0030] This invention provides a segmented compensated bandgap reference voltage source with a high power supply rejection ratio, the structure of which is as follows: Figure 1 As shown. The bandgap reference voltage source includes a bandgap core circuit, a segmented compensation circuit, and a startup circuit.

[0031] The bandgap reference core circuit generates a reference voltage independent of temperature and power supply voltage, while using high loop gain to achieve a high power supply rejection ratio. The segmented compensation circuit generates a negative temperature coefficient current and transmits it to the bandgap reference core circuit for compensation, thereby achieving fine adjustment of the bandgap reference voltage and further improving the accuracy of the voltage output, ensuring a high-precision reference voltage output under different operating conditions. The startup circuit provides appropriate current during circuit power-on, enabling the bandgap reference core circuit to quickly jump out of the degenerate state and enter a stable operating state, ensuring the reliability of the circuit during startup.

[0032] Please continue reading. Figure 1 The bandgap reference core circuit includes a first operational amplifier A1 to a third operational amplifier A3, a first resistor R1 to a fifth resistor R5, a first MOSFET M1, a first NPN bipolar transistor Q1, a second NPN bipolar transistor Q2, a first capacitor C1, a second capacitor C2, and a first adjustment resistor R. trim1The non-inverting input of the first operational amplifier A1 is simultaneously connected to the first terminal of the first resistor R1 and the collector of the first NPN bipolar transistor Q1; the inverting input of the first operational amplifier A1 is simultaneously connected to the first terminal of the second resistor R2 and the collector of the second NPN bipolar transistor Q2; the non-inverting output of the first operational amplifier A1 is connected to the non-inverting input of the second operational amplifier A2, and the inverting output of the first operational amplifier A1 is connected to the inverting input of the second operational amplifier A2; the non-inverting input of the third operational amplifier A3 is simultaneously connected to the non-inverting output of the second operational amplifier A2 and the first terminal of the fourth resistor R4, the second terminal of the fourth resistor R4 is connected to the first terminal of the first capacitor C1, and the third operational amplifier A3... The inverting input is connected to the inverting output of the second operational amplifier A2. The output is simultaneously connected to the second terminal of the first capacitor C1, the first terminal of the fifth resistor R5, and the gate of the first MOSFET M1. The source of the first MOSFET M1 is connected to the power supply VDD, and the drain is connected to the second terminal of the second capacitor C2. The second terminal of the fifth resistor R5 is connected to the first terminal of the second capacitor C2. The base of the first NPN bipolar transistor Q1 is simultaneously connected to the base of the second NPN bipolar transistor Q2, the second terminal of the first resistor R1, and the second terminal of the second resistor R2. The emitter of the first NPN bipolar transistor Q1 is connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is simultaneously connected to the emitter of the second NPN bipolar transistor Q2 and the first adjustment resistor R. trim1 The first terminal; the first adjustment resistor R trim1 The second terminal is grounded.

[0033] The first operational amplifier A1 is as follows Figure 2 As shown, this includes the seventh NPN bipolar transistor Q7 to the tenth NPN bipolar transistor Q10. 10 The tenth resistor R 10 ~Fourteenth resistor R 14 The third capacitor is C3; the emitter of the seventh NPN transistor Q7 is grounded, and its base is connected to both its own collector and the base of the eighth NPN transistor Q8. The collector is connected to the tenth resistor R. 10 Connected to power supply VDD; the emitter of the eighth NPN transistor Q8 is connected to the eleventh resistor R. 11 Grounded, the collector is connected to both the emitter of the ninth NPN transistor Q9 and the tenth NPN transistor Q. 10 The emitter of the ninth NPN transistor Q9 is connected to the base of the non-inverting input terminal INP1, and the collector is simultaneously connected to the inverting output terminal OUTN1, the first terminal of the third capacitor C3, and the twelfth resistor R. 12 The second end; the tenth NPN transistor Q 10 The base is connected to the inverting input terminal INN1, and the collector is simultaneously connected to the non-inverting output terminal OUTP1 and the fourteenth resistor R. 14 The second terminal and the thirteenth resistor R 13 The second terminal; the second terminal of the third capacitor C3 is connected to the fourteenth resistor R. 14The first terminal; the twelfth resistor R 12 and the thirteenth resistor R 13 The first end is also connected to the power supply VDD.

[0034] The second operational amplifier A2 is as follows Figure 3 As shown, it includes the eleventh NPN bipolar transistor Q. 11 ~Thirteenth NPN bipolar transistor Q 13 The second MOSFET M2 and the third MOSFET M3, and the fifteenth resistor R 15 ~Sixteenth resistor R 16 Fourth capacitor C4; Eleventh NPN transistor Q 11 The base is biased by voltage V bias The emitter is connected to the sixteenth resistor R. 16 Grounded, with the collector simultaneously connected to the twelfth NPN transistor Q. 12 and the thirteenth NPN transistor Q 13 The emitter; the twelfth NPN transistor Q 12 The base of the transistor is connected to the non-inverting input terminal INP2, and the collector is simultaneously connected to the inverting output terminal OUTN2, the first terminal of the fourth capacitor C4, the drain of the second MOSFET M2, the gate of the second MOSFET M2, and the gate of the third MOSFET M3; the thirteenth NPN transistor Q... 13 The base is connected to the inverting input terminal INN2, and the collector is simultaneously connected to the non-inverting output terminal OUTP2 and the fifteenth resistor R. 15 The second terminal is connected to the drain of the third MOSFET M3; the second terminal of the fourth capacitor C4 is connected to the fifteenth resistor R. 15 The first terminal; the source of the second MOSFET M2 and the source of the third MOSFET M3 are simultaneously connected to the power supply VDD.

[0035] The third operational amplifier A3 is as follows Figure 4 As shown, it includes the fourth MOSFET M4 to the eleventh MOSFET M 11 The gate of the fourth MOSFET M4 is connected to the non-inverting output terminal INP3, and its drain is simultaneously connected to the drain of the sixth MOSFET M6, the gate of the sixth MOSFET M6, and the gate of the eighth MOSFET M8; the sources of the sixth MOSFET M6 and the eighth MOSFET M8 are both grounded; the drain of the eighth MOSFET M8 is connected to the tenth MOSFET M... 10 The drain of the tenth MOSFET M 10 The source of the fifth MOSFET M5 is connected to the power supply VDD; the gate of the fifth MOSFET M5 is connected to the inverting input terminal INN3, and its drain is connected to the drain of the seventh MOSFET M7, the gate of the seventh MOSFET M7, and the gate of the ninth MOSFET M9; the sources of the seventh MOSFET M7 and the ninth MOSFET M9 are grounded simultaneously; the drain of the ninth MOSFET M9 and the eleventh MOSFET M... 11 The drain of the eleventh MOSFET M is connected to the output terminal OUT3.11 The source is connected to VDD, and the gate is connected to the tenth MOSFET M. 10 The gate.

[0036] The segmented compensation circuit includes a third NPN bipolar transistor Q3, resistors R6 to R8 (sixth to eighth resistors), and a second adjustment resistor R. trim2 The first switch is Switch1, the second switch is Switch2; the second terminals of the sixth resistor R6 and the seventh resistor R7 are grounded; the emitter of the third NPN bipolar transistor Q3 is connected to the first terminal of the sixth resistor R6, the base is connected to the first terminal of the seventh resistor R7 and the second terminal of the eighth resistor R8, and the collector is connected to the second adjustment resistor R. trim2 The second terminal; the second adjustment resistor R trim2 The first terminal of the resistor R8 is connected to the second terminal of the first switch (Switch 1); the first terminal of the eighth resistor R8 is connected to the second terminal of the second switch (Switch 2). The bandgap reference voltage V ultimately generated by the bandgap reference voltage source of this invention... BG Simultaneously connect the base of the first NPN bipolar transistor Q1, the base of the second NPN bipolar transistor Q2, the second terminal of the second capacitor C2, the drain of the first MOSFET M1, the first terminal of the first switch Switch1, and the first terminal of the second switch Switch2.

[0037] The startup circuit includes a fourth NPN bipolar transistor Q4 to a sixth NPN bipolar transistor Q6, and a ninth resistor R9; the emitters of the fourth NPN bipolar transistor Q4, the fifth NPN bipolar transistor Q5, and the sixth NPN bipolar transistor Q6 are all grounded; the base of the fourth NPN bipolar transistor Q4 is simultaneously connected to the bases of the fifth NPN bipolar transistor Q5, the base of the sixth NPN bipolar transistor Q6, and the second terminal of the ninth resistor R9; the first terminal of the ninth resistor R9 is connected to the power supply VDD.

[0038] The output voltage of the bandgap reference voltage source is as follows: Figure 5 As shown, the output voltage range is 1.1597V to 1.1625V at -55℃ to 125℃, and the temperature drift coefficient is 17.3ppm / ℃, achieving a high-precision low-temperature drift reference voltage over a wide range.

[0039] The power supply suppression of the bandgap reference voltage source, for example Figure 6 As shown, the power supply rejection ratio is -132dB at low frequencies, which provides excellent resistance to power supply noise.

[0040] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A segmented compensated bandgap reference voltage source with a high power supply rejection ratio, characterized in that, include: The bandgap reference core circuit, segmented compensation circuit, and startup circuit; The bandgap reference core circuit is used to generate a reference voltage that is independent of temperature and power supply voltage, while using high loop gain to achieve a high power supply rejection ratio. The segmented compensation circuit generates a negative temperature coefficient current and transmits it to the bandgap reference core circuit for compensation, thereby achieving fine adjustment of the reference voltage, further improving the accuracy of the voltage output, and ensuring high-precision reference voltage output under different operating conditions. The startup circuit is used to provide appropriate current during the power-on process of the circuit, so that the bandgap reference core circuit can quickly jump out of the degenerate state and enter a stable working state, ensuring the reliability of the circuit during startup.

2. The segmented compensated bandgap reference voltage source with high power supply rejection ratio as described in claim 1, characterized in that, The bandgap reference core circuit includes a first operational amplifier to a third operational amplifier, a first resistor to a fifth resistor, a first MOS transistor, a first NPN bipolar transistor, a second NPN bipolar transistor, a first capacitor, a second capacitor, and a first adjustment resistor; The non-inverting input of the first operational amplifier is simultaneously connected to the first terminal of the first resistor and the collector of the first NPN bipolar transistor; the inverting input of the first operational amplifier is simultaneously connected to the first terminal of the second resistor and the collector of the second NPN bipolar transistor; the non-inverting output of the first operational amplifier is connected to the non-inverting input of the second operational amplifier, and the inverting output of the first operational amplifier is connected to the inverting input of the second operational amplifier; the non-inverting input of the third operational amplifier is simultaneously connected to the non-inverting output of the second operational amplifier and the first terminal of the fourth resistor, the second terminal of the fourth resistor is connected to the first terminal of the first capacitor, the inverting input of the third operational amplifier is connected to the inverting output of the second operational amplifier, and the output terminal is simultaneously connected to the second terminal of the first capacitor, the first terminal of the fifth resistor, and the gate of the first MOSFET; the source of the first MOSFET is connected to the power supply VDD, and the drain is connected to the second terminal of the second capacitor; the second terminal of the fifth resistor is connected to the first terminal of the second capacitor; the base of the first NPN bipolar transistor is simultaneously connected to the base of the second NPN bipolar transistor, the second terminal of the first resistor, the second terminal of the second resistor, and the bandgap reference voltage V generated by the bandgap reference voltage source. BG The emitter of the first NPN bipolar transistor is connected to the first terminal of the third resistor; the second terminal of the third resistor is connected to both the emitter of the second NPN bipolar transistor and the first terminal of the first adjustment resistor; the second terminal of the first adjustment resistor is grounded; the second terminal of the second capacitor and the drain of the first MOSFET are both connected to the bandgap reference voltage V generated by the bandgap reference voltage source. BG .

3. The segmented compensated bandgap reference voltage source with high power supply rejection ratio as described in claim 2, characterized in that, The first operational amplifier includes the seventh NPN bipolar transistor to the tenth NPN bipolar transistor, the tenth resistor to the fourteenth resistor, and the third capacitor; The emitter of the seventh NPN transistor is grounded, and its base is connected to both its own collector and the base of the eighth NPN transistor. The collector is connected to the power supply VDD through the tenth resistor. The emitter of the eighth NPN transistor is grounded through the eleventh resistor, and its collector is connected to both the emitters of the ninth and tenth NPN transistors. The base of the ninth NPN transistor is connected to the non-inverting input terminal INP1, and its collector is connected to the inverting output terminal OUTN1, the first terminal of the third capacitor, and the second terminal of the twelfth resistor. The base of the tenth NPN transistor is connected to the inverting input terminal INP1, and its collector is connected to the non-inverting output terminal OUTP1, the second terminal of the fourteenth resistor, and the second terminal of the thirteenth resistor. The second terminal of the third capacitor is connected to the first terminal of the fourteenth resistor. The first terminals of the twelfth and thirteenth resistors are both connected to the power supply VDD.

4. The segmented compensated bandgap reference voltage source with high power supply rejection ratio as described in claim 2, characterized in that, The second operational amplifier includes an eleventh to thirteenth NPN bipolar transistor, a second MOSFET and a third MOSFET, a fifteenth to a sixteenth resistor, and a fourth capacitor. The base of the eleventh NPN transistor is connected to a bias voltage, the emitter is grounded through the sixteenth resistor, and the collector is connected to the emitters of both the twelfth and thirteenth NPN transistors. The base of the twelfth NPN transistor is connected to the non-inverting input terminal INP2, and the collector is connected to the inverting output terminal OUTN2, the first terminal of the fourth capacitor, the drain of the second MOSFET, the gate of the second MOSFET, and the gate of the third MOSFET. The base of the thirteenth NPN transistor is connected to the inverting input terminal INP2, and the collector is connected to the non-inverting output terminal OUTP2, the second terminal of the fifteenth resistor, and the drain of the third MOSFET. The second terminal of the fourth capacitor is connected to the first terminal of the fifteenth resistor. The sources of the second and third MOSFETs are connected to the power supply VDD.

5. The segmented compensated bandgap reference voltage source with high power supply rejection ratio as described in claim 2, characterized in that, The third operational amplifier includes MOSFETs four through MOSFET eleven. The gate of the fourth MOSFET is connected to the non-inverting output terminal INP3, and its drain is simultaneously connected to the drain, gate, and gate of the sixth MOSFET and the eighth MOSFET. The sources of the sixth and eighth MOSFETs are grounded. The drain of the eighth MOSFET is connected to the drain of the tenth MOSFET. The source of the tenth MOSFET is connected to the power supply VDD. The gate of the fifth MOSFET is connected to the inverting input terminal INN3, and its drain is simultaneously connected to the drain, gate, and gate of the seventh MOSFET and the ninth MOSFET. The sources of the seventh and ninth MOSFETs are grounded. The drains of the ninth and eleventh MOSFETs are simultaneously connected to the output terminal OUT3. The source of the eleventh MOSFET is connected to VDD, and its gate is connected to the gate of the tenth MOSFET.

6. The segmented compensated bandgap reference voltage source with high power supply rejection ratio as described in claim 2, characterized in that, The first trimming resistor is used to generate a voltage with a low temperature drift coefficient by adjusting the resistance value of the first trimming resistor after a temperature and power supply-independent voltage is generated in the band gap.

7. The segmented compensated bandgap reference voltage source with high power supply rejection ratio as described in claim 1, characterized in that, The segmented compensation circuit includes a third NPN bipolar transistor, a sixth to eighth resistor, a second adjustment resistor, a first switch, and a second switch. The second terminals of the sixth and seventh resistors are grounded. The emitter of the third NPN bipolar transistor is connected to the first terminal of the sixth resistor, its base is connected to the first terminal of the seventh resistor and the second terminal of the eighth resistor, and its collector is connected to the second terminal of the second adjustment resistor. The first terminal of the second adjustment resistor is connected to the second terminal of the first switch. The first terminal of the eighth resistor is connected to the second terminal of the second switch. Both the first terminals of the first and second switches are connected to the bandgap reference voltage V generated by the bandgap reference voltage source. BG .

8. The segmented compensated bandgap reference voltage source with high power supply rejection ratio as described in claim 1, characterized in that, The startup circuit includes a fourth NPN bipolar transistor to a sixth NPN bipolar transistor and a ninth resistor; the emitters of the fourth, fifth, and sixth NPN bipolar transistors are simultaneously grounded; the base of the fourth NPN bipolar transistor is simultaneously connected to the bases of the fifth and sixth NPN bipolar transistors and the second terminal of the ninth resistor; the first terminal of the ninth resistor is connected to the power supply VDD.

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