Reference current generation circuit

Abstract

The application provides a reference current generation circuit, comprising: a positive temperature coefficient current providing end configured to provide a positive temperature coefficient current to a first current synthesis circuit; a negative temperature coefficient current providing end configured to provide a negative temperature coefficient current to the first current synthesis circuit; the first current synthesis circuit is configured to linearly synthesize the positive temperature coefficient current and the negative temperature coefficient current into a first reference current which changes linearly with temperature at a respective adjustable proportion, and a slope of the first reference current which changes linearly with temperature is determined according to the adjustable proportion corresponding to the positive temperature coefficient current and / or the adjustable proportion corresponding to the negative temperature coefficient current; and a second current synthesis circuit configured to obtain the first reference current and the negative temperature coefficient current from the first current synthesis circuit, and generate a second reference current which changes nonlinearly with temperature according to the first reference current and the negative temperature coefficient current.

Description

Technical Field

[0001] This application relates to the field of current generation technology, specifically to a reference current generation circuit. Background Technology

[0002] With the development of radio frequency (RF) technology, higher demands are placed on the robustness of RF chips. In various applications such as automotive radar and communication base stations, performance stability needs to be maintained over a wide temperature range, thus placing high demands on the temperature compensation circuits in RF chips. Furthermore, the performance of RF circuits is mainly adjusted through bias circuits, which are designed primarily by mirroring the reference current using a current mirror. Therefore, optimizing the temperature stability of RF chip performance is typically achieved by adjusting the slope of the reference current relative to temperature changes. Moreover, different RF modules performing different functions will have different temperature slopes for the reference current. Based on this, designing a flexible, slope-adjustable reference current synthesis circuit has broad application prospects and value.

[0003] In traditional analog circuit chips, the reference current of the bias circuit is usually directly provided by the reference source circuit, which generates current with a positive temperature coefficient, current with a negative temperature coefficient, and current that does not change with temperature. This reference current cannot flexibly compensate for the high and low temperature performance of RF and analog chips, and is not suitable for the design requirements of RF and analog circuits. Summary of the Invention

[0004] This application provides a reference current generation circuit.

[0005] This application embodiment provides a reference current generation circuit, the reference current generation circuit including:

[0006] The positive temperature coefficient current supply terminal is configured to provide a positive temperature coefficient current to the first current synthesis circuit;

[0007] The negative temperature coefficient current supply terminal is configured to supply a negative temperature coefficient current to the first current synthesis circuit;

[0008] The first current synthesis circuit is configured to linearly synthesize the positive temperature coefficient current and the negative temperature coefficient current into a first reference current that varies linearly with temperature, each with its corresponding adjustable ratio. The slope of the first reference current that varies linearly with temperature is determined based on the adjustable ratio corresponding to the positive temperature coefficient current and / or the adjustable ratio corresponding to the negative temperature coefficient current.

[0009] The second current synthesis circuit is configured to obtain the first reference current and the negative temperature coefficient current from the first current synthesis circuit, and generate a second reference current that varies non-linearly with temperature based on the first reference current and the negative temperature coefficient current.

[0010] According to the reference current generation circuit of this application embodiment, in one aspect, a first current synthesis circuit linearly synthesizes a positive temperature coefficient current and a negative temperature coefficient current into a first reference current that changes linearly with temperature using their respective adjustable proportions. The slope of the linearly synthesized first reference current changing with temperature can be adjusted according to the adjustable proportions of the positive and / or negative temperature coefficient currents. This allows for the generation of reference currents with different slopes changing with temperature based on the different temperature compensation requirements of different external circuits. The slope of the reference current changing with temperature is flexibly and precisely adjustable, which can better compensate for the performance stability of external circuits over a wide temperature range and improve the performance stability of external circuits relative to temperature changes. In another aspect, a second current synthesis circuit can further generate a second reference current that changes non-linearly with temperature based on the first reference current and the negative temperature coefficient current. This second reference current, which changes non-linearly with temperature, has high-order current-temperature curve characteristics, causing it to change curvilinearly with temperature. This allows for the generation of a larger high-temperature current under the same current or temperature conditions, thereby better compensating for the performance of external circuits over a wide temperature range.

[0011] Further details regarding the above embodiments and other aspects of this application, as well as their implementations, are provided in the accompanying drawings, detailed description, and claims. Attached Figure Description

[0012] In the accompanying drawings of the embodiments of this application:

[0013] Figure 1 This diagram illustrates the structural composition of a reference current generation circuit provided in an embodiment of this application.

[0014] Figure 2 This diagram illustrates the structural composition of a first current synthesis circuit provided in an embodiment of this application.

[0015] Figure 3 This diagram illustrates the structural composition of another first current synthesis circuit provided in an embodiment of this application.

[0016] Figure 4 This diagram illustrates the structural composition of yet another first current synthesis circuit provided in an embodiment of this application.

[0017] Figure 5 This diagram illustrates the implementation circuit structure of a first current synthesis circuit provided in an embodiment of this application.

[0018] Figure 6 A schematic diagram of a circuit structure showing multiple second transistors M2 connected in parallel is shown.

[0019] Figure 7This diagram illustrates the variation of positive temperature coefficient current and negative temperature coefficient current with temperature in embodiments of this application.

[0020] Figure 8 A schematic diagram of the first reference current under different slopes is shown.

[0021] Figure 9 This diagram illustrates the structural composition of a second current synthesis circuit provided in an embodiment of this application.

[0022] Figure 10 This diagram illustrates the structural composition of another second current synthesis circuit provided in an embodiment of this application.

[0023] Figure 11 This diagram illustrates the structural composition of yet another second current synthesis circuit provided in an embodiment of this application.

[0024] Figure 12 This diagram illustrates the implementation circuit structure of a second current synthesis circuit provided in an embodiment of this application.

[0025] Figure 13 A schematic diagram of the simulation results for a second reference current is shown. Detailed Implementation

[0026] To enable those skilled in the art to better understand the technical solutions of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0027] The present application will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present application should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this application will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the application.

[0028] The accompanying drawings of the embodiments of this application are used to provide a further understanding of the embodiments of this application and constitute a part of the specification. They are used together with the detailed embodiments to explain this application and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0029] This application can be described with reference to plan views and / or cross-sectional views using the ideal schematic diagram of this application. Therefore, the example illustrations can be modified according to manufacturing techniques and / or tolerances.

[0030] Where there is no conflict, the various embodiments of this application and the features thereof may be combined with each other.

[0031] The terminology used in this application is for describing specific embodiments only and is not intended to limit the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used herein are also intended to include the plural forms unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used herein, specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0032] Unless otherwise specified, all terms used in this application (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this application.

[0033] This application is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown in the drawings illustrate the specific shapes of the areas of the element, but are not intended to be limiting.

[0034] It should be noted that the transistors used in the embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with the same or similar characteristics. Since the source (emitter) and drain (collector) of the transistors used are symmetrical, there is no distinction between the source and drain. In the embodiments of this disclosure, to distinguish the source and drain of the transistor, one of them is called the first electrode, the other is called the second electrode, and the gate (base) is called the control electrode.

[0035] Furthermore, based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. For example, N-type transistors include N-type MOSFETs (Metal-Oxide Semiconductor FETs) and NPN transistors, while P-type transistors include P-type MOSFETs and PNP transistors. When a transistor is N-type, its on-state voltage is high and its off-state voltage is low. When a transistor is P-type, its on-state voltage is low and its off-state voltage is high. When using a P-type transistor, its first electrode is the drain / collector, and its second electrode is the source / emitter. Conversely, when using an N-type transistor, its first electrode is the source / emitter, and its second electrode is the drain / collector.

[0036] Figure 1 This illustration shows a schematic diagram of the composition structure of a reference current generation circuit provided in an embodiment of this application, as shown below. Figure 1 As shown, this application embodiment provides a reference current generation circuit, which includes a positive temperature coefficient current providing terminal A, a negative temperature coefficient current providing terminal B, a first current synthesis circuit 100, and a second current synthesis circuit 200.

[0037] Among them, the positive temperature coefficient current providing terminal A is configured to provide a positive temperature coefficient current I to the first current synthesis circuit 100. PTAT The negative temperature coefficient current providing terminal B is configured to provide a negative temperature coefficient current I to the first current combining circuit 100. CTAT The first current synthesis circuit 100 is configured to synthesize the positive temperature coefficient current I... PTAT and negative temperature coefficient current I CTAT Each current is linearly synthesized using its corresponding adjustable ratio to form a first reference current I that varies linearly with temperature. Out1 The first reference current I that varies linearly with temperature Out1 The slope is based on the positive temperature coefficient current I. PTAT The corresponding adjustable proportional and / or negative temperature coefficient current I CTAT The corresponding adjustable ratio is determined; the second current synthesis circuit 200 is configured to obtain the first reference current I from the first current synthesis circuit 100. Out1 and negative temperature coefficient current I CTAT And according to the first reference current I Out1 and negative temperature coefficient current I CTAT Generate a second reference current I that varies non-linearly with temperature. Out2 .

[0038] In this embodiment, the positive temperature coefficient current providing terminal A and the negative temperature coefficient current providing terminal B are respectively connected to the two input terminals of the first current synthesis circuit 100. The positive temperature coefficient current providing terminal A is a reference source circuit whose output current has a positive temperature coefficient, and this reference source circuit with a positive temperature coefficient output current is used to generate a positive temperature coefficient current I. PTAT And output a positive temperature coefficient current I PTAT A corresponding input terminal of the first current synthesis circuit 100 is connected to provide a positive temperature coefficient current I to the first current synthesis circuit 100. PTAT The negative temperature coefficient current supply terminal B is a reference source circuit whose output current has a negative temperature coefficient. This reference source circuit with a negative temperature coefficient output current is used to generate a negative temperature coefficient current I. CTAT And output a negative temperature coefficient current I CTATA corresponding input terminal of the first current synthesis circuit 100 is connected to provide a negative temperature coefficient current I to the first current synthesis circuit 100. CTAT .

[0039] Among them, the positive temperature coefficient current I PTAT This refers to current that is proportional to absolute temperature (PTAT), specifically, negative temperature coefficient current I. CTAT This refers to the current that is inversely proportional to absolute temperature (CTAT).

[0040] This application does not impose special restrictions on the specific implementation of reference source circuits with positive and negative temperature coefficients of output current, as long as the required positive temperature coefficient current I can be generated. PTAT and negative temperature coefficient current I CTAT That's all.

[0041] In this embodiment, the first current synthesis circuit 100 further includes a first reference current output terminal Out1, which can be used to output a first reference current I to an external circuit (such as an RF chip circuit or an analog chip circuit). Out1 .

[0042] In this embodiment, the first current synthesis circuit 100 is also connected to the second current synthesis circuit 200. The second current synthesis circuit 200 has a second reference current output terminal Out2, which can be used to output a second reference current I to an external circuit (such as an RF chip circuit or an analog chip circuit). Out2 .

[0043] In this embodiment, on one hand, a first current synthesis circuit linearly synthesizes a positive temperature coefficient current and a negative temperature coefficient current into a first reference current that varies linearly with temperature using their respective adjustable ratios. The slope of the linearly synthesized first reference current as a function of temperature can be adjusted according to the adjustable ratios of the positive and / or negative temperature coefficient currents. This allows for the generation of reference currents with different slopes as a function of temperature, based on the varying temperature compensation requirements of different external circuits. The slope of the reference current as a function of temperature is flexibly and precisely adjustable, which can better compensate for the performance stability of external circuits over a wide temperature range and improve the performance stability of external circuits relative to temperature changes. On the other hand, a second current synthesis circuit can further generate a second reference current that varies non-linearly with temperature based on the first reference current and the negative temperature coefficient current. This second reference current, which varies non-linearly with temperature, exhibits high-order current-temperature curve characteristics, causing it to change curvilinearly with temperature. This allows for the generation of a larger high-temperature current under the same current or temperature conditions, thereby better compensating for the performance of external circuits over a wide temperature range.

[0044] In practical applications, the reference current generation circuit of this application embodiment can be applied to the bias circuit of various modules of external circuits such as radio frequency chip circuits or analog chip circuits. According to actual needs, reference currents with different slopes that change linearly or nonlinearly with temperature can be flexibly configured through the first current synthesis circuit and the second current synthesis circuit, so as to effectively compensate and improve the changes in the performance of external circuits with temperature fluctuations and improve the temperature robustness of external circuits.

[0045] Figure 2 This diagram illustrates the structural composition of a first current synthesis circuit according to an embodiment of this application. In some embodiments, such as... Figure 2 As shown, the first current synthesis circuit 100 includes a first current mirror module 101 and a second current mirror module 102.

[0046] The input terminal of the first current mirror module 101 is connected to the positive temperature coefficient current providing terminal A, and the output terminal is connected to the current combining node N1. The first current mirror module 101 is configured to mirror the positive temperature coefficient current I provided by the positive temperature coefficient current providing terminal A. PTAT The image is mirrored to a first current I1 using the first adjustable scaling factor K1, and then output to the current synthesis node N1. Here, the first current I1 is a positive temperature coefficient current I0. PTAT The product of the first adjustable ratio K1, i.e., I1 = I PTAT ×K1.

[0047] The input terminal of the second current mirror module 102 is connected to the negative temperature coefficient current providing terminal B, and the output terminal is connected to the current combining node N1. The second current mirror module 102 is configured to mirror the negative temperature coefficient current I provided by the negative temperature coefficient current providing terminal B. CTAT The second adjustable ratio K2 is used to mirror the first current I1 and the second current I2, and output to the current synthesis node N1. The current synthesis node N1 is used to linearly synthesize the first current I1 and the second current I2 into a first reference current I that varies linearly with temperature. Out1 Among them, the second current I2 is a negative temperature coefficient current I. CTAT The product of the second adjustable ratio K2, i.e., I2 = I CTAT ×K2.

[0048] In some embodiments, the first current I1 output by the first current mirroring module 101 and the second current I2 output by the second current mirroring module 102 are linearly superimposed at the current synthesis node N1 to synthesize the first reference current I. Out1 First reference current I Out1 It is the sum of the first current I1 and the second current I2, i.e., I Out1 =I1+I2.

[0049] In some embodiments, the positive temperature coefficient current I PTAT and negative temperature coefficient current I CTAT The temperature characteristics of both are linearly changing, and the values ​​of the first adjustable ratio K1 and the second adjustable ratio K2 are adjustable. Therefore, by mirroring the positive temperature coefficient current I... PTAT The first current I1 obtained and the current I obtained through the mirror image with negative temperature coefficient are CTAT The temperature characteristics of the obtained second current I2 are all linearly changing and the slope is adjustable. Therefore, a first reference current I that varies linearly with temperature can be generated by linearly superimposing the first current I1 and the second current I2 at the current synthesis node N1. Out1 And the first reference current I Out1 The slope of the linear change with temperature is adjustable, and the first reference current I... Out1 The slope of the linear change with temperature can be adjusted and determined according to the first adjustable ratio K1 and the second adjustable ratio K2.

[0050] Figure 3 This illustration shows a schematic diagram of the composition structure of another first current synthesis circuit provided in an embodiment of this application. In some embodiments, such as... Figure 3 As shown, the first current synthesis circuit 100 also includes a third current mirror module 103. The input terminal of the third current mirror module 103 is connected to the current synthesis node N1, and the output terminal is the first reference current output terminal Out1.

[0051] The third current mirror module 103 is configured to output the first reference current I from the current synthesis node N1. Out1 After mirroring, the output is generated through the first reference current output terminal Out1.

[0052] In some embodiments, the first reference current I is reflected by the third current mirror module 103. Out1 After mirroring, the first reference current is output to an external circuit through the first reference current output terminal Out1, which helps to achieve a stable first reference current output. Furthermore, the current mirroring ratio of the third current mirroring module 103 can be configured according to the required magnitude of the first reference current to mirror the first reference current I. Out1 The output is mirrored according to the pre-configured current mirror ratio.

[0053] Figure 4 This illustration shows a schematic diagram of the composition structure of another first current synthesis circuit provided in an embodiment of this application. In some embodiments, such as... Figure 4 As shown, the first current synthesis circuit 100 also includes a fourth current mirror module 104 and a first bias voltage generation module 105. The input terminal of the fourth current mirror module 105 is connected to the current synthesis node N1, and the output terminal is connected to the first bias voltage generation module 105.

[0054] The fourth current mirror module 104 is configured to output the first reference current I from the current synthesis node N1. Out1 After mirroring, the output is sent to the first bias voltage generation module 105; the first bias voltage generation module 105 is configured to output the first reference current I based on the first reference current I output by the fourth current mirroring module 104. Out1 A first bias voltage V_linear1 and a second bias voltage V_linear2 are generated and provided to the second current synthesis circuit 200. The first bias voltage V_linear1 and the second bias voltage V_linear2 are used by the second current synthesis circuit 200 to mirror the first reference current I based on the first bias voltage V_linear1 and the second bias voltage V_linear2. Out1 .

[0055] In some embodiments, the first bias voltage generation module 105 has a first bias voltage terminal linear1 and a second bias voltage terminal linear2. The first bias voltage generation module 105 generates a first reference current I output by the fourth current mirror module 104. Out1 A first bias voltage V_linear1 is generated at the first bias voltage terminal linear1, and a second bias voltage V_linear2 is generated at the second bias voltage terminal linear2.

[0056] In some embodiments, the first current synthesis circuit 100 and the second current synthesis circuit 200 are connected via a first bias voltage terminal linear1 and a second bias voltage terminal linear2 to provide the second current synthesis circuit 200 with a current for mirroring the first reference current I. Out1 Given a first bias voltage V_linear1 and a second bias voltage V_linear2, the second current synthesis circuit 200 can obtain a first reference current I based on the first bias voltage V_linear1 and the second bias voltage V_linear2. Out1 .

[0057] In some embodiments, the first reference current is mirrored by the fourth current mirroring module 104 and coupled to the second current synthesis circuit 200 via the first bias voltage generation module 105. The first bias voltage generation module 105 can generate the first reference current I output by the fourth current mirroring module 104. Out1 Provides the second current synthesis circuit 200 with a current mirror for the first reference current I. Out1 The first bias voltage V_linear1 and the second bias voltage V_linear2 can help to provide a precise and stable first reference current I for the second current synthesis circuit 200. Out1 .

[0058] In some embodiments, such as Figure 4 As shown, the second current mirror module 102 is also configured to receive the negative temperature coefficient current I provided by the negative temperature coefficient current providing terminal B. CTAT The system generates a third bias voltage V_ctat1 and a fourth bias voltage V_ctat2, and provides the third bias voltage V_ctat1 and the fourth bias voltage V_ctat2 to the second current synthesis circuit 200. The third bias voltage V_ctat1 and the fourth bias voltage V_ctat2 are used by the second current synthesis circuit 200 to mirror the negative temperature coefficient current I based on the third bias voltage V_ctat1 and the fourth bias voltage V_ctat2. CTAT .

[0059] In some embodiments, such as Figure 4 As shown, the second current mirror module 102 has a third bias voltage terminal ctat1 and a fourth bias voltage terminal ctat2. The second current mirror module 102 is based on the negative temperature coefficient current I provided by the negative temperature coefficient current providing terminal B. CTAT A third bias voltage V_ctat1 is generated at the third bias voltage terminal ctat1, and a fourth bias voltage V_ctat2 is generated at the fourth bias voltage terminal ctat2.

[0060] In some embodiments, the first current combining circuit 100 and the second current combining circuit 200 are further connected via a third bias voltage terminal ctat1 and a fourth bias voltage terminal ctat2 to provide the second current combining circuit 200 with a current I for mirroring the negative temperature coefficient current. CTAT The third bias voltage V_ctat1 and the fourth bias voltage V_ctat2 are used as references to obtain the negative temperature coefficient current I. The second current synthesis circuit 200 can obtain the negative temperature coefficient current I based on the third bias voltage V_ctat1 and the fourth bias voltage V_ctat2. CTAT .

[0061] In some embodiments, a second current mirror module 102 is also coupled to a second current synthesis circuit 200. The second current mirror module 102 can provide a negative temperature coefficient current I output from terminal B based on the negative temperature coefficient current. CTAT Provides the second current synthesis circuit 200 with a current I for mirroring the negative temperature coefficient current. CTAT The third bias voltage V_ctat1 and the fourth bias voltage V_ctat2 can help to provide a precise and stable negative temperature coefficient current I to the second current synthesis circuit 200. CTAT .

[0062] Figure 5 This diagram illustrates a schematic of the implementation circuit structure of a first current synthesis circuit according to an embodiment of this application. In some embodiments, the first current mirror module 101 is implemented using a current mirror circuit, such as... Figure 5 As shown, the first current mirror module 101 includes a first transistor M1, a plurality of second transistors M2 connected in parallel, a third transistor M3 connected in parallel, and a plurality of fourth transistors M4 connected in parallel.

[0063] The first transistor M1 has its first terminal connected to its control terminal and connected to the positive temperature coefficient current supply terminal A, and its second terminal connected to the first terminal of the third transistor M3.

[0064] Multiple second transistors M2 connected in parallel have their control electrodes interconnected and connected to the control electrode of the first transistor M1; their first electrodes are interconnected and connected to the current synthesis node N1; their second electrodes are interconnected and connected to the first electrode of multiple fourth transistors M4 connected in parallel. The first adjustable ratio K1 is adjusted according to the number of the multiple second transistors M2 connected in parallel that are turned on.

[0065] The third transistor M3 has its control electrode connected to the first electrode, and its second electrode grounded (GND).

[0066] Multiple fourth transistors M4 connected in parallel have their control electrodes interconnected and connected to the control electrode of the third transistor M3; their first electrodes are interconnected and connected to the second electrodes of multiple second transistors M2 connected in parallel; their second electrodes are interconnected and grounded (GND).

[0067] In some embodiments, such as Figure 5 As shown, the input terminal of the positive temperature coefficient current providing terminal A is connected to the high-level voltage providing terminal VDD, and the output terminal is connected to the first electrode and the control electrode of the first transistor M1. The high-level voltage providing terminal is used to provide a high-level voltage. Based on the high-level voltage provided by the high-level voltage providing terminal VDD, the positive temperature coefficient current providing terminal A provides a positive temperature coefficient current I to the first electrode and the control electrode of the first transistor M1. PTAT .

[0068] In some embodiments, in the first current mirror module 101, a current mirror circuit is formed using a first transistor M1, a plurality of second transistors M2 connected in parallel, a third transistor M3, and a plurality of fourth transistors M4 connected in parallel. The positive temperature coefficient current I output from the positive temperature coefficient current supply terminal A is then transmitted through the current mirror circuit. PTAT The first current I1 is mirrored by the first adjustable ratio K1 and is provided to the current synthesis node N1.

[0069] In some embodiments, the first current mirror module 101 can be a common-source cascode current mirror structure or a common-source current mirror structure.

[0070] In this embodiment, the first current mirror module 101 can be any suitable current mirror circuit structure, including but not limited to the cascode current mirror structure.

[0071] In some embodiments, the first transistor M1 to the fourth transistor M4 are all N-type MOS transistors or NPN transistors, wherein the first electrode of the transistor is the drain (collector), the second electrode is the source (emitter), and the control electrode is the gate (base).

[0072] In some embodiments, the number of second transistors M2 is the same as the number of fourth transistors M4, and the transistor sizes of the first transistors M1 to the fourth transistors M4 are the same. The size of a transistor usually refers to its width-to-length ratio (W / L), that is, the ratio of width (W) to length (L). The same transistor size means that the width-to-length ratio W / L is the same.

[0073] In some embodiments, the number of transistors turned on (conducting) in a plurality of parallel second transistors M2 and the number of transistors turned on (conducting) in a plurality of parallel fourth transistors M4 can be controlled by a switching structure, wherein the number of second transistors M2 turned on is the same as the number of fourth transistors M4 turned on.

[0074] Figure 6 A schematic diagram of a circuit structure showing multiple second transistors M2 connected in parallel is shown. In some embodiments, such as... Figure 6As shown, there are N (N is greater than or equal to 2) second transistors M2. Each second transistor M2 is provided with a first switching structure (S11, S12, S13, ..., S1N) and a second switching structure (S11', S12', S13', ..., S1N'). The first switching structure (S11, S12, S13, ..., S1N) is coupled between the control electrode of the corresponding second transistor M2 and the control electrode of the first transistor M1, used to control the connection or disconnection between the control electrodes of the corresponding second transistor M2 and the first transistor M1. The second switching structure (S11', S12', S13', ..., S1N') is coupled between the control electrode of the corresponding second transistor M2 and a low-level voltage terminal, used to control the connection or disconnection between the control electrode of the corresponding second transistor M2 and the low-level voltage terminal, which provides a low-level voltage VSS.

[0075] In some embodiments, both the first and second switch structures can be implemented using digital control switches. The first and second switch structures can be turned on or off via digital voltage / potential control, thereby controlling the corresponding second transistor M2 to turn on or off. When it is necessary to turn on the second transistor M2, the first switch structure corresponding to the second transistor M2 can be turned on, and the corresponding second switch structure can be turned off, thereby connecting the control electrode of the second transistor M2 with the control electrode of the first transistor M1, and turning it on under the bias voltage of the control electrode of the first transistor M1. When it is necessary to turn off the second transistor M2, the first switch structure corresponding to the second transistor M2 can be turned off, and the corresponding second switch structure can be turned on, thereby connecting the control electrode of the second transistor M2 with the low-level voltage terminal, and turning it off under the low-level voltage VSS provided by the low-level voltage terminal.

[0076] The circuit structure of multiple fourth transistors M4 connected in parallel is similar to that of multiple second transistors M2 connected in parallel, and will not be described in detail here. Please refer to [reference needed]. Figure 6 In the circuit structure shown, the first switch structure corresponding to the fourth transistor M4 is coupled between the control electrode of the fourth transistor M4 and the control electrode of the third transistor M3, and is used to control the connection or disconnection between the control electrode of the fourth transistor M4 and the control electrode of the third transistor M3; the second switch structure corresponding to the fourth transistor M4 is coupled between the control electrode of the fourth transistor M4 and the low-level voltage terminal, and is used to control the connection or disconnection between the control electrode of the fourth transistor M4 and the low-level voltage terminal, which is used to provide a low-level voltage VSS.

[0077] When the fourth transistor M4 needs to be turned on, the first switch structure corresponding to the fourth transistor M4 can be turned on and the corresponding second switch structure can be turned off, thereby connecting the control electrode of the fourth transistor M4 with the control electrode of the third transistor M3, and turning on under the bias voltage of the control electrode of the third transistor M3; when the fourth transistor M4 needs to be turned off, the first switch structure corresponding to the fourth transistor M4 can be turned off and the corresponding second switch structure can be turned on, thereby connecting the control electrode of the fourth transistor M4 with the low-level voltage terminal, and turning off under the low-level voltage VSS provided by the low-level voltage terminal.

[0078] The circuit implementation principle of the first current mirror module 101 will be explained below, taking the first transistor M1 to the fourth transistor M4 as examples, where all are N-type MOS transistors.

[0079] Combination Figure 5 and Figure 6 As shown, transistors M1 to M4 form a current mirror circuit, which uses a common-source, common-gate current mirror to reflect the positive temperature coefficient current I. PTAT The first adjustable ratio K1 is used to mirror the first transistor M1 and the third transistor M3 to the second transistor M2 and the fourth transistor M4.

[0080] Specifically, the positive temperature coefficient current I output from terminal A is... PTAT The current enters the first transistor M1 and the third transistor M3, and the first transistor M1 and the third transistor M3 are in the positive temperature coefficient current I. PTAT Under the action of these bias voltages, a bias voltage is generated at their respective control electrodes. Through the action of these bias voltages, the multiple parallel second transistors M2 and the multiple parallel fourth transistors M4 mirror the positive temperature coefficient current I with a first adjustable ratio K1. PTAT Let I1 be the first current.

[0081] M2 and M4 are both parallel MOS transistor arrays controlled by switches. A set number X (X greater than or equal to 0 and less than or equal to N) M2 and X M4 transistors can be turned on each time. According to the current mirror principle, the current mirror ratio when one second transistor M2 and one fourth transistor M4 are turned on is 1:Kp. The current mirror ratio is the ratio of the current before and after the mirror, and Kp is a constant coefficient related to the transistor's width-to-length ratio W / L. Therefore, the current mirror ratio when X second transistors M2 and X fourth transistors M4 are turned on is 1:X*Kp. The current flowing through M2 and M4, i.e., the first current, is I1 = K1·I PTAT K1 = X·Kp, where K1 is the first adjustable ratio.

[0082] In some embodiments, the second current mirror module 102 is implemented using a current mirror circuit, such as... Figure 5As shown, the second current mirror module 102 includes a fifth transistor M5, a plurality of sixth transistors M6 connected in parallel, a seventh transistor M7 connected in parallel, and a plurality of eighth transistors M8 connected in parallel.

[0083] Among them, the fifth transistor M5 has its first terminal connected to the negative temperature coefficient current providing terminal B; its control terminal is connected to the first terminal and connected to the third bias voltage terminal ctat1, which is used to provide the third bias voltage V_ctat1 to the second current synthesis circuit 200; its second terminal is connected to the first terminal of the seventh transistor M7.

[0084] Multiple sixth transistors M6 connected in parallel have their control electrodes interconnected and connected to the control electrode of the fifth transistor M5; their first electrodes are interconnected and connected to the current synthesis node N1; their second electrodes are interconnected and connected to the first electrode of multiple eighth transistors M8 connected in parallel. The second adjustable ratio K2 is adjusted according to the number of the multiple sixth transistors M6 connected in parallel that are turned on.

[0085] The seventh transistor M7 has its control terminal connected to the first terminal and to the fourth bias voltage terminal ctat2. The fourth bias voltage terminal ctat2 is used to provide the fourth bias voltage V_ctat2 to the second current synthesis circuit 200; its second terminal is grounded GND.

[0086] Multiple eighth transistors M8 connected in parallel have their control electrodes interconnected and connected to the control electrode of the seventh transistor M7; their first electrodes are interconnected and connected to the second electrodes of multiple sixth transistors M6 connected in parallel; their second electrodes are interconnected and grounded (GND).

[0087] In some embodiments, such as Figure 5 As shown, the input terminal of the negative temperature coefficient current providing terminal B is connected to the high-level voltage providing terminal VDD, and the output terminal is connected to the first terminal and the control terminal of the fifth transistor M5. The high-level voltage providing terminal VDD is used to provide a high-level voltage, and the negative temperature coefficient current providing terminal B provides a negative temperature coefficient current I to the first terminal and the control terminal of the fifth transistor M5 based on the high-level voltage provided by the high-level voltage providing terminal VDD. CTAT .

[0088] In some embodiments, in the second current mirror module 102, a current mirror circuit is formed using a fifth transistor M5, multiple sixth transistors M6 connected in parallel, a seventh transistor M7 connected in parallel, and multiple eighth transistors M8 connected in parallel. The negative temperature coefficient current I output from the negative temperature coefficient current supply terminal B is then transmitted through the current mirror circuit. CTAT The second current I2 is mirrored by the second adjustable ratio K2 and is supplied to the current synthesis node N1.

[0089] In some embodiments, the second current mirror module 102 can be a common-source cascode current mirror structure or a common-source electrode current mirror structure.

[0090] In this embodiment, the second current mirror module 102 can be any suitable current mirror circuit structure, including but not limited to the cascode current mirror structure.

[0091] In some embodiments, the fifth transistor M5 to the eighth transistor M8 are all N-type MOS transistors or NPN transistors, wherein the first electrode of the transistor is the drain (collector), the second electrode is the source (emitter), and the control electrode is the gate (base).

[0092] In some embodiments, the number of sixth transistors M6 is the same as the number of eighth transistors M8, and the transistor sizes of fifth transistors M5 to eighth transistors M8 are the same, that is, the width-to-length ratio (W / L) of the transistors is the same.

[0093] In some embodiments, the number of transistors turned on (conducting) in a plurality of parallel sixth transistors M6 and the number of transistors turned on (conducting) in a plurality of parallel eighth transistors M8 can be controlled by a switching structure, wherein the number of turned-on sixth transistors M6 is the same as the number of turned-on eighth transistors M8.

[0094] The circuit structure of multiple sixth transistors M6 connected in parallel is similar to the circuit structures of multiple second transistors M2 and multiple fourth transistors M4 connected in parallel, as described above, and will not be repeated here. Please refer to [reference needed]. Figure 6 The circuit structure is shown. The first switch structure corresponding to the sixth transistor M6 is coupled between the control electrode of the sixth transistor M6 and the control electrode of the fifth transistor M5, used to control the connection or disconnection between the control electrodes of the sixth transistor M6 and the fifth transistor M5; the second switch structure corresponding to the sixth transistor M6 is coupled between the control electrode of the sixth transistor M6 and the low-level voltage terminal, used to control the connection or disconnection between the control electrode of the sixth transistor M6 and the low-level voltage terminal, which provides a low-level voltage VSS.

[0095] When the sixth transistor M6 needs to be turned on, the first switch structure corresponding to the sixth transistor M6 can be turned on and the corresponding second switch structure can be turned off, thereby connecting the control electrode of the sixth transistor M6 with the control electrode of the fifth transistor M5, and turning on under the bias voltage of the control electrode of the fifth transistor M5; when the sixth transistor M6 needs to be turned off, the first switch structure corresponding to the sixth transistor M6 can be turned off and the corresponding second switch structure can be turned on, thereby connecting the control electrode of the sixth transistor M6 with the low-level voltage terminal, and turning off under the low-level voltage VSS provided by the low-level voltage terminal.

[0096] Similarly, the circuit structure of multiple eighth transistors M8 connected in parallel is similar to the circuit structures of multiple second transistors M2 and multiple fourth transistors M4 connected in parallel, as described above, and will not be repeated here. Please refer to [reference needed]. Figure 6 The circuit structure shown is shown.

[0097] The circuit implementation principle of the second current mirror module 102 will be explained below, taking the fifth transistor M5 to the eighth transistor M8 as examples, which are all N-type MOS transistors.

[0098] Combination Figure 5 and Figure 6 As shown, transistors M5 through M8 form a current mirror circuit, which uses a common-source, common-gate current mirror to reflect the negative temperature coefficient current I. CTAT The fifth transistor M5 and the seventh transistor M7 are mirrored to the sixth transistor M6 and the eighth transistor M8 by a second adjustable ratio K2.

[0099] Specifically, the negative temperature coefficient current I output from terminal B is... CTAT Entering the fifth transistor M5 and the seventh transistor M7, the fifth transistor M5 is in the negative temperature coefficient current I CTAT Under its influence, a third bias voltage V_ctat1 is generated at its control terminal, i.e., the third bias voltage terminal ctat1. The seventh transistor M7 generates a third bias voltage V_ctat1 at the negative temperature coefficient current I. CTAT Under its action, a fourth bias voltage V_ctat2 is generated at its control terminal, i.e., the fourth bias voltage terminal ctat2. Through the action of the bias voltage, the multiple sixth transistors M6 and the multiple eighth transistors M8 connected in parallel mirror the negative temperature coefficient current I with the second adjustable ratio K2. CTAT This is the second current I2.

[0100] M6 and M8 are both parallel MOS transistor arrays controlled by switches. Each time, a set number of N×M6 transistors and N×M8 transistors (where X is the number of times M2 and M4 are turned on) can be activated. According to the current mirror principle, the current mirror ratio when one sixth transistor M6 and one eighth transistor M8 are activated is 1:Kc, where Kc is a constant coefficient related to the transistor's width-to-length ratio W / L. Therefore, the current mirror ratio when N×Sixth Transistors M6 and N×SEighth Transistors M8 are activated is 1:(N×M6)*Kc. The current flowing through M6 and M8, i.e., the second current, is I2 = K2·I CTAT K2 = (N - ×)·Kc, where K2 is the second adjustable ratio.

[0101] In some embodiments, M2, M4, M6, and M8 are of the same quantity and size. For example, each of M2, M4, M6, and M8 is composed of N (N is greater than or equal to 2) MOS transistors of the same size connected in parallel, and the number of transistors turned on is controlled by a switch. If the number of transistors turned on by M2 and M4 each time is X, then the number of transistors turned on by M6 and M8 each time is N. The sum of the number of transistors turned on by M2 and the number of transistors turned on by M6 is N.

[0102] In some embodiments, the first current I1 output by the first current mirroring module 101 and the second current I2 output by the second current mirroring module 102 are superimposed and synthesized at the current synthesis node N1 to form the first reference current I. Out1 Based on the above analysis, the first current I1 = K1·I RTAT K1 = X·Kp, the second current I2 = K2·I CTAT If K2 = (NX)·Kc, then the current at the current-combining node N1 is I. N1 =I1+I2=K1*I PTAT +K2*I CTAT =I Out1 .

[0103] Figure 7 This diagram illustrates the variation of positive temperature coefficient current and negative temperature coefficient current with temperature in embodiments of this application. Figure 8 A schematic diagram showing the first reference current under different slopes is provided in the embodiments of this application, such as... Figure 7 As shown, the positive temperature coefficient current I PTAT For a current that is positively correlated with and linearly changes with temperature, the negative temperature coefficient current I CTAT The current is negatively correlated with temperature and changes linearly.

[0104] like Figure 8 As shown, in the same coordinate system, the positive temperature coefficient current I PTAT Linear variation with temperature and negative temperature coefficient current I CTAT The linear equations that change with temperature intersect at a fixed point O, which is the positive temperature coefficient current I. PTAT and negative temperature coefficient current I CTAT The current is the same at a certain temperature.

[0105] Therefore, at the current synthesis node N1, the positive temperature coefficient current I PTAT and negative temperature coefficient current I CTAT The first reference current used for superposition will also change linearly with temperature, and the straight line presented in the same coordinate system will also pass through the positive temperature coefficient current I. PTAT The corresponding straight line and negative temperature coefficient current I CTAT The fixed intersection point O between the corresponding straight lines, such as Figure 8As shown, the slope of the synthesized first reference current as a function of temperature is linearly different from that of the positive temperature coefficient current I. PTAT The slope and negative temperature coefficient of the current I CTAT The slope is related, and the positive temperature coefficient current I is adjusted. PTAT The slope and / or negative temperature coefficient of the current I CTAT The slope of the synthesized reference current can be adjusted to allow for linear variation with temperature. Specifically, the adjustable slope range of the first reference current's linear variation with temperature is greater than or equal to the negative temperature coefficient current I. CTAT The slope of the current I is less than or equal to the positive temperature coefficient. PTAT The slope of the synthesized first reference current varies with temperature, and the straight line of the first reference current varies with temperature under different slopes, all pass through the above fixed intersection point O.

[0106] Based on the current formula for the current synthesis node N1, the positive temperature coefficient current I can be controlled by the first adjustable ratio K1. PTAT The slope of the negative temperature coefficient current I can be controlled by the second adjustable ratio K2. CTAT Therefore, by adjusting the first adjustable ratio K1 and / or the second adjustable ratio K2, the slope of the first reference current I can be effectively controlled. Out1 Adjustment of the slope.

[0107] In some embodiments, by controlling the number X of the second transistor M2 and the fourth transistor M4 that are turned on, the first adjustable ratio K1 can be adjusted; by controlling the number NX of the sixth transistor M6 and the fourth transistor M8 that are turned on, the second adjustable ratio K2 can be adjusted, thereby controlling the first reference current I. Out1 The slope of the first reference current is adjusted based on the different number of turns on (X) of the second transistor M2 and the fourth transistor M4, under a positive temperature coefficient current I. PTAT and negative temperature coefficient current I CTAT The temperature slopes of the two are transformed, and the first reference current I is made possible. Out1 It remains relatively constant at a certain temperature (the temperature corresponding to the fixed intersection point O mentioned above) under different slopes.

[0108] In some embodiments, in the first current synthesis circuit 100, the first current mirror module 101 and the second current mirror module 102 respectively mirror the positive temperature coefficient current I through current mirrors composed of MOS transistors. PTAT and negative temperature coefficient current I CTAT A linear operation is performed at current synthesis node N1 to synthesize the first reference current. This first reference current is unaffected by the nonlinearity of the MOSFET and its high / low temperature characteristics, resulting in a more accurate synthesized reference current. Among these, the positive temperature coefficient current I... PTAT and negative temperature coefficient current ICTAT The first reference current is synthesized according to an adjustable ratio. The total number of MOSFETs turned on in the first current mirror module 101 and the second current mirror module 102 is fixed. The number of MOSFETs turned on in the first current mirror module 101 and the second current mirror module 102 can be symmetrically controlled by a single set of control words. By turning on different numbers of MOSFETs, the magnitude of the synthesized first reference current is kept constant at a certain temperature point. This makes it more convenient and concise to use, and achieves the function of adjusting the slope of the precise first reference current. Moreover, there is a clear and accurate mapping relationship between the output first reference current and the input positive and negative temperature coefficient current.

[0109] In some embodiments, the third current mirror module 103 is implemented using a current mirror circuit, such as... Figure 5 As shown, the third current mirror module 103 includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12.

[0110] Among them, the control electrode of the ninth transistor M9 is connected to the control electrode of the eleventh transistor M11; its first electrode is connected to the high-level voltage supply terminal VDD, which is used to provide a high-level voltage; its second electrode is connected to the control electrode and is connected to the first electrode of the tenth transistor M10.

[0111] The tenth transistor M10 has its control electrode connected to the second electrode and connected to the current synthesis node N1.

[0112] The eleventh transistor M11 has its first terminal connected to the high-level voltage supply terminal VDD, and its second terminal connected to the first terminal of the twelfth transistor M12.

[0113] The twelfth transistor M12 has its control electrode connected to the control electrode of the tenth transistor M10, and its second electrode is the first reference current output terminal Out1.

[0114] In some embodiments, in the third current mirror module 103, a current mirror circuit is formed using the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12, and the current at the current synthesis node N1 is the first reference current I. Out1 The first reference current I is reflected by the current mirror circuit composed of transistors M9, M10, M11, and M12. The current mirror is then reflected from M9 and M10 to M11 and M12, and finally output to an external circuit through the second terminal of transistor M12, i.e., the first reference current output terminal Out1. Specifically, the current mirror circuit composed of transistors M9, M10, M11, and M12 reflects the first reference current I.Out1 The current mirror ratio can be configured according to the actual reference current required by the external circuit, and this application embodiment does not impose any special restrictions on this.

[0115] In some embodiments, the third current mirror module 103 can be a common-source cascode current mirror structure or a common-source current mirror structure.

[0116] In this embodiment, the third current mirror module 103 can be any suitable current mirror circuit structure, including but not limited to the cascode current mirror structure.

[0117] In some embodiments, the ninth transistor M9 to the twelfth transistor M2 are all P-type MOS transistors or PNP transistors, wherein the first electrode of the transistor is the source (emitter), the second electrode is the drain (collector), and the control electrode is the gate (base).

[0118] In some embodiments, the transistor dimensions, i.e. the width-to-length ratio (W / L), of the ninth transistor M9 to the twelfth transistor M12 can be pre-configured according to the reference current required by the actual external circuit. This application does not impose any special restrictions on this.

[0119] The circuit implementation principle of the third current mirror module 103 will be explained below, taking the ninth transistor M9 to the twelfth transistor M12 as examples, which are all P-type MOS transistors.

[0120] like Figure 5 As shown, transistors M9 to M12 form a current mirror circuit, which synthesizes the current at node N1, i.e., the first reference current I, using a common-source, common-gate current mirror method. Out1 The current mirroring ratio is pre-configured from the ninth transistor M9 and the tenth transistor M10 to the eleventh transistor M11 and the twelfth transistor M12.

[0121] Specifically, the first reference current I output from the current synthesis node N1 Out1 Entering the tenth transistor M10, the tenth transistor M10 is subjected to the first reference current I. Out1 The transistor is turned on by its function, and a corresponding bias voltage is generated at the control electrode of the tenth transistor M10. At the same time, the first reference current I... Out1 The current flows through the conducting tenth transistor M10 to the ninth transistor M9, which is then subjected to the first reference current I. Out1 The transistor is turned on by the action of the control electrode of the ninth transistor M9, and a corresponding bias voltage is generated at the control electrode of the tenth transistor M10. Through the bias voltage of the control electrodes of the ninth transistor M9 and the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 mirror the first reference current I with a pre-configured current mirror ratio (e.g., current mirror ratio is 1).Out1 First reference current I Out1 The current is output through the eleventh transistor M11 and the twelfth transistor M12, and through the second terminal of the twelfth transistor M12, which is the first reference current output terminal Out1.

[0122] In some embodiments, the fourth current mirror module 104 is implemented using a current mirror circuit, such as... Figure 5 As shown, the fourth current mirror module 104 includes a ninth transistor M9, a tenth transistor M10, a thirteenth transistor M13, and a fourteenth transistor M14. That is, the fourth current mirror module 104 and the third current mirror module 103 share the ninth transistor M9 and the tenth transistor M10.

[0123] Among them, the control electrode of the ninth transistor M9 is connected to the control electrode of the thirteenth transistor M13; its first electrode is connected to the high-level voltage supply terminal VDD; its second electrode is connected to the control electrode and connected to the first electrode of the tenth transistor M10.

[0124] The tenth transistor M10 has its control electrode connected to the second electrode and connected to the current synthesis node N1.

[0125] The thirteenth transistor M13 has its first terminal connected to the high-level voltage supply terminal VDD, and its second terminal connected to the first terminal of the fourteenth transistor M14.

[0126] The fourteenth transistor M14 has its control electrode connected to the control electrode of the tenth transistor M10, and its second electrode connected to the first bias voltage generation module 105.

[0127] In some embodiments, in the fourth current mirror module 104, a current mirror circuit is formed using the ninth transistor M9, the tenth transistor M10, the thirteenth transistor M13, and the fourteenth transistor M14, and the current at the current synthesis node N1 is the first reference current I. Out1 The first bias voltage is reflected by the current mirror circuit composed of transistors M9, M10, M13, and M14. The current mirror is then reflected from M9 and M10 to M13 and M14, and finally output to the first bias voltage generation module 105 via the second terminal of the fourteenth transistor M14. Specifically, the current mirror circuit reflects the first reference current I. Out1 The current mirror ratio is 1:1.

[0128] In some embodiments, the fourth current mirror module 104 can be a common-source cascode current mirror structure or a common-source electrode current mirror structure.

[0129] In this embodiment, the third current mirror module 104 can be any suitable current mirror circuit structure, including but not limited to the cascode current mirror structure.

[0130] In some embodiments, the thirteenth transistor M13 and the fourteenth transistor M4 are both P-type MOS transistors or PNP transistors, wherein the first electrode of the transistor is the source (emitter), the second electrode is the drain (collector), and the control electrode is the gate (base).

[0131] In some embodiments, the transistor dimensions, i.e. width-to-length ratio (W / L), of the thirteenth transistor M13 and the fourteenth transistor M14 are the same as those of the ninth transistor M9 and the tenth transistor M10.

[0132] For the circuit implementation principle of the fourth current mirror module 104, please refer to the above description of the circuit implementation principle of the third current mirror module 103, which will not be repeated here.

[0133] In some embodiments, such as Figure 5 As shown, the first bias voltage generation module 105 includes a fifteenth transistor M15 and a sixteenth transistor M16.

[0134] Among them, the fifteenth transistor M15 has its first terminal connected to the output terminal of the fourth current mirror module 104 (that is, the second terminal of the fourteenth transistor M14); its control terminal is connected to the first terminal and connected to the first bias voltage terminal linear1, which is used to provide the first bias voltage V_linear1 to the second current synthesis circuit 200; its second terminal is connected to the first terminal of the sixteenth transistor M16.

[0135] The sixteenth transistor M16 has its control terminal connected to the first terminal and connected to the second bias voltage terminal linear2. The second bias voltage terminal linear2 is used to provide the second bias voltage V_linear2 to the second current synthesis circuit 200; its second terminal is grounded GND.

[0136] In some embodiments, in the first bias voltage generation module 105, the first terminal of the fifteenth transistor M15 is shorted to the control terminal and connected to the output terminal of the fourth current mirror module 104 (i.e., the second terminal of the fourteenth transistor M14) to receive the first reference current I output from the output terminal of the fourth current mirror module 104. Out1 The fifteenth transistor M15 is in the first reference current I Out1 Under the action of [something], it is turned on, and a corresponding first bias voltage V_linear1 is generated at the control terminal of the fifteenth transistor M15, which is also the first bias voltage terminal linear1. At the same time, the first reference current I [something].Out1 The signal flows from the fifteenth transistor M15 to the sixteenth transistor M16, which is in operation. The sixteenth transistor M16 then operates at the first reference current I. Out1 Under the action of the transistor, the transistor is turned on, and at the control terminal of the sixteenth transistor M16, which is also the second bias voltage terminal linear2, a corresponding second bias voltage V_linear2 is generated. The first bias voltage V_linear1 and the second bias voltage V_linear2 can be used to mirror the first reference current.

[0137] In some embodiments, the fifteenth transistor M15 and the sixteenth transistor M16 are both N-type MOS transistors or NPN transistors, wherein the first electrode of the transistor is the drain (collector), the second electrode is the source (emitter), and the control electrode is the gate (base).

[0138] Figure 9 This diagram illustrates the structural composition of a second current synthesis circuit according to an embodiment of this application. In some embodiments, such as... Figure 9 As shown, the second current synthesis circuit 200 includes a reference current mirror module 201, a negative temperature coefficient current mirror module 202, a current synthesis module 203, a fifth current mirror module 204, and a current decomposition module 205. The reference current mirror module 201, the current synthesis module 203, and the fifth current mirror module 204 are all connected to the first control node C1. The negative temperature coefficient current mirror module 202, the current synthesis module 203, and the fifth current mirror module 204 are all connected to the second control node C2. The fifth current mirror module 204 and the current decomposition module 205 are both connected to the current decomposition node N2.

[0139] The reference current mirror module 201 is configured to mirror the first reference current I. Out1 According to the first preset ratio K I The image is a third current I3, which is transmitted to the first control node C1. Here, the third current I3 is the first reference current I. Out1 With the first preset ratio K I The product of, i.e., I3 = I PTAT ×K I .

[0140] The negative temperature coefficient current mirror module 202 is configured to reflect the negative temperature coefficient current I. CTAT Mirror K according to the second preset ratio c2 This is the fourth current I4, which is transmitted to the second control node C2. The fourth current I4 is a negative temperature coefficient current I... CTAT With the second preset ratio K c2 The product of, i.e., I4 = I CTAT ×K c2 .

[0141] The current synthesis module 203 is configured to generate a fifth current I5 based on the third current I3 of the first control node C1 and the fourth current I4 of the second control node C2.

[0142] The fifth current mirroring module 204 is configured to mirror the fifth current I5 output by the current synthesis module 203 and output it to the current decomposition node N2 based on the third current I3 of the first control node C1 and the fourth current I4 of the second control node.

[0143] The current decomposition module 205 is configured to decompose a second reference current I that varies non-linearly with temperature from the fifth current I5 at the current decomposition node N2. Out2 .

[0144] In some embodiments, such as Figure 4 and Figure 9 As shown, the reference current mirror module 201 and the first current synthesis circuit 100 are coupled through the first bias voltage terminal linear1 and the second bias voltage terminal linear2.

[0145] The first current synthesis circuit 100 is further configured to synthesize currents based on a first reference current I. Out1 A first bias voltage V_linear1 and a second bias voltage V_linear2 are generated, which are used to mirror the first reference current I. Out1 A first bias voltage V_linear1 is provided to the first bias voltage terminal linear1, and a second bias voltage V_linear2 is provided to the second bias voltage terminal linear2; the reference current mirror module 201 is configured to mirror the first reference current I based on the first bias voltage V_linear1 of the first bias voltage terminal linear1 and the second bias voltage V_linear2 of the second bias voltage terminal linear2. Out1 According to the first preset ratio K I The mirror image is the third current I3.

[0146] In some embodiments, the reference current I is mirrored from the first current synthesis circuit 100 using the reference current mirroring module 201. Out1 This is beneficial for improving the acquisition of the first reference current I by the second current synthesis circuit 200. Out1 The accuracy and stability.

[0147] In some embodiments, such as Figure 4 and Figure 9 As shown, the negative temperature coefficient current mirror module 202 and the first current synthesis circuit 100 are coupled through the third bias voltage terminal ctat1 and the fourth bias voltage terminal ctat2.

[0148] The first current synthesis circuit 100 is also configured to synthesize currents based on the negative temperature coefficient current I. CTAT A third bias voltage V_ctat1 and a fourth bias voltage V_ctat2 are generated. These three bias voltages V_ctat1 and V_ctat2 are used to mirror the negative temperature coefficient current I. CTAT A third bias voltage V_ctat1 is provided to the third bias voltage terminal ctat1, and a fourth bias voltage V_ctat2 is provided to the fourth bias voltage terminal ctat2; the negative temperature coefficient current mirror module 202 is configured to reflect the negative temperature coefficient current I based on the third bias voltage V_ctat1 at the third bias voltage terminal ctat1 and the fourth bias voltage V_ctat2 at the fourth bias voltage terminal ctat2. CTAT According to the second preset ratio K c2 The mirror image is the fourth current I4.

[0149] In some embodiments, the negative temperature coefficient current I is mirrored from the first current synthesis circuit 100 using the negative temperature coefficient current mirroring module 202. CTAT This is beneficial for improving the acquisition of negative temperature coefficient current I by the second current synthesis circuit 200. CTAT The accuracy and stability.

[0150] In some embodiments, the fifth current I5 generated by the current synthesis module 203 is composed of the first portion of the current I. 51 The second part of the current I 52 and the third part of the current I 53 Superposition and synthesis, the first part of the current I 51 The second part of the current I is related to the fourth current I4. 52 The third part of the current I is related to the third current I3. 53 The currents associated with the fourth current I4 and the third current I3, wherein the first part of the current I 51 Second part of the current I 52 All are currents that change linearly with temperature; the third part is the current I. 53 For a current that varies non-linearly with temperature, the current decomposition module 205 obtains the third part of the current I from the fifth current I5 at the current decomposition node N2. 53 As the second reference current I Out2 .

[0151] In some embodiments, the current synthesis module 203 synthesizes a current I including the first part, based on a third current I3 obtained by mirroring the first reference current and a fourth current I4 obtained by comparing the negative temperature coefficient current. 51 The second part of the current I 52 and the third part of the current I 53The fifth current I5 is used to extract the third part of the current I5 as the second reference current I through the current decomposition module 205. Out2 Second reference current I Out2 It features high-order curve current characteristics, with the current changing non-linearly with temperature, thus generating a larger high-temperature reference current, which can better compensate for the performance of external circuit modules over a wide temperature range.

[0152] In some embodiments, such as Figure 9 As shown, the output terminal of the current decomposition module 205 is the second reference current output terminal Out2, which is used to output the second reference current I to an external circuit. Out2 .

[0153] Figure 10 This illustration shows a schematic diagram of the composition structure of another second current synthesis circuit provided in an embodiment of this application. In some embodiments, such as... Figure 10 As shown, in the second current synthesis circuit 200, the current decomposition module 205 includes a first current submodule 2051, a second current submodule 2052, and a third current submodule 2053.

[0154] The first current submodule 2051, the second current submodule 2052, and the third current submodule 2053 are all connected to the current decomposition node N2; the first current submodule 2051 and the first current synthesis circuit 100 are coupled through the third bias voltage terminal ctat1 and the fourth bias voltage terminal ctat2; the second current submodule 2052 and the first current synthesis circuit 100 are coupled through the first bias voltage terminal linear1 and the second bias voltage terminal linear2.

[0155] Combination Figure 4 and Figure 10 As shown, the first current synthesis circuit 100 is also configured to synthesize currents based on the negative temperature coefficient current I. CTAT A third bias voltage V_ctat1 and a fourth bias voltage V_ctat2 are generated. The third bias voltage V_ctat1 is provided to the third bias voltage terminal ctat1, and the fourth bias voltage V_ctat2 is provided to the fourth bias voltage terminal ctat2. The third bias voltage V_ctat1 and the fourth bias voltage V_ctat2 are used to mirror the negative temperature coefficient current.

[0156] The first current submodule 2051 is configured to transfer the negative temperature coefficient current I based on the third bias voltage V_ctat1 at the third bias voltage terminal ctat1 and the fourth bias voltage V_ctat2 at the fourth bias voltage terminal ctat2. CTAT According to the second preset ratio K c2The mirror image is the first sub-current, which is the first part of the fifth current I5 in the current decomposition node N2. 51 The first sub-current is equal to the fourth current I4 mentioned above, i.e., I 51 =K c2 *I CTAT =I4.

[0157] Combination Figure 4 and Figure 10 As shown, the first current synthesis circuit 100 is also configured to synthesize currents based on a first reference current I. PTAT A first bias voltage V_linear1 and a second bias voltage V_linear2 are generated. The first bias voltage V_linear1 is provided to the first bias voltage terminal linear1, and the second bias voltage V_linear2 is provided to the second bias voltage terminal linear2. The first bias voltage V_linear1 and the second bias voltage V_linear2 are used to mirror the first reference current I. PTAT .

[0158] The second current submodule 2052 is configured to, based on the first bias voltage V_linear1 of the first bias voltage terminal linear1 and the second bias voltage V_linear2 of the second bias voltage terminal linear2, convert the first reference current I... PTAT According to the third preset ratio K I1 The mirror image is the second sub-current, which is the second part of the fifth current I5 in the current decomposition node N2. 52 The third preset ratio K I1 The first preset ratio K I The second sub-current is half of the aforementioned third current I3, i.e., I 52 =K I1 *I PTAT =K I *I PTAT / 2 = I3 / 2.

[0159] The third current submodule 2053 is configured to receive the third portion of the fifth current I5 from the current decomposition node N2. 53 and the third part of the current I 53 The mirror image is the second reference current I. Out2 .

[0160] In some embodiments, such as Figure 10 As shown, the output terminal of the third current submodule 2053 is also the output terminal of the current decomposition module 205, which serves as the second reference current output terminal Out2, used to output the second reference current I to the external circuit. Out2 .

[0161] In some embodiments, by setting the first current submodule 2051, the second current submodule 2051, and the third current submodule 2053 as three current branches connecting the current decomposition node N2, the fifth current I5 of the current decomposition node N2 is decomposed. Specifically, the first current submodule 2051 generates a first sub-current to decompose a first portion of current I from the fifth current I5 of the current decomposition node N2. 51 The second sub-current is generated by the second current sub-module 2052 to decompose the second part of the current I from the fifth current I5 at the current decomposition node N2. 52 The remaining portion of the fifth current I5 at node N2, which is the third portion of the current I... 53 The current then flows to the third current submodule 2053, where it is mirrored to generate the second reference current I. Out2 .

[0162] Figure 11 This illustration shows a schematic diagram of the composition structure of another second current synthesis circuit provided in an embodiment of this application. In some embodiments, such as... Figure 11 As shown, the second current synthesis circuit 200 also includes a sixth current mirror module 206. The input terminal of the sixth current mirror module 206 is connected to the output terminal of the current decomposition module 205, and the output terminal of the sixth current mirror module 206 is the second reference current output terminal Out2.

[0163] The sixth current mirror module 206 is configured to output the second reference current I from the current decomposition module 205. Out2 According to the fourth preset ratio K sq After mirroring, the output is transmitted through the second reference current output terminal Out2.

[0164] In some embodiments, such as Figure 11 As shown, the input terminal of the sixth current mirror module 206 is connected to the output terminal of the third current submodule 2053.

[0165] In some embodiments, the second reference current I is reflected by the sixth current mirror module 206. Out2 After mirroring, the second reference current is output to an external circuit through the second reference current output terminal Out2, which helps to achieve a stable second reference current output. Furthermore, the current mirroring ratio of the sixth current mirroring module 206 can be configured according to the required magnitude of the second reference current to mirror the second reference current I. Out2 The output is mirrored according to the pre-configured current mirror ratio.

[0166] Figure 12 This illustration shows a schematic diagram of the implementation circuit structure of a second current synthesis circuit provided in an embodiment of this application. In some embodiments, such as... Figure 12 As shown, the reference current mirror module 201 includes a seventeenth transistor M17 and an eighteenth transistor M18.

[0167] Among them, the seventeenth transistor M17 has its control terminal connected to the first bias voltage terminal linear1; its first terminal is connected to the first control node C1; and its second terminal is connected to the first terminal of the eighteenth transistor M18.

[0168] The eighteenth transistor, M18, has its control terminal connected to the second bias voltage terminal, linear2; its second terminal is grounded, GND.

[0169] In some embodiments, combined with Figure 5 and Figure 12 As shown, the reference current mirror module 201, through the seventeenth transistor M17 and the eighteenth transistor M18, forms a current mirror circuit with the fifteenth transistor M15 and the sixteenth transistor M16 in the first bias voltage generation module 105 of the first current synthesis circuit 100. Utilizing the current mirroring effect of the current mirror circuit, the first reference current I is reflected by the fifteenth transistor M15 and the sixteenth transistor M16. Out1 With the first preset ratio K I Mirroring to the seventeenth transistor M17 and the eighteenth transistor M18, the current flowing through the seventeenth transistor M17 and the eighteenth transistor M18 is the third current I3, I3 = K. I *I Out1 .

[0170] In some embodiments, combined with Figure 5 and Figure 12 As shown, the current mirror circuit formed by the reference current mirror module 201 and the first bias voltage generation module 105 can be a common source cascode current mirror structure or a common source current mirror structure.

[0171] In some embodiments, combined with Figure 5 and Figure 12 As shown, the current mirror circuit formed by the reference current mirror module 201 and the first bias voltage generation module 105 can be any suitable current mirror circuit structure, including but not limited to the cascode current mirror structure.

[0172] In some embodiments, the seventeenth transistor M17 and the eighteenth transistor M18 are both N-type MOS transistors or NPN transistors, wherein the first electrode of the transistor is the drain (collector), the second electrode is the source (emitter), and the control electrode is the gate (base).

[0173] In some embodiments, the transistor dimensions of the seventeenth transistor M17 and the eighteenth transistor M18, i.e., the width-to-length ratio (W / L), can be configured according to a current mirror ratio, i.e., a first preset ratio K.I Configure it, and the first preset ratio K I The reference current required by the actual external circuit can be pre-configured, and this application embodiment does not impose any special restrictions on this.

[0174] The circuit implementation principle of the reference current mirror module 201 will be explained below, taking the seventeenth transistor M17 and the eighteenth transistor M18 as examples, both of which are N-type MOS transistors.

[0175] Combination Figure 5 and Figure 12 As shown, transistors M15 through M18 form a current mirror circuit. Transistors M17 and M18 use a common-source, common-gate current mirror to reflect the currents of transistors M15 and M16, i.e., the first reference current I. Out1 The current mirror ratio is pre-configured, i.e., the first preset ratio K. I The mirror image is the third current I3.

[0176] Specifically, the first reference current I Out1 Entering the fifteenth transistor M15, at the first reference current I Out1 Under the action of the fifteenth transistor M15, the control terminal, i.e., the first bias voltage terminal linear1, generates the first bias voltage V_linear1 and the first reference current I. Out1 The current flows through the fifteenth transistor M15 to the sixteenth transistor M16, at the first reference current I. Out1 Under the action of the control terminal of the sixteenth transistor M16, namely the second bias voltage terminal linear2, a second bias voltage V_linear2 is generated.

[0177] Under the action of the first bias voltage V_linear1 at the first bias voltage terminal linear1 and the second bias voltage V_linear2 at the second bias voltage terminal linear2, the seventeenth transistor M17 and the eighteenth transistor M18 move in a pre-configured current mirror ratio, i.e., the first preset ratio K. I Mirroring the first reference current I Out1 With the first preset ratio K I The first reference current I of the mirror Out1 The current becomes the third current I3. At this time, the current flowing through the seventeenth transistor M17 and the eighteenth transistor M18 is the third current I3, which is also the current at the first control node C1. I3 = K I *I Out1 .

[0178] In some embodiments, such as Figure 12As shown, the negative temperature coefficient current mirror module 202 includes a nineteenth transistor M19 and a twentieth transistor M20.

[0179] Among them, the nineteenth transistor M19 has its control terminal connected to the third bias voltage terminal ctat1; its first terminal connected to the second control node C2; ​​and its second terminal connected to the first terminal of the twentieth transistor M20.

[0180] The twentieth transistor M20 has its control terminal connected to the fourth bias voltage terminal ctat2; its second terminal is grounded (GND).

[0181] In some embodiments, combined with Figure 5 and Figure 12 As shown, the negative temperature coefficient current mirror module 202, through the nineteenth transistor M19 and the twentieth transistor M20, forms a current mirror circuit with the fifth transistor M5 and the seventh transistor M7 in the second current mirror module 102 of the first current synthesis circuit 100. Utilizing the current mirroring effect of the current mirror circuit, the negative temperature coefficient current I is amplified through the fifth transistor M5 and the seventh transistor M7. CTAT With the second preset ratio K c2 Mirroring to the nineteenth transistor M19 and the twentieth transistor M18, the current flowing through the nineteenth transistor M19 and the twentieth transistor M20 is the fourth current I4, I4 = K. c2 *I CTAT .

[0182] In some embodiments, combined with Figure 5 and Figure 12 As shown, the current mirror circuit formed by the negative temperature coefficient current mirror module 202 and the fifth transistor M5 and the seventh transistor M7 in the second current mirror module 102 can be a common source cascode current mirror structure or a common source current mirror structure.

[0183] In some embodiments, combined with Figure 5 and Figure 12 As shown, the current mirror circuit formed by the negative temperature coefficient current mirror module 202 and the fifth transistor M5 and the seventh transistor M7 in the second current mirror module 102 can be any suitable current mirror circuit structure, including but not limited to the cascode current mirror structure.

[0184] In some embodiments, the nineteenth transistor M19 and the twentieth transistor M20 are both N-type MOS transistors or NPN transistors, wherein the first electrode of the transistor is the drain (collector), the second electrode is the source (emitter), and the control electrode is the gate (base).

[0185] In some embodiments, the transistor dimensions of the nineteenth transistor M19 and the twentieth transistor M20, i.e., the aspect ratio (W / L), can be configured as needed by a current mirror ratio, i.e., a second preset ratio K. c2 Configure it, and the second preset ratio K c2 The reference current required by the actual external circuit can be pre-configured, and this application embodiment does not impose any special restrictions on this.

[0186] The circuit implementation principle of the negative temperature coefficient current mirror module 202 will be explained below, taking the nineteenth transistor M19 and the twentieth transistor M20 as examples, both of which are N-type MOS transistors.

[0187] Combination Figure 5 and Figure 12 As shown, the fifth transistor M5, the seventh transistor M7, the nineteenth transistor M19, and the twentieth transistor M20 form a current mirror circuit. The nineteenth transistor M19 and the twentieth transistor M20 convert the current of the fifth transistor M5 and the seventh transistor M7, i.e., the negative temperature coefficient current I, into a common-source, common-gate current mirror. CTAT The pre-configured current mirror ratio, i.e., the second preset ratio K, is used. c2 The mirror image is the fourth current I4.

[0188] Specifically, the negative temperature coefficient current I CTAT Entering the fifth transistor M5, at the negative temperature coefficient current I CTAT Under the action of the fifth transistor M5, the control electrode, i.e., the third bias voltage terminal ctat1, generates the third bias voltage V_ctat1, and the negative temperature coefficient current I. CTAT The current flows through the conducting fifth transistor M5 to the seventh transistor M7, where the negative temperature coefficient current I... CTAT Under the action of the control terminal of the seventh transistor M7, namely the fourth bias voltage terminal ctat2, a fourth bias voltage V_ctat2 is generated.

[0189] Under the action of the third bias voltage V_ctat1 at the third bias voltage terminal ctat1 and the fourth bias voltage V_ctat2 at the fourth bias voltage terminal ctat2, the nineteenth transistor M19 and the twentieth transistor M20 operate at a pre-configured current mirror ratio, i.e., the second preset ratio K. c2 Mirroring the negative temperature coefficient current I CTAT With the second preset ratio K c2 The negative temperature coefficient current I of the mirror image CTAT The current becomes the fourth current I4. At this time, the current flowing through the nineteenth transistor M19 and the twentieth transistor M20 is the fourth current I4, which is also the current at the second control node C2. I4 = K c2 *I CTAT .

[0190] In some embodiments, such as Figure 12 As shown, the current synthesis module 203 includes a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, and a twenty-fifth transistor M25.

[0191] Among them, the first terminal of the twenty-first transistor M21 is connected to the high-level voltage supply terminal VDD; its control terminal is connected to the second terminal and connected to the first terminal of the twenty-second transistor M22.

[0192] The twenty-second transistor M22 has its control electrode connected to its second electrode and connected to the second control node C2.

[0193] The twenty-third transistor M23 has its first terminal connected to the high-level voltage supply terminal VDD; its control terminal is connected to its second terminal and connected to the first control node C1.

[0194] The first terminal of the twenty-fourth transistor M24 is connected to the second terminal of the twenty-third transistor M23; its control terminal is connected to the control terminal of the twenty-second transistor M22; and its second terminal is connected to the first terminal of the twenty-fifth transistor M25.

[0195] The twenty-fifth transistor, M25, has its control electrode connected to its first electrode, and its second electrode grounded (GND).

[0196] In some embodiments, transistors M21 to M24 are all P-type MOS transistors or PNP transistors, wherein the first electrode of the transistor is the source (emitter), the second electrode is the drain (collector), and the control electrode is the gate (base).

[0197] In some embodiments, the twenty-fifth transistor M25 is an N-type MOS transistor or an NPN transistor, wherein the first electrode of the transistor is the drain (collector), the second electrode is the source (emitter), and the control electrode is the gate (base).

[0198] In some embodiments, the transistor dimensions, i.e. width-to-length ratio (W / L), of the twenty-first transistor M21 to the twenty-fourth transistor M24 are the same.

[0199] The circuit implementation principle of the current synthesis module 203 will be explained below, taking the twenty-first transistor M21 to the twenty-fourth transistor M24 as examples, all of which are P-type MOS transistors.

[0200] It should be noted that the formula for the saturation current of a MOSFET can be expressed as I D =C×(V) gs -Vth) 2 C = 0.5 * k * (W / L), where I DWhere is the saturation current, k is the saturation current gain coefficient, W / L is the width-to-length ratio of the transistor, and V is the gain coefficient. gs Vth is the gate-source voltage of the transistor, and Vth is the threshold voltage of the transistor. Since the transistor sizes of transistors M21 to M24 are the same, the C parameter is assumed to be the same in the saturation current of transistors M21 to M24, and the threshold voltage Vth parameter is assumed to be the same.

[0201] Combination Figure 12 As shown, based on the above analysis of the negative temperature coefficient current mirror module 202, the current at the second control node C2 is the fourth current I4, that is, the current flowing through the twenty-first transistor M21 and the twenty-second transistor M22 is the fourth current I4.

[0202] Since transistors M21 through M24 have the same size, the gate-source voltage V of transistor M21 is... gs21 Equal to the gate-source voltage V of the twenty-second transistor M22 gs22 The saturation current I of the twenty-first transistor M21 D21 Equal to the saturation current I of the twenty-second transistor M22 D22 The saturation current I of the twenty-second transistor M22 D22 Let I4 be the fourth current. According to the above formula for the saturation region current, we can obtain:

[0203] I D21 =I D22 =I4=C×(V) gs21 -Vth) 2 =C×(V) gs22 -Vth) 2

[0204] Therefore, the gate-source voltage V of the twenty-first transistor M21 can be obtained. gs21 The gate-source voltage V of the twenty-second transistor M22 gs22 for:

[0205]

[0206] Based on the above analysis of the reference current mirror module 201, the current at the first control node C1 is the third current I3. Assuming the saturation current of the twenty-fourth transistor M24 is I... D24 =I a Therefore, it can be determined that the saturation current I of the twenty-third transistor M23 is... D23 The current I flowing through the twenty-fourth transistor M24 a The sum of the third current I3 and the first control node C1, i.e., I D23 =Ia +I3, based on the above saturation current formula, the gate-source voltage V of the twenty-third transistor M23 can be determined. gs23 And the gate-source voltage V of the twenty-fourth transistor M24 gs24 They are respectively:

[0207]

[0208] Since transistors M21 through M24 have the same size, the gate voltage V of transistor M22 is... g22 Equal to the gate voltage V of the twenty-fourth transistor M24 g24 The gate voltage V of the twenty-second transistor M22 g22 Equal to the gate-source voltage V of the twenty-first transistor M21 gs21 With the gate-source voltage V of the twenty-second transistor M22 gs22 The sum of these values ​​represents the gate voltage V of the twenty-fourth transistor M24. g24 Equal to the gate-source voltage V of the twenty-third transistor M23 gs23 With the gate-source voltage V of the twenty-fourth transistor M24 gs24 Therefore, the gate-source voltage V of the twenty-first transistor M21 can be determined. gs21 The gate-source voltage V of the twenty-second transistor M22 gs22 The gate-source voltage V of the twenty-third transistor M23 gs23 The gate-source voltage V of the twenty-fourth transistor M24 gs24 The following relationship must be satisfied:

[0209] V gs21 +V gs22 =V gs23 +V gs24

[0210] Combining the above with the gate-source voltage V of transistors M21 to M24 (21st to 24th transistors) gs From the analysis, we can obtain:

[0211]

[0212] Further simplification of the above formula yields:

[0213]

[0214] The current I flowing through the 24th transistor M24 can be calculated using the above formula. a The third current I3 and the fourth current I4 satisfy the following relationship:

[0215]

[0216] Based on the above analysis, the current flowing through the twenty-third transistor M23, i.e., the saturation current I of the twenty-third transistor M23... D23 The current I flowing through the twenty-fourth transistor M24 a The sum of the third current I3, i.e., I D23 =I a +I3, combined with the above current I a The relationship between the currents I3 and I4 can be used to determine the current I flowing through the twenty-third transistor M23. D23 The third current I3 and the fourth current I4 satisfy the following relationship:

[0217]

[0218] Combining the aforementioned third current I3 with the first reference current I Out1 Relationship: I3 = K I *I Out1 And the fourth current I4 and the negative temperature coefficient current I CTAT Relationship: I4 = K c2 *I CTAT The current I flowing through the twenty-third transistor M23 can be determined. D23 With the first reference current I Out1 Negative temperature coefficient current I CTAT The following relationship must be satisfied:

[0219]

[0220] Among them, the current I flowing through the twenty-third transistor M23 D23 This is the fifth current I5, and the fifth current I5 = I D23 .

[0221] Based on the above analysis, the current synthesis module 203 utilizes the transistor characteristics of the twenty-first transistor M21 to the twenty-fourth transistor M23 of the same size to synthesize a fifth current I5 based on the third current I3 generated by the reference current mirror module 201 and the fourth current I4 generated by the negative temperature coefficient current mirror module 202. The fifth current I5 satisfies the above current I... D23 The relationship with the third current I3 and the fourth current I4 is based on the above current I. D23 With the first reference current I Out1 Negative temperature coefficient current I CTAT From the relationship, we can see that the fifth current I5 is composed of the superposition of three currents, where the fourth current I4 = K c2 ×I CTAT As the first part of the current I 51 Half of the third current I3 is I3 / 2 = KI ×I Out1 / 2 serves as the second part of the current I 52 The remaining current As the third part of the current I 53 .

[0222] According to the first part of the fifth current I5 mentioned above, the current I 51 The second part of the current I 52 and the third part of the current I 53 It can be seen that the first part of the current I 51 To match the negative temperature coefficient of the current I that varies linearly with temperature CTAT The relevant current exhibits a current characteristic that changes linearly with temperature; the second part is the current I. 52 To match the first reference current I that varies linearly with temperature Out1 The relevant current exhibits a current characteristic that changes linearly with temperature; while the third part, current I... 53 With the first reference current I Out1 The sum of the squares of the negative temperature coefficient of the current I CTAT The relevant current exhibits high-order current curve characteristics, which change nonlinearly with temperature.

[0223] In some embodiments, such as Figure 12 As shown, the fifth current mirror module 204 includes the twenty-sixth transistor M26 and the twenty-seventh transistor M27.

[0224] Among them, the twenty-sixth transistor M26 has its first terminal connected to the high-level voltage supply terminal VDD; its control terminal is connected to the first control node C1; and its second terminal is connected to the first terminal of the twenty-seventh transistor M27.

[0225] The twenty-seventh transistor M27 has its control terminal connected to the second control node C2, and its second terminal, as the output terminal of the fifth current mirror module 204, is connected to the current decomposition node N2.

[0226] In some embodiments, in the fifth current mirror module 204, the twenty-sixth transistor M26 and the twenty-third transistor M23 in the current synthesis module 203 form a current mirror circuit. The current flowing through the twenty-third transistor M23, i.e. the aforementioned fifth current I5, is mirrored to the twenty-sixth transistor M26 through the mirroring effect of the current mirror circuit, and then flows into the current decomposition node N2 through the twenty-sixth transistor M26 and the twenty-seventh transistor M27.

[0227] In some embodiments, the transistor dimensions, i.e. the aspect ratio, of the twenty-sixth transistor M26 and the twenty-seventh transistor M27 are the same as those of the twenty-third transistor M23. The current mirroring ratio of the current mirror circuit composed of the twenty-sixth transistor M26 and the twenty-third transistor M23 is 1:1, that is, the fifth current I5 flowing through the twenty-third transistor M23 is mirrored to the twenty-sixth transistor M26 at a ratio of 1:1.

[0228] In some embodiments, the twenty-sixth transistor M26 and the twenty-seventh transistor M27 are both P-type MOS transistors or PNP transistors, wherein the first electrode of the transistor is the source (emitter), the second electrode is the drain (collector), and the control electrode is the gate (base).

[0229] The circuit implementation principle of the fifth current mirror module 204 will be explained below, taking the twenty-sixth transistor M26 and the twenty-seventh transistor M27, both of which are P-type MOS transistors.

[0230] like Figure 12 As shown, the twenty-sixth transistor M26 and the twenty-third transistor M23 in the current synthesis module 203 form a current mirror circuit. The fifth current I5 flowing through the twenty-third transistor M23 is mirrored to the twenty-sixth transistor M26 through the current mirror. At this time, the current flowing through the twenty-sixth transistor M26 is the fifth current I5, which is transmitted to the current decomposition node N2 through the twenty-seventh transistor M27, which is turned on by the current control at the second control node C2.

[0231] In some embodiments, such as Figure 12 As shown, in the current decomposition module 205, the first current submodule 2051 includes the twenty-eighth transistor M28 and the twenty-ninth transistor M29.

[0232] Among them, the twenty-eighth transistor M28 has its first terminal connected to the current decomposition node N2; its control terminal connected to the third bias voltage terminal ctat1; and its second terminal connected to the first terminal of the twenty-ninth transistor M29.

[0233] The twenty-ninth transistor, M29, has its control terminal connected to the fourth bias voltage terminal, ctat2; its second terminal is grounded, GND.

[0234] In some embodiments, combined with Figure 5 and Figure 12 As shown, in order to decompose the first part of the current I from the fifth current I5 at the current decomposition node N2... 51The first current submodule 2051, through the twenty-eighth transistor M28 and the twenty-ninth transistor M29, forms a current mirror circuit with the fifth transistor M5 and the seventh transistor M7 in the second current mirror module 102 of the first current synthesis circuit 100. Utilizing the current mirroring effect of the current mirror circuit, the negative temperature coefficient current I is amplified through the fifth transistor M5 and the seventh transistor M7. CTAT With the second preset ratio K c2 Mirroring to the twenty-eighth transistor M28 and the twenty-ninth transistor M29, the current flowing through the twenty-eighth transistor M28 and the twenty-ninth transistor M29 is the first sub-current, which is also the first part of the fifth current I3, the current I. 51 I 51 =I4=K c2 *I CTAT .

[0235] In some embodiments, combined with Figure 5 and Figure 12 As shown, the current mirror circuit formed by the fifth transistor M5 and the seventh transistor M7 in the first current submodule 2051 and the second current mirror module 102 can be a common-source cascode current mirror structure or a common-source current mirror structure.

[0236] In some embodiments, combined with Figure 5 and Figure 12 As shown, the current mirror circuit formed by the fifth transistor M5 and the seventh transistor M7 in the first current submodule 2051 and the second current mirror module 102 can be any suitable current mirror circuit structure, including but not limited to the cascode current mirror structure.

[0237] In some embodiments, the twenty-eighth transistor M28 and the twenty-ninth transistor M29 are both N-type MOS transistors or NPN transistors, wherein the first electrode of the transistor is the drain (collector), the second electrode is the source (emitter), and the control electrode is the gate (base).

[0238] In some embodiments, the 28th transistor M28 and the 29th transistor M29 have the same transistor dimensions, i.e., aspect ratio (W / L), as the 19th transistor M19 and the 20th transistor M20. Correspondingly, the 28th transistor M28 and the 29th transistor M29 are compatible with the negative temperature coefficient current I. CTAT The current mirror ratio of the nineteenth transistor M19 and the twentieth transistor M20 for the negative temperature coefficient current I CTAT The current mirror ratios are the same, both being the second preset ratio K. c2 This allows the mirror image to reproduce the first sub-current I, which is identical to the fourth current I4. 51 .

[0239] The circuit implementation principle of the first current submodule 2051 will be explained below, taking the twenty-eighth transistor M28 and the twenty-ninth transistor M29 as examples, both of which are N-type MOS transistors.

[0240] Combination Figure 5 and Figure 12 As shown, transistors M5 (fifth), M7 (seventh), M28 (twenty-eighth), and M29 (twenty-ninth) form a current mirror circuit. Transistors M28 and M29, through a common-source, common-gate current mirror, convert the currents (i.e., the negative temperature coefficient current I) of transistors M5 and M7. CTAT The pre-configured current mirror ratio, i.e., the second preset ratio K, is used. c2 The mirror image is the first subcurrent I. 51 .

[0241] Specifically, the negative temperature coefficient current I CTAT Entering the fifth transistor M5, at the negative temperature coefficient current I CTAT Under the action of the fifth transistor M5, the control electrode, i.e., the third bias voltage terminal ctat1, generates the third bias voltage V_ctat1, and the negative temperature coefficient current I. CTAT The current flows through the conducting fifth transistor M5 to the seventh transistor M7, where the negative temperature coefficient current I... CTAT Under the action of the control terminal of the seventh transistor M7, namely the fourth bias voltage terminal ctat2, a fourth bias voltage V_ctat2 is generated.

[0242] Under the action of the third bias voltage V_ctat1 at the third bias voltage terminal ctat1 and the fourth bias voltage V_ctat2 at the fourth bias voltage terminal ctat2, the twenty-eighth transistor M28 and the twenty-ninth transistor M29 operate at a pre-configured current mirror ratio, i.e., the second preset ratio K. c2 Mirroring the negative temperature coefficient current I CTAT With the second preset ratio K c2 The negative temperature coefficient current I of the mirror image CTAT It becomes the first sub-current, and the first sub-current is equal to the fourth current I4 = K. c2 *I CTAT That is, the first part of the fifth current I5, the current I. 51 At this time, the current flowing through the twenty-eighth transistor M28 and the twenty-ninth transistor M29 is the first part of the fifth current I3, namely current I. 51 I 51 =I4=K c2 *I CTAT .

[0243] In some embodiments, such as Figure 12As shown, in the current decomposition module 205, the second current submodule 2052 includes the thirtieth transistor M30 and the thirty-first transistor M31.

[0244] Among them, the thirtieth transistor M20 has its first terminal connected to the current decomposition node N2; its control terminal connected to the first bias voltage terminal linear1; and its second terminal connected to the first terminal of the thirty-first transistor M31.

[0245] The thirty-first transistor M31 has its control terminal connected to the second bias voltage terminal linear2; its second terminal is grounded GND.

[0246] In some embodiments, in order to decompose the second portion of current I from the fifth current I5 at current decomposition node N2 52 , combined Figure 5 and Figure 12 As shown, the second current submodule 2052, through the thirtieth transistor M30 and the thirty-first transistor M31, forms a current mirror circuit with the fifteenth transistor M15 and the sixteenth transistor M16 in the first bias voltage generation module 105 of the first current synthesis circuit 100. Utilizing the current mirroring effect of the current mirror circuit, the first reference current I is reflected by the fifteenth transistor M15 and the sixteenth transistor M16. Out1 With the third preset ratio K I1 The current flowing through the 30th transistor M30 and the 31st transistor M31 is the second sub-current, where the third preset ratio K... I1 The first preset ratio K I Half of it, the second sub-current is the second part of the fifth current I5, the current I. 52 I 52 =I3 / 2=K I *I Out1 / 2.

[0247] In some embodiments, combined with Figure 5 and Figure 12 As shown, the current mirror circuit formed by the second current submodule 2052 and the first bias voltage generation module 105 can be a common source cascode current mirror structure or a common source current mirror structure.

[0248] In some embodiments, combined with Figure 5 and Figure 12 As shown, the current mirror circuit formed by the second current submodule 2052 and the first bias voltage generation module 105 can be any suitable current mirror circuit structure, including but not limited to the cascode current mirror structure.

[0249] In some embodiments, the thirtieth transistor M30 and the thirty-first transistor M31 are both N-type MOS transistors or NPN transistors, wherein the first electrode of the transistor is the drain (collector), the second electrode is the source (emitter), and the control electrode is the gate (base).

[0250] In some embodiments, the transistor dimensions, i.e., the width-to-length ratio (W / L), of the thirtieth transistor M30 and the thirty-first transistor M31 are half the transistor dimensions of the seventeenth transistor M17 and the eighteenth transistor M18. Correspondingly, the thirtieth transistor M30 and the thirty-first transistor M31 are related to the first reference current I. Out1 The current mirror ratio, i.e., the third preset ratio K I1 For the seventeenth transistor M17 and the eighteenth transistor M18, the first reference current I is... Out1 The current mirror ratio is the first preset ratio K. I Half of, that is, K I1 =K I / 2, thus making the second sub-current mirrored from the 30th transistor M30 and the 31st transistor M31 half of the third current I3, which is also the second part of the fifth current I5. 52 This allows for the extraction of the second current I from the fifth current I5. 52 .

[0251] The circuit implementation principle of the second current submodule 2052 will be explained below, taking the 30th transistor M30 and the 31st transistor M31 as examples, both of which are N-type MOS transistors.

[0252] Combination Figure 5 and Figure 12 As shown, the fifteenth transistor M15, the sixteenth transistor M16, the thirtieth transistor M30, and the thirty-first transistor M31 form a current mirror circuit. The thirtieth transistor M30 and the thirty-first transistor M31 use a common-source, common-gate current mirror to reflect the current of the fifteenth transistor M15 and the sixteenth transistor, i.e., the first reference current I. Out1 The pre-configured current mirror ratio, i.e., the third preset ratio K, is used. I1 The mirror image is the second subcurrent I. 51 .

[0253] Specifically, the first reference current I Out1 Entering the fifteenth transistor M15, at the first reference current I Out1 Under the action of the fifteenth transistor M15, the control terminal, i.e., the first bias voltage terminal linear1, generates the first bias voltage V_linear1 and the first reference current I. Out1 The current flows through the fifteenth transistor M15 to the sixteenth transistor M16, at the first reference current I. Out1Under the action of the control terminal of the sixteenth transistor M16, namely the second bias voltage terminal linear2, a second bias voltage V_linear2 is generated.

[0254] Under the action of the first bias voltage V_linear1 at the first bias voltage terminal linear1 and the second bias voltage V_linear2 at the second bias voltage terminal linear2, the thirtieth transistor M30 and the thirty-first transistor M31 operate at a pre-configured current mirror ratio, i.e., the third preset ratio K. I1 Mirroring the first reference current I Out1 With the third preset ratio K I1 The first reference current I of the mirror Out1 It becomes the second sub-current, which is half of the third current I3, and is also the second part of the fifth current I5. 52 At this time, the current flowing through the thirtieth transistor M30 and the thirty-first transistor M31 is the second part of the fifth current I5, namely current I. 52 I 52 =I3 / 2=K I *I Out1 / 2.

[0255] In some embodiments, such as Figure 12 As shown, in the current decomposition module 205, the first current submodule 2051, the second current submodule 2052, and the third current submodule 2053 are respectively connected to the current decomposition node N2. Since the first current submodule 2051 mirrors the first part of the fifth current I5 of the current decomposition node N2, the current I is... 51 The second current submodule 2052 mirrors the second part of the current I5 in the fifth current I5 of the current decomposition node N2. 52 That is, the first current submodule 2051 and the second current submodule 2052 respectively extract the first part of the fifth current I5, namely the current I. 51 Second part of the current I 52 Therefore, the remaining third part of the current I in the fifth current I5 53 The current will flow into the third current submodule 2053, and be controlled by the third current submodule 2053 at a fourth preset ratio K. n The mirror image is the second reference current I. Out2 Then output, the second reference current I Out2 =K n *I 53 .

[0256] In some embodiments, such as Figure 12As shown, in the current decomposition module 205, the third current submodule 2053 includes the thirty-second transistor M32, the thirty-third transistor M33, the thirty-fourth transistor M34, and the thirty-fifth transistor M35.

[0257] Among them, the first terminal of the thirty-second transistor M32 is connected to the control terminal and to the current decomposition node N2; its second terminal is connected to the first terminal of the thirty-third transistor M33.

[0258] The thirty-third transistor M33 has its control electrode connected to its first electrode; its second electrode is grounded (GND).

[0259] The thirty-fourth transistor M34 has its first terminal as the output terminal of the current decomposition module 205, which is used to output the second reference current I. Out2 Its control electrode is connected to the control electrode of the thirty-second transistor M32; its second electrode is connected to the first electrode of the thirty-fifth transistor M35.

[0260] The control electrode of the thirty-fifth transistor M35 is connected to the control electrode of the thirty-third transistor M33; its second electrode is grounded (GND).

[0261] In some embodiments, in the third current submodule 2053, a current mirror circuit is formed using the thirty-second transistor M32 to the thirty-fifth transistor M35 to decompose the third portion of current I from the fifth current I5 at the current decomposition node N2. 53 Through the mirroring effect of the current mirror circuit composed of transistors 32 to 35, the current is mirrored by transistors 34 and 35 at a pre-configured current mirroring ratio K. n The mirror image is the second reference current I. Out2 Second reference current I Out2 The output is achieved through the first terminal of the thirty-fourth transistor M34.

[0262] In some embodiments, the third current submodule 2053 can be a common-source cascode current mirror structure or a common-source electrode current mirror structure.

[0263] In some embodiments, the third current submodule 2053 can be any suitable current mirror circuit structure, including but not limited to the cascode current mirror structure.

[0264] In some embodiments, transistors M32 through M35 are all N-type MOS transistors or NPN transistors, wherein the first electrode of the transistor is the drain (collector), the second electrode is the source (emitter), and the control electrode is the gate (base).

[0265] In some embodiments, the transistor dimensions, i.e., the width-to-length ratio (W / L), of the thirty-second transistor M32 to the thirty-fifth transistor M35 can be configured according to the current mirror ratio K as needed. n Pre-configured, and this application embodiment does not impose any special restrictions on this.

[0266] The circuit implementation principle of the third current submodule 2053 will be explained below, taking the thirty-second transistor M32 to the thirty-fifth transistor M35 as examples, all of which are N-type MOS transistors.

[0267] like Figure 12 As shown, transistors M32 to M35 form a current mirror circuit, which uses a common-source, common-gate current mirror to decompose the third part of the current I from the fifth current I5 at the current decomposition node N2. 53 With a pre-configured current mirror ratio K n Mirroring from transistors M32 (thirty-second) and M33 (thirty-third) to transistors M34 (thirty-fourth) and M35 (thirty-fifth).

[0268] Specifically, the third part of the current I is decomposed from the fifth current I5 at the current decomposition node N2. 53 The current enters the thirty-second transistor M32, which is subjected to the third part of the current I. 53 The transistor is turned on by its function, and a corresponding bias voltage is generated at the control electrode of the thirty-second transistor M32. At the same time, the third part of the current I... 53 The current flows through the conducting 32nd transistor M32 to the 33rd transistor M33, which is then subjected to the third part of the current I. 53 The transistor is turned on by the action of the control electrode of the 33rd transistor M33, and a corresponding bias voltage is generated at the control electrode of the 32nd transistor M32 and the 33rd transistor M33. Through the bias voltage of the control electrode of the 34th transistor M34 and the 35th transistor M35, the third part of the current I is turned on. 53 With a pre-configured current mirror ratio K n The mirror image is the second reference current I. Out2 I Out2 =K n *I 53 Second reference current I Out2 The output is via the first terminal of the thirty-fourth transistor M34.

[0269] In some embodiments, the current mirror ratio K of the current mirror circuit composed of the thirty-second transistor M32 to the thirty-fifth transistor M35 is... n It can be pre-configured to a 1:1 ratio, that is, the third part of the current I flowing through the thirty-second transistor M32 and the thirty-third transistor M33 is reflected by this current mirror circuit.53 The current is mirrored to transistors M34 and M35 at a 1:1 ratio, and the resulting second reference current is I. Out2 =I 53 .

[0270] In some embodiments, the output terminal of the current decomposition module 205, i.e., the first terminal of the thirty-fourth transistor M34, can be used as the second reference current output terminal Out2, which is used to output the second reference current I to an external circuit. Out2 .

[0271] In some embodiments, the output terminal of the current decomposition module 205, i.e., the first terminal of the thirty-fourth transistor M34, is connected to the sixth current mirror module 206, and the second reference current I generated by the first terminal of the thirty-fourth transistor M34... Out2 The current can be mirrored by the sixth current mirror module 206 at a certain current mirror ratio and then output to the external circuit. The output terminal of the sixth current mirror module 206 serves as the second reference current output terminal Out2.

[0272] In some embodiments, such as Figure 12 As shown, in the second current synthesis circuit 200, the sixth current mirror module 206 includes the thirty-sixth transistor, the thirty-seventh transistor, the thirty-eighth transistor, and the thirty-ninth transistor.

[0273] Among them, the first terminal of the thirty-sixth transistor M36 is connected to the high-level voltage supply terminal VDD; its second terminal is connected to the control terminal and is connected to the first terminal of the thirty-seventh transistor M37.

[0274] The thirty-seventh transistor M37 has its second terminal connected to the control terminal and connected to the output terminal of the current decomposition module 205.

[0275] The thirty-eighth transistor M38 has its first terminal connected to the high-level voltage supply terminal VDD; its control terminal connected to the control terminal of the thirty-sixth transistor M36; and its second terminal connected to the first terminal of the thirty-ninth transistor M39.

[0276] The thirty-ninth transistor M39 has its control electrode connected to the control electrode of the thirty-seventh transistor M37; its second electrode is the second reference current output terminal Out2.

[0277] In some embodiments, in the sixth current mirror module 206, a current mirror circuit is formed using the thirty-sixth transistor M36 to the thirty-ninth transistor M39, and the second reference current I is output from the output terminal of the current decomposition module 205. Out2Through the mirroring effect of the current mirror circuit composed of transistors 36 to 39, the current mirroring ratio is achieved by transistors 38 and 39 at a pre-configured ratio, namely the fourth preset ratio K. sq Mirroring the second reference current I Out2 Then, the output is achieved through the second terminal of the thirty-ninth transistor M39, namely the second reference current output terminal Out2. The current output after mirroring becomes the fourth preset ratio K. sq With the second reference current I Out2 The product of.

[0278] In some embodiments, the sixth current mirror module 206 can be a common-source cascode current mirror structure or a common-source electrode current mirror structure.

[0279] In some embodiments, the sixth current mirror module 206 can be any suitable current mirror circuit structure, including but not limited to the cascode current mirror structure.

[0280] In some embodiments, transistors M36 to M39 are all P-type MOS transistors or PNP transistors, wherein the first electrode of the transistor is the source (emitter), the second electrode is the drain (collector), and the control electrode is the gate (base).

[0281] In some embodiments, the transistor dimensions (width / length ratio) of transistors 32 to 35 (M35) can be configured according to the current mirror ratio, i.e., the fourth preset ratio K, as needed. sq Pre-configured, and this application embodiment does not impose any special restrictions on this.

[0282] The circuit implementation principle of the sixth current mirror module 206 will be explained below, taking the thirty-sixth transistor M36 to the thirty-ninth transistor M39 as examples, all of which are P-type MOS transistors.

[0283] like Figure 12 As shown, transistors M36 to M39 form a current mirror circuit, which uses a common-source, common-gate current mirror to extract the second reference current I from the current decomposition module 205. Out2 The pre-configured current mirror ratio, i.e., the fourth preset ratio K, is used. sq Mirroring from transistors M36 (thirty-sixth) and M37 (thirty-seventh) to transistors M38 (thirty-eighth) and M39 (thirty-ninth).

[0284] Specifically, the second reference current I output from the current decomposition module 205 Out2 The 37th transistor M37 is connected to the second reference current I. Out2The transistor is turned on by its function, and a corresponding bias voltage is generated at the control electrode of the thirty-seventh transistor M37. At the same time, the second reference current I... Out2 The current flows through the conducting 37th transistor M37 to the 36th transistor M36, which is then subjected to the second reference current I. Out2 The transistor is turned on by the action of the control electrode of the 36th transistor M36, and a corresponding bias voltage is generated at the control electrode of the 36th transistor M36 and the 37th transistor M37. Through the bias voltage of the control electrodes of the 36th transistor M36 and the 37th transistor M37, the 38th transistor M38 and the 39th transistor M39 will draw the second reference current I flowing through the 36th transistor M36 and the 37th transistor M37. Out2 The pre-configured current mirror ratio, i.e., the fourth preset ratio K, is used. sq After mirroring, the current is output through the second terminal of the thirty-ninth transistor M39, namely the second reference current output terminal Out2. The second reference current output after mirroring becomes K. sq *I Out2 .

[0285] According to the third part above, current I 53 The current formula and the second reference current are I Out2 With the third part of the current I 53 The relationship can be used to determine the second reference current I. Out2 With the first reference current I Out1 and negative temperature coefficient current I CTAT The following relationship must be satisfied:

[0286]

[0287] In some embodiments, the current mirror ratio K of the third current submodule 2053 is... n The first reference current I is 1. Out1 The sixth current mirror module 206 uses the fourth preset ratio K. sq The output after mirroring, the second reference current I. Out2 Change to K sq ×I Out2 Combined with the aforementioned second reference current I Out2 With the first reference current I Out1 and negative temperature coefficient current I CTAT From the relationship, we can obtain:

[0288]

[0289] According to the aforementioned second reference current I Out2 With the first reference current I Out1 and negative temperature coefficient current I CTATFrom the relationship, it can be seen that the second reference current I synthesized by the second current synthesis circuit 200 Out2 With the first reference current I Out1 The sum of the squares of the negative temperature coefficient of the current I CTAT The ratio is related to the second reference current I. Out2 It exhibits high-order current curve characteristics, changing non-linearly with temperature, compared to the first reference current I generated by the first current synthesis circuit 100, which changes linearly with temperature. Out1 The second current synthesis circuit 200 can generate a larger high-temperature current under the same temperature and current conditions, which can better compensate for the performance of external circuit modules over a wide temperature range.

[0290] In practical simulation applications, the second reference current I synthesized by the second current synthesis circuit 200 is... Out2 It can be based on the first reference current I Out1 Adjusting the slope results in different curve shapes. Figure 13 A schematic diagram of the simulation results for a second reference current is shown, as follows. Figure 13 As shown, in the first current synthesis circuit 100, the output first reference current I can be adjusted by adjusting the second transistor M2 that is turned on and the number X. Out1 The slope, based on the first reference current I with different slopes. Out1 The second reference current I synthesized by the second current synthesis circuit 200 Out2 The second reference current I exhibited different curve forms and slopes. Out2 There is a fixed intersection point between the corresponding curves, namely, the second reference current I at a certain temperature. Out2 The magnitude of the current is constant.

[0291] In this embodiment, the reference current generation circuit has two output modes. One mode generates and outputs a first reference current that changes linearly with temperature through a first current synthesis circuit 100, and the linear slope of the first reference current is adjustable. The other mode generates and outputs a second reference current that changes nonlinearly with temperature through a second current synthesis circuit 200, and the curve shape of the second reference current can be adjusted based on the slope of the first reference current. In practical applications, linear or curved reference currents with different temperature slopes can be flexibly configured according to the actual reference current output requirements of the external circuit, thereby effectively compensating for the performance stability of the external circuit over a wide temperature range.

[0292] A detailed description of exemplary embodiments of this application has been provided above through exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, without departing from the scope of this application. Therefore, the proper scope of this application will be determined by the claims.

Claims

1. A reference current generation circuit, comprising: The positive temperature coefficient current supply terminal is configured to provide a positive temperature coefficient current to the first current synthesis circuit; The negative temperature coefficient current supply terminal is configured to provide a negative temperature coefficient current to the first current synthesis circuit. The first current synthesis circuit is configured to linearly synthesize the positive temperature coefficient current and the negative temperature coefficient current into a first reference current that varies linearly with temperature, each with its corresponding adjustable ratio. The slope of the first reference current that varies linearly with temperature is determined based on the adjustable ratio corresponding to the positive temperature coefficient current and / or the adjustable ratio corresponding to the negative temperature coefficient current. The second current synthesis circuit is configured to obtain the first reference current and the negative temperature coefficient current from the first current synthesis circuit, and generate a second reference current that varies non-linearly with temperature based on the first reference current and the negative temperature coefficient current.

2. The reference current generation circuit according to claim 1, wherein, The first current synthesis circuit includes a first current mirror module and a second current mirror module; The input terminal of the first current mirroring module is connected to the positive temperature coefficient current providing terminal, and the output terminal is connected to the current synthesis node. The first current mirroring module is configured to mirror the positive temperature coefficient current provided by the positive temperature coefficient current providing terminal into a first current according to a first adjustable ratio, and output it to the current synthesis node. The input terminal of the second current mirroring module is connected to the negative temperature coefficient current providing terminal, and the output terminal is connected to the current synthesis node. The second current mirroring module is configured to mirror the negative temperature coefficient current provided by the negative temperature coefficient current providing terminal into a second current according to a second adjustable ratio, and output it to the current synthesis node. The current synthesis node is used to linearly synthesize the first current and the second current into the first reference current that changes linearly with temperature.

3. The reference current generation circuit according to claim 2, wherein, The first current synthesis circuit further includes a third current mirror module, the input of which is connected to the current synthesis node, and the output is a first reference current output. The third current mirroring module is configured to mirror the first reference current output by the current synthesis node and output it through the first reference current output terminal.

4. The reference current generation circuit according to claim 2, wherein, The first current synthesis circuit further includes a fourth current mirror module and a first bias voltage generation module. The input terminal of the fourth current mirror module is connected to the current synthesis node, and the output terminal is connected to the first bias voltage generation module. The fourth current mirroring module is configured to mirror the first reference current output by the current synthesis node and output it to the first bias voltage generation module. The first bias voltage generation module is configured to generate a first bias voltage and a second bias voltage based on the first reference current output by the fourth current mirror module, and to provide the first bias voltage and the second bias voltage to the second current synthesis circuit. The first bias voltage and the second bias voltage are used by the second current synthesis circuit to mirror the first reference current based on the first bias voltage and the second bias voltage.

5. The reference current generation circuit according to claim 2, wherein, The second current mirror module is also configured to generate a third bias voltage and a fourth bias voltage based on the negative temperature coefficient current provided by the negative temperature coefficient current providing terminal, and to provide the third bias voltage and the fourth bias voltage to the second current synthesis circuit; The third bias voltage and the fourth bias voltage are used by the second current synthesis circuit to mirror the negative temperature coefficient current based on the third bias voltage and the fourth bias voltage.

6. The reference current generation circuit according to claim 2, wherein, The first current mirror module includes a first transistor, a plurality of second transistors connected in parallel, a third transistor, and a plurality of fourth transistors connected in parallel; The first transistor has its first terminal connected to its control terminal and connected to the positive temperature coefficient current supply terminal, and its second terminal connected to the first terminal of the third transistor; The control electrodes of the multiple second transistors connected in parallel are interconnected and connected to the control electrode of the first transistor. Their first poles are interconnected and connected to the current synthesis node; Their second poles are interconnected and connected to the first poles of the plurality of fourth transistors in parallel, and the first adjustable ratio is adjusted according to the number of the plurality of second transistors in parallel being turned on. The third transistor has its control electrode connected to its first electrode and its second electrode grounded. The control electrodes of the multiple fourth transistors connected in parallel are interconnected and connected to the control electrode of the third transistor. Their first terminals are interconnected and connected to the second terminals of the plurality of parallel second transistors; Their second poles are interconnected and grounded.

7. The reference current generation circuit according to claim 6, wherein, The number of the second transistors is the same as the number of the fourth transistors, and the transistors are the same size.

8. The reference current generation circuit according to claim 5, wherein, The second current mirror module includes a fifth transistor, multiple sixth transistors and a seventh transistor connected in parallel, and multiple eighth transistors connected in parallel. The first terminal of the fifth transistor is connected to the negative temperature coefficient current supply terminal. Its control electrode is connected to the first electrode and connected to the third bias voltage terminal, which is used to provide the third bias voltage to the second current synthesis circuit; Its second terminal is connected to the first terminal of the seventh transistor; The control electrodes of the multiple sixth transistors connected in parallel are interconnected and connected to the control electrode of the fifth transistor; Their first poles are interconnected and connected to the current synthesis node; Their second poles are interconnected and connected to the first poles of the plurality of eighth transistors in parallel, and the second adjustable ratio is adjusted according to the number of sixth transistors in parallel that are turned on. The seventh transistor has its control electrode connected to the first electrode and to the fourth bias voltage terminal, which is used to provide the fourth bias voltage to the second current synthesis circuit. Its second electrode is grounded; The control electrodes of the multiple eighth transistors connected in parallel are interconnected and connected to the control electrode of the seventh transistor. Their first terminals are interconnected and connected to the second terminals of the plurality of sixth transistors in parallel; Their second poles are interconnected and grounded.

9. The reference current generation circuit according to claim 8, wherein, The sixth transistor has the same number of transistors as the eighth transistor, and the transistors are the same size.

10. The reference current generation circuit according to claim 3, wherein, The third current mirror module includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; The control electrode of the ninth transistor is connected to the control electrode of the eleventh transistor; its first electrode is connected to the high-level voltage supply terminal. Its second electrode is connected to the control electrode and to the first electrode of the tenth transistor; The tenth transistor has its control electrode connected to the second electrode and connected to the current combining node; The eleventh transistor has its first terminal connected to the high-level voltage supply terminal, and its second terminal connected to the first terminal of the twelfth transistor. The control electrode of the twelfth transistor is connected to the control electrode of the tenth transistor, and the second electrode is the first reference current output terminal.

11. The reference current generation circuit according to claim 4, wherein, The fourth current mirror module includes a ninth transistor, a tenth transistor, a thirteenth transistor, and a fourteenth transistor; The control electrode of the ninth transistor is connected to the control electrode of the thirteenth transistor; its first electrode is connected to the high-level voltage supply terminal. Its second electrode is connected to the control electrode and to the first electrode of the tenth transistor; The tenth transistor has its control electrode connected to the second electrode and connected to the current combining node; The thirteenth transistor has its first terminal connected to the high-level voltage supply terminal, and its second terminal connected to the first terminal of the fourteenth transistor; The fourteenth transistor has its control electrode connected to the control electrode of the tenth transistor, and its second electrode connected to the first bias voltage generation module.

12. The reference current generation circuit according to claim 4, wherein, The first bias voltage generation module includes a fifteenth transistor and a sixteenth transistor; The first terminal of the fifteenth transistor is connected to the output terminal of the fourth current mirror module. Its control electrode is connected to the first electrode and connected to the first bias voltage terminal, which is used to provide the first bias voltage to the second current synthesis circuit; Its second terminal is connected to the first terminal of the sixteenth transistor; The sixteenth transistor has its control electrode connected to the first electrode and connected to the second bias voltage terminal, which is used to provide the second bias voltage to the second current synthesis circuit. Its second electrode is grounded.

13. The reference current generation circuit according to claim 1, wherein, The second current synthesis circuit includes a reference current mirror module, a negative temperature coefficient current mirror module, a current synthesis module, a fifth current mirror module, and a current decomposition module. The reference current mirror module, the current synthesis module, and the fifth current mirror module are all connected to a first control node. The negative temperature coefficient current mirror module, the current synthesis module, and the fifth current mirror module are all connected to a second control node. The fifth current mirror module and the current decomposition module are all connected to a current decomposition node. The reference current mirroring module is configured to mirror the first reference current into a third current according to a first preset ratio and transmit it to the first control node; The negative temperature coefficient current mirroring module is configured to mirror the negative temperature coefficient current into a fourth current according to a second preset ratio and transmit it to the second control node. The current synthesis module is configured to generate a fifth current based on the third current of the first control node and the fourth current of the second control node. The fifth current mirroring module is configured to mirror the fifth current output by the current synthesis module and output it to the current decomposition node based on the third current of the first control node and the fourth current of the second control node. The current decomposition module is configured to decompose a second reference current that varies non-linearly with temperature from the fifth current of the current decomposition node.

14. The reference current generation circuit according to claim 13, wherein, The reference current mirror module and the first current synthesis circuit are coupled through a first bias voltage terminal and a second bias voltage terminal. The first current synthesis circuit is further configured to generate a first bias voltage and a second bias voltage based on the first reference current, the first bias voltage and the second bias voltage being used to mirror the first reference current, the first bias voltage being provided to the first bias voltage terminal, and the second bias voltage being provided to the second bias voltage terminal; The reference current mirroring module is configured to mirror the first reference current into a third current according to a first preset ratio based on the first bias voltage at the first bias voltage terminal and the second bias voltage at the second bias voltage terminal.

15. The reference current generation circuit according to claim 14, wherein, The reference current mirror module includes a seventeenth transistor and an eighteenth transistor; The seventeenth transistor has its control electrode connected to the first bias voltage terminal; Its first terminal is connected to the first control node, and its second terminal is connected to the first terminal of the eighteenth transistor; The eighteenth transistor has its control electrode connected to the second bias voltage terminal; Its second electrode is grounded.

16. The reference current generation circuit according to claim 13, wherein, The negative temperature coefficient current mirror module and the first current synthesis circuit are coupled through a third bias voltage terminal and a fourth bias voltage terminal. The first current synthesis circuit is further configured to generate a third bias voltage and a fourth bias voltage based on the negative temperature coefficient current, the third bias voltage and the fourth bias voltage being used to mirror the negative temperature coefficient current, the third bias voltage being provided to the third bias voltage terminal, and the fourth bias voltage being provided to the fourth bias voltage terminal. The negative temperature coefficient current mirroring module is configured to mirror the negative temperature coefficient current into a fourth current according to a second preset ratio based on the third bias voltage of the third bias voltage terminal and the fourth bias voltage of the fourth bias voltage terminal.

17. The reference current generation circuit according to claim 16, wherein, The negative temperature coefficient current mirror module includes a nineteenth transistor and a twentieth transistor. The nineteenth transistor has its control electrode connected to the third bias voltage terminal; Its first pole is connected to the second control node; Its second terminal is connected to the first terminal of the twentieth transistor; The twentieth transistor has its control electrode connected to the fourth bias voltage terminal; Its second electrode is grounded.

18. The reference current generation circuit according to claim 13, wherein, The current synthesis module includes a 21st transistor, a 22nd transistor, a 23rd transistor, a 24th transistor, and a 25th transistor; The 21st transistor has its first terminal connected to a high-level voltage supply terminal; its control terminal is connected to its second terminal and is also connected to the first terminal of the 22nd transistor. The twentieth transistor has its control electrode connected to its second electrode and connected to the second control node; The first terminal of the twenty-third transistor is connected to the high-level voltage supply terminal; Its control electrode is connected to the second electrode and then to the first control node; The first terminal of the twenty-fourth transistor is connected to the second terminal of the twenty-third transistor; Its control electrode is connected to the control electrode of the 22nd transistor; Its second terminal is connected to the first terminal of the twenty-fifth transistor; The 25th transistor has its control electrode connected to its first electrode, and its second electrode grounded.

19. The reference current generation circuit according to claim 13, wherein, The fifth current mirror module includes a twenty-sixth transistor and a twenty-seventh transistor; The 26th transistor has its first terminal connected to a high-level voltage supply terminal; its control terminal connected to the first control node; and its second terminal connected to the first terminal of the 27th transistor. The 27th transistor has its control electrode connected to the 2nd control node and its second electrode connected to the current decomposition node.

20. The reference current generation circuit according to claim 13, wherein, The current decomposition module includes a first current submodule, a second current submodule, and a third current submodule; The first current submodule, the second current submodule, and the third current submodule are all connected to the current decomposition node; The first current submodule and the first current synthesis circuit are coupled through a third bias voltage terminal and a fourth bias voltage terminal; The second current submodule and the first current synthesis circuit are coupled through a first bias voltage terminal and a second bias voltage terminal. The first current synthesis circuit is further configured to generate a third bias voltage and a fourth bias voltage based on the negative temperature coefficient current, the third bias voltage and the fourth bias voltage being used to mirror the negative temperature coefficient current; The first current submodule is configured to mirror the negative temperature coefficient current into a first subcurrent according to a second preset ratio based on the third bias voltage of the third bias voltage terminal and the fourth bias voltage of the fourth bias voltage terminal. The first subcurrent is the first part of the fifth current in the current decomposition node. The first current synthesis circuit is further configured to generate a first bias voltage and a second bias voltage based on the first reference current, the first bias voltage and the second bias voltage being used to mirror the first reference current; The second current submodule is configured to mirror the first reference current into a second subcurrent according to a third preset ratio based on the first bias voltage at the first bias voltage terminal and the second bias voltage at the second bias voltage terminal. The second subcurrent is the second part of the fifth current in the current decomposition node. The third current submodule is configured to receive the third portion of the fifth current from the current decomposition node and mirror the third portion of the current as the second reference current.

21. The reference current generation circuit according to claim 20, wherein, The first current submodule includes a twenty-eighth transistor and a twenty-ninth transistor; The 28th transistor has its first terminal connected to the current decomposition node; Its control electrode is connected to the third bias voltage terminal; Its second terminal is connected to the first terminal of the twenty-ninth transistor; The control electrode of the twenty-ninth transistor is connected to the fourth bias voltage terminal; Its second electrode is grounded.

22. The reference current generation circuit according to claim 20, wherein, The second current submodule includes the thirtieth transistor and the thirty-first transistor; The thirtieth transistor has its first terminal connected to the current decomposition node; Its control electrode is connected to the first bias voltage terminal; Its second terminal is connected to the first terminal of the thirty-first transistor; The control electrode of the thirty-first transistor is connected to the second bias voltage terminal; Its second electrode is grounded.

23. The reference current generation circuit according to claim 20, wherein, The third current submodule includes the thirty-second transistor, the thirty-third transistor, the thirty-fourth transistor, and the thirty-fifth transistor; The thirty-second transistor has its first terminal connected to the control terminal and connected to the current decomposition node; Its second terminal is connected to the first terminal of the thirty-third transistor; The control electrode of the thirty-third transistor is connected to the first electrode; Its second electrode is grounded; The first terminal of the thirty-fourth transistor is the output terminal of the current decomposition module, and the first terminal is used to output the second reference current. Its control electrode is connected to the control electrode of the thirty-second transistor; Its second terminal is connected to the first terminal of the thirty-fifth transistor; The control electrode of the thirty-fifth transistor is connected to the control electrode of the thirty-third transistor; Its second electrode is grounded.

24. The reference current generation circuit according to claim 13, wherein, The second current synthesis circuit also includes a sixth current mirror module; The input terminal of the sixth current mirror module is connected to the output terminal of the current decomposition module, and the output terminal of the sixth current mirror module is the second reference current output terminal. The sixth current mirroring module is configured to mirror the second reference current output by the current decomposition module according to a fourth preset ratio and then output it through the second reference current output terminal.

25. The reference current generation circuit according to claim 24, wherein, The sixth current mirror module includes the thirty-sixth transistor, the thirty-seventh transistor, the thirty-eighth transistor, and the thirty-ninth transistor; The first terminal of the thirty-sixth transistor is connected to the high-level voltage supply terminal; Its second electrode is connected to the control electrode and to the first electrode of the thirty-seventh transistor; The third-seventh transistor has its second electrode connected to the control electrode and connected to the output terminal of the current decomposition module; The first terminal of the thirty-eighth transistor is connected to the high-level voltage supply terminal; Its control electrode is connected to the control electrode of the thirty-sixth transistor; Its second terminal is connected to the first terminal of the thirty-ninth transistor; The control electrode of the thirty-ninth transistor is connected to the control electrode of the thirty-seventh transistor; Its second electrode is the second reference current output terminal.

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