Clock synthesis system, chip and electronic device

Abstract

Embodiments of the present application relate to the chip technical field, and provide a clock synthesis system, a chip and an electronic device. The clock synthesis system comprises: a fishbone type clock tree trunk, a trunk driving chain and at least one sub-clock group connected with the trunk driving chain in sequence. Each sub-clock group is constructed based on the logic depth and physical position of a timing unit in a homologous clock structure. The fishbone type clock tree trunk is used to perform driving enhancement processing after receiving a clock signal of a clock input source, and send the processed clock signal to the trunk driving chain. The trunk driving chain is used to converge the processed clock signal and input the processed clock signal to each sub-clock group. Each sub-clock group uses traditional clock tree synthesis to distribute the processed clock signal to respective timing units after receiving the processed clock signal. In the technical solution, the effects of low delay, low power consumption and high reliability are achieved in the clock signal transmission process.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a clock synthesis system, chip, and electronic device. Background Technology

[0002] In the physical design phase of a chip, clock tree synthesis (CTS) is a core component that ensures chip performance, power consumption, and timing convergence. The clock signal acts as the heartbeat of synchronous logic circuits, and the uniformity of its transmission delay directly affects whether the chip's setup time and hold time meet the design requirements.

[0003] Traditional Clock Tree Synthesis (TCTS) starts from the clock source and gradually balances the delay of each path by inserting buffers or inverters.

[0004] However, due to the limitations of physical layout dispersion and load capacity, the clock path forks too early in TCTS, making it difficult to balance low latency, low power consumption and high reliability. Summary of the Invention

[0005] This application provides a clock integration system, chip, and electronic device to achieve the technical effect of stable in-vehicle display with lower computing resources.

[0006] In a first aspect, embodiments of this application provide a clock synthesis system, including: a fishbone-shaped clock tree trunk, a trunk drive chain, and at least one sub-clock group connected in sequence to the trunk drive chain, wherein each sub-clock group is constructed based on the logical depth and physical location of timing units in the same clock structure;

[0007] The fishbone-shaped clock tree trunk is used to receive the clock signal from the clock input source, perform drive enhancement processing, and send the processed clock signal into the trunk drive chain.

[0008] The main drive chain is used to aggregate the processed clock signals and input them to each sub-clock group respectively;

[0009] After receiving the processed clock signal, each sub-clock group uses conventional clock tree synthesis to distribute the clock signal to its respective timing unit.

[0010] In one or more embodiments, the fishbone-shaped clock tree trunk includes: a first-level buffer unit and a multi-level parallel large drive buffer connected to the first-level buffer unit;

[0011] The first-stage buffer unit is used to receive the clock signal from the clock input source and then perform buffering and drive capability preprocessing.

[0012] The multi-level parallel large drive buffer is used to perform strong drive enhancement processing on the processed clock signal and transmit it to the main drive chain.

[0013] In one or more embodiments, the multi-stage parallel large drive buffer includes: a multi-stage drive unit group connected end to end, each stage of the drive unit group including: multiple buffers or inverters connected in parallel;

[0014] Each stage of the drive unit group is used to perform step-by-step strong drive processing on the processed clock signal.

[0015] In one or more embodiments, the clock synthesis system further includes: sub-clock group source points respectively disposed between each sub-clock group and the main drive chain;

[0016] For each sub-clock group source point, the sub-clock group source point is used to receive the clock signal distributed by the trunk drive chain and serve as the clock starting point for the synthesis of the clock tree within the corresponding sub-clock group.

[0017] In one or more embodiments, each sub-clock group includes: a clock distribution network and a set of timing units connected to the clock distribution network;

[0018] The clock distribution network is used to receive the clock signal output by the backbone drive chain and perform hierarchical distribution drive.

[0019] The timing unit set includes multiple timing units, each of which is connected to the clock distribution network and is used to receive the distributed clock signal to complete timing operations.

[0020] In one or more embodiments, the clock distribution network is a clock tree structure constructed using traditional clock tree synthesis, and the signal flip time of the buffers or inverters in the clock distribution network does not exceed the maximum flip time constraint.

[0021] The clock delay of each timing unit is flattened by inserting a buffer or a pair of inverters, and then the clock delay of each timing unit is adjusted by a useful skew to ensure that the setup time margin and hold time margin of each timing unit meet the preset timing constraints.

[0022] The setup time margin satisfies the timing constraint requirement as follows: the settling time of the data input signal of the timing unit before the arrival of the clock effective edge is not less than the setup time of the timing unit; the hold time margin satisfies the timing constraint requirement as follows: the hold time of the data input signal of the timing unit after the arrival of the clock effective edge is not less than the hold time of the timing unit.

[0023] In one or more embodiments, each sub-clock group further includes a clock logic unit connected between the clock distribution network and the timing unit set;

[0024] The clock logic unit includes at least one of an XOR gate, a NOR gate, and a gating unit, used to process the clock signal according to the logic function of the clock logic unit and then transmit it to the corresponding timing unit.

[0025] In one or more embodiments, the backbone drive chain is a low-resistance physical trace;

[0026] The low-resistance physical traces are constructed using high-layer metal traces or top-layer metal traces.

[0027] Secondly, embodiments of this application provide a chip, including: the clock integration system described in the first aspect and any one of the first aspects.

[0028] Thirdly, embodiments of this application provide an electronic device, including: a clock integration system according to the first aspect and any one of the first aspects;

[0029] Or, the chip described in the second aspect.

[0030] The clock synthesis system, chip, and electronic device provided in this application include: a fishbone-shaped clock tree trunk, a trunk drive chain, and at least one sub-clock group connected in sequence. Each sub-clock group is constructed based on the logic depth and physical location of the timing unit in the same clock structure. The fishbone-shaped clock tree trunk receives the clock signal from the clock input source, performs drive enhancement processing, and sends the processed clock signal to the trunk drive chain. The trunk drive chain aggregates the processed clock signals and inputs them to each sub-clock group. After receiving the processed clock signal, each sub-clock group uses traditional clock tree synthesis to distribute the clock signal to its respective timing unit. In this technical solution, the fishbone-shaped clock tree trunk is responsible for long-distance strong drive transmission from the clock source to the trunk drive chain. The trunk drive chain is responsible for the convergence of clock signals and multi-branch distribution. The sub-clock groups are responsible for fine-grained clock distribution and timing optimization within the branches. The three work together to shorten the overall clock delay, increase the common path, and avoid the problem that the delay of a pure fishbone-shaped clock tree cannot be calculated by automated placement and routing tools and requires manual processing. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0032] Figure 1 A simplified schematic diagram of the clock logic provided in this application;

[0033] Figure 2 A simplified schematic diagram of the conventional clock synthesis logic structure provided in this application;

[0034] Figure 3 A simplified schematic diagram of the fishbone-shaped clock logic structure provided in this application;

[0035] Figure 4 Schematic diagram of the clock synthesis system provided in this application Figure 1 ;

[0036] Figure 5 This is a schematic diagram of the structure of the fishbone-shaped clock tree trunk provided in this application;

[0037] Figure 6 Schematic diagram of the clock synthesis system provided in this application Figure 2 ;

[0038] Figure 7 A schematic diagram of the sub-clock group provided in this application;

[0039] Figure 8 Schematic diagram of the clock synthesis system provided in this application Figure 3 ;

[0040] Figure 9 This is a schematic diagram of the chip structure provided in this application;

[0041] Figure 10 A schematic diagram of the structure of the electronic device provided in this application;

[0042] Figure 11 The flowcharts for the back-end implementation of the traditional clock synthesis technology provided in this application and the clock synthesis technology in this solution are shown below.

[0043] Figure 12 The digital backend flowchart provided in this application is after extracting the timing file and physical library file of the fishbone clock structure.

[0044] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0046] In the chip physical implementation stage, clock tree synthesis is the core link to ensure chip performance, power consumption and timing convergence. The clock signal is the heartbeat of synchronous logic circuit, and the uniformity of its transmission delay directly affects whether the chip's setup time and hold time meet the design requirements.

[0047] In complex System-on-Chip (SoC) designs, clock networks typically need to drive hundreds of thousands or even millions of timing units (such as flip-flops, latches, etc.).

[0048] Figure 1 A simplified schematic diagram of the clock logic provided in this application is shown below. Figure 1 As shown, from left to right, they are: clock input source CLOCK, buffer (represented by a triangle symbol), fan-out connection, and n load units (D flip-flops).

[0049] The clock input source CLOCK serves as the starting point of the entire clock network, providing the original clock signal. The buffer is used to drive the clock signal through this buffer first. Then, it is output to the fan-out connection, which is divided into multiple branches from one line and directly connected to the clock ports of each timing unit on the right. The output is given to multiple timing units (flip-flops) with D, Q, and CP ports, with the number of up to n indicated by ellipses.

[0050] Traditional clock tree synthesis methods balance clock delay by inserting buffers or inverters, but due to the dispersion of physical layout and load capacity, clock paths branch prematurely and the proportion of common paths is insufficient, thereby weakening robustness to process, voltage, and temperature (PVT) fluctuations.

[0051] Furthermore, as chip manufacturing processes move into advanced process nodes (e.g., below 7nm), the requirements for timing margin become increasingly stringent due to clock signal latency fluctuations, making it difficult for traditional methods to simultaneously achieve low latency, low power consumption, and high reliability.

[0052] For example, Figure 2 A simplified schematic diagram of the conventional clock synthesis logic structure provided in this application is shown below. Figure 2 As shown, from left to right, they are: clock input source CLOCK, first-level buffer, a tree-like buffer chain that branches out at each level, end buffer, and n load units (D flip-flops).

[0053] The clock input source CLOCK is the starting point of the clock signal; the clock signal first passes through the first-level buffer; the tree-like buffer chain that branches step by step divides the clock signal into multiple paths, and each path then passes through multiple cascaded buffers that branch step by step (that is, each path has multiple triangles connected in series, with ellipses indicating more levels in between), forming a typical binary / multi-branch tree structure; then the end buffer drives the corresponding timing unit individually; each flip-flop on the right is driven by its own independent clock path, and the path length and the number of buffer levels may be different.

[0054] A fishbone clock tree forms a backbone structure by connecting large drive buffers / inverters in parallel, which can significantly increase the proportion of common paths and reduce clock skew.

[0055] However, its reliance on manual script intervention to handle latency issues that automated tools cannot accurately calculate leads to long and error-prone design iteration cycles.

[0056] For example, Figure 3 A simplified schematic diagram of the fishbone-shaped clock logic structure provided in this application is shown below. Figure 3 As shown, from left to right, they are: clock input source CLOCK, first-stage buffer, parallel buffer group (fishbone trunk), second-stage parallel buffer group, and n load units (D flip-flops).

[0057] The clock input source CLOCK is the starting point of the clock signal; the clock signal enters the first-stage buffer; the clock signal is then divided into multiple paths in the parallel buffer group, each path consisting of multiple buffers / inverters connected end to end and arranged in parallel (multiple triangles side by side, with ellipses indicating more parallel units in between), forming a fishbone backbone with high driving capability; after the second-stage parallel buffer group has passed through the first stage of parallel driving, it enters the next stage of the same parallel buffer array to further enhance the driving force; then the clock ports of n load units, that is, all timing units, are connected to the output of the fishbone backbone, sharing the same large driving point.

[0058] In other words, the following technical problems often exist in the above process:

[0059] 1) Short common paths: Dispersed physical locations lead to early path forking, low proportion of common paths, and poor resistance to PVT fluctuations;

[0060] 2) High load problem: The load capacity of a single drive unit is limited, and buffers need to be inserted frequently, increasing area and power consumption.

[0061] 3) Delay calculation and constraint back-annotation: In a fishbone structure, how to automatically extract the main delay and back-annotate it to the sub-clock group to avoid efficiency loss caused by manual adjustment.

[0062] 4) Process compatibility: How to seamlessly integrate the fishbone structure with the traditional clock tree integrated process to ensure the executability of subsequent digital back-end (such as wire wrapping, timing signature).

[0063] To address the technical problems existing in the prior art, the inventors of this application propose the following concept: The root cause of the difficulty in achieving low latency, low power consumption, and high reliability in traditional clock tree synthesis lies in the premature branching of the clock signal after originating from the source point. Each path is driven independently with significant differences in physical distance, resulting in a short common path and the need to insert numerous buffers to smooth the delay. This increases power consumption and introduces greater skew and insertion delay. Therefore, a fishbone-shaped clock tree trunk, composed of parallel buffers connected end-to-end, can be used at the beginning of the clock path for strong drive enhancement. This, combined with the trunk drive chain, ensures the clock signal is properly routed. The clock signal is transmitted over a long distance to the concentrated load area, allowing all sub-clock groups to share a long common path. This reduces trunk latency, decreases the total number of buffers, and enhances the ability to resist PVT fluctuations. In the latter part of the clock path, the load is further divided into multiple sub-clock groups according to the logic depth and physical location of the timing units in the same clock structure. After being distributed by the trunk drive chain, each sub-clock group is distributed and timing optimized step by step using traditional clock tree synthesis. This ensures local timing convergence while taking into account low latency, low power consumption, and high reliability of the clock signal transmission as a whole.

[0064] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments.

[0065] The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0066] Figure 4 Schematic diagram of the clock synthesis system provided in this application Figure 1 ,like Figure 4 As shown, the clock synthesis system 40 includes: a fishbone-shaped clock tree trunk 41, a trunk drive chain 42 (thick black line in the figure) connected in sequence, and at least one sub-clock group 43 connected to the trunk drive chain 42 (two are shown in the figure, the actual number depends on the situation). Each sub-clock group 43 is constructed based on the logic depth and physical location of the timing unit in the same clock structure.

[0067] In this implementation, the fishbone-shaped clock tree trunk 41 serves as the strong drive transmission channel for clock signals, the trunk drive chain 42 serves as the convergence and distribution node for clock signals, and the sub-clock group 43 serves as the end distribution and load drive unit for clock signals.

[0068] For each sub-clock group 43, timing units with the same or similar logic depth and adjacent physical locations or located in the same region can be grouped into the same sub-clock group, thereby ensuring that the clock path length and logic level within the sub-clock group are consistent, which facilitates subsequent unified optimization using traditional clock tree synthesis.

[0069] For example, the fishbone-shaped clock tree trunk 41 receives the clock signal from the clock input source, performs drive enhancement processing, and sends the processed clock signal to the trunk drive chain 42; the trunk drive chain 42 aggregates the processed clock signals and inputs them to each sub-clock group 43; each sub-clock group 43, after receiving the processed clock signal, uses traditional clock tree synthesis to distribute the clock signal to its respective timing unit.

[0070] In this implementation, during the transmission of the clock signal, the fishbone-shaped clock tree trunk 41 first receives the clock signal from the clock input source and performs drive enhancement processing on the clock signal to improve the driving capability of the clock signal so that it can drive the large load on the subsequent long-distance routing line. The clock signal after being driven and enhanced by the fishbone-shaped clock tree trunk 41 is sent to the trunk drive chain 42. The trunk drive chain 42 aggregates the processed clock signal and inputs it to each of the sub-clock groups 43 connected to it, thereby realizing the distribution of the clock signal from the trunk to each branch.

[0071] After receiving the processed clock signal, each sub-clock group 43 uses conventional clock tree synthesis to distribute the clock signal to its respective timing unit.

[0072] For example, traditional clock tree synthesis drives the clock signal to the clock port of each timing unit step by step by inserting buffers or inverters inside the sub-clock group 43, and performs balanced optimization on the clock delay of each timing unit.

[0073] Optionally, the main drive chain 42 is a low-resistance physical trace;

[0074] Low-resistance physical traces are constructed using high-layer metal traces or top-layer metal traces.

[0075] In this implementation, the backbone drive chain 42 is a low-impedance physical trace used to reduce the transmission loss of the clock signal during the backbone distribution stage.

[0076] For example, low-resistance physical traces can be constructed using high-layer metal traces. High-layer metal traces have a wider linewidth and a thicker metal layer than low-layer metal traces, resulting in lower resistance per unit length. This effectively reduces the resistance-capacitance (RC) load introduced by the traces, thereby reducing the attenuation and delay of the clock signal on the main drive chain 42.

[0077] In addition, low-resistance physical traces can also be constructed using top-layer metal traces. The top-layer metal trace has the widest line width and the lowest resistance per unit length. Being on the same layer as the power grid, it can effectively reduce RC load.

[0078] In practical implementation, the physical path of the main drive chain 42 can be planned by drawing lines by hand, so that it avoids congested areas and uses the shortest path to connect each sub-clock group 43. This ensures the low impedance characteristics of the main drive chain 42 at the physical implementation level, and ensures that the clock signal enhanced by the fishbone clock tree trunk 41 can be distributed to each sub-clock group 43 with high quality.

[0079] The clock synthesis system provided in this application includes: a fishbone-shaped clock tree trunk, a trunk drive chain, and at least one sub-clock group connected in sequence. Each sub-clock group is constructed based on the logical depth and physical location of timing units in the same clock structure. The fishbone-shaped clock tree trunk receives the clock signal from the clock input source, performs drive enhancement processing, and sends the processed clock signal to the trunk drive chain. The trunk drive chain aggregates the processed clock signals and inputs them to each sub-clock group. After receiving the processed clock signal, each sub-clock group uses traditional clock tree synthesis to distribute the clock signal to its respective timing unit. In this technical solution, the fishbone-shaped clock tree trunk is responsible for long-distance strong drive transmission from the clock source to the trunk drive chain, the trunk drive chain is responsible for clock signal aggregation and multi-branch distribution, and the sub-clock groups are responsible for fine-grained clock distribution and timing optimization within their branches. The three work together to shorten the overall clock delay, increase the common path, and avoid the problem that a pure fishbone-shaped clock tree cannot be used by automated placement and routing tools to calculate delays and requires manual processing.

[0080] Based on the above embodiments, Figure 5 A schematic diagram of the structure of the fishbone-shaped clock tree trunk provided in this application is shown below. Figure 5 As shown, the fishbone-shaped clock tree trunk 41 includes: a first-level buffer unit 411 and a multi-level parallel large drive buffer 412 connected to the first-level buffer unit 411;

[0081] The fishbone clock tree trunk 41 adopts a hierarchical driving architecture. The first-level buffer unit 411 is located at the front end of the fishbone clock tree trunk 41 and is directly connected to the clock input source, serving as the first-level driving node for the clock signal entering the fishbone clock tree trunk 41. The multi-level parallel large driving buffer 412 is cascaded with the first-level buffer unit 411 and is located downstream of the first-level buffer unit 411, serving as the main driving enhancement stage for the clock signal.

[0082] For example, the first-level buffer unit 411 is used to receive the clock signal from the clock input source and perform buffering and drive capability preprocessing; the multi-level parallel large drive buffer 412 is used to perform strong drive enhancement processing on the processed clock signal and transmit it to the main drive chain 42.

[0083] In this implementation, during one possible operation, the first-stage buffer unit 411 receives the clock signal output from the clock input source and then performs buffering and drive capability preprocessing on the clock signal.

[0084] For example, buffering and drive capability preprocessing are used to isolate the impact of large loads in the subsequent stage on the clock signal quality at the clock source.

[0085] The clock signal, after initial processing by the first-level buffer unit 411, is sent to the multi-level parallel large drive buffer 412. The multi-level parallel large drive buffer 412 performs strong drive enhancement processing on the initially processed clock signal, greatly improving the driving capability of the clock signal, enabling it to drive the main drive chain 42 and the large load composed of multiple sub-clock groups 43 connected to the main drive chain 42, and transmits the clock signal after strong drive enhancement processing to the main drive chain 42.

[0086] Optionally, the multi-stage parallel large drive buffer 412 includes: a multi-stage drive unit group 4121 connected end to end, and each stage of the drive unit group 4121 includes: multiple buffers or inverters connected in parallel (the number of each stage is not limited; for example, they can be added sequentially).

[0087] For example, each stage of the drive unit group 4121 is used to perform step-by-step strong drive processing on the processed clock signal.

[0088] In this implementation, the multi-level parallel large drive buffer 412 adopts a multi-level cascaded parallel drive architecture, including: a multi-level drive unit group 4121 connected end to end. Here, three levels are used as an example for explanation. In actual applications, the number of levels can be adjusted according to the load size and drive requirements.

[0089] Each stage of the drive unit group 4121 includes multiple buffers or inverters connected in parallel. The input terminals and output terminals of multiple buffers or inverters in the same stage are connected together. By connecting them in parallel, the driving capabilities of multiple units are superimposed, thereby obtaining a driving capability much greater than that of a single buffer or inverter.

[0090] The multi-stage drive unit groups 4121 are connected end-to-end, meaning that the output of the previous stage drive unit group 4121 is connected to the input of the next stage drive unit group 4121, forming a chain structure of progressively driving. During operation, each stage drive unit group 4121 performs progressively stronger driving processing on the clock signal output from the previous stage, further enhancing the driving capability of the clock signal at each stage. After multiple stages of progressive enhancement, the final output clock signal has sufficient driving force to drive the main drive chain 42 and the multiple sub-clock groups 43 connected to it.

[0091] Preferably, a three-stage large drive buffer is sufficient to drive the clock source to the sub-clock group source. The specific number of stages can be adjusted according to the actual load and process conditions.

[0092] The clock synthesis system provided in this application embodiment includes a fishbone-shaped clock tree trunk comprising: a first-level buffer unit and a multi-level parallel large-drive buffer connected to the first-level buffer unit; the first-level buffer unit receives the clock signal from the clock input source and performs buffering and drive capability preprocessing; the multi-level parallel large-drive buffer performs strong drive enhancement processing on the processed clock signal and transmits it to the trunk drive chain. In this technical solution, through the processing of the first-level buffer unit and the multi-level parallel large-drive buffer, the first-level buffer unit ensures stable access of the clock signal from the source, and the multi-level parallel large-drive buffer provides sufficient drive force to overcome the impedance caused by long-distance traces and multi-branch loads. The two work together to realize the drive enhancement function of the fishbone-shaped clock tree trunk.

[0093] Based on the above embodiments, Figure 6 Schematic diagram of the clock synthesis system provided in this application Figure 2 ,like Figure 6 As shown, the clock integration system 40 also includes: sub-clock group source points 44 respectively arranged between each sub-clock group 43 and the main drive chain 42;

[0094] The clock integration system 40 also includes: sub-clock group source points 44, which are respectively arranged between each sub-clock group 43 and the main drive chain 42, serving as connection nodes between the main drive chain 42 and the sub-clock group 43.

[0095] For example, the number of sub-clock group source points 44 corresponds one-to-one with the number of sub-clock groups 43. Taking the two sub-clock groups 43 in the example above as an example, two sub-clock group source points 44 are set accordingly. In actual applications, the number of sub-clock group source points 44 is determined based on the number of sub-clock groups 43.

[0096] Each sub-clock group source point 44 is physically located close to its corresponding sub-clock group 43 and is connected to the output of the fishbone clock tree trunk 41 via the trunk drive chain 42. By setting the sub-clock group source point 44 between the trunk drive chain 42 and the sub-clock group 43, the clock signal distribution path can be divided into two parts: the trunk segment and the sub-segment. The trunk segment runs from the clock input source through the fishbone clock tree trunk 41 and the trunk drive chain 42 to the sub-clock group source point 44, while the sub-segment runs from the sub-clock group source point 44 to the various timing units within the sub-clock group 43. This division facilitates independent timing analysis and optimization of the two segments.

[0097] For example, for each sub-clock group source point 44, the sub-clock group source point 44 is used to receive the clock signal distributed by the trunk drive chain 42 and serve as the clock starting point for the synthesis of the internal clock tree of the corresponding sub-clock group 43.

[0098] In this implementation, in one possible operation, each sub-clock group source point 44 receives a clock signal distributed by the trunk drive chain 42 and uses the clock signal as the clock starting point for the synthesis of the clock tree within its corresponding sub-clock group 43.

[0099] For example, after completing the physical implementation of the fishbone clock tree trunk 41 and trunk drive chain 42, the clock delay from the clock input source to each sub-clock group source point 44 is calculated using a timing check tool, and the delay result is recorded. Then, the clock constraints are modified, and the delay is back-annotated to the corresponding sub-clock group source point 44 to establish new constraints. The original overall clock structure is replaced by sub-clock group 43 for clock tree synthesis, while retaining all logical relationships.

[0100] In this way, sub-clock group source point 44 becomes the virtual clock source for clock tree synthesis within sub-clock group 43. Traditional clock tree synthesis tools start from sub-clock group source point 44 and construct and optimize the clock tree within sub-clock group 43, thus achieving the connection between the fishbone-shaped clock tree backbone and traditional clock tree synthesis. The setting of sub-clock group source point 44 allows the clock delay of the backbone to be accurately quantified and back-annotated to the constraints of the sub-clock group, ensuring the accuracy and completeness of the timing analysis of the entire clock network.

[0101] The clock synthesis system provided in this application further includes: sub-clock group source points respectively arranged between each sub-clock group and the main drive chain; for each sub-clock group source point, the sub-clock group source point is used to receive the clock signal distributed by the main drive chain and serves as the clock starting point for clock tree synthesis within the corresponding sub-clock group. In this technical solution, the setting of sub-clock group source points decomposes the originally globally unified clock tree synthesis problem into multiple independent local clock tree synthesis problems. Each sub-clock group independently performs clock delay optimization and skew adjustment with its own sub-clock group source point as the clock starting point, avoiding the problem of mutual restraint between long physical distance paths and short physical distance paths in traditional global clock tree synthesis; at the same time, the sub-clock group source point serves as the boundary node between the main chain and the sub-groups, so that the addition, removal or adjustment of sub-clock groups will not affect the structure of the fishbone clock tree main chain, improving the scalability and maintainability of the clock synthesis system, and the local optimization results within each sub-clock group can be independently verified, reducing the iteration cycle of timing convergence of large-scale clock networks.

[0102] Based on the above embodiments, Figure 7 A schematic diagram of the sub-clock group provided in this application is shown below. Figure 7 As shown, each sub-clock group 43 includes: a clock distribution network 431 and a timing unit set 432 connected to the clock distribution network 431;

[0103] Each sub-clock group 43 can use a traditional clock tree synthesis architecture for internal clock distribution, including: a clock distribution network 431 and a timing unit set 432 connected to the clock distribution network 431.

[0104] The clock distribution network 431 is located at the front end of the sub-clock group 43 and is connected to the source point 44 of the sub-clock group, serving as the distribution channel for the clock signal within the sub-clock group 43; the timing unit set 432 is located at the end of the sub-clock group 43 and is connected to the clock distribution network 431, serving as the load end of the clock signal.

[0105] The clock distribution network 431 and the timing unit set 432 are connected sequentially within the sub-clock group 43. The clock signal enters the clock distribution network 431 from the sub-clock group source point 44, and after being distributed and driven, it reaches each timing unit in the timing unit set 432, completing the complete transmission path of the clock signal within the sub-clock group 43.

[0106] For example, the clock distribution network 431 is used to receive the clock signal output by the main drive chain 42 and perform step-by-step distribution drive; the timing unit set 432 includes: multiple timing units 4321 (two are shown in the figure as an example, the actual number depends on the actual situation), each timing unit 4321 is connected to the clock distribution network 431 and is used to receive the distributed clock signal to complete the timing operation.

[0107] In this implementation, the clock distribution network 431 receives the clock signal output by the main drive chain 42 (which can be accessed via the sub-clock group source point 44) and distributes the clock signal step by step.

[0108] For example, the clock distribution network 431 distributes a single clock signal into multiple paths through the cascading and branching of multi-level buffers or inverters, which then drive the various timing units in the timing unit set 432.

[0109] The timing unit set 432 includes multiple timing units 4321. Two are shown in the figure as an example. The actual number depends on the size of the sub-clock group 43. The clock port of each timing unit 4321 is connected to the corresponding output terminal of the clock distribution network 431 to receive the distributed clock signal to complete the timing operation.

[0110] For example, when data sampling, latching, or transmission is performed under the trigger of the clock effective edge, the step-by-step distribution drive of the clock distribution network 431 can ensure that each timing unit 4321 can receive a clock signal that meets the requirements of driving capability and signal quality, thereby ensuring the normal operation of all timing units in the timing unit set 432.

[0111] Optionally, the clock distribution network 431 is a clock tree structure constructed using traditional clock tree synthesis, and the signal transition time of the buffers or inverters in the clock distribution network 431 does not exceed the maximum transition time constraint.

[0112] The clock distribution network 431 is a clock tree structure constructed using traditional clock tree synthesis. That is, by using automated placement and routing tools, buffers or inverters are automatically inserted into the sub-clock group 43 to construct a tree-like clock distribution network from the source point 44 of the sub-clock group to each timing unit 4321.

[0113] In the process of traditional clock tree synthesis, the signal toggle time of the buffers or inverters in the clock distribution network 431 is first constrained so that the signal toggle time of each buffer or inverter does not exceed the maximum toggle time constraint, so as to ensure that the edge rate of the clock signal meets the requirements of the technology library and timing convergence.

[0114] For example, if the toggle time of a buffer or inverter exceeds the maximum toggle time constraint, the tool will reduce the toggle time by adjusting the drive size of the unit or adding a pre-stage drive unit, ensuring that the toggle time of all units in the clock distribution network 431 is within the constraint range.

[0115] For example, the clock delay of each timing unit 4321 is flattened by inserting a buffer or a pair of inverters, and then the clock delay of each timing unit is adjusted by useful skew so that the setup time margin and hold time margin of each timing unit meet the preset timing constraints.

[0116] The setup time margin satisfies the timing constraint requirement that the settling time of the data input signal of timing unit 4321 before the arrival of the clock effective edge is not less than the setup time of the timing unit; the hold time margin satisfies the timing constraint requirement that the hold time of the data input signal of timing unit 4321 after the arrival of the clock effective edge is not less than the hold time of the timing unit.

[0117] In this implementation, during the construction of the clock distribution network 431, the clock delay of each timing unit 4321 is further balanced and optimized while satisfying the flip-flop time constraint.

[0118] For example, by inserting buffers or pairs of inverters into the clock path to increase the delay of shorter paths, the clock delay of each timing unit 4321 can be flattened, reducing clock skew. The insertion of pairs of inverters does not change the phase of the clock signal; it only increases the delay, making it suitable for scenarios requiring precise delay adjustment where phase shift is undesirable.

[0119] Based on the flattening of the delay, the clock delay of each timing unit 4321 is adjusted by the useful skew technique. That is, according to the actual needs of the timing path, some timing units are intentionally assigned earlier or later clock arrival times to optimize the margin of the timing path.

[0120] In addition, the setup time margin can meet the timing constraints if the settling time of the data input signal of timing unit 4321 before the arrival of the clock effective edge is not less than the setup time of the timing unit. The setup time can be an inherent parameter of the timing unit itself, which represents the minimum time that the data signal needs to be stabilized before the clock effective edge. Only when the settling time of the data signal is greater than or equal to the setup time can the timing unit correctly sample data at the clock effective edge.

[0121] The time margin can satisfy the timing constraints as follows: the time for holding the data input signal of timing unit 4321 after the arrival of the clock effective edge is not less than the time for holding the timing unit. The time for holding can also be an inherent parameter of the timing unit, which represents the minimum time for the data signal to remain stable after the clock effective edge. Only when the time for holding the data signal is greater than or equal to the time for holding can the timing unit avoid data confusion or missampling at the clock effective edge.

[0122] By ensuring that the setup time margin and the hold time margin simultaneously meet the constraints, it can be guaranteed that each timing unit 4321 in the sub-clock group 43 can correctly and reliably complete the data sampling and latching operations on the effective clock edge.

[0123] Optionally, each sub-clock group 43 further includes a clock logic unit 433 connected between the clock distribution network 431 and the timing unit set 432;

[0124] Each sub-clock group 43 also includes a clock logic unit 433, which is connected between the clock distribution network 431 and the timing unit set 432, and serves as a logic processing node for clock signals from the distribution network to the timing units.

[0125] For example, the input of clock logic unit 433 is connected to the output of clock distribution network 431, and the output of clock logic unit 433 is connected to the clock port of the corresponding timing unit in timing unit set 432. After the clock signal is distributed by clock distribution network 431, it is first processed by clock logic unit 433 and then transmitted to the corresponding timing unit.

[0126] In actual clock structures, not all timing units are directly connected to the clock source point through buffers. The clock paths of some timing units also contain various logic gates. Therefore, by setting clock logic units 433 between the clock distribution network 431 and the timing unit set 432, the difference in logic depth in the actual clock structure can be accurately reflected, so that the internal structure of the sub-clock group 43 is consistent with the logic relationship of the original clock design.

[0127] For example, the clock logic unit 433 includes at least one of an XOR gate, a NOR gate, and a gating unit, used to process the clock signal according to the logic function of the clock logic unit 433 and then transmit it to the corresponding timing unit.

[0128] In this implementation, XOR gates can be used to implement logic functions such as phase selection or frequency switching of clock signals; NOR gates can be used to implement enable control or logic combination of clock signals; and gating units (such as clock gating units) can be used to turn off the clock of the corresponding timing unit when the clock signal is not needed, so as to reduce dynamic power consumption.

[0129] After the clock signal is processed by the logic function of the clock logic unit 433, the processed clock signal is transmitted to the corresponding timing unit.

[0130] The clock synthesis system provided in this application embodiment includes a clock distribution network and a set of timing units connected to the clock distribution network in each sub-clock group. The clock distribution network receives the clock signal output from the main drive chain and performs hierarchical distribution driving. The set of timing units includes multiple timing units, each connected to the clock distribution network, for receiving the distributed clock signal to complete timing operations. In this technical solution, the clock distribution network adopts a tree structure with hierarchical distribution driving, which is compatible with the automated implementation of traditional clock tree synthesis tools. By inserting buffers or inverters, it can ensure that the driving capability and toggle time of each stage meet the constraints, while providing an operable structural basis for subsequent delay and useful skew optimization. Each timing unit in the set of timing units is connected to the clock distribution network, ensuring that each timing unit can receive a clock signal that meets the signal quality requirements to complete timing operations. The cooperation between the two enables the clock distribution within the sub-clock group to achieve locally optimal timing convergence with the support of automated tools.

[0131] Based on the above embodiments, Figure 8 Schematic diagram of the clock synthesis system provided in this application Figure 3 ,like Figure 8 As shown, as an example, the clock synthesis system 40 may include:

[0132] Clock input source CLOCK: The signal starting point of the entire clock synthesis system 40, providing the original clock signal to the clock synthesis system 40;

[0133] First-stage buffer unit 411 (single triangular buffer): After receiving the clock signal from the clock input source, it performs buffering and drive capability preprocessing;

[0134] Multi-level parallel large drive buffer 412 (two-level parallel triangular array, with more levels indicated by ellipses): each level is a drive unit group 4121, each group consists of multiple buffers or inverters connected in parallel, and the multiple levels are connected end to end to perform step-by-step strong drive enhancement processing on the pre-processed clock signal; the first-level buffer unit 411 and the multi-level parallel large drive buffer 412 together form the fishbone-shaped clock tree trunk 41.

[0135] Main drive chain 42 (thick black vertical line in the figure): gathers the clock signals after being enhanced by the main drive 41 of the fishbone clock tree, and distributes them to each sub-clock group 43.

[0136] Sub-clock group source point 44 (multiple triangular buffers on the right side of the main drive chain 42, labeled as sub-clock group 1 source point, sub-clock group 2 source point, ..., sub-clock group N source point respectively): respectively arranged between each sub-clock group 43 and the main drive chain 42, receiving the clock signal distributed by the main drive chain 42, and serving as the clock starting point for the synthesis of the clock tree inside the corresponding sub-clock group 43.

[0137] Sub-clock group 43 (multiple rectangles on the right, labeled Sub-clock group 1 clock logic complex, Sub-clock group 2 clock logic complex, ..., Sub-clock group N clock logic complex): Each sub-clock group 43 is constructed based on the logic depth and physical location of the timing unit in the same clock structure. It contains a clock distribution network 431 and a timing unit set 432, and may also contain clock logic units 433 (XOR gate, NOR gate, gated unit, etc.). After receiving the processed clock signal, the sub-clock group 43 uses traditional clock tree synthesis to distribute the clock signal to its respective timing unit.

[0138] The clock integration system provided in this application embodiment offers advantages in power consumption, performance, and area.

[0139] Based on the above embodiments, Figure 9 This is a schematic diagram of the chip structure provided in this application, such as... Figure 9 As shown, the chip 91 includes: the clock synthesis system 40 in any of the above embodiments.

[0140] The chip provided in this application embodiment has similar technical effects to the above embodiments, and will not be described again here.

[0141] Based on the above embodiments, Figure 10 A schematic diagram of the structure of the electronic device provided in this application, such as... Figure 10 As shown, the electronic device 101 includes: the clock integration system 40 in any of the above embodiments;

[0142] or, Figure 9 Chip 91 in the illustrated embodiment.

[0143] The electronic device provided in this application has similar technical effects to the above embodiments, and will not be described again here.

[0144] Based on the above embodiments, Figure 11 The back-end implementation flowcharts of the traditional clock synthesis technology provided in this application and the clock synthesis technology in this solution are as follows: Figure 11 As shown, the process includes:

[0145] For traditional clock synthesis technologies, including:

[0146] Step 1-1: Design data input (physical library, timing library);

[0147] Steps 1-2: Layout;

[0148] Steps 1-3: Layout;

[0149] Steps 1-4: Clock tree synthesis;

[0150] Steps 1-5: Wiring;

[0151] Steps 1-6: Timing tag check.

[0152] The clock synthesis technology in this solution includes:

[0153] Step 2-1: Design data input (physical library, timing library);

[0154] Step 2-2, Layout;

[0155] Steps 2-3: Layout;

[0156] Steps 2-4: (Insert fishbone clock structure (after placement and before clock tree synthesis, insert the fishbone clock tree trunk and trunk drive chain to complete the drive enhancement process from the clock input source to the source points of each sub-clock group)) Check for voltage flip-time violations in the fishbone clock structure;

[0157] After inserting the fishbone clock structure, the timing check tool is used to verify whether the driving force from the source point to the source point of the sub-clock group meets the standard and whether there is a voltage flip-flop time violation. If there is a violation, the number of parallel buffers or inverters needs to be adjusted to increase the driving force, or wider, lower resistance layer traces can be used to reduce the load.

[0158] Steps 2-5: Clock tree synthesis;

[0159] In this process, based on the completion of the fishbone-shaped clock tree trunk and trunk drive chain, traditional clock tree synthesis is used to construct a clock distribution network for each sub-clock group, and the clock signal is distributed and driven to each timing unit in the timing unit set step by step.

[0160] In addition, for clocks of the same origin involved in this solution, traditional clock tree synthesis is used within the sub-clock group; other non-same-origin clocks still use traditional clock synthesis to complete the subsequent process.

[0161] Steps 2-6: Wiring;

[0162] Steps 2-7: Check for voltage flip-time violations in the fishbone clock structure;

[0163] After routing, the voltage flip-over time of the fishbone clock structure is checked again to ensure that timing constraints are still met after routing.

[0164] Based on the above embodiments, Figure 12 The digital backend flowchart provided in this application, after extracting the timing file and physical library file of the fishbone clock structure, is as follows: Figure 12 As shown, the process includes:

[0165] Step 121: Design data input (physical library, timing library);

[0166] Step 122, Layout;

[0167] Steps 1, 2, and 3: Layout;

[0168] Step 124, (Insert fishbone clock structure (insert fishbone clock tree trunk and trunk drive chain)) Check for voltage flip-time violations in the fishbone clock structure;

[0169] Among them, it is necessary to verify whether the driving force and the flip time meet the standards;

[0170] Step 125: Extract timing library files and physical library files;

[0171] In this process, the buffers and inverters connected end to end in the fishbone clock structure are treated as a macro unit, and a library is built for it to extract timing library file and physical library file information.

[0172] Step 126, (Data Import (Import the extracted timing library file and physical library file into the original digital back-end process on the right)) Design data input (physical library, timing library); at the same time, receive the fishbone clock structure macrocell library file imported from the left column;

[0173] Step 127, Layout;

[0174] Step 128, Layout;

[0175] Step 129: Clock Tree Synthesis;

[0176] Since the fishbone clock tree trunk has been imported as a macro unit, the tool can automatically complete the clock tree synthesis according to the original process without manually modifying constraints or back-annotating delays.

[0177] Step 130: Wiring;

[0178] Step 131: Check for voltage flip-over time violations in the fishbone clock structure; during final approval, check whether the timing of the fishbone clock structure meets the constraints.

[0179] The implementation principles and technical effects of the embodiments provided in this application are as shown above, and will not be repeated here.

[0180] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A clock integration system, characterized in that, include: The fishbone-shaped clock tree trunk, the trunk drive chain, and at least one sub-clock group connected to the trunk drive chain are connected in sequence. Each sub-clock group is constructed based on the logical depth and physical location of the timing unit in the same clock structure. The fishbone-shaped clock tree trunk is used to receive the clock signal from the clock input source, perform drive enhancement processing, and send the processed clock signal into the trunk drive chain. The main drive chain is used to aggregate the processed clock signals and input them to each sub-clock group respectively; After receiving the processed clock signal, each sub-clock group uses conventional clock tree synthesis to distribute the clock signal to its respective timing unit.

2. The clock integration system according to claim 1, characterized in that, The fishbone-shaped clock tree trunk includes: a first-level buffer unit and a multi-level parallel large drive buffer connected to the first-level buffer unit; The first-stage buffer unit is used to receive the clock signal from the clock input source and then perform buffering and drive capability preprocessing. The multi-level parallel large drive buffer is used to perform strong drive enhancement processing on the processed clock signal and transmit it to the main drive chain.

3. The clock integration system according to claim 2, characterized in that, The multi-stage parallel large drive buffer includes: a multi-stage drive unit group connected end to end, and each stage of the drive unit group includes: multiple buffers or inverters connected in parallel. Each stage of the drive unit group is used to perform step-by-step strong drive processing on the processed clock signal.

4. The clock integration system according to any one of claims 1-3, characterized in that, The clock integration system also includes: sub-clock group source points respectively arranged between each sub-clock group and the main drive chain; For each sub-clock group source point, the sub-clock group source point is used to receive the clock signal distributed by the trunk drive chain and serve as the clock starting point for the synthesis of the clock tree within the corresponding sub-clock group.

5. The clock integration system according to any one of claims 1-3, characterized in that, Each sub-clock group includes: a clock distribution network and a set of timing units connected to the clock distribution network; The clock distribution network is used to receive the clock signal output by the backbone drive chain and perform hierarchical distribution drive. The timing unit set includes multiple timing units, each of which is connected to the clock distribution network and is used to receive the distributed clock signal to complete timing operations.

6. The clock integration system according to claim 5, characterized in that, The clock distribution network is a clock tree structure constructed using traditional clock tree synthesis, and the signal flip time of the buffers or inverters in the clock distribution network does not exceed the maximum flip time constraint. The clock delay of each timing unit is flattened by inserting a buffer or a pair of inverters, and then the clock delay of each timing unit is adjusted by a useful skew to ensure that the setup time margin and hold time margin of each timing unit meet the preset timing constraints. The setup time margin satisfies the timing constraint requirement as follows: the settling time of the data input signal of the timing unit before the arrival of the clock effective edge is not less than the setup time of the timing unit; the hold time margin satisfies the timing constraint requirement as follows: the hold time of the data input signal of the timing unit after the arrival of the clock effective edge is not less than the hold time of the timing unit.

7. The clock integration system according to claim 5, characterized in that, Each sub-clock group also includes a clock logic unit connected between the clock distribution network and the timing unit set; The clock logic unit includes at least one of an XOR gate, a NOR gate, and a gating unit, used to process the clock signal according to the logic function of the clock logic unit and then transmit it to the corresponding timing unit.

8. The clock integration system according to any one of claims 1-3, characterized in that, The main drive chain is a low-resistance physical trace. The low-resistance physical traces are constructed using high-layer metal traces or top-layer metal traces.

9. A chip, characterized in that, include: The clock integration system according to any one of claims 1-8.

10. An electronic device, characterized in that, include: The clock synthesis system according to any one of claims 1-8; Or, the chip as described in claim 9.

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