Chip clock frequency determination method, device, equipment, medium and product

Abstract

The application discloses a chip clock frequency determination method, device, equipment, medium and product, and relates to the technical field of chips. The method comprises the following steps: determining a chip working mode, wherein the chip working mode is used for indicating a power distribution mode between a first chip and a second chip; determining index data corresponding to the first chip and the second chip, wherein the index data is used for indicating a power balance degree between the first chip and the second chip; and determining a first clock frequency of the first chip and a second clock frequency of the second chip based on the chip working mode and the index data. The processing efficiency between the first chip and the second chip is balanced according to the index data, the target clock frequency is dynamically adjusted in the process of chip working, and the determination efficiency of the clock frequency is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, apparatus, device, medium and product for determining chip clock frequency. Background Technology

[0002] The clock frequency determines the time base for the operations performed by the internal logic units of the chip. To meet the needs of different application scenarios, the chip's clock frequency is adjusted by the chip's built-in frequency management unit.

[0003] In related technologies, the clock frequencies of at least two chips in a heterogeneous computing system are determined based on a preset fixed ratio allocation. Specifically, target power is allocated to at least two chips based on the total power budget of the heterogeneous computing system, and the clock frequency of the chips is determined based on the target power.

[0004] However, the power allocation strategy of the above method is fixed, which leads to low overall system processing efficiency in scenarios with load fluctuations. Summary of the Invention

[0005] This application provides a method, apparatus, device, medium, and product for determining chip clock frequency. The technical solution provided by this application includes the following aspects.

[0006] According to one aspect of the embodiments of this application, a method for determining the clock frequency of a chip is provided, the method comprising: Determine the chip operating mode, which indicates the power distribution method between the first chip and the second chip; Determine the indicator data corresponding to the first chip and the second chip, the indicator data being used to indicate the degree of power balance between the first chip and the second chip; Based on the chip's operating mode and the indicator data, the first clock frequency to be adjusted for the first chip and the second clock frequency to be adjusted for the second chip are determined.

[0007] According to another aspect of the embodiments of this application, a chip clock frequency determination apparatus is provided, the apparatus comprising: The determination module is configured to determine the chip operating mode, which is used to indicate the power distribution method between the first chip and the second chip; The determining module is further configured to determine the index data corresponding to the first chip and the second chip, the index data being used to indicate the degree of power balance between the first chip and the second chip; The processing module is configured to determine, based on the chip's operating mode and the indicator data, the first clock frequency to be adjusted to and the second clock frequency to be adjusted to.

[0008] On the other hand, a processor is provided, which includes: a device for determining the chip clock frequency as described in the above embodiment.

[0009] On the other hand, a board is provided, which includes: a device for determining the chip clock frequency as described in the above embodiment.

[0010] On the other hand, a computer device is provided, comprising: a chip clock frequency determination device as provided in the above embodiments, or a processor as provided in the above embodiments, or a board as provided in the above embodiments.

[0011] According to one aspect of the embodiments of this application, another computer device is provided, the computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-described method for determining the chip clock frequency.

[0012] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, the computer program being loaded and executed by a processor to implement the above-described method for determining the chip clock frequency.

[0013] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program stored in a computer-readable storage medium, and a processor reading from the computer-readable storage medium and executing the computer program to implement the above-described method for determining the chip clock frequency.

[0014] The technical solution provided in this application can bring the following beneficial effects: By determining the chip operating mode corresponding to the heterogeneous system, a connection is established between the chip clock frequency determination method in the heterogeneous system and the working scenario and user requirements. Based on the indicator data corresponding to the first chip and the second chip, the first clock frequency for the first chip to perform the task and the second clock frequency for the second chip to perform the task, as indicated by the chip operating mode, are determined. In this process, indicator data is acquired in real time to indicate the balance between the processing efficiency of the first chip and the second chip. The target clock frequency is dynamically adjusted during the operation of the first chip and the second chip, which improves the applicability of the clock frequency determination method in different chip application scenarios, thereby improving the efficiency of clock frequency determination during chip operation. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a computer system provided in an exemplary embodiment of this application; Figure 2This is a flowchart of a method for determining the chip clock frequency provided in an exemplary embodiment of this application; Figure 3 This is a flowchart of a method for determining the chip clock frequency provided in another exemplary embodiment of this application; Figure 4 This is a schematic diagram of the process for determining the clock frequency in a first chip operating mode provided in an exemplary embodiment of this application; Figure 5 This is a schematic diagram illustrating the process of determining the clock frequency in a second chip operating mode, provided in an exemplary embodiment of this application. Figure 6 This is a schematic diagram of the process for determining the clock frequency in a third chip operating mode provided in an exemplary embodiment of this application; Figure 7 This is a flowchart of a method for determining the chip clock frequency provided in yet another exemplary embodiment of this application; Figure 8 This is a schematic diagram of the process for determining the clock frequency in the fourth chip operating mode provided in an exemplary embodiment of this application; Figure 9 This is a structural block diagram of a chip clock frequency determination device provided in an exemplary embodiment of this application; Figure 10 This is a schematic block diagram of a processor provided in an exemplary embodiment of this application; Figure 11 This is a schematic block diagram of a board provided in an exemplary embodiment of this application; Figure 12 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application; Figure 13 This is a schematic block diagram of a computer device provided in another exemplary embodiment of this application; Figure 14 This is a schematic block diagram of a computer device provided in yet another exemplary embodiment of this application; Figure 15 This is a schematic block diagram of a computer device provided in another exemplary embodiment of this application; Figure 16 This is a structural block diagram of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0016] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0017] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0018] It should be understood that although the terms first, second, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0019] It should be noted that this application may display prompt interfaces, pop-ups, or output voice prompts before and during the collection of user, processor, and computer device data. These prompt interfaces, pop-ups, or voice prompts are used to inform the user that their data is being collected. This ensures that the application only begins the steps for collecting user data after receiving confirmation from the user regarding the prompt interface or pop-up; otherwise (i.e., without user confirmation), the steps for collecting user data end, meaning no user data is collected. In other words, all user data collected in this application is collected with the user's consent and authorization, and the collection, use, and processing of related user data must comply with the relevant laws, regulations, and standards of the relevant countries and regions.

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0021] The clock frequency determines the time base for the operations performed by the internal logic units of a chip. To meet the needs of different application scenarios, the chip's clock frequency is adjusted by the chip's built-in frequency management unit. Illustratively, the chip's clock frequency is adjusted between a base frequency and a boost frequency. In related technologies, for heterogeneous computing systems with at least two chips collaborating, the overall processing efficiency is determined by the minimum of the clock frequencies corresponding to the two chips; that is, the system's processing efficiency is determined by the chip with the lower processing efficiency.

[0022] For example, taking the first chip as a Vision Processing Unit (VPU), the second chip as a Graphics Processing Unit (GPU), and the heterogeneous computing system as a VPU-GPU serial pipeline system, the overall frame rate of the heterogeneous computing system is used to indicate the overall processing efficiency of the system. It is determined by the slower one of the VPU and GPU, i.e., the overall frame rate of the system FPS_system = min(FPS_vpu, FPS_gpu); where frame rate (Frames Per Second, FPS) is the number of image frames processed per unit time, image frames are the computational processing objects of the VPU-GPU serial pipeline system, FPS_vpu is the frame rate of the VPU, and FPS_gpu is the frame rate of the GPU. When there is a significant difference in processing efficiency between VPU and GPU, the performance of the faster one cannot be fully utilized, resulting in wasted hardware processing performance. For example, if the VPU has a frame rate of 50 frames per second, while the GPU has a frame rate of only 30 frames per second, the overall frame rate of the heterogeneous computing system is limited to 30 frames per second, and the 20 frames per second performance margin of the VPU is wasted.

[0023] Therefore, the above method for determining the clock frequency of the chip results in low chip performance utilization when there are large differences in processing efficiency between cooperating chips, leading to low overall computing system processing efficiency. It is necessary to perform power management on at least two chips based on their actual processing efficiency in the heterogeneous computing system, thereby determining suitable clock frequencies for at least two chips, balancing the processing efficiency of at least two chips, and thus improving the overall processing efficiency of the heterogeneous computing system.

[0024] In related technologies, methods for determining the clock frequencies of at least two chips in a heterogeneous computing system include at least one of the following approaches.

[0025] (1) When the heterogeneous computing system is started, the total power budget of the system is allocated to the target power of at least two chips according to a preset fixed ratio, and the clock frequency corresponding to the at least two chips is determined based on the target power. Schematic, in the case of a heterogeneous computing system including a first chip and a second chip, taking a total power budget of 15 watts (W) and a fixed ratio of 1:4 as an example, the target power of the first chip is 3W, and the target power of the second chip is 12W.

[0026] However, the above method does not take into account the load variations of at least two chips during the actual operation of a heterogeneous computing system. This leads to significant differences in processing efficiency between the two chips under unbalanced load conditions, resulting in low hardware performance utilization. This method cannot dynamically respond to changes in chip load during system operation, leading to low overall system processing efficiency in scenarios with fluctuating loads.

[0027] (2) Perform independent power management for at least two chips, that is, obtain appropriate target power based on the load and temperature of each of the at least two chips, and then dynamically determine the clock frequency of each of the at least two chips through Dynamic Voltage and Frequency Scaling (DVFS).

[0028] However, this method ignores the collaborative relationship between at least two chips in a heterogeneous computing system. When at least two chips are performing tasks as a pipeline, this method cannot perceive the pipeline's balance. For example, if the first chip's processing efficiency is slow, causing it to become a performance bottleneck, the clock frequency of the second chip determined by this method may be high, which may cause the second chip to still operate in a high-power state, resulting in wasted system power, low hardware utilization, and low overall system processing efficiency.

[0029] (3) A temperature threshold is preset. When at least one of the two chips reaches the temperature threshold, the overall power budget and system frequency of the heterogeneous computing system are forcibly reduced, thereby updating the clock frequencies of the two chips respectively. However, this method causes a sharp drop in system performance through passive thermal management, reduces the task processing efficiency of the heterogeneous computing system, reduces the smoothness of system task processing, and damages the user experience; moreover, this method only focuses on temperature indicators and cannot maintain a balance between temperature and system performance.

[0030] In response to the above problems, this application provides a method for determining chip clock frequency, which achieves coordinated management, considers chip performance utilization and power allocation from the overall perspective of heterogeneous computing system, adaptively determines the clock frequency of at least two chips according to different tasks and loads, and allows users to set chip working modes according to application scenarios, thereby improving the flexibility and customizability of chip clock frequency determination.

[0031] Figure 1 This is a schematic diagram of the structure of a computer system provided in an exemplary embodiment of this application. The computer system 100 can implement a system architecture that is a method for determining the chip clock frequency, or a hardware architecture that is a device for determining the chip clock frequency, wherein the device is used to apply the method for determining the chip clock frequency. The computer system 100 includes: a computer device 120.

[0032] In some embodiments, the computer device 120 executes the chip clock frequency determination method of this embodiment; or, the computer device 120 includes a processor, and the processor executes the chip clock frequency determination method of this embodiment. The computer device 120 can be a terminal or a server, and this application embodiment does not limit this. The model training method provided in this application embodiment can be executed independently by the terminal, independently by the server, or jointly by the terminal and the server, and is not limited here.

[0033] The chip clock frequency determination method provided in this application can be executed by a computer device 120 or a chip clock frequency determination device within the computer device 120. In some embodiments, the computer device includes a heterogeneous computing system, which includes at least two types of hardware devices, including but not limited to a central processing unit (CPU), GPU, general-purpose graphics processor (GPGPU), application-specific integrated circuit (ASIC), neural network processing unit (NPU), tensor processing unit (TPU), virtual processor (VPU), digital signal processing (DSP), field-programmable gate array (FPGA), and other hardware devices that perform tasks based on clock frequency. The aforementioned chip clock frequency determination device can be implemented as, but is not limited to, a microcontroller integrated within the chip and its stored firmware code, or a scheduling module in the operating system responsible for resource allocation; this application does not limit this implementation.

[0034] In one example, when the heterogeneous computing system includes a first chip and a second chip, the chip operating mode of the heterogeneous computing system is determined, which is used to indicate the power distribution method between the first chip and the second chip; index data is determined to indicate the degree of power balance between the first chip and the second chip; and the clock frequencies corresponding to the first chip and the second chip are determined respectively based on the chip operating mode and the index data.

[0035] Optionally, taking the method of determining the chip clock frequency jointly implemented by the server and the terminal as an example, the server responds to the mode configuration signal triggered by the user, determines the chip working mode, and sends the chip working mode to the terminal. The terminal is configured with a heterogeneous computing system whose clock frequency is to be determined. The terminal performs at least one of the following steps: acquiring indicator data, and determining the first clock frequency and the second clock frequency based on the indicator data and the chip working mode.

[0036] It is worth noting that the aforementioned terminal can be at least one of the following electronic devices: smartphone, desktop computer, laptop computer, personal computer (PC), tablet computer, e-book reader, intelligent robot, augmented reality (AR) device, virtual reality (VR) device, Moving Picture Experts Group Audio Layer III (MP3) player, Moving Picture Experts Group Audio Layer IV (MP4) player, smart TV, in-vehicle terminal, wearable device, etc., and this application embodiment does not limit it in this way.

[0037] The aforementioned server includes at least one of a single server, multiple servers, a cloud computing platform, and a virtualization center. The server provides functional services for implementing model training. Optionally, the server undertakes the primary computational work, and the terminal undertakes secondary computational work; or, the server undertakes secondary computational work, and the terminal undertakes primary computational work; or, the server and terminal collaborate on computation using a distributed computing architecture. The server can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. In some embodiments, the aforementioned server can also be implemented as a node in a blockchain system.

[0038] Cloud technology refers to a managed technology that unifies a series of resources such as hardware, software, and networks within a wide area network or local area network to achieve data computing, storage, processing, and sharing.

[0039] The terminal connects to the server via a wireless network or a wired network. Those skilled in the art will understand that the number of computer devices 120 can be more or less. For example, there may be only one computer device 120, or there may be dozens, hundreds, or more computer devices 120. This application does not limit the number or type of computer devices 120.

[0040] Please refer to Figure 2This document illustrates a flowchart of a method for determining a chip clock frequency according to an exemplary embodiment of this application. This method can be executed by a computer device; for example, it can be executed by a terminal, a server, or a combination of both. Figure 2 As shown, the method includes at least one of the following steps.

[0041] Step 210: Determine the chip's operating mode.

[0042] The chip operating mode is used to indicate the power distribution method between the first chip and the second chip. The total power of the heterogeneous computing system is a pre-set power budget for the heterogeneous computing system, which is the sum of the target power of each processor in the heterogeneous computing system; for example, the total power can be set to 15W.

[0043] In the tasks to be executed in the heterogeneous computing system, there is a dependency between the first task executed by the first chip and the second task executed by the second chip; correspondingly, the first power corresponding to the first chip executing the first task and the second power corresponding to the second chip executing the second task are obtained based on the total power allocation of the heterogeneous computing system.

[0044] The tasks to be executed in a heterogeneous computing system correspond to the application scenarios of that system. The task data for these tasks includes, but is not limited to, data frames and task packages awaiting processing. Illustratively, the application scenarios of a heterogeneous computing system include, but are not limited to: 1. Artificial intelligence scenarios, such as model training, including processor clusters accelerating large-scale matrix multiplication and addition operations; or model inference, including tasks such as image classification or speech recognition performed on the terminal side using neural network models. 2. Multimedia processing scenarios, such as real-time rendering of 3D graphics pipelines; or video encoding and decoding, including streaming media playback and video conferencing. 3. Scientific computing or engineering simulation scenarios, such as using processors for massively parallel processing to accelerate computationally intensive tasks such as fluid mechanics and genome sequence alignment. 4. Autonomous driving scenarios, such as: Image Signal Processors (ISPs) processing raw data collected by cameras, NPUs running object detection, GPUs for bird's-eye view rendering, and CPUs executing decision planning to achieve perception fusion; or radar and / or LiDAR processing accelerating point cloud data. 5. Cloud computing scenarios, such as cloud gaming and database acceleration. 6. Network communication scenarios, such as baseband processors performing channel coding and decoding.

[0045] The chip's operating mode corresponds to the tasks to be executed in the heterogeneous computing system. Illustratively, when the first chip's operating mode is performance-priority, the tasks to be executed might be high-throughput, computationally intensive tasks such as streaming media playback and game rendering; when the second chip's operating mode is energy-saving-priority, the tasks to be executed might be low-latency tasks such as background email synchronization and music playback; when the third chip's operating mode is low-latency, the tasks to be executed might be low-data-interaction, latency-sensitive tasks such as touch input; and when the fourth chip's operating mode is bursty performance mode, the tasks to be executed might be highly bursty, latency-sensitive, and complex tasks such as interface rendering in response to user interactions, mobile phone photography, and data transmission via network communication.

[0046] Different chip operating modes correspond to preset clock frequency adjustment strategies; each mode has independent optimization objectives, constraints, and algorithm strategies, supporting dynamic switching between heterogeneous computing systems during runtime. In some embodiments, the chip operating mode is determined by the user. In response to receiving a mode setting request triggered by the user, the target chip operating mode is determined. The user can select the chip operating mode according to the needs and preferences of the application scenario, expanding the frequency determination method, increasing the scope of application scenarios, and improving the flexibility of frequency adjustment. For example, a low-latency mode can be selected in application scenarios with high real-time requirements; a power-saving priority mode can be selected when the battery power is low; and a burst performance mode can be selected when short-term high loads are required. Alternatively, the chip operating mode can be determined automatically based on at least one of the following: the type of task to be executed, the application scenario, or the current hardware state, according to a complete set of pre-set mode switching rules.

[0047] Different chip operating modes include preset mode parameters, which include, but are not limited to: 1. Pre-set fixed static parameters, including but not limited to: 1.1 Fixed parameters indicating system performance; 1.2 Constraints indicating clock frequency adjustment strategies, such as upper and lower limits of target power, total power budget, etc. 2. User-set dynamic parameters, such as the operating mode identifier that uniquely identifies the chip operating mode in the mode setting request; optionally, the constraints corresponding to the chip operating mode can be executed by the user, such as threshold parameters or range parameters for indicator data, used to indicate that frequency adjustment is performed when the indicator data meets the conditions corresponding to the parameters. 3. Dynamic parameters determined according to the operating state of the heterogeneous computing system, such as power adjustment parameters, etc.

[0048] Black-box management solutions exclude users from decision-making. Users cannot adjust system behavior according to application needs, nor can they know the current state of the heterogeneous computing system or whether optimization decisions can meet diverse performance requirements. For example, a game application prioritizes performance, a video conferencing application prioritizes low latency, and a background task prioritizes energy saving. Heterogeneous computing systems achieve chip operating mode switching and determination through multiple mode setting methods, including but not limited to at least one of the following: Application Programming Interface (API), system configuration files, and command-line tools. This exposes power management behavior to user control. Users can set chip operating modes through API calls, editing configuration files, or using command-line tools, thereby dynamically switching chip operating modes during heterogeneous system operation. The chip operating mode switching process is implemented by verifying the legality of the conversion (e.g., verifying permissions) and security (e.g., verifying whether the indicator data meets security conditions) before performing the switch smoothly and without interruption, avoiding impact on running tasks and providing users with flexible and controllable customization capabilities for the behavior of heterogeneous computing systems. Optionally, users can selectively set mode parameters.

[0049] Step 220: Determine the corresponding indicator data for the first chip and the second chip.

[0050] The indicator data is used to indicate the degree of power balance between the first chip and the second chip. In some embodiments, the indicator data includes at least one function such as indicating the degree of power balance, judging the hardware safety status, and performing fault diagnosis and root cause analysis; illustratively, by acquiring the indicator data, the key state trajectory of the heterogeneous computing system during operation can be saved before the anomaly occurs, which facilitates the subsequent location of design defects or abnormal events.

[0051] The indicator data is used to dynamically determine the chip's frequency adjustment strategy. Specifically, based on the indicator data, a power adjustment strategy is dynamically determined to determine the target power, thereby determining the chip clock frequency based on the determined target power. By indicating the operating states of the first and second chips respectively through the indicator data, the heterogeneous computing system has adaptive capabilities, which can automatically adapt to different task types, load changes, and hardware configurations, thereby improving the efficiency and accuracy of chip clock frequency determination.

[0052] In some embodiments, when the heterogeneous computing system starts up, the system's power management framework is initialized, and a continuously running control loop is initiated to determine the clock frequency of each chip in the system. Initializing the system's power management framework includes, but is not limited to: initializing the hardware corresponding to the first and second chips; establishing hardware connections and driver interfaces; setting initial power budgets, initial power allocation, determining clock frequencies based on initial power, and initial chip operating modes; creating user-mode setting interfaces (at least one of API, configuration files, and command-line tools); and initiating a real-time system status monitoring unit to acquire indicator data.

[0053] In some embodiments, determining the chip operating mode includes receiving a mode setting request and extracting the chip operating mode from the mode setting request.

[0054] In some embodiments, if no mode setting request is received, cycle information is determined, which indicates the current cycle in the process of determining the chip clock frequency; the chip operating mode is determined based on the cycle information.

[0055] In some embodiments, if the round information indicates that the current cycle is in the first cycle of the chip clock frequency determination process, the chip operating mode is determined based on the default mode information; if the round information indicates that the current cycle is not in the first cycle of the chip clock frequency determination process, the chip operating mode is determined based on the chip operating mode of the previous cycle.

[0056] Schematic illustration: Upon receiving a mode setting request from a user, the validity of the user parameters in the request is verified. If the parameters are invalid, an error message is returned, and the default mode information is used instead of the mode setting request. If no user mode setting request is received, the default behavior for when no user setting is received is executed. Specifically, if the round information indicates that the current process for determining the chip clock frequency is the first round (including but not limited to the system's first startup adjustment process or before system initialization), the chip operating mode and its parameters are determined based on the default mode information; otherwise, the current mode is maintained, i.e., the chip operating mode from the previous round is used as the chip operating mode.

[0057] By expanding the method of determining the chip's operating mode, a continuously running control loop is constructed during the chip clock frequency determination process. This loop periodically collects system status, determines the chip's operating mode, executes optimization strategies, records results, and returns to the start of the loop. It also supports receiving user mode setting requests at any time. Power management and frequency management are changed from one-time or trigger-based to a continuously running optimized closed loop, achieving adaptive control. The control loop runs uninterrupted, responding in real time to load changes in heterogeneous computing systems. This improves the adaptability of the chip clock frequency determination process to different application scenarios, thereby increasing the accuracy of clock frequency determination.

[0058] Different application scenarios have significantly different performance requirements for heterogeneous computing systems. To illustrate, smart cameras need to maximize frame rate to capture details, AR glasses need to minimize latency to ensure a real-time experience, mobile devices need to minimize power consumption to extend battery life, and high-performance computing needs to maximize computing power within power constraints. A single chip operating mode cannot simultaneously meet these diverse needs. A multi-mode framework enables heterogeneous computing systems to adapt to various application scenarios. Users or applications can select the most suitable chip operating mode according to actual needs, thereby dynamically adjusting the clock frequency under the target chip operating mode. This improves the scenario adaptability of chip frequency adjustment strategies, enhancing the practicality and user experience of heterogeneous computing systems.

[0059] Step 230: Based on the chip operating mode and indicator data, determine the first clock frequency to be adjusted for the first chip and the second clock frequency to be adjusted for the second chip.

[0060] In some embodiments, a first target power corresponding to a first chip and a second target power corresponding to a second chip are determined based on the chip's operating mode and indicator data; a first clock frequency is determined based on the first target power, and a second clock frequency is determined based on the second target power.

[0061] In some embodiments, the bottleneck identification and analysis unit determines the processor currently experiencing a performance bottleneck in the heterogeneous computing system; and the power budget dynamic balancing algorithm unit dynamically adjusts the power budgets of the first chip and the second chip based on the bottleneck analysis results and the chip's operating mode.

[0062] By determining the target power in the target chip's operating mode, and thus determining the clock frequency, the power budget allocation is dynamically adjusted to avoid performance waste caused by differences in chip processing speeds. This achieves an adaptive balancing strategy, improves the data processing efficiency of heterogeneous computing systems, fully leverages the hardware performance potential under the same total power budget, and improves power consumption utilization. Illustratively, for battery-powered mobile devices and embedded systems, the clock frequency determination method of this application can extend device battery life, improve user experience, reduce unnecessary energy consumption, lower the average heat generation of the device, and provide a foundation for thermal management.

[0063] In some embodiments, the method for determining the clock frequency based on dynamically determined target power is highly versatile and adaptable to various hardware configurations, different processor combinations, and application scenarios, thereby improving the hardware compatibility of the chip clock frequency determination method. Indicatively, heterogeneous computing systems can adapt to various power budget ranges, including but not limited to low-power embedded devices and high-performance workstations, and support different application scenarios, including but not limited to small mobile devices (such as smart cameras and augmented reality glasses), real-time computing terminals (such as autonomous driving systems), and large computing platforms (such as edge computing servers); thus improving the portability and scalability of the chip clock frequency determination method.

[0064] The first clock frequency is the target frequency that the first chip needs to be adjusted to achieve, and the second clock frequency is the target frequency that the second chip needs to be adjusted to achieve.

[0065] The heterogeneous computing system has tasks to be executed, including a first task and a second task. The system controls a first chip to execute the first task at a first clock frequency and controls a second chip to execute the second task at a second clock frequency. The specific implementation process of controlling the first chip to execute the first task and controlling the second chip to execute the second task based on a first target power and a second target power includes, but is not limited to, at least one of the following; wherein the target power includes at least one of the first target power and the second target power.

[0066] 1. Output the target power to the system scheduling module. The system scheduling module is a kernel program in the operating system used to adjust the clock frequency, controlling the chip hardware to adjust the clock frequency. Schematic, the system scheduling module can be implemented as a Dynamic Voltage and Frequency Scaling (DVFS) controller.

[0067] 2. The system scheduling module adjusts the voltage based on the target power to regulate the chip's clock frequency. Indicatively, increasing the voltage speed increases the transistor switching speed on the first chip, thus increasing the clock frequency; decreasing the voltage slows down the transistor switching speed, correspondingly decreasing the clock frequency.

[0068] 3. The system scheduling module determines the clock frequency of the chip corresponding to the target power, thereby changing the frequency of the clock signal and controlling the processing unit executing the task to be executed through the clock signal. Illustratively, the system scheduling module sends a command to the phase-locked loop (PLL) circuit to adjust the clock frequency. The PLL circuit generates a stable and adjustable clock signal. Upon receiving the command from the system scheduling module, the PLL distributes the corresponding clock signal at the clock frequency corresponding to the target power to the processing unit on the chip for executing the task.

[0069] In some embodiments, the fast response execution unit utilizes DVFS technology to rapidly adjust the first clock frequency of the first chip based on a first target frequency, and rapidly adjusts the second clock frequency of the second chip based on a second target frequency.

[0070] Optionally, the above-described heterogeneous computing system including the first chip and the second chip is merely an illustrative example, and this application does not limit the number or type of chips whose clock frequency needs to be determined. Taking a heterogeneous computing system including at least two chips as an example, the chip operating mode determined in step 210 is used to indicate the power distribution method between the at least two chips; step 220 can be implemented by determining the index data corresponding to the at least two chips respectively; the index data is used to indicate the degree of power balance between the at least two chips; step 230 can be implemented by determining the target power corresponding to the at least two chips respectively based on the chip operating mode and index data, and determining the clock frequency of each chip based on the target power corresponding to each chip.

[0071] The target power is determined in the target chip's operating mode, and the chip clock frequency is determined based on the target power. After frequency adjustment is completed, the heterogeneous computing system is allowed to stabilize, for example, after 100-200 milliseconds, before the next round of frequency adjustment is executed. In some embodiments, the process data of the current round of frequency adjustment is recorded and saved to the storage space corresponding to the historical records. The process data of frequency adjustment includes, but is not limited to, the current chip operating mode; the first power and the first target power, the second power and the second target power before and after frequency adjustment; the index data before and after frequency adjustment, such as the first frame rate of the first chip and the second frame rate of the second chip; and the timestamp of the completion of frequency adjustment. Optionally, before executing the next round of frequency adjustment, temporary data is cleared, and the frequency adjustment process is checked for any abnormal information and whether the status needs to be reported.

[0072] In summary, this method establishes a connection between the determination of chip clock frequencies in a heterogeneous system and the working scenario and user requirements by determining the chip operating mode corresponding to the heterogeneous system. Based on the indicator data corresponding to the first chip and the second chip, it determines the first clock frequency for the first chip to perform tasks and the second clock frequency for the second chip to perform tasks, as indicated by the chip operating mode. In particular, the method acquires indicator data in real time to indicate the balance between the processing efficiency of the first and second chips and dynamically adjusts the target clock frequency during the operation of the first and second chips. This improves the applicability of the clock frequency determination method in different chip application scenarios, thereby improving the efficiency of clock frequency determination during chip operation.

[0073] In some embodiments, a first target power corresponding to a first chip and a second target power corresponding to a second chip are determined based on the chip's operating mode and indicator data; a first clock frequency is determined based on the first target power, and a second clock frequency is determined based on the second target power.

[0074] Please refer to Figure 3 This illustrates a flowchart of a method for determining a chip clock frequency according to another exemplary embodiment of this application. This method can be executed by a computer device; for example, it can be executed by a terminal, a server, or a combination of both. Figure 3 As shown, the above method includes at least one of the following steps 310 to 330.

[0075] Schematic, step 230 includes steps 310 to 330; and determining a first clock frequency based on a first target power and determining a second clock frequency based on a second target power.

[0076] Step 310: Determine the constraints corresponding to the chip's operating mode.

[0077] The constraints are implemented as mode parameters for the chip's operating mode, indicating the decision-making method for adjusting the target power of the chip under that operating mode. The constraints, based on the performance data, are set as thresholds for the bottleneck identification and analysis unit to automatically trigger power adjustment processing, thereby converting the operating state of the heterogeneous computing system indicated by the performance data into explicit frequency adjustment signals and strategies.

[0078] The constraints include, but are not limited to, at least one of the following: indicator data, first target power, second power, and process indication data. The process indication data describes the process of adjusting the clock frequency based on the target power. The indicator data includes indicator data at various moments during the adjustment of chip power and / or clock frequency in chip operating mode, as well as indicator data before the start of chip power and / or clock frequency adjustment. Illustratively, the process indication data includes, but is not limited to, the duration of chip power and / or clock frequency adjustment in chip operating mode, data transmission delay between the first chip and the second chip, etc.; this application does not limit this.

[0079] In some embodiments, determining the indicator data corresponding to the first chip and the second chip includes at least one of the following.

[0080] 1. Determine the frame rate difference between the first chip and the second chip. The frame rate difference is used to indicate the difference in data processing efficiency between the first chip and the second chip.

[0081] 2. Obtain the first power of the first chip under its current operating state, and obtain the second power of the second chip under its current operating state.

[0082] 3. Determine the temperatures corresponding to the current operating states of the first and second chips.

[0083] 4. Determine the clock frequencies corresponding to the current operating states of the first and second chips.

[0084] 5. Determine the queue depth of the first chip and the second chip in their current operating state. The queue depth is used to indicate the number of data units to be processed by the second chip that the first chip is transmitting to the second chip, or the queue depth is used to indicate the number of data units to be processed by the first chip that the second chip is transmitting to the first chip.

[0085] The first target power is the power to be achieved by the first chip to be adjusted, and the first power is the current operating power of the first chip; the second target power is the power to be achieved by the second chip to be adjusted, and the second power is the current operating power of the second chip. The first power and the second power can be acquired in real time.

[0086] By acquiring multi-dimensional index data through the real-time system status detection unit, the working status of the heterogeneous computing system can be determined in real time from different perspectives, improving the accuracy of quantifying the working status of the first chip and the second chip. In response to different chip working modes, the clock frequency decision process is set to a multi-constraint response based on multiple indicators, thereby improving the accuracy of determining the chip's clock frequency.

[0087] In some embodiments, the number of first data frames processed by the first chip within a preset sampling period is determined, and the number of second data frames processed by the second chip within the sampling period is determined; a first frame rate of the first chip is determined based on the number of first data frames, and a second frame rate of the second chip is determined based on the number of second data frames; and a frame rate difference is determined based on the first frame rate and the second frame rate.

[0088] By directly counting the number of data frames processed per unit time, interference from heterogeneous computing systems during the output of calculation results is avoided. This directly reflects the working status of the first and second chips respectively, improving the efficiency of determining the frame rate and the accuracy of using the frame rate as an indicator for chip frequency adjustment. This, in turn, improves the accuracy and efficiency of clock frequency determination and the processing efficiency of tasks to be executed.

[0089] Specifically, a first data frame count is collected using a first frame counter set on the first chip. The first data frame count is the number of data frames processed by the first chip within the sampling period. A second data frame count is collected using a second frame counter set on the second chip. The second data frame count is the number of data frames processed by the second chip within the sampling period. Schematic, a first frame counter is set at the output of the first chip to record the number of processed frames N1 (N1 is a positive integer) within a time interval Δt, where Δt is the sampling period. A second frame counter is set at the output of the second chip to record the number of processed frames N2 (N2 is a positive integer) within a time interval Δt. For example, the value of Δt ranges from 100 to 500 milliseconds.

[0090] Accordingly, the frame rate corresponding to the sampling period is obtained based on the number of data frames of the chip; illustratively, taking the first chip as a VPU and the second chip as a GPU as an example, the first frame rate FPS_vpu_instant = N_vpu / Δt, the second frame rate FPS_gpu_instant = N_gpu / Δt, and the system frame rate of the heterogeneous computing system FPS_system = min(FPS_vpu, FPS_gpu), where N_vpu is the number of the first data frames, N_gpu is the number of the second data frames, and Δt is the sampling period.

[0091] In some embodiments, given a fixed frame rate for the chip, a moving average algorithm is used to smooth the frame rate to avoid instantaneous fluctuations. Illustratively, the moving average algorithm includes, but is not limited to, a first-order exponential moving average, i.e., the current estimated value... From the current instantaneous value The weighted average of the weight α and the previous time-series estimate (weight 1-α) is used to obtain the smoothing effect. A larger α results in a faster response but poorer smoothness. Taking the first chip as a VPU and the second chip as a GPU as an example, processing the instantaneous frame rate includes, but is not limited to, the first frame rate FPS_vpu_avg(k) = α × FPS_vpu_instant(k) + (1-α) × FPS_vpu_avg(k-1), and the second frame rate FPS_gpu_avg(k) = α × FPS_gpu_instant(k) + (1-α) × FPS_gpu_avg(k-1), where α is a preset smoothing coefficient, and k is the index of the sampling point in the time series. That is, the first instantaneous frame rate FPS_vpu_instant(k) or the second instantaneous frame rate FPS_gpu_instant(k) is obtained in the k-th sampling period.

[0092] Step 320: Determine the power adjustment parameters corresponding to the chip's operating mode based on the constraints and index data.

[0093] The power adjustment parameters indicate the method of power adjustment for at least one of the first chip and the second chip. The power adjustment parameters are determined based on the chip operating mode parameters and performance data, and are used to indicate the method of power adjustment for the first chip and the second chip. The chip operating mode parameters include, but are not limited to, constraints.

[0094] In some embodiments, the power adjustment parameters include, but are not limited to, at least one of the following parameters: power adjustment amount, power adjustment coefficient, and flag information indicating a power adjustment strategy; wherein, the power adjustment coefficient is used to indicate the chip object whose power is to be adjusted and whether the power of the chip object should be increased or decreased. This application does not limit the implementation method of the power adjustment parameters.

[0095] Step 330: Determine the first target power and the second target power based on the power adjustment parameters, the first power of the first chip under the current operating state, and the second power of the second chip under the current operating state.

[0096] Based on the power adjustment strategy indicated by the power adjustment parameters, the first power and / or the second power are adjusted; wherein, the first power and the first target power can be the same, and the first power is kept as the first target power, in which case the power adjustment parameters may not be applied to the first power; the second power and the second target power can be the same, and the second power is kept as the second target power, in which case the power adjustment parameters may not be applied to the second power.

[0097] In some embodiments, the chip operating mode includes a first chip operating mode, the first constraint condition corresponding to the first chip operating mode includes a constraint on the total power of the first target power and the second target power, and the index data includes the frame rate difference between the first chip and the second chip; the power adjustment parameters corresponding to the first chip operating mode are determined based on the frame rate difference and the total power.

[0098] The total power is the upper limit of the sum of the power of the first chip and the second chip at any time under any operating state, such as the upper limit of the sum of the first power and the second power, or the upper limit of the sum of the first target power and the second target power.

[0099] In some embodiments, when the frame rate difference indicates that the first frame rate of the first chip is less than the second frame rate of the second chip, and the absolute value of the frame rate difference is greater than a preset frame rate balancing threshold, the first power is increased to a first target power and the second power is decreased to a second target power based on power adjustment parameters, and the frame rate balancing threshold is used to indicate the upper limit of the absolute value of the frame rate difference; when the frame rate difference indicates that the first frame rate of the first chip is greater than the second frame rate of the second chip, and the absolute value of the frame rate difference is greater than the frame rate balancing threshold, the second power is increased to a second target power and the first power is decreased to a first target power based on power adjustment parameters.

[0100] If the frame rate difference indicates that the first frame rate of the first chip is equal to the second frame rate of the second chip, and / or the absolute value of the frame rate difference is less than or equal to a preset frame rate balance threshold, the first power and the second power are not adjusted, and the first power is kept as the first target power and the second power is kept as the second target power.

[0101] The power adjustment parameters also include flag information indicating the power adjustment strategy, such as a first flag indicating an increase in first power and a second flag indicating an increase in second power.

[0102] Schematic, when the frame rate difference indicates that the first frame rate of the first chip is less than the second frame rate of the second chip, and the absolute value of the frame rate difference is greater than a preset frame rate balancing threshold, a first flag is determined. The first flag is used to indicate triggering a power adjustment based on the operating mode of the first chip to increase the first power to a first target power. When the frame rate difference indicates that the first frame rate of the first chip is greater than the second frame rate of the second chip, and the absolute value of the frame rate difference is greater than the frame rate balancing threshold, a second flag is determined. The second flag is used to indicate triggering a power adjustment based on the operating mode of the first chip to increase the second power to a second target power.

[0103] In the first chip's operating mode, the target power of the chip is adjusted. Using the frame rate difference between the first and second chips as a feedback signal, the power budget allocation among different processors is dynamically adjusted to make their respective data processing efficiencies similar, thereby maximizing the overall performance of the serial pipeline in the heterogeneous computing system. The frame rate difference is used as the control variable for closed-loop feedback control, avoiding the limitations of traditional static power allocation. This eliminates the performance waste caused by inconsistent data processing speeds among processors in the serial pipeline and avoids the need for pre-built complex models to improve clock frequency determination efficiency, thus improving hardware utilization and the overall performance of the heterogeneous computing system. Optionally, the first chip's operating mode can be implemented as a performance-priority mode.

[0104] The system status real-time detection unit of the heterogeneous computing system determines the frame rate difference in real time; illustratively, taking the first chip as a VPU and the second chip as a GPU as an example, the frame rate difference ΔFPS = FPS_vpu - FPS_gpu, where FPS_vpu is the first frame rate and FPS_gpu is the second frame rate.

[0105] In some embodiments, a performance bottleneck is determined by setting a frame rate balancing threshold, i.e., determining whether chip power needs adjustment. The frame rate balancing threshold includes a first frame rate balancing threshold and a second frame rate balancing threshold, which can be opposites or unrelated. Illustratively, if the absolute value of the frame rate difference |ΔFPS| ≤ ΔFPS_threshold, the heterogeneous computing system is determined to be in a balanced state, where ΔFPS_threshold is the first frame rate balancing threshold; if ΔFPS > ΔFPS_threshold, the GPU is determined to be the performance bottleneck, i.e., the GPU processing speed is slow, and a second flag is determined; if ΔFPS < -ΔFPS_threshold, the VPU is determined to be the bottleneck, i.e., the VPU processing speed is slow, and a first flag is determined, where -ΔFPS_threshold is the second frame rate balancing threshold.

[0106] In some embodiments, the power adjustment direction is determined based on the result of the performance bottleneck assessment; specifically, the power adjustment amount and direction are determined based on the sign and magnitude of the frame rate difference. Illustratively, when the first chip is the performance bottleneck, the first power of the first chip is increased, and the second power of the second chip is decreased; when the second chip is the performance bottleneck, the first power of the first chip is decreased, and the second power of the second chip is increased; when the heterogeneous computing system is in a balanced state, the current power allocation is maintained.

[0107] The power adjustment amount corresponding to the first chip's operating mode is calculated based on the frame rate difference. The power adjustment amount is directly proportional to the frame rate difference, and the proportionality coefficient is determined by the second power adjustment coefficient and the ratio between the total power of the first chip and the second chip and the average frame rate. The second power adjustment coefficient is a pre-configured mode parameter used to indicate the calculation method for the power adjustment amount corresponding to the first chip's mode. Schematic, the power adjustment amount ΔP = K × |ΔFPS| × P_total / FPS_avg, where ΔFPS is the frame rate difference, K is the second power adjustment coefficient, P_total is the total power of the heterogeneous computing system, and FPS_avg is the average frame rate of the heterogeneous computing system.

[0108] In some embodiments, when the power adjustment amount is determined, a boundary check is performed on the power adjustment amount. The boundary check is used to limit the power adjustment range, that is, to set an upper limit and a lower limit for the power adjustment amount; illustratively, taking the lower limit (ΔP_min) of the power adjustment amount as 0.2W and the upper limit (ΔP_max) of the power adjustment amount as 1W as an example, ΔP = max(ΔP_min, min(ΔP, ΔP_max)) = max(0.2W, min(ΔP, 1W)); optionally, the mode parameters of the first chip operating mode include the upper limit and the lower limit of the power adjustment amount.

[0109] In some embodiments, a first target power is obtained by increasing the first power in response to a first flag, i.e., increasing the first power based on a power adjustment amount when the first chip is a performance bottleneck. Schematic example: taking the first chip as a VPU and the second chip as a GPU, the first target power P_vpu_new = P_vpu_current + ΔP, and the second target power P_gpu_new = P_gpu_current – ​​ΔP, where P_vpu_current is the first power, P_gpu_current is the second power, and ΔP is the power adjustment amount. Similarly, a second target power is obtained by increasing the second power based on a second flag in response to a second flag, i.e., increasing the second power based on a power adjustment amount when the second chip is a performance bottleneck. Schematic example: taking the first chip as a VPU and the second chip as a GPU, the first target power P_vpu_new = P_vpu_current - ΔP, and the second target power P_gpu_new = P_gpu_current + ΔP, where P_vpu_current is the first power, P_gpu_current is the second power, and ΔP is the power adjustment amount.

[0110] In some embodiments, boundary checks are performed on the first target power and the second target power after adjusting the target power. Illustratively, taking a first chip implemented as a VPU and a second chip implemented as a GPU as an example, the boundary checks include, but are not limited to, P_vpu_min ≤ P_vpu_new ≤ P_vpu_max, P_gpu_min ≤ P_gpu_new ≤ P_gpu_max, P_vpu_new + P_gpu_new ≤ P_total_budget, where P_vpu_new is the first target power, P_gpu_new is the second target power, P_vpu_min and P_vpu_max indicate the upper and lower limits of the first power, respectively, P_gpu_min and P_gpu_max indicate the upper and lower limits of the second power, respectively, and P_total_budget is the total power budget.

[0111] For illustrative purposes, please refer to the following: Figure 4 This illustrates a flowchart of determining the clock frequency in a first chip operating mode according to an exemplary embodiment of this application. Figure 4 As shown, in the first chip operating mode 410, a frame rate difference 420 is obtained, and a bottleneck judgment is performed using a frame rate balancing threshold 430 to obtain at least one of a first flag 431 and a second flag 432. For example, if the frame rate difference 420 indicates that the first frame rate is less than the second frame rate, and the absolute value of the frame rate difference 420 is greater than the preset frame rate balancing threshold 430, the first flag 431 is obtained; if the frame rate difference 420 indicates that the first frame rate is greater than the second frame rate, and the absolute value of the frame rate difference 420 is greater than the frame rate balancing threshold 430, the second flag 432 is obtained.

[0112] like Figure 4 As shown, a power adjustment amount 440 is obtained based on a preset second power adjustment coefficient, a frame rate difference 420, the average frame rate between the first chip and the second chip, and the total power. The power adjustment amount 440 is directly proportional to the absolute value of the frame rate difference 420, and the proportionality coefficient is determined by the second power adjustment coefficient and the ratio of the total power to the average frame rate. A first target power 451 is obtained based on the power adjustment amount 440 and a first flag 431, and a second target power 452 is obtained based on the power adjustment amount 440 and the second flag 432. Optionally, when obtaining the first target power 451 and the second target power 452, a boundary check is performed on the first target power 451 and the second target power 452.

[0113] In some embodiments, the chip operating mode includes a second chip operating mode, and the second constraint condition corresponding to the second chip operating mode includes a constraint on the indicator data based on an indicator threshold; determining an indicator margin based on the indicator threshold and the indicator data; and determining the power adjustment parameter corresponding to the second chip operating mode based on the indicator margin.

[0114] In some embodiments, the indicator margin includes a first margin and a second margin. The first margin indicates the adjustment range of the first power, and the second margin indicates the adjustment range of the second power. Determining the power adjustment parameters corresponding to the second chip operating mode based on the indicator margin includes: when the first margin is higher than a preset first threshold, determining a first power reduction parameter, which indicates reducing the first power to a first target power based on the first margin; when the first margin is lower than a preset second threshold, determining a first power increase parameter, which indicates increasing the first power to a first target power based on the first margin; when the second margin is higher than a preset third threshold, determining a second power reduction parameter, which indicates reducing the second power to a second target power based on the second margin; and when the second margin is lower than a preset fourth threshold, determining a second power increase parameter, which indicates increasing the second power to a second target power based on the second margin.

[0115] The purpose of adjusting the target power of the chip in the second chip operating mode is to minimize the total power of the heterogeneous computing system while meeting basic performance requirements, thereby addressing battery-powered application scenarios, reducing system power consumption, and extending device lifespan. It expands the applicability of the chip clock frequency determination method, setting a margin to indicate the strategy for adjusting the chip clock frequency, improving the accuracy and efficiency of determination during chip operation. Optionally, the second chip operating mode can be implemented as an energy-saving priority mode.

[0116] In some embodiments, the indicator threshold corresponds to the operating mode of the second chip, and the indicator threshold is implemented as a mode parameter corresponding to the operating mode of the second chip. Taking the indicator data as the frame rate as an example, the indicator threshold is implemented as a frame rate threshold, which is used to indicate the lower limit of the data processing efficiency of the heterogeneous computing system corresponding to the first chip and the second chip; illustratively, the indicator data and its corresponding indicator threshold can also be implemented as at least one of the following: chip data throughput and its corresponding throughput threshold, energy efficiency ratio and its corresponding ratio threshold, etc., which are not limited in this embodiment.

[0117] The indicator margin is calculated based on the indicator threshold and indicator data. This margin indicates the range within which the power of the first and second chips can be adjusted respectively in the second chip's operating mode. Specifically, the first and second power are adjusted respectively, thereby adjusting the clock frequency of the first chip based on the first target power and the clock frequency of the second chip based on the second target power. Illustratively, taking the first chip implemented as a VPU and the second chip implemented as a GPU as an example, the first margin FPS_vpu_margin = FPS_vpu_current - FPS_min, and the second margin FPS_gpu_margin = FPS_gpu_current - FPS_min, where FPS_vpu_current is the first frame rate of the first chip, FPS_gpu_margin is the second frame rate of the second chip, and FPS_min is the frame rate threshold.

[0118] The performance judgment process involves determining the power adjustment parameters corresponding to the operating mode of the second chip based on the indicator margin: For both the first and second chips, the relationship between the first and second margins and preset performance margin thresholds is assessed to determine whether the first and / or second chip is in a state of performance surplus or underperformance. This determines the indicator parameters instructing the target power adjustment and clarifies the frequency adjustment strategy of the heterogeneous computing system. The performance margin thresholds include, but are not limited to, at least one of a first threshold, a second threshold, a third threshold, and a fourth threshold; the indicator parameters include at least one of a first power reduction parameter, a first power increase parameter, a second power reduction parameter, and a second power increase parameter.

[0119] To illustrate, taking the first chip as a VPU as an example, when the first margin (FPS_vpu_margin) reaches the first threshold, a first power reduction parameter is determined, for example, if FPS_vpu_margin>5: vpu_need_reduce =true, where the first threshold is 5, and the flag bit vpu_need_reduce = true corresponding to the first power reduction parameter indicates that the VPU performance has surplus and power can be reduced; when the first margin is lower than the second threshold, a first power increase parameter is determined, for example, else if FPS_vpu_margin<0: vpu_need_increase = true, where the second threshold is 0, and the flag bit vpu_need_increase = true corresponding to the first power increase parameter indicates that the VPU performance is lower than the minimum requirement.

[0120] Independent of the judgment process of the first chip, taking the second chip implemented as a GPU as an example, when the second margin (FPS_gpu_margin) reaches the third threshold, the second power reduction parameter is determined, for example, if FPS_gpu_margin>5:gpu_need_reduce = true, where the third threshold is 5, and the flag bit gpu_need_reduce = true corresponding to the second power reduction parameter indicates that the GPU performance has surplus and power can be reduced; when the second margin is lower than the fourth threshold, the second power increase parameter is determined, for example, else if FPS_gpu_margin<0: gpu_need_increase = true, where the fourth threshold is 0, and the flag bit gpu_need_increase = true corresponding to the second power increase parameter indicates that the GPU performance is lower than the minimum requirement.

[0121] It is worth noting that the aforementioned performance margin threshold values ​​are merely illustrative examples, and this application does not limit them. The first threshold, second threshold, third threshold, and fourth threshold can be the same or different. In the absence of at least one indicator parameter, it is indicated that the performance of the first chip and the second chip does not require adjustment, and the heterogeneous computing system maintains its current state to perform tasks.

[0122] The power adjustment amount is determined based on the indicator parameters and indicator margins, whereby the power adjustment parameters include the aforementioned indicator parameters, the power adjustment amount, and the preset power adjustment coefficients corresponding to each indicator parameter. By defining complete power adjustment rules, the frequency modulation processes of the first chip and the second chip are made independent, improving the efficiency of clock frequency determination. Independent power adjustment processing is performed for the first chip and the second chip respectively, including at least one of the following steps.

[0123] 1. Power Adjustment for the First Chip: 1.1 Given a first power reduction parameter, determine the corresponding power adjustment coefficient to determine the power adjustment amount for the first chip. Illustratively, taking a VPU implementation as an example, the power adjustment amount ΔP_vpu = FPS_vpu_margin × power adjustment coefficient × P_vpu_current / FPS_vpu_current, where FPS_vpu_margin is the first margin, P_vpu_current is the first power, and FPS_vpu_current is the first frame rate. Given the determined power adjustment amount for the first chip, perform boundary checks on the power adjustment amount. Boundary checks are used to limit the power adjustment amplitude, i.e., setting upper and lower limits for the power adjustment amount. To illustrate, taking a lower limit of 0.2W and an upper limit of 2.0W for power adjustment as an example, ΔP_vpu = max(0.2W, min(ΔP_vpu, 2.0W)); optionally, the mode parameters of the second chip's operating mode include the upper and lower limits of power adjustment corresponding to each index parameter.

[0124] Accordingly, when the first target power is determined based on the first power and the power adjustment amount, a boundary check is performed on the target power to avoid exceeding the frequency reduction limit. Illustratively, the first target power P_vpu_new = P_vpu_current - ΔP_vpu, and P_vpu_new = max(P_vpu_new, P_vpu_min), where P_vpu_min is the lower power limit of the first chip; optionally, the mode parameters of the second chip's operating mode include the lower power limits corresponding to the first and second chips, respectively.

[0125] 1.2 Given a first power increase parameter, determine the power adjustment coefficient corresponding to the first power increase parameter, thereby determining the power adjustment amount of the first chip; wherein, the power adjustment coefficient corresponding to the first power increase parameter is larger than the power adjustment coefficient corresponding to the first power decrease parameter, in order to ensure the performance of the first chip in processing data. Schematic, taking the first chip implemented as a VPU as an example, the power adjustment amount ΔP_vpu of the first chip is = -FPS_vpu_margin × power adjustment coefficient × P_vpu_current / FPS_vpu_current, where FPS_vpu_margin is the first margin, P_vpu_current is the first power, and FPS_vpu_current is the first frame rate; boundary checks are performed on the power adjustment amount, taking the lower limit of the power adjustment amount as 0.3W and the upper limit of the power adjustment amount as 2.0W as an example, ΔP_vpu = max(0.3W,min(ΔP_vpu, 2.0W)); the first target power P_vpu_new = P_vpu_current + ΔP_vpu, and P_vpu_new = max(P_vpu_new, P_vpu_max), where P_vpu_max is the power upper limit of the first chip; optionally, the mode parameters of the second chip's working mode include the power upper limits corresponding to the first chip and the second chip respectively.

[0126] 2. Power Adjustment for the Second Chip: 2.1 Given a determined second power reduction parameter, determine the corresponding power adjustment coefficient to determine the power adjustment amount for the second chip. Illustratively, taking a GPU implementation as an example, the power adjustment amount for the first chip is ΔP_gpu = FPS_gpu_margin × power adjustment coefficient × P_gpu_current / FPS_gpu_current, where FPS_gpu_margin is the second margin, P_gpu_current is the second power, and FPS_gpu_current is the second frame rate. Given the determined power adjustment amount for the second chip, perform boundary checks on the power adjustment amount. Boundary checks are used to limit the power adjustment range, i.e., setting upper and lower limits for the power adjustment amount. To illustrate, taking a lower limit of 0.2W and an upper limit of 2.0W for power adjustment as an example, ΔP_gpu = max(0.2W, min(ΔP_gpu, 2.0W)); optionally, the mode parameters of the second chip's operating mode include the upper and lower limits of power adjustment corresponding to each index parameter.

[0127] Accordingly, when determining the second target power based on the second power and the power adjustment amount, a boundary check is performed on the target power to avoid exceeding the frequency reduction limit. Illustratively, the second target power P_gpu_new = P_gpu_current - ΔP_gpu, and P_gpu_new = max(P_gpu_new, P_gpu_min), where P_gpu_min is the lower power limit of the second chip.

[0128] 2.2 Given the second power enhancement parameter, determine the power adjustment coefficient corresponding to the second power enhancement parameter, thereby determining the power adjustment amount of the second chip; wherein, the power adjustment coefficient corresponding to the second power enhancement parameter is larger than the power adjustment coefficient corresponding to the second power reduction parameter, in order to ensure the performance of the second chip in processing data. Schematic, taking the second chip implemented as a GPU as an example, the power adjustment amount of the second chip ΔP_gpu = -FPS_gpu_margin × power adjustment coefficient × P_gpu_current / FPS_gpu_current, where FPS_gpu_margin is the second margin, P_gpu_current is the second power, and FPS_gpu_current is the second frame rate; boundary checks are performed on the power adjustment amount, taking the lower limit of the power adjustment amount as 0.3W and the upper limit of the power adjustment amount as 2.0W as an example, ΔP_gpu = max(0.3W,min(ΔP_gpu, 2.0W)); the second target power P_gpu_new = P_gpu_current + ΔP_gpu, and P_gpu_new = max(P_gpu_new, P_gpu_max), where P_gpu_max is the upper limit of the power of the second chip.

[0129] 3. After adjusting the target power for the first chip and the second chip respectively, perform boundary verification on the total power of the heterogeneous computing system. Illustratively, taking the first chip as a VPU and the second chip as a GPU as an example, the total target power P_total_new = P_vpu_new + P_gpu_new, P_total_new = min(P_total_new, P_total_budget), where P_vpu_new is the first target power, P_gpu_new is the second target power, and P_total_budget is the total power budget, used to indicate the upper limit of the total power.

[0130] For illustrative purposes, please refer to the following: Figure 5 This illustrates a flowchart of determining the clock frequency in a second chip operating mode according to an exemplary embodiment of this application. Figure 5As shown, in the second chip operating mode 510, indicator data 520 is acquired, and performance is judged by the minimum indicator requirement 530 to determine at least one of the first margin 531 corresponding to the first chip and the second margin 532 corresponding to the second chip. For example, the minimum indicator requirement 530 is used to indicate the lower limit of the indicator data 520 corresponding to the first chip and the second chip respectively, and the minimum indicator requirement 530 is implemented as an indicator threshold. Illustratively, when the indicator threshold includes the first indicator threshold corresponding to the first chip and the second indicator threshold corresponding to the second chip, taking the indicator data as frame rate (including the first frame rate and the second frame rate) as an example, the first margin 531 is calculated by subtraction based on the first frame rate and the first indicator threshold, and the second margin 532 is calculated by subtraction based on the second frame rate and the second indicator threshold.

[0131] like Figure 5 As shown, based on the first margin 531, a first power reduction parameter 551 or a first power increase parameter 552 is determined by the first chip performance judgment 541; based on the second margin 532, a second power reduction parameter 553 or a second power increase parameter 554 is determined by the second chip performance judgment 542. The first chip performance judgment 541 includes, but is not limited to, determining the first power reduction parameter 551 when the first margin 531 reaches a preset first threshold, and determining the first power increase parameter 552 when the first margin 531 is lower than a preset second threshold; the second chip performance judgment 542 includes, but is not limited to, determining the second power reduction parameter 553 when the second margin 532 reaches a preset third threshold, and determining the second power increase parameter 554 when the second margin 532 is lower than a preset fourth threshold.

[0132] like Figure 5 As shown, a first target power 571 is determined based on a third power adjustment coefficient 561, a first margin 531, and a first power reduction parameter 551 or a first power increase parameter 552; a second target power 572 is determined based on a fourth power adjustment coefficient 562, a second margin 532, and a second power reduction parameter 553 or a second power increase parameter 554. The power adjustment amount corresponding to the first target power 571 is directly proportional to the first margin 531, and the proportionality coefficient is determined by the third power adjustment coefficient 561 and the ratio of the first power to the first frame rate; the power adjustment amount corresponding to the second target power 572 is directly proportional to the second margin 532, and the proportionality coefficient is determined by the fourth power adjustment coefficient 562 and the ratio of the second power to the second frame rate. Optionally, when the first target power 571 and the second target power 572 are determined, a boundary check is performed on the first target power 571 and the second target power 572.

[0133] In some embodiments, the chip operating mode includes a third chip operating mode, and the third constraint condition corresponding to the third chip operating mode includes a constraint on the queue depth between the first chip and the second chip based on a latency threshold; determining a target queue depth based on the latency threshold and indicator data; determining the queue depth difference based on the target queue depth and the queue depth of the first chip and the second chip in their current operating states; and determining the power adjustment parameter corresponding to the third chip operating mode based on the queue depth difference.

[0134] In some embodiments, when the queue depth difference reaches a preset first queue balance threshold, the second power is increased to a second target power based on the power adjustment parameters corresponding to the third chip's operating mode, and the first queue balance threshold is used to indicate the upper limit of the queue depth difference; when the queue depth difference is lower than or equal to a preset second queue balance threshold, the first power is increased to a first target power based on the power adjustment parameters corresponding to the third chip's operating mode, and the second queue balance threshold is used to indicate the lower limit of the queue depth difference.

[0135] The power adjustment parameters also include flags indicating the power adjustment strategy, such as a third flag indicating an increase in the second power and a fourth flag indicating an increase in the first power. Typically, the first queue balance threshold differs from the second queue balance threshold.

[0136] Schematic, when the queue depth difference reaches a preset first queue balance threshold, a third flag is determined, which is used to indicate the triggering of a power adjustment based on the third chip operating mode to increase the second power to the second target power; when the queue depth difference is lower than or equal to the preset second queue balance threshold, a fourth flag is determined, which is used to indicate the triggering of a power adjustment based on the third chip operating mode to increase the first power to the first target power.

[0137] The purpose of adjusting the target power of the chip in the third chip operating mode is to minimize the end-to-end latency within the heterogeneous computing system under the constraint of total power, that is, to minimize the data transmission and synchronization latency between the first chip and the second chip, so as to cope with the time-latency sensitive tasks corresponding to the heterogeneous computing system, such as the tasks to be executed for wearable devices with high real-time requirements.

[0138] This method uses queue depth as a metric and employs different strategies based on the cache queue status (including maintaining or gradually restoring balance when the queue is healthy, prioritizing acceleration of the second chip in the pipeline when the queue depth increases, adopting a more aggressive acceleration strategy for the second chip when the queue depth is large, and gradually restoring the balance between the first and second chips when the queue depth decreases). This expands the applicability of the chip clock frequency determination method, using queue depth to indicate the strategy for adjusting the chip clock frequency, thus improving the accuracy and efficiency of determination during chip operation. Optionally, the third chip's operating mode can be implemented as a low-latency mode.

[0139] In a heterogeneous computing system, taking the collaborative processing of task data corresponding to a task to be executed by the first chip and the second chip as an example, the second chip performs subsequent processing on the intermediate data produced by the first chip to complete the task to be processed. There is a difference between the data output rate of the first chip and the data consumption rate of the second chip. Therefore, a buffer queue is set in the memory of the heterogeneous computing system. The buffer queue is used to temporarily store data to achieve matching between hardware with different processing rates.

[0140] The queue depth is the number of data units of task data in the buffer queue. The task data in the buffer queue is the output of the first chip and the input of the second chip. In other words, the data units in the buffer queue are the data units that the first chip transmits to the second chip and that the second chip has not yet processed.

[0141] The greater the queue depth, the higher the stability of the heterogeneous computing system. In other words, in the event of instantaneous fluctuations, such as chip processing blockage, the impact on other chips is smaller, but the latency is correspondingly higher. If the queue depth is too small, it may cause downstream processing units (such as the second chip) to be idle or buffer queue data to overflow, resulting in lower processing stability and lower hardware resource utilization of the heterogeneous computing system.

[0142] Optionally, the task data in the buffer queue can also be the output of the second chip and the input of the first chip, determined by the data processing dependency between the first and second chips. Illustratively, taking the first chip as a VPU and the second chip as a GPU as an example, the data units in the buffer queue are those sent to the second chip after processing by the first chip, those awaiting processing by the second chip, and those that the second chip has not yet completed processing or has not yet processed.

[0143] Alternatively, end-to-end latency within the heterogeneous computing system can be minimized by keeping the queue depth low.

[0144] The latency threshold (Max_Latency) indicates the upper limit of data transmission and synchronization latency between the first chip and the second chip. Since the queue depth directly affects data transmission and synchronization between the first chip and the second chip, the target queue depth is determined based on the latency threshold. Optionally, the latency threshold corresponds to the operating mode of the third chip, and the latency threshold is implemented as a mode parameter corresponding to the operating mode of the third chip. The mode parameter corresponding to the operating mode of the third chip also includes at least one of the following.

[0145] 1. Single-frame processing time (Frame_Time): This indicates the average time required for a heterogeneous computing system to process a single data frame. It depends on hardware performance, algorithm complexity, the data size of the task to be executed, etc., and is essentially the total latency from input data to output data processing result in the heterogeneous computing system. This includes the latency of the first and second chips processing data respectively, as well as the data transmission latency between the first and second chips. The single-frame processing time can be obtained in real-time during chip operation from a set time and the total number of frames processed within that set time. Optionally, the aforementioned data frame is a data unit to be processed corresponding to the task to be executed; this application does not limit this.

[0146] 2. Fixed Pipeline Latency: This indicates the time consumed for deterministic data transmission and synchronization between the first and second chips due to pipelined operations. Illustratively, since the task cycles of the first and second chips are aligned, the fixed pipeline latency is implemented as a constant value.

[0147] 3. Threshold parameters or range parameters for indicator data are used to indicate the frequency adjustment to be performed when the indicator data meets the conditions corresponding to the parameters; schematically, the indicator data corresponding to the third chip working mode is implemented as the queue depth difference. The above threshold parameters include, but are not limited to, the first queue balance threshold and the second queue balance threshold, and the corresponding range parameters include, but are not limited to, the target range defined by the first queue balance threshold and the second queue balance threshold.

[0148] In some embodiments, the target queue depth (Target_Queue_Depth) is determined based on mode parameters such as single-frame processing time, fixed pipeline delay, and a delay threshold. Illustratively, delay = queue depth × single-frame processing time + fixed pipeline delay, i.e., target queue depth = (delay threshold - fixed pipeline delay) / single-frame processing time. Optionally, when the target queue depth is determined, the target queue depth is limited by a target threshold to ensure a reasonable target queue depth; the target threshold includes a first target threshold and a second target threshold, where the first target threshold indicates the upper limit of the target queue depth, and the second target threshold indicates the lower limit of the target queue depth; illustratively, taking a first target threshold of 10 and a second target threshold of 0 as an example, Target_Queue_Depth = max(0, min(Target_Queue_Depth, 10)).

[0149] Obtain the queue depth (Q_depth_current) corresponding to the first chip and the second chip, and calculate the queue depth difference (Q_margin) based on the target queue depth and the queue depth; schematically, the queue depth difference = queue depth - target queue depth, that is, Q_margin = Q_depth_current - Target_Queue_Depth.

[0150] In some embodiments, the frequency adjustment strategy is determined based on the queue depth difference, and there is consistency between the frequency adjustment strategy and the power adjustment strategy, such as increasing the first power indicator to increase the first clock frequency. Specifically, the first queue balance threshold and the second queue balance threshold are used as the basis for determining the frequency adjustment strategy, and the third and fourth flags are used as power adjustment parameters indicating different frequency adjustment strategies.

[0151] Schematic example, taking a first queue balance threshold of 1 and a second queue balance threshold of -2 as an example: when the queue depth is within the target range indicated by the first and second queue balance thresholds (i.e., Q_margin < 1 AND Q_margin > = -2), it means that the clock frequencies of both the first and second chips do not need to be adjusted. When the queue depth reaches the first queue balance threshold (i.e., Q_margin > = 1), a third flag is determined, indicating that the second chip has become a performance bottleneck and the data processing rate needs to be accelerated by increasing the clock frequency of the second chip. Schematic example, the third flag is implemented as reduce_queue to indicate that the queue depth is reduced by increasing the second power. When the queue depth is lower than or equal to the second queue balance threshold (i.e., Q_margin < = -2), a fourth flag is determined, indicating that the first chip has become a performance bottleneck and the data processing efficiency needs to be accelerated by increasing the clock frequency of the first chip. Schematic example, the fourth flag is implemented as restore_balance to indicate that the queue depth is increased to restore the performance balance between the first and second chips.

[0152] It is worth noting that the target range [-2,1] indicated by the first queue balance threshold and the second queue balance threshold mentioned above is only an illustrative example, and this application does not limit it.

[0153] The power adjustment amount corresponding to the third chip's operating mode is determined based on the queue depth. The power adjustment amount is directly proportional to the difference in queue depth. The proportionality coefficient is determined by the fifth power adjustment coefficient and the ratio between the total power and the average frame rate of the first and second chips. The fifth power adjustment coefficient is a pre-configured mode parameter used to indicate how the power adjustment amount corresponding to the third chip mode is calculated. Illustratively, the fifth power adjustment coefficient = 0.15, and the power adjustment amount ΔP = ΔQ × 0.15 × P_total / FPS_avg, where ΔQ = abs(Q_margin), P_total is the total power of the heterogeneous computing system, and FPS_avg is the average frame rate of the heterogeneous computing system.

[0154] In some embodiments, when the power adjustment amount is determined, a boundary check is performed on the power adjustment amount; illustratively, taking a lower limit of 0.3W and an upper limit of 2.5W as an example, ΔP = max(0.3W, min(ΔP, 2.5W)); optionally, the mode parameters of the third chip operating mode include the upper and lower limits of the power adjustment amount.

[0155] In some embodiments, determining a first target power based on power adjustment parameters and a first power corresponding to a first chip, and determining a second target power based on power adjustment parameters and a second power corresponding to a second chip, includes, but is not limited to, at least one of the following steps.

[0156] 1. In response to the third flag, a portion of the total power budget is transferred from allocation to the first chip to allocation to the second chip. That is, based on the power adjustment amount, the second target power is increased and the first target power is decreased, thereby improving the processing efficiency of the second chip and correspondingly reducing the processing efficiency of the first chip, realizing balanced management of processor processing efficiency in heterogeneous computing systems. Schematic, taking the first chip as a VPU and the second chip as a GPU as an example, the first target power P_vpu_new = P_vpu – ΔP, the second target power P_gpu_new = P_gpu + ΔP, where P_vpu is the first power, P_gpu is the second power, and ΔP is the power adjustment amount corresponding to the third chip's operating mode.

[0157] 2. In response to the fourth flag, a portion of the total power budget is transferred from allocation to the second chip to allocation to the first chip. That is, based on the power adjustment amount, the first target power is increased and the second target power is decreased, thereby improving the processing efficiency of the first chip and correspondingly reducing the processing efficiency of the second chip, realizing balanced management of processor processing efficiency in heterogeneous computing systems. Schematic, taking the first chip as a VPU and the second chip as a GPU as an example, the first target power P_vpu_new = P_vpu + ΔP / 2, the second target power P_gpu_new = P_gpu - ΔP / 2, where P_vpu is the first power, P_gpu is the second power, and ΔP is the power adjustment amount corresponding to the third chip's operating mode.

[0158] In some embodiments, after adjusting the target power, boundary checks are performed on the first target power and the second target power respectively. Illustratively, if the first target power reaches a preset threshold, the first target power is limited to that threshold; that is, the boundary check is implemented using the logic P_vpu_new = max(P_vpu_new, P_vpu_min). If the second target power reaches a preset threshold, the second target power is limited to that threshold; that is, the boundary check is implemented using P_gpu_new = min(P_gpu_new, P_gpu_max).

[0159] For illustrative purposes, please refer to the following: Figure 6 This illustrates a flowchart of determining the clock frequency in a third chip operating mode according to an exemplary embodiment of this application. Figure 6As shown, in the third chip operating mode 610, indicator data 620 and latency threshold 630 are acquired, and the target queue depth 641 is determined based on the indicator data 620 and latency threshold 630. The latency threshold 630 is used to indicate the target time delay for the collaborative data processing of the first and second chips. Given the single-frame processing time and fixed pipeline delay corresponding to the heterogeneous computing system, the target queue depth 641 is determined based on the single-frame processing time, fixed pipeline delay, and latency threshold. Optionally, when the target queue depth 641 is determined, a reasonableness check is performed on the target queue depth 641. For example, if the target queue depth 641 exceeds the target threshold, the target queue depth 641 is limited to the target threshold.

[0160] like Figure 6 As shown, a queue depth difference 650 is determined based on the current queue depth 642 and the target queue depth 641 between the first and second chips. A power adjustment amount 660 corresponding to the operating mode of the third chip is determined based on the queue depth difference 650; wherein, the power adjustment amount 660 is directly proportional to the queue depth difference 650, and the proportionality coefficient is determined by a fifth power adjustment coefficient and the ratio between the total power and the average frame rate corresponding to the first and second chips. Optionally, when the power adjustment amount 660 is determined, a boundary check is performed on the power adjustment amount 660.

[0161] like Figure 6 As shown, a third flag 671 or a fourth flag 672 is obtained based on the queue depth difference 650. When the queue depth difference 650 reaches a preset first queue balance threshold, the third flag 671 is obtained. The third flag 671 indicates that the first power is reduced and the second power is correspondingly increased based on the power adjustment amount 660, thereby improving the processing efficiency of the second chip. The first queue balance threshold indicates the upper limit of the queue depth difference 650. When the queue depth difference 650 is lower than or equal to the preset second queue balance threshold, the fourth flag 672 is obtained. The fourth flag 672 indicates that the second power is reduced and the first power is correspondingly increased based on the power adjustment amount 660, thereby improving the processing efficiency of the first chip. The second queue balance threshold indicates the lower limit of the queue depth difference 650. Optionally, when the queue depth difference 650 is within the queue balance range indicated by the first and second queue balance thresholds, it indicates that the processing efficiency between the first and second chips is balanced, and neither the first nor the second power needs to be adjusted.

[0162] like Figure 6As shown, a first target power 681 is determined based on a third flag 671 and a power adjustment amount 660; a second target power 682 is determined based on a fourth flag 672 and a power adjustment amount 660. Optionally, when the first target power 681 and the second target power 682 are determined, a boundary check is performed on the first target power 681 and the second target power 682.

[0163] In summary, this method establishes a connection between the determination of chip clock frequencies in a heterogeneous system and the working scenario and user requirements by determining the chip operating mode corresponding to the heterogeneous system. Based on the indicator data corresponding to the first chip and the second chip, it determines the first clock frequency for the first chip to perform tasks and the second clock frequency for the second chip to perform tasks, as indicated by the chip operating mode. In particular, the method acquires indicator data in real time to indicate the balance between the processing efficiency of the first and second chips and dynamically adjusts the target clock frequency during the operation of the first and second chips. This improves the applicability of the clock frequency determination method in different chip application scenarios, thereby improving the efficiency of clock frequency determination during chip operation.

[0164] The method provided in this embodiment determines the power adjustment parameters required for the current application scenario based on indicator data through decision rules for different chip operating modes. It adjusts the first power of the first chip and the second power of the second chip to their respective target powers. Furthermore, it restricts the indicator data during the decision-making process through constraints corresponding to the chip operating modes, thereby improving the accuracy of power decision-making and thus improving the accuracy of clock frequency determination.

[0165] In some embodiments, the chip operating mode includes a fourth chip operating mode. Please refer to [reference needed]. Figure 7 This illustrates a flowchart of a method for determining a chip clock frequency according to yet another exemplary embodiment of this application. This method can be executed by a computer device; for example, it can be executed by a terminal, a server, or a combination of both. Figure 7 As shown, the above method includes the following step 710.

[0166] Step 710: If the indicator data meets the preset safety conditions, in response to the start signal corresponding to the fourth chip's working mode, adjust the first power of the first chip in its current operating state to the first target power based on the power adjustment parameters corresponding to the fourth chip's working mode, and adjust the second power of the second chip in its current operating state to the second target power based on the power adjustment parameters corresponding to the fourth chip's working mode.

[0167] The purpose of adjusting the target power of the chip in the fourth chip operating mode is to maximize the performance of the heterogeneous computing system in the short term, thereby enabling it to handle the critical tasks associated with the heterogeneous computing system. Optionally, the fourth chip operating mode can be implemented as a burst performance mode.

[0168] Security checks on indicator data are performed using security conditions as a fourth constraint, wherein there is a correspondence between the security conditions and the type of indicator data. In some embodiments, the indicator data meets preset security conditions, including at least one of the following situations.

[0169] 1. The temperatures corresponding to the first chip and the second chip are respectively lower than the preset temperature threshold corresponding to the fourth chip's operating mode; wherein, the temperatures corresponding to the first chip and the second chip are indicator data. Illustratively, the temperature threshold is used to indicate the upper temperature limit that the heterogeneous computing system needs to meet to start the fourth chip's operating mode. If at least one of the temperatures corresponding to the first chip and the second chip reaches the temperature threshold, it indicates that the temperature of the heterogeneous computing system does not meet the safety conditions, and it is not advisable to adjust the power of the first chip and / or the second chip in the fourth chip's operating mode.

[0170] 2. The time interval between the exit time corresponding to the last start signal and the current time reaches a preset interval threshold; where the time interval between the exit time corresponding to the last start signal and the current time is used to indicate the cooling period of the sudden fourth chip operating mode, and this time interval is an indicator data. Illustratively, according to the rules and theoretical settings of chip design, in the fourth chip operating mode, the power of the first and second chips increases respectively, and the heat generated by the chips cannot be completely dissipated in the short term, that is, the heat dissipation system (such as a heat sink or fan) corresponding to the heterogeneous computing system has a thermal response delay.

[0171] By setting the aforementioned time interval, the target power of the chip is repeatedly increased during the cooling period, ensuring sufficient heat capacity when adjusting the frequency in the fourth chip's operating mode. This avoids cumulative fatigue damage to the chip packaging layer caused by frequent thermal cycling (repeated rapid heating and cooling), shortening the hardware lifespan, and preventing the heat generated by the chip from accumulating to the over-limit temperature, thereby improving the chip's thermal management efficiency. Optionally, if the temperature of the first chip or the second chip reaches the over-limit temperature, the temperature protection mechanism is triggered, resulting in forced frequency reduction. That is, without the safety conditions corresponding to the time interval, the processing efficiency of the heterogeneous computing system may decrease instead of increase, or fluctuate significantly, and the determination efficiency of the chip clock frequency is low.

[0172] 3. The battery levels corresponding to the first and second chips have reached a preset power threshold; where battery level is an indicator. The preset power threshold indicates that the energy resources of the heterogeneous computing system corresponding to the first and second chips are sufficient, and is used to indicate the lower limit of power required for the heterogeneous computing system to perform tasks in the fourth chip's operating mode. Indicatively, a battery level of Battery_level > 20% indicates that the indicator data meets safety conditions.

[0173] It is worth noting that the above-mentioned indicators and data meet the security conditions only as illustrative examples, and this application does not limit the methods of security checks or the types of indicators and data.

[0174] Specifically, this refers to the startup signal corresponding to the operating mode of the fourth chip in Huqiu, provided that multiple safety conditions for various indicator data are met. If any of the multiple safety conditions are not met, the safety check for the fourth chip's operating mode fails, the safety check result is output to the log file, and the startup operation for power adjustment in the fourth chip's operating mode is skipped, i.e., the startup signal acquisition is skipped. Illustratively, the safety check result, implemented as a text string, is output to at least one of the control platform, log file, or debugging terminal via log("Burst performance mode safety check failed, startup refused"), recording the operating status and clock frequency determination process information of the heterogeneous computing system.

[0175] By setting multi-dimensional security conditions for the indicator data, a security check is performed on the heterogeneous computing system corresponding to the first chip and the second chip. If any of the multiple security conditions are not met, power adjustment of the first chip and / or the second chip is avoided in the fourth chip working mode. This protects the hardware of the heterogeneous computing system and avoids the system efficiency from decreasing instead of increasing when power adjustment is performed without passing the security check, thereby improving the accuracy of chip clock frequency determination.

[0176] In some embodiments, upon receiving a frequency adjustment request, the frequency adjustment process corresponding to the fourth chip's operating mode is triggered; if the security check passes, a start signal is acquired, and the current time is recorded as the start time. Schematic, burst_start_time = current_time(), where burst_start_time is the start time, and current_time() is used to determine the current time; based on the start time, the adjustment duration for frequency adjustment of the heterogeneous computing system based on the first target power and the second target power can be determined.

[0177] The power adjustment parameters corresponding to the fourth chip operating mode include a preset first power adjustment coefficient. Illustratively, the first power adjustment coefficient is the ratio between the target power and the chip power in the current state.

[0178] In response to the startup signal, a first target power is determined based on a first power adjustment coefficient and a first power corresponding to the fourth chip's operating mode; a second target power is determined based on the first power adjustment coefficient and a second power. Illustratively, the preset first power adjustment coefficient K_boost is a coefficient greater than 1, used to indicate the target power of the chip to be increased; taking the first chip as a VPU and the second chip as a GPU as an example, the first target power P_vpu_burst = P_vpu × K_boost, and the second target power P_gpu_burst = P_gpu × K_boost, where P_vpu is the first power corresponding to the startup time when the startup signal is acquired / received, and P_gpu is the second power corresponding to the startup time; correspondingly, the total target power of the heterogeneous computing system corresponding to the first and second chips, P_total_burst = P_total × K_boost, where P_total is the total power of the heterogeneous computing system.

[0179] In some embodiments, the step of determining the chip clock frequency is performed after determining the target power. Not limited to the chip operating mode, after determining the first target power and the second target power, determining the first clock frequency based on the first target power and determining the second clock frequency based on the second target power includes at least one of the following steps: determining a first correlation between the clock frequency and power corresponding to the first chip, and determining a second correlation between the clock frequency and power corresponding to the second chip; determining the first clock frequency based on the first target power through the first correlation, and determining the second clock frequency based on the second target power through the second correlation.

[0180] A first correlation between the clock frequency and power of the first chip and a second correlation between the clock frequency and power of the second chip are established in advance. Schematic, power corresponding to each clock frequency is collected on sample chips corresponding to the first and second chips respectively, thereby establishing the first and second correlations through lookup tables or mathematical models.

[0181] Optionally, the first and second association relationships can be implemented as at least one of the following: 1. Mapping function: Describes the correspondence between power and clock frequency through mathematical expressions and other rules. For each power value within the domain of the mapping function, there is a unique clock frequency corresponding to that power. The mathematical model consists of at least one mapping function representing the association between power and clock frequency. Optionally, the mapping function includes linear functions, polynomial functions, piecewise functions, and other fitting functions. 2. Lookup table: Establishes a data structure containing the correspondence between power and clock frequency, such as an array, hash table, or database. 3. Logical rules: Establishes the correspondence between input and output parameters through pre-defined conditional statements, such as if-then statements and switch-case statements. Illustratively, the relationship between power and clock frequency is achieved through the statement "IF power = (0.5W) THEN clock frequency = (1.5GHz)". 4. Deep learning model: A deep learning network architecture based on multi-layer nonlinear transformations learns the hierarchical feature representation of the training data to achieve the mapping from power to clock frequency.

[0182] It is worth noting that the above-described methods of implementing the correlation are merely illustrative examples, and the embodiments of this application do not limit the specific implementation of the correlation between power and clock frequency. Optionally, the correlation between power and clock frequency can be implemented by combining the above-described methods of implementing the correlation.

[0183] In the fourth chip mode, in response to the start signal, the first chip adjusts the first clock frequency based on the first target power via DVFS, and the second chip adjusts the second clock frequency based on the second target power, and the frequency adjustment information is output to the log file. Illustratively, the frequency adjustment information, implemented as a text string, is output to at least one of the control platform, log file, or debugging terminal via log("Burst mode start: System target power → %dW, duration ≤ 3 seconds", P_total_burst), recording the operating status of the heterogeneous computing system and the process information of clock frequency determination; where P_total_burst is the total target power of the heterogeneous computing system, and the adjustment duration is 3 seconds.

[0184] By precisely configuring the chip clock frequency (including the first clock frequency of the first chip and the second clock frequency of the second chip) corresponding to the target power (including the first target power and the second target power) through pre-established correlations between clock frequency and power (including the first correlation and the second correlation), the rules for determining the clock frequency based on the target power are clarified, improving the interpretability of the clock frequency determination process and thus improving the accuracy of chip frequency tuning. Furthermore, by using the pre-set first and second correlations, the method for determining the clock frequency from the target power for different chips is explicitly determined, transforming the step of determining the clock frequency into determining the target power. With the target power as input and the clock frequency corresponding to the target power, used to indicate the execution of the task, as output, the efficiency of determining the chip clock frequency is improved.

[0185] In some embodiments, the fourth constraint condition corresponding to the fourth chip operating mode includes an adjustment duration threshold. If the adjustment duration for the first power and the second power reaches the adjustment duration threshold based on the start signal, the power of the first chip and the second chip is restored to the power before the power was adjusted in response to the start signal in response to the first exit signal corresponding to the fourth chip operating mode.

[0186] The adjustment duration is the duration for adjusting the first power and the second power. That is, for the process of adjusting the clock frequencies corresponding to the first chip and the second chip respectively in the fourth chip operating mode, a start signal indicates the start of the adjustment process, and a first exit signal indicates the end of the adjustment process; wherein the time interval between the start time corresponding to the start signal and the exit time corresponding to the first exit signal is the adjustment duration. Optionally, the exit signal includes at least one of a first exit signal and a second exit signal.

[0187] The adjustment duration threshold corresponds to the fourth chip's operating mode, and is implemented as a mode parameter corresponding to the fourth chip's operating mode. Factors determining the adjustment duration threshold include, but are not limited to, the task requirements of the task to be executed in the heterogeneous computing system, the application scenario of the task to be executed, and the thermal management information of the first and second chips respectively. In some embodiments, in response to receiving a user-triggered mode setting request, the chip's operating mode is switched to the fourth chip's operating mode. The mode setting request includes the adjustment duration threshold corresponding to the fourth chip's operating mode. Optionally, the adjustment duration threshold can be a preset static parameter of the fourth chip's operating mode, or a dynamic parameter determined according to the application scenario. For example, assuming the adjustment duration threshold is implemented as a dynamic parameter and the task to be executed is a photo-taking task, high frame rate processing is required during the short period of photo-taking; correspondingly, the duration requirement of the photo-taking task indicates the adjustment duration threshold.

[0188] In some embodiments, if the indicator data does not meet the safety conditions, a second exit signal is received, wherein the second exit signal is used to indicate skipping the response to the start signal before the start signal is acquired, and the second exit signal is used to indicate restoring the power of the first chip and the second chip to the power before the power adjustment in response to the start signal after the start signal is received.

[0189] That is, the situations in which the second exit signal is received include, but are not limited to: 1. If the indicator data does not meet the safety conditions before receiving the start signal, the second exit signal is received, and the acquisition of the start signal is skipped. 2. If the indicator data does not meet the safety conditions during the clock frequency adjustment in response to the start signal, the second exit signal is acquired, and the power of the first chip and the second chip is restored to the power before the power adjustment in response to the start signal.

[0190] Schematic, the start signal is generated by the control module corresponding to the chip's clock frequency determination process and sent by the control module to the power adjustment module; the power adjustment module receives the start signal and adjusts the first power and / or the second power in response to receiving the start signal.

[0191] Indicatively, during the clock frequency adjustment process in response to the start signal, the indicator data limited by the safety conditions are continuously acquired, and the compliance between the indicator data and the safety conditions is periodically checked; indicatively, when the temperatures corresponding to the first chip and the second chip respectively reach the temperature threshold, even if the time interval between the current moment and the start moment does not reach the adjustment duration threshold, a second exit signal is received, and the target power is restored to the power before the frequency adjustment in the fourth chip's working mode, thereby restoring the chip clock frequency to the clock frequency before the start moment; the frequency adjustment end information implemented in the form of a text string is output to at least one of the control platform, log file, or debugging terminal through log("Burst mode terminated: temperature exceeded limit"), recording the operating status of the heterogeneous computing system and the process information of clock frequency determination.

[0192] The fixed power budget scheme in related technologies has limitations in dealing with sudden high load application scenarios. For example, when an AR device, such as AR glasses, starts up, it needs to load an AR model and initialize the device; or, a terminal with a camera needs to perform high frame rate processing when taking a picture; or, a game program on the terminal experiences a sudden increase in load during scene switching. These critical moments require brief periods of high performance to handle latency-sensitive tasks. If the fixed power budget cannot meet the performance requirements of the task to be executed, users will experience lag and delays. Furthermore, the low accuracy of chip clock frequency determination in heterogeneous computing systems leads to low task processing efficiency. The fourth chip operating mode of this application, namely the burst performance mode, allows the system to briefly overclock under safe conditions such as temperature, power, and cooling period, temporarily increasing the total power budget to cope with sudden loads. This enables the heterogeneous computing system to provide additional performance at critical moments, improving the user experience. Simultaneously, multiple safety checks and cooling period mechanisms ensure that overclocking will not cause overheating or hardware damage, thereby improving the efficiency and accuracy of chip clock frequency determination.

[0193] For illustrative purposes, please refer to the following: Figure 8 This illustrates a flowchart of determining the clock frequency in a fourth chip operating mode according to an exemplary embodiment of this application. Figure 8 As shown, in the fourth chip operating mode 810, indicator data 820 is acquired, a security check is performed through security conditions 830, and a start signal 840 corresponding to the fourth chip operating mode 810 is acquired. In response to the start signal 840, a first target power 861 and a second target power 862 are determined based on a preset first power adjustment coefficient 850. Optionally, the first target power 861 is proportional to the first power before power adjustment in response to the start signal 840, and the second target power 862 is proportional to the second power before power adjustment in response to the start signal 840, with the aforementioned proportionality coefficients corresponding to the first power adjustment coefficient 850.

[0194] like Figure 8As shown, in the fourth chip operating mode 810, before power adjustment in response to the start signal 840, the first power and the second power are recorded, and the start time of power adjustment is also recorded. The adjustment duration 870 is updated in real time based on the start time. When the adjustment duration 870 reaches the adjustment duration threshold based on the start signal, an exit signal 880 corresponding to the fourth chip operating mode 810 is obtained. This exit signal 880 is implemented as the first exit signal. In response to the exit signal 880, the power of the first chip is restored from the first target power 861 to the first power recorded before power adjustment, and the power of the second chip is restored from the second target power 862 to the second power recorded before power adjustment. Specifically, the exit signal 880 is obtained when the adjustment duration 870 reaches the preset duration threshold. Optionally, the exit signal 880 may be triggered in ways including but not limited to the following: when the security check corresponding to the security condition 830 is performed periodically, if the indicator data 820 of the first chip and the second chip do not match the security condition 830, an exit signal 880 is obtained accordingly. This exit signal 880 is implemented as a second exit signal. In response to the exit signal 880, the acquisition of the start signal is skipped.

[0195] In summary, this method establishes a connection between the determination of chip clock frequencies in a heterogeneous system and the working scenario and user requirements by determining the chip operating mode corresponding to the heterogeneous system. Based on the indicator data corresponding to the first chip and the second chip, it determines the first clock frequency for the first chip to perform tasks and the second clock frequency for the second chip to perform tasks, as indicated by the chip operating mode. In particular, the method acquires indicator data in real time to indicate the balance between the processing efficiency of the first and second chips and dynamically adjusts the target clock frequency during the operation of the first and second chips. This improves the applicability of the clock frequency determination method in different chip application scenarios, thereby improving the efficiency of clock frequency determination during chip operation.

[0196] The method provided in this embodiment provides a short-term overclocking operation mode through the fourth chip working mode. Under the premise of meeting multiple safety conditions, it temporarily increases the total power budget of the heterogeneous computing system and the clock frequency of any processor in the first and second chips to cope with sudden high load tasks. It also prevents frequent triggering by adjusting the duration of the cooling period, expands the adaptability of the chip clock frequency determination method in different application scenarios, and improves the efficiency of clock frequency determination during chip operation.

[0197] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0198] Please refer to Figure 9 This illustrates a structural block diagram of a chip clock frequency determination apparatus provided in an exemplary embodiment of this application. Figure 9 As shown, the device includes: The determination module 910 is configured to determine the chip operating mode, which is used to indicate the power distribution method between the first chip and the second chip. The determination module 910 is also configured to determine the indicator data corresponding to the first chip and the second chip, the indicator data being used to indicate the degree of power balance between the first chip and the second chip; The processing module 920 is configured to determine the first clock frequency to which the first chip should be adjusted and the second clock frequency to which the second chip should be adjusted, based on the chip's operating mode and indicator data.

[0199] In an optional embodiment, the determining module 910 determines the indicator data corresponding to the first chip and the second chip, including at least one of the following: The determining module 910 is also configured to determine the frame rate difference between the first chip and the second chip, the frame rate difference being used to indicate the difference in data processing efficiency between the first chip and the second chip; The determination module 910 is also configured to obtain the first power of the first chip under the current operating state and the second power of the second chip under the current operating state; The determination module 910 is also configured to determine the temperatures corresponding to the current operating states of the first chip and the second chip, respectively. The determination module 910 is also configured to determine the clock frequencies corresponding to the current operating states of the first chip and the second chip, respectively. The determining module 910 is further configured to determine the queue depth of the first chip and the second chip in their current operating states. The queue depth is used to indicate the number of data units to be processed by the second chip that are transmitted from the first chip to the second chip, or the queue depth is used to indicate the number of data units to be processed by the first chip that are transmitted from the second chip to the first chip.

[0200] In an optional embodiment, the determining module 910 is further configured to determine the number of first data frames processed by the first chip within a preset sampling period, and to determine the number of second data frames processed by the second chip within the sampling period. The processing module 920 is also configured to determine a first frame rate of the first chip based on a first data frame number, and to determine a second frame rate of the second chip based on a second data frame number. The processing module 920 is also configured to determine the frame rate difference based on the first frame rate and the second frame rate.

[0201] In an optional embodiment, the determining module 910 is also configured to receive a mode setting request; The processing module 920 is also configured to extract the chip operating mode from the mode setting request.

[0202] In an optional embodiment, the chip clock frequency determination process includes multiple loop rounds; the determination module 910 is further configured to determine loop information in the absence of a mode setting request, the loop information being used to indicate the current loop round in the chip clock frequency determination process. The processing module 920 is also configured to determine the chip's operating mode based on the round information.

[0203] In an optional embodiment, the processing module 920 is further configured to determine the chip operating mode based on the default mode information when the round information indicates that it is currently in the first cycle in the chip clock frequency determination process. The processing module 920 is also configured to determine the chip operating mode based on the chip operating mode of the previous cycle when the cycle information indicates that the current cycle is not the first cycle in the chip clock frequency determination process.

[0204] In an optional embodiment, the processing module 920 is further configured to determine the first target power corresponding to the first chip and the second target power corresponding to the second chip based on the chip operating mode and indicator data. The processing module 920 is also configured to determine a first clock frequency based on a first target power and a second clock frequency based on a second target power.

[0205] In an optional embodiment, the determining module 910 is further configured to determine the constraints corresponding to the chip operating mode. The processing module 920 is also configured to determine power adjustment parameters corresponding to the chip operating mode based on constraints and index data. The power adjustment parameters are used to indicate the method of power adjustment for at least one of the first chip and the second chip. The processing module 920 is also configured to determine the first target power and the second target power based on the power adjustment parameters, the first power of the first chip in its current operating state, and the second power of the second chip in its current operating state.

[0206] In an optional embodiment, the chip operating mode includes a first chip operating mode, the first constraint condition corresponding to the first chip operating mode includes a constraint on the total power of the first target power and the second target power, and the indicator data includes the frame rate difference between the first chip and the second chip. The processing module 920 is also configured to determine the power adjustment parameters corresponding to the first chip's operating mode based on the frame rate difference and total power.

[0207] In an optional embodiment, the processing module 920 is further configured to, when the frame rate difference indicates that the first frame rate of the first chip is less than the second frame rate of the second chip, and the absolute value of the frame rate difference is greater than a preset frame rate balancing threshold, increase the first power to a first target power and decrease the second power to a second target power based on power adjustment parameters, wherein the frame rate balancing threshold is used to indicate the upper limit of the absolute value of the frame rate difference. The processing module 920 is further configured to increase the second power to the second target power and decrease the first power to the first target power based on the power adjustment parameters when the frame rate difference indicates that the first frame rate of the first chip is greater than the second frame rate of the second chip, and the absolute value of the frame rate difference is greater than the frame rate balance threshold.

[0208] In an optional embodiment, the chip operating mode includes a second chip operating mode, and the second constraint condition corresponding to the second chip operating mode includes a constraint on the indicator data based on an indicator threshold. The processing module 920 is also configured to determine the indicator margin based on the indicator threshold and indicator data; The processing module 920 is also configured to determine the power adjustment parameters corresponding to the second chip's operating mode based on the index margin.

[0209] In an optional embodiment, the indicator margin includes a first margin and a second margin, the first margin being used to indicate the adjustment range of the first power and the second margin being used to indicate the adjustment range of the second power. The processing module 920 is further configured to determine a first power reduction parameter when the first margin is higher than a preset first threshold. The first power reduction parameter is used to indicate the reduction of the first power based on the first margin. The processing module 920 is further configured to determine a first power increase parameter when the first margin is lower than a preset second threshold, the first power increase parameter being used to indicate an increase in first power based on the first margin; The processing module 920 is also configured to determine a second power reduction parameter when the second margin is higher than a preset third threshold. The second power reduction parameter is used to indicate the reduction of the second power based on the second margin. The processing module 920 is also configured to determine a second power enhancement parameter when the second margin is lower than a preset fourth threshold. The second power enhancement parameter is used to indicate the enhancement of the second power based on the second margin.

[0210] In an optional embodiment, the chip operating mode includes a third chip operating mode, and the third constraint corresponding to the third chip operating mode includes a constraint on the queue depth between the first chip and the second chip based on a latency threshold. The processing module 920 is also configured to determine the target queue depth based on latency thresholds and metric data; The processing module 920 is also configured to determine the queue depth difference based on the target queue depth and the queue depth of the first chip and the second chip in their current operating states; The processing module 920 is also configured to determine the power adjustment parameters corresponding to the operating mode of the third chip based on the queue depth difference.

[0211] In an optional embodiment, the processing module 920 is further configured to increase the second power to the second target power based on the power adjustment parameters corresponding to the third chip operating mode when the queue depth difference reaches a preset first queue balance threshold. The first queue balance threshold is used to indicate the upper limit of the queue depth difference. The processing module 920 is also configured to increase the first power to the first target power based on the power adjustment parameters corresponding to the third chip operating mode when the queue depth difference is lower than or equal to a preset second queue balance threshold. The second queue balance threshold is used to indicate the lower limit of the queue depth difference.

[0212] In an optional embodiment, the chip operating mode includes a fourth chip operating mode; the determining module 910 is further configured to, in response to a start signal corresponding to the fourth chip operating mode, adjust the first power of the first chip in its current operating state to a first target power based on the power adjustment parameters corresponding to the fourth chip operating mode, and adjust the second power of the second chip in its current operating state to a second target power based on the power adjustment parameters corresponding to the fourth chip operating mode, provided that the indicator data meets preset safety conditions;

[0213] In an optional embodiment, the fourth constraint condition corresponding to the fourth chip operating mode includes an adjustment duration threshold. The determining module 910 is further configured to, in response to a first exit signal corresponding to the fourth chip operating mode, restore the power of the first chip and the second chip to the power before the power was adjusted in response to the start signal when the adjustment duration of the first power and the second power reaches the adjustment duration threshold based on the start signal.

[0214] In an optional embodiment, the determining module 910 is further configured to receive a second exit signal if the indicator data does not meet the safety conditions, wherein the second exit signal is used to indicate skipping the response to the start signal before receiving the start signal, and the second exit signal is used to indicate restoring the power of the first chip and the second chip to the power before the power adjustment in response to the start signal after receiving the start signal.

[0215] In an optional embodiment, the indicator data meets preset security conditions, including at least one of the following: The temperatures corresponding to the first and second chips are lower than the preset temperature threshold corresponding to the working mode of the fourth chip. The time interval between the exit time corresponding to the last start signal and the current time reaches a preset interval threshold; The battery levels corresponding to the first and second chips have reached the preset power threshold.

[0216] In an optional embodiment, the processing module 920 is further configured to determine a first correlation between the clock frequency and power corresponding to the first chip, and to determine a second correlation between the clock frequency and power corresponding to the second chip. The processing module 920 is also configured to determine a first clock frequency based on a first target power through a first correlation relationship, and to determine a second clock frequency based on a second target power through a second correlation relationship.

[0217] In summary, this device establishes a connection between the chip clock frequency determination method and the working scenario and user requirements in a heterogeneous system by determining the chip operating mode corresponding to the heterogeneous system. Based on the indicator data corresponding to the first chip and the second chip, it obtains the first clock frequency for the first chip to perform the task and the second clock frequency for the second chip to perform the task, as indicated by the chip operating mode. In particular, the real-time acquisition of indicator data indicates the balance between the processing efficiency of the first chip and the second chip, and the dynamic adjustment of the target clock frequency during the operation of the first chip and the second chip improves the applicability of the clock frequency determination method in different chip application scenarios, thereby improving the efficiency of clock frequency determination during chip operation.

[0218] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the content structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0219] This application provides a processor. Figure 10 This is a schematic block diagram of a processor provided in an exemplary embodiment of this application. The processor 1000 includes the chip clock frequency determination device provided in the above embodiments. Alternatively, an embodiment of this application provides a processor including programmable logic circuitry and / or program instructions, which, when running on a computer device, implement the chip clock frequency determination method provided in the above method embodiments.

[0220] This application provides a circuit board. Figure 11This is a schematic block diagram of a board provided in an exemplary embodiment of this application. The board 1100 includes the chip clock frequency determination device provided in the above embodiment. Alternatively, this application embodiment provides a board that, when running on a computer device, is used to implement the chip clock frequency determination method provided in the above method embodiment. Specifically, the board can also be called a server board. A board is a type of printed circuit board (PCB), which is manufactured with a socket and can be inserted into a slot on a server's motherboard to control the operation of hardware, such as controlling the operation of hardware devices like displays and data acquisition cards. After installing a driver or computer program on the board, the board can perform the corresponding functions. The driver or computer program can be installed in a processor, which controls the execution of the driver or computer program, and in conjunction with the chip clock frequency determination device, implements the corresponding functions of the board 1100.

[0221] This application provides a computer device. Figure 12 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The first computer device 1200 includes the chip clock frequency determination device provided in the above embodiment; or, an embodiment of this application provides a computer device. Figure 13 This is a schematic block diagram of a computer device provided in another exemplary embodiment of this application. The second computer device 1300 includes the processor provided in the above embodiments, and the computer device can be implemented as a terminal; or, embodiments of this application provide a computer device. Figure 14 This is a schematic block diagram of a computer device provided in yet another exemplary embodiment of this application. The third computer device 1400 includes the board provided in the above embodiments, and the third computer device 1400 can be implemented as a server.

[0222] Optionally, embodiments of this application also provide a computer device, which includes: a processor and a memory, wherein the memory stores a computer program; the processor is used to execute the computer program in the memory to implement the chip clock frequency determination method provided in the above method embodiments.

[0223] Figure 15 This is a schematic block diagram of a computer device provided in another exemplary embodiment of this application. The computer device is a server 1500. Typically, the server 1500 includes a first processor 1501 and a first memory 1502.

[0224] The first processor 1501 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. The first processor 1501 may be implemented using at least one hardware form selected from DSP, FPGA, and Programmable Logic Array (PLA). The first processor 1501 may also include a main processor and a coprocessor. The main processor, also known as a CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the first processor 1501 may integrate a GPU, which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the first processor 1501 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0225] The first memory 1502 may include one or more computer-readable storage media, which may be non-transitory. The first memory 1502 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the first memory 1502 are used to store at least one instruction, which is executed by the first processor 1501 to implement the chip clock frequency determination method provided in the method embodiments of this application.

[0226] In some embodiments, the server 1500 may optionally include an input interface 1503 and an output interface 1504. The first processor 1501, the first memory 1502, and the input interface 1503 and output interface 1504 can be connected via a bus or signal lines. Various peripheral devices can be connected to the input interface 1503 and output interface 1504 via a bus, signal lines, or a circuit board. The input interface 1503 and output interface 1504 can be used to connect at least one I / O-related peripheral device to the first processor 1501 and the first memory 1502. In some embodiments, the first processor 1501, the first memory 1502, and the input interface 1503 and output interface 1504 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the first processor 1501, the first memory 1502, and the input interface 1503 and output interface 1504 can be implemented on separate chips or circuit boards, and this application embodiment does not limit this.

[0227] Figure 16 This is a structural block diagram of a computer device provided in an exemplary embodiment of this application. Optionally, the fourth computer device 1600 is a terminal.

[0228] The fourth computer device 1600 may be a portable mobile terminal, also referred to as a mobile terminal in this embodiment. Examples include smartphones, tablets, MP3 players, and MP4 players. The fourth computer device 1600 may also be referred to as user equipment, portable terminal, or other names.

[0229] Typically, the fourth computer device 1600 includes: a second processor 1601 and a second memory 1602.

[0230] The second processor 1601 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The second processor 1601 may be implemented using at least one hardware form selected from DSP, FPGA, and PLA. The second processor 1601 may also include a main processor and a coprocessor. The main processor, also known as a CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the second processor 1601 may integrate a GPU, which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the second processor 1601 may also include an AI processor, which is used to handle computational operations related to machine learning.

[0231] The second memory 1602 may include one or more computer-readable storage media, which may be tangible and non-transitory. The second memory 1602 may also include high-speed random access memory devices and non-volatile storage devices, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the second memory 1602 are used to store at least one instruction, which is executed by the second processor 1601 to implement the chip clock frequency determination method provided in the various method embodiments of this application.

[0232] In some embodiments, the fourth computer device 1600 may optionally include a peripheral device interface 1603 and at least one peripheral device. Specifically, the peripheral device includes at least one of a radio frequency circuit 1604, a touch display screen 1605, a camera assembly 1606, an audio circuit 1607, and a power supply 1608. The fourth computer device 1600 also includes one or more sensors 1609. The one or more sensors 1609 include, but are not limited to, an accelerometer 1610, a gyroscope 1611, a pressure sensor 1612, an optical sensor 1613, and a proximity sensor 1614.

[0233] Those skilled in the art will understand that Figure 10The structure shown does not constitute a limitation on the processor. Figure 11 The structure shown does not constitute a limitation on the board. Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 The structure shown does not constitute a limitation on the computer device and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0234] On the other hand, embodiments of this application provide a computer device including the processor described above. Optionally, the processor is a GPU. The computer device can be at least one of a portable computer, a desktop computer, a server, a server cluster, an AI computing cluster, and a cloud computing cluster. The AI ​​computing cluster can also be simply referred to as an intelligent computing cluster or a smart computing cluster.

[0235] This application provides a computer-readable storage medium storing a computer program. The computer program is loaded and executed by a processor to implement the chip clock frequency determination method provided in the above-described method embodiments. Optionally, the computer-readable storage medium may include: read-only memory (ROM), random access memory (RAM), solid-state drives (SSDs), or optical discs, etc. The random access memory may include resistive random access memory (ReRAM) and dynamic random access memory (DRAM).

[0236] This application provides a computer program product, which includes a computer program stored in a computer-readable storage medium. A processor reads and executes the computer program from the computer-readable storage medium to implement the chip clock frequency determination method provided in the above-described method embodiments.

[0237] It should be noted that the collection and processing of relevant data (such as indicator data, target power, etc.) in this application should strictly comply with the requirements of relevant national laws and regulations, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing within the scope of laws and regulations and the authorization of the personal information subject.

[0238] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0239] Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in the order shown in the figures, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the figures. This application does not limit this. That is, the sequence numbers of the embodiments described above are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0240] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0241] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0242] The above are merely optional embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for determining the clock frequency of a chip, characterized in that, The method includes: Determine the chip operating mode, which indicates the power distribution method between the first chip and the second chip; Determine the indicator data corresponding to the first chip and the second chip, the indicator data being used to indicate the degree of power balance between the first chip and the second chip; Based on the chip's operating mode and the indicator data, the first clock frequency to be adjusted for the first chip and the second clock frequency to be adjusted for the second chip are determined.

2. The method according to claim 1, characterized in that, The determination of the indicator data corresponding to the first chip and the second chip includes at least one of the following: Determine the frame rate difference between the first chip and the second chip, the frame rate difference being used to indicate the difference in data processing efficiency between the first chip and the second chip; Obtain the first power of the first chip under its current operating state, and obtain the second power of the second chip under its current operating state; Determine the temperatures corresponding to the current operating states of the first chip and the second chip, respectively; Determine the clock frequencies corresponding to the current operating states of the first chip and the second chip, respectively; Determine the queue depth of the first chip and the second chip in their current operating states. The queue depth is used to indicate the number of data units to be processed by the second chip that the first chip is transmitting to the second chip, or the queue depth is used to indicate the number of data units to be processed by the first chip that the second chip is transmitting to the first chip.

3. The method according to claim 2, characterized in that, Determining the frame rate difference between the first chip and the second chip includes: Determine the number of first data frames processed by the first chip within a preset sampling period, and determine the number of second data frames processed by the second chip within the sampling period; The first frame rate of the first chip is determined based on the first data frame count, and the second frame rate of the second chip is determined based on the second data frame count. The frame rate difference is determined based on the first frame rate and the second frame rate.

4. The method according to claim 1, characterized in that, The determination of the chip's operating mode includes: Upon receiving a mode setting request, the chip operating mode is extracted from the mode setting request.

5. The method according to claim 4, characterized in that, The process for determining the chip clock frequency includes multiple iterations. The method further includes: If the mode setting request is not received, the cycle information is determined, which indicates the current cycle in the process of determining the chip clock frequency; The chip's operating mode is determined based on the round information.

6. The method according to claim 5, characterized in that, Determining the chip's operating mode based on the round information includes: When the round information indicates that the current cycle is in the first loop of the chip clock frequency determination process, the chip operating mode is determined based on the default mode information; If the round information indicates that the current cycle is not the first cycle in the process of determining the chip clock frequency, the chip operating mode is determined based on the chip operating mode of the previous cycle.

7. The method according to claim 1, characterized in that, The step of determining the first clock frequency to be adjusted for the first chip and the second clock frequency to be adjusted for the second chip based on the chip's operating mode and the indicator data includes: Based on the chip's operating mode and the indicator data, determine the first target power corresponding to the first chip and the second target power corresponding to the second chip; The first clock frequency is determined based on the first target power, and the second clock frequency is determined based on the second target power.

8. The method according to claim 7, characterized in that, Determining the first target power corresponding to the first chip and the second target power corresponding to the second chip based on the chip's operating mode and the indicator data includes: Determine the constraints corresponding to the chip's operating mode; Based on the constraints and the index data, the power adjustment parameters corresponding to the chip's operating mode are determined. The power adjustment parameters are used to indicate the method of power adjustment for at least one of the first chip and the second chip. Based on the power adjustment parameters, the first power of the first chip under its current operating state, and the second power of the second chip under its current operating state, the first target power and the second target power are determined.

9. The method according to claim 8, characterized in that, The chip operating mode includes a first chip operating mode, and the first constraint condition corresponding to the first chip operating mode includes a constraint on the total power of the first target power and the second target power. The index data includes the frame rate difference between the first chip and the second chip. Determining the power adjustment parameters corresponding to the chip's operating mode based on the constraints and the indicator data includes: The power adjustment parameters corresponding to the operating mode of the first chip are determined based on the frame rate difference and the total power.

10. The method according to claim 9, characterized in that, The step of determining the first target power and the second target power based on the power adjustment parameters, the first power of the first chip under its current operating state, and the second power of the second chip under its current operating state includes: When the frame rate difference indicates that the first frame rate of the first chip is less than the second frame rate of the second chip, and the absolute value of the frame rate difference is greater than a preset frame rate balancing threshold, the first power is increased to the first target power and the second power is decreased to the second target power based on the power adjustment parameter. The frame rate balancing threshold is used to indicate the upper limit of the absolute value of the frame rate difference. When the frame rate difference indicates that the first frame rate of the first chip is greater than the second frame rate of the second chip, and the absolute value of the frame rate difference is greater than the frame rate balance threshold, the second power is increased to the second target power and the first power is decreased to the first target power based on the power adjustment parameters.

11. The method according to claim 8, characterized in that, The chip operating mode includes a second chip operating mode, and the second constraint condition corresponding to the second chip operating mode includes a constraint on the indicator data based on an indicator threshold. Determining the power adjustment parameters corresponding to the chip's operating mode based on the constraints and the indicator data includes: The indicator margin is determined based on the indicator threshold and the indicator data; Based on the aforementioned margin, the power adjustment parameters corresponding to the operating mode of the second chip are determined.

12. The method according to claim 11, characterized in that, The indicator margin includes a first margin and a second margin, wherein the first margin is used to indicate the adjustment range of the first power and the second margin is used to indicate the adjustment range of the second power. The step of determining the power adjustment parameters corresponding to the second chip's operating mode based on the indicator margin includes: If the first margin is higher than a preset first threshold, a first power reduction parameter is determined. The first power reduction parameter is used to indicate that the first power is reduced to the first target power based on the first margin. If the first margin is lower than a preset second threshold, a first power increase parameter is determined. The first power increase parameter is used to indicate that the first power is increased to the first target power based on the first margin. If the second margin is higher than a preset third threshold, a second power reduction parameter is determined, which is used to indicate that the second power is reduced to the second target power based on the second margin. If the second margin is lower than a preset fourth threshold, a second power increase parameter is determined, which is used to indicate that the second power is increased to the second target power based on the second margin.

13. The method according to claim 8, characterized in that, The chip operating mode includes a third chip operating mode, and the third constraint condition corresponding to the third chip operating mode includes a constraint on the queue depth between the first chip and the second chip based on a latency threshold. Determining the power adjustment parameters corresponding to the chip's operating mode based on the constraints and the indicator data includes: The target queue depth is determined based on the latency threshold and the indicator data; Based on the target queue depth and the queue depths of the first chip and the second chip in their current operating states, the queue depth difference is determined. The power adjustment parameters corresponding to the operating mode of the third chip are determined based on the queue depth difference.

14. The method according to claim 13, characterized in that, The step of determining the first target power and the second target power based on the power adjustment parameters, the first power of the first chip under its current operating state, and the second power of the second chip under its current operating state includes: When the queue depth difference reaches a preset first queue balance threshold, the second power is increased to the second target power based on the power adjustment parameter corresponding to the third chip's operating mode. The first queue balance threshold is used to indicate the upper limit of the queue depth difference. When the queue depth difference is lower than or equal to a preset second queue balance threshold, the first power is increased to the first target power based on the power adjustment parameter corresponding to the third chip's operating mode. The second queue balance threshold is used to indicate the lower limit of the queue depth difference.

15. The method according to claim 7, characterized in that, The chip operating mode includes a fourth chip operating mode; Determining the first target power corresponding to the first chip and the second target power corresponding to the second chip based on the chip's operating mode and the indicator data includes: When the indicator data meets the preset safety conditions, in response to the start signal corresponding to the fourth chip's operating mode, the first power of the first chip in its current operating state is adjusted to the first target power based on the power adjustment parameters corresponding to the fourth chip's operating mode, and the second power of the second chip in its current operating state is adjusted to the second target power based on the power adjustment parameters corresponding to the fourth chip's operating mode.

16. The method according to claim 15, characterized in that, The fourth constraint condition corresponding to the fourth chip operating mode includes an adjustment duration threshold; the method further includes: If, based on the start signal, the adjustment duration for the first power and the second power reaches the adjustment duration threshold, in response to the first exit signal corresponding to the fourth chip's operating mode, the power of the first chip and the second chip is restored to the power before the power was adjusted in response to the start signal.

17. The method according to claim 15, characterized in that, After determining the indicator data corresponding to the first chip and the second chip, the method further includes: If the indicator data does not meet the security conditions, a second exit signal is received, wherein the second exit signal is used to indicate skipping the response to the start signal before receiving the start signal, and the second exit signal is used to indicate restoring the power of the first chip and the second chip to the power before the power adjustment in response to the start signal after receiving the start signal.

18. The method according to claim 15, characterized in that, The indicator data meets preset security conditions, including at least one of the following: The temperatures corresponding to the first chip and the second chip are respectively lower than the preset temperature threshold corresponding to the working mode of the fourth chip; The time interval between the exit time corresponding to the last start signal and the current time reaches a preset interval threshold; The battery levels corresponding to the first chip and the second chip have reached a preset power threshold.

19. The method according to claim 7, characterized in that, The steps of determining the first clock frequency based on the first target power and determining the second clock frequency based on the second target power include: Determine a first correlation between the clock frequency and power of the first chip, and determine a second correlation between the clock frequency and power of the second chip; The first clock frequency is determined based on the first target power through the first correlation relationship, and the second clock frequency is determined based on the second target power through the second correlation relationship.

20. A device for determining the clock frequency of a chip, characterized in that, The device includes: The determination module is configured to determine the chip operating mode, which is used to indicate the power distribution method between the first chip and the second chip; The determining module is further configured to determine the index data corresponding to the first chip and the second chip, the index data being used to indicate the degree of power balance between the first chip and the second chip; The processing module is configured to determine, based on the chip's operating mode and the indicator data, the first clock frequency to be adjusted to and the second clock frequency to be adjusted to.

21. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded and executed by the processor to implement the method for determining the chip clock frequency as described in any one of claims 1 to 19.

22. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the method for determining the chip clock frequency as described in any one of claims 1 to 19.

23. A computer program product, characterized in that, The computer program product includes a computer program stored in a computer-readable storage medium, and a processor reads from and executes the computer program to implement the method for determining the chip clock frequency as described in any one of claims 1 to 19.

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