Digital circuit with improved multi-reset domain reset architecture and corresponding method of operation

Abstract

The present disclosure relates to digital circuits with improved multiple reset domain reset architecture and corresponding methods of operation. A digital circuit is described that includes a communication bus interface, first and second flip-flops, a reset register, a first logic gate, and a gating circuit. The communication bus interface receives and decodes bus signals and generates a reset initiator signal when a reset is required. The first flip-flop is clocked by a first clock signal and reset by a first reset signal. The second flip-flop is clocked by a second clock signal, reset by a second reset signal, and receives data from the first flip-flop. The reset register is reset by the second reset signal and receives the reset initiator signal to generate a reset source signal. The first logic gate asserts the first reset signal when the second reset signal is asserted or the reset source signal is asserted. The gating circuit generates the second clock signal by passing the first clock signal when the reset initiator signal and the reset source signal are de-asserted and disabling the output when one of them is asserted.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Italian patent application No. 10202500009657, filed on April 30, 2025, entitled "Digital circuit with improved reset architecture for multiple reset domains, and corresponding method of operation", which is hereby incorporated by reference. Technical Field

[0003] This specification relates to digital circuits (e.g., included in a system-on-chip SoC) that operate using multiple reset domains. Background Technology

[0004] In complex digital circuits (e.g., SoCs) that include multiple reset domains, reset signals can propagate across different domains, which can lead to timing issues across reset domains (RDCs).

[0005] During the design phase of an integrated circuit (IC), the analysis of RDC timing is relevant for two main reasons.

[0006] The first reason is that if the flip-flop (FF) is reset asynchronously (that is, by a reset signal that is not synchronized with the clock signal), the set time (i.e., the period before the clock edge during which the input signal is expected to stabilize) and / or hold time (i.e., the period after the clock edge during which the input signal is expected to stabilize) of the target flip-flop may be violated. Figure 1 This is illustrated in the circuit diagram, which shows a first flip-flop 11 and a second flip-flop 12. The data output terminal Q of flip-flop 11 is connected to the data input terminal D of flip-flop 12 (flip-flop 12 is therefore the "target" flip-flop). Flip-flop 11 is timed by a first clock signal CLK1 and reset by a first reset signal RST1 (e.g., active low), while flip-flop 12 is timed by a second clock signal CLK2 and reset by a second reset signal RST2 (e.g., active low). It can be assumed that the clear terminal CLR of both flip-flops (…) Figure 1 (Not visible in the text) is asynchronous. Clock signals CLK1 and CLK2 can be the same or different. If flip-flop 11 is asynchronously reset, the set / hold time of flip-flop 12 may be violated (because the data output terminal q of flip-flop 11 may switch near the edge of clock signal CLK2), which may cause the data signal at the data output terminal Q of flip-flop 12 to be in a metastable state.

[0007] A second reason for the relevance of RDC timing analysis is that static timing analysis (STA), practiced during digital design verification, routinely does not check for preset / reset arcs (i.e., the signal propagation path through one or more reset terminals of the flip-flop), as this analysis can produce unpredictable violations, especially in complex digital designs. Because preset / reset arcs are typically not checked during STA, even synchronized assertions can result in set / hold timing violations if not handled properly. Figure 2 This is illustrated in the circuit diagram. Figure 2 This shows that it can be generated by the same clock signal ( Figure 2 The timing is achieved using a first flip-flop 21, a second flip-flop 22, and a third flip-flop 23 (not visible in the image). The data output terminal Q of flip-flop 21 (e.g., via combinational circuit 24) is coupled to the reset terminal of flip-flop 22, making flip-flop 21 act as a synchronous reset source for flip-flop 22. The data output terminal Q of flip-flop 22 is connected to the data input terminal D of flip-flop 23. During STA (Synchronous Stability), the signal path from the data input terminal D of flip-flop 22 to the data output terminal Q of flip-flop 23 can be checked, while the signal path from the data output terminal Q of flip-flop 21 to the data output terminal Q of flip-flop 23 can be ignored (because this signal path passes through the reset terminal of flip-flop 22).

[0008] In this field, document US 10936774 B1 is an example of prior art because it discloses a method for identifying RDC metastability faults by means of static analysis. According to this document, RDC metastability is a reset-dependent metastability caused by a prior reset assertion in one reset domain affecting flip-flops in different reset domains. According to this document, RDC metastability can be avoided by preventing the effects of the prior reset assertion transition from reaching the downstream flip-flops, which can be achieved by using blocking logic gates (called "reset clamps") in all paths from the prior reset assertion flip-flop to the data input terminals of the downstream flip-flops.

[0009] Document US 2021 / 0333852A1 is also an example of prior art in this field, as it discloses an RDC checker circuit configured to prevent metastability when data leaves the MCU used for the bus system, provided that the source domain undergoes a reset but the destination domain will not be reset. The RDC checker circuit is positioned to intercept output data from the MCU toward the bus system.

[0010] Other potentially relevant documents in this field include US 2013 / 0013950 A1, US 2003 / 0115497A1, US 2024 / 0192745 A1, and US 2024 / 0012446 A1.

[0011] Despite advancements in this field, there is a need for improved (e.g., robust) reset architectures for digital circuits (e.g., SoCs) that include multiple reset domains, specifically to address potential RDC timing issues associated with so-called software-triggered (SW-triggered) resets. Summary of the Invention

[0012] This embodiment describes a digital circuit including a communication bus interface, a first flip-flop and a second flip-flop, a reset register, a first logic gate, and a gating circuit. The communication bus interface receives and decodes bus signals and generates a reset initiator signal when a reset is requested. The first flip-flop is timed by a first clock signal and reset by a first reset signal. The second flip-flop is timed by a second clock signal, reset by a second reset signal, and receives data from the first flip-flop. The reset register is reset by the second reset signal and receives the reset initiator signal to generate a reset source signal. The first logic gate receives the second reset signal and a complement of the reset source signal, and asserts the first reset signal when either the second reset signal or the reset source signal is asserted. The gating circuit receives the reset initiator signal, the reset source signal, and the first clock signal, and generates the second clock signal by passing the first clock signal when both the reset initiator signal and the reset source signal are deasserted and by disabling the output when either the reset initiator signal or the reset source signal is asserted.

[0013] This embodiment describes a method for operating digital circuitry. The method includes providing a communication bus interface, a reset register, a first logic gate, and a gating circuit to the digital circuitry. At the communication bus interface, bus signals are received and decoded, and a reset initiator signal is generated and asserted to indicate a reset request. The reset initiator signal is received at the reset register, which generates a reset source signal. A second reset signal and a complement signal to the reset source signal are received at the first logic gate, which asserts the first reset signal when either the second reset signal or the reset source signal is asserted. The gating circuit receives the reset initiator signal, the reset source signal, and a first clock signal, and generates the second clock signal by passing the first clock signal when both the reset initiator signal and the reset source signal are deasserted and by disabling the output when either the reset initiator signal or the reset source signal is asserted.

[0014] This embodiment describes a reset control circuit for a digital circuit having a first reset domain and a second reset domain. The reset control circuit includes a reset register, a first logic gate, and a gating circuit. The reset register receives a reset initiator signal from a communication bus interface and generates a reset source signal, which is timed by a first clock signal and reset by a second reset signal associated with the second reset domain. The first logic gate receives the complement of the second reset signal and the reset source signal, and asserts the first reset signal associated with the first reset domain when the second reset signal or the reset source signal is asserted. The gating circuit receives the reset initiator signal, the reset source signal, and the first clock signal, and generates a gating clock signal by passing the first clock signal when both the reset initiator signal and the reset source signal are deasserted and by disabling the output when either the reset initiator signal or the reset source signal is asserted. Attached Figure Description

[0015] Now, one or more embodiments will be described by way of example only with reference to the accompanying drawings, in which:

[0016] Figure 1 This is an exemplary circuit diagram of interconnected flip-flops with different reset signals;

[0017] Figure 2 This is an exemplary circuit diagram of interconnected flip-flops with different reset signals and reset arcs;

[0018] Figure 3 It is an exemplary circuit diagram of a digital circuit that includes multiple reset domains;

[0019] Figure 4 This is an exemplary circuit diagram of a digital circuit including multiple reset domains and an improved reset architecture according to one or more embodiments of this specification;

[0020] Figure 5 This includes situations where a software-triggered reset is performed via the AMBA APB interface (Advanced Microcontroller Bus Architecture - Advanced Peripheral Bus - see ARM specification IHI 0024D (ID041221)). Figure 4 The timing diagram of the signal waveform of the circuit; and

[0021] Figure 6 This includes situations where a software-triggered reset is performed via the AMBA AHB interface (Advanced Microcontroller Bus Architecture - Advanced High Performance Bus - see ARM specification IHI 0033C (ID090921)). Figure 4 The timing diagram of the signal waveform of the circuit. Detailed Implementation

[0022] One or more embodiments provide digital circuits with an improved reset architecture and corresponding operating methods.

[0023] According to a first aspect of this specification, a digital circuit includes a communication bus interface configured to receive and decode one or more bus signals and generate a reset initiator signal based thereon. The reset initiator signal is asserted to indicate a reset request. The circuit includes at least one first flip-flop configured to be timed by a first clock signal and reset by a first reset signal. The circuit includes at least one second flip-flop configured to be timed by a second clock signal and reset by a second reset signal. The at least one second flip-flop is configured to receive a data signal from the at least one first flip-flop. The circuit includes a reset register configured to be reset by the second reset signal and configured to receive the reset initiator signal and generate a reset source signal based thereon. The circuit includes a first logic gate configured to receive a complement signal to the second reset signal and the reset source signal, and configured to assert the first reset signal in response to the second reset signal being asserted or the reset source signal being asserted. For example, in one embodiment, the first logic gate may be configured to assert the first reset signal in response to both the second reset signal and the reset source signal being asserted.

[0024] The circuit includes a gating circuit configured to receive a reset initiator signal, a reset source signal, and a first clock signal, and configured to generate a second clock signal at the output of the gating circuit by: passing the first clock signal to the output of the gating circuit in response to the reset initiator signal and the reset source signal being deasserted; and disabling the output of the gating circuit in response to either the reset initiator signal or the reset source signal being asserted.

[0025] Therefore, one or more embodiments can provide digital circuitry with an improved (e.g., robust) reset architecture that facilitates the resolution of potential timing issues associated with software-triggered (e.g., firmware-triggered, FW-triggered) resets, which are typically not captured in STA analysis. Additionally, one or more embodiments can provide a solution that is independent of process, voltage, and temperature (PVT) variations, or relies on an implementation with a low (e.g., minimal) number of logic gates, where all signal propagation paths (e.g., arcs) can be inspected by STA tools. For example, one embodiment can provide a solution that is independent of process, voltage, and temperature (PVT) variations and relies on an implementation with a low (e.g., minimal) number of logic gates, where all signal propagation paths (e.g., arcs) can be inspected by STA tools.

[0026] According to the features of the first aspect of this specification, the reset register is configured to be timed by a first clock signal.

[0027] According to the features of the first aspect of this specification, the gated circuit includes: a NOR (or NOT) logic gate configured to receive a reset initiator signal and a reset source signal, and to generate an intermediate output signal based thereon; and a clock gate unit configured to receive the intermediate output signal and a first clock signal, and to generate a second clock signal based thereon.

[0028] According to a first aspect of this specification, the digital circuit includes a reset synchronizer circuit configured to be timed by a first clock signal and reset by an asynchronous reset signal to generate a second reset signal.

[0029] According to the features of the first aspect of this specification, the reset register includes a register flip-flop configured to receive a first clock signal at a corresponding clock terminal, a second reset signal at a corresponding reset terminal, a reset initiator signal at a corresponding data input terminal, and generate a reset source signal at a corresponding data output terminal.

[0030] According to the features of the first aspect of this specification, the communication bus interface includes a slave interface configured to receive and decode signals encoded according to the Advanced Microcontroller Bus Architecture (AMBA) protocol (preferably, the Advanced Peripheral Bus (APB) protocol or the Advanced High Performance Bus (AHB) protocol).

[0031] According to the features of the first aspect of this specification, the communication bus interface is configured to assert a reset initiator signal during the access phase of an APB transaction.

[0032] According to the features of the first aspect of this specification, the communication bus interface is configured to assert a reset initiator signal during the data phase of an AHB transaction.

[0033] According to a second aspect of this specification, a method of operating a digital circuit according to one or more embodiments includes: receiving and decoding one or more bus signals at a communication bus interface, and generating a reset initiator signal based thereon, asserting the reset initiator signal to indicate a reset request; receiving the reset initiator signal at a reset register, and generating a reset source signal based thereon; receiving a second reset signal and a complement signal of the reset source signal at a first logic gate, and asserting a first reset signal in response to the second reset signal being asserted and / or the reset source signal being asserted; receiving the reset initiator signal, the reset source signal, and a first clock signal at a gating circuit, and generating a second clock signal at the output of the gating circuit by: passing the first clock signal to the output of the gating circuit in response to the reset initiator signal and the reset source signal being deasserted; and disabling the output of the gating circuit in response to either the reset initiator signal or the reset source signal being asserted.

[0034] In the following description, one or more specific details are set forth to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more of these specific details, or by other methods, components, materials, etc. In other instances, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of the embodiments will not be obscured.

[0035] The references to "embodiment" or "an embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Phrases that may appear in one or more points of this specification (such as "in an embodiment," "in one embodiment") do not necessarily refer to the same embodiment. Furthermore, particular configurations, structures, or features may be combined in one or more embodiments in any desired manner.

[0036] The headings and references used herein are provided for convenience only and therefore do not define the limits of protection or the scope of embodiments.

[0037] In the figures accompanying this document, similar parts or elements are indicated by similar reference numerals / labels unless the context otherwise indicates, and corresponding descriptions will not be repeated for the sake of brevity.

[0038] As expected, the purpose of one or more embodiments of this specification is to provide digital circuits with an improved reset architecture that facilitates the resolution of potential timing problems associated with software-triggered resets, which are typically not detected in STA analysis.

[0039] As a detailed description of exemplary embodiments, reference may initially be made to Figure 3 , Figure 3 This is an exemplary circuit diagram of a digital circuit 30 including multiple reset domains, where a reset can be triggered by software (specifically, by firmware). For example, the digital circuit 30 may be a microcontroller unit (MCU). Commonly, MCUs have modules that can be independently (e.g., individually) reset (referred to as SW reset) via firmware writing to dedicated bit registers. Therefore, multiple reset domains can coexist in a digital design. For example, when two reset domains are connected to each other and differ due to the presence of a software reset source, it is possible that the hold and / or set times of one or more flip-flops in the destination reset domain may violate the rules when the software reset signal is asserted in the source reset domain (even if the assertion of the software reset signal is synchronized with a clock signal, as referenced). Figure 2 (as described).

[0040] Figure 3The digital circuit 30 (e.g., an MCU) includes an interface 302 configured to receive signals (e.g., from a communication bus). For example, interface 302 may be a slave interface configured to connect to a bus operating according to the Advanced Microcontroller Bus Architecture (AMBA) Advanced Peripheral Bus (APB) protocol (in short, AMBA APB protocol or APB-only protocol). Interface 302 may have one or more inputs (e.g., Figure 3 The inputs, labeled X1, X2, X3, X4, X5, and X6, are used to receive one or more of the following signals: the paddr signal (e.g., an APB address bus from master to slave, which can be up to 32 bits wide); the pwrite signal (indicating an APB write access when asserted or high, and an APB read access when deasserted or low); the psel signal (indicating that the slave device is selected and data transfer is required); the penable signal (indicating the second and subsequent cycles of an APB transfer); the pwdata signal (e.g., driven by the APB master during a write cycle when the pwrite signal is high, and including write data, which can be 8, 16, or 32 bits wide); and the preready signal (e.g., for extending an APB transfer from the slave device). Interface 302 may have outputs (e.g., Figure 3 (marked as Y), this output is used to generate a reset initiator signal sw_rst1_wr based on one or more of the input signals (e.g., after decoding the input signals). The signal sw_rst1_wr can optionally be passed to the APB software reset register 306 via combinational circuitry 304 to write the value of a dedicated reset bit in register 306. Specifically, as... Figure 3As exemplified, the signal sw_rst1_wr can be received at the data input terminal D of the software reset trigger 308. The trigger 308 is timed, for example, by a first clock signal clk1 received at its clock terminal. The trigger 308 is reset, for example, by a first reset signal rst1_n (e.g., active low) generated as described below and received at its reset terminal R. The data output terminal Q of the trigger 308 generates an output signal, which is passed to a delay block 310, which in turn generates a reset source signal sw_rst1. An AND logic gate 312 receives the complement of the reset source signal sw_rst1 at its first input terminal and a second reset signal rst2_n (e.g., active low) at its second input terminal to generate an asynchronous reset signal as_rst (e.g., active low). The second reset signal rst2_n can be a master power-on reset (POR) of the system including the digital circuitry 30, or it can be generated by synchronizing an asynchronous reset of the entire digital circuitry 30 at a reset synchronizer (whose internal architecture may be known). It should be noted that the source reset signal sw_rst1 can be complemented before being passed to the AND gate 312, because the reset initiator signal sw_rst1_wr can have assertion logic that is complementary to the assertion logic of the low-active reset signal (e.g., the reset initiator signal sw_rst1_wr can be asserted as a high logic value to indicate that a reset must be performed, otherwise it is de-asserted as a low logic value). The asynchronous reset signal as_rst is passed to the reset terminal R of the reset synchronizer circuit 314 (whose internal architecture may be known). The reset synchronizer circuit 314 receives the system clock signal sys_clk at its clock terminal and a stable logic value (e.g., permanently high or "1") at its data input terminal D (e.g., via a connection to the power supply voltage). Therefore, the data output terminal Q of the reset synchronizer circuit 314 generates a first reset signal rst1_n, whose assertion edges (e.g., high-low edges) are synchronized with the system clock signal sys_clk. In other words, the reset release of the signal rst1_n (at the output of the reset synchronizer 314) is synchronized with the synchronizer's own clock signal sys_clk. Alternatively, an inverted clock signal (e.g., the complement of the system clock signal sys_clk) can be used for the synchronizer circuit 314, and in this case, the reset release of the signal rst1_n is synchronized with the falling edge of the system clock signal sys_clk.

[0041] like Figure 3As illustrated, the digital circuit 30 may include one or more first flip-flops 316 timed by a first clock signal clk1 and reset by a first reset signal rst1_n, and one or more second flip-flops 318 timed by a second clock signal clk2 and reset by a second reset signal rst2_n. The data output terminal Q1 of at least one of the first flip-flops 316 is coupled to the data input terminal D2 of at least one of the second flip-flops 318 (optionally via combination circuit 320) to form a data processing chain. The second clock signal clk2 may be the same as or different from the first clock signal clk1.

[0042] Therefore, basically, interface 302, register 306, and the first flip-flop 316 are implemented in the first reset domain 31 of digital circuit 30, while the second flip-flop 318 is implemented in the second reset domain 32 of digital circuit 30, with the boundary of the reset domain being... Figure 3 The first domain 31 (whose components are reset by the first reset signal rst1_n) is called the "source reset domain" and involves the SW reset source (that is, the signal SW_rst1, which can be generated in response to a firmware write to the APB on a dedicated bit in register 306) in addition to the second reset signal rst2_n. Therefore, the first reset domain 31 is reset based on a reset trigger from either the signal rst2_n or sw_rst1. The second domain 32 (whose components are reset by the second reset signal rst2_n) is called the "destination reset domain" and does not involve the software-triggered reset source sw_rst1. Therefore, the second reset domain 32 is reset based on a reset trigger from (only) the signal rst2_n. Thus, from the perspective of possible reset sources, the second domain 32 can be considered a subset of the first domain 31. The two domains 31 and 32 are connected to each other via at least one data path (e.g., from terminal Q1 of flip-flop 316 to terminal D2 of flip-flop 318), such that when signal sw_rst1 is asserted but signal rst2_n is not asserted, flip-flop 318 in the second reset domain 32 may violate hold / set, as long as data input D2 can be switched to near the edge of the second clock signal clk2, which is an undesirable event.

[0043] A possible solution to the hold / set timing violation problem described above involves gating the clock signal of flip-flop 318 in destination domain 32. In fact, if destination flip-flop 318 is not receiving clock signal clk2 when the source is reset, the hold / set timing problem can be prevented. In some cases, clock gating (also known as clock gate) can be implemented via firmware of digital circuitry 30 by writing to a dedicated register of the clock / reset control unit. Specifically, in the first step, the clock signal clk2 of destination reset domain 32 is gated (e.g., disabled) by writing to a dedicated register of the clock / reset control unit via firmware. In the second step, the SW reset of source reset domain 31 is implemented by writing to a dedicated register of the clock / reset control unit (e.g., register 306) via firmware. In the third step, the clock signal clk2 of destination reset domain 32 is re-enabled by writing to (e.g., overwriting) the corresponding dedicated register of the clock / reset control unit again via firmware.

[0044] However, gating the clock signal clk2 of the trigger 318 in the destination domain 32 via firmware may sometimes be unsuitable because, for example, gating the clock signal clk2 of the destination reset domain 32 in the first step may prevent further firmware execution (e.g., since the processor responsible for executing the firmware is implemented in the destination reset domain 32 itself). Furthermore, clock gating by firmware implies an additional configuration step for the firmware, thus increasing program memory and degrading system performance.

[0045] Therefore, solutions other than gating the clock signal of the destination domain via firmware are desired. Thus, one or more embodiments relate to having... Figure 4 The circuit diagram illustrates the digital circuit 40 of the reset architecture, wherein components or elements similar to those previously described are indicated by the same or similar reference numerals and are not described in detail hereafter.

[0046] and Figure 3 The circuits are different, in Figure 4 In the circuit, the software reset register 306 is implemented in the destination reset domain 32 instead of the source reset domain 31: therefore, the flip-flop 308 is reset by the second reset signal rst2_n (e.g., active low) received at its reset terminal R. Additionally, the flip-flop 308 can be timed by the first clock signal clk1 received at its clock terminal. The output signal sw_rst1 from register 306 does not need to be processed like... Figure 3In the same architecture, the signal is passed to the delay circuit or reset synchronizer circuit because it is generated by register 306, which belongs to the same clock domain as flip-flop 316. Therefore, the complement of the reset source signal sw_rst1 from the data output terminal Q of flip-flop 308 can be directly passed to the first input terminal of AND logic gate 312, which receives the second reset signal rst2_n (e.g., active low) at the second input terminal to generate the first reset signal rst1_n (e.g., active low). The second reset signal rst2_n can be generated by another reset synchronizer circuit 414. Specifically, the reset synchronizer circuit 414 receives the first clock signal clk1 at its clock terminal, a stable logic value (e.g., permanently high or "1") at its data input terminal D (e.g., via a connection to the power supply voltage), and another asynchronous reset signal rst_n (e.g., active low) at its reset terminal R. The second reset signal rst2_n can be the main power-on reset (POR) of the system including digital circuitry 40, or it can be generated by an asynchronous reset signal rst_n that synchronizes the entire digital circuitry 40 at reset synchronizer 414 (whose internal structure may be known). Therefore, the data output terminal Q of reset synchronizer circuit 414 generates the second reset signal rst2_n, whose assertion edge (e.g., high-low edge) is synchronized with the first clock signal clk1. Similar to... Figure 3 The circuit, Figure 4 The digital circuit 40 may include one or more first flip-flops 316 that are timed by a first clock signal clk1 and reset by a first reset signal rst1_n, and one or more second flip-flops 318 that are reset by a second reset signal rst2_n.

[0047] However, with Figure 3 The architectures are different. Figure 4The second flip-flop 318 in the architecture is timed by a gated clock signal clk1_gated generated based on the first clock signal clk1. Essentially, the gated clock signal clk1_gated is a copy of the first clock signal clk1, but is disabled (e.g., stably low) in response to a software-triggered reset requiring the first reset domain 31. For example, the gated clock signal clk1_gated can be disabled in response to the reset initiator signal sw_rst1_wr being asserted (e.g., high), or the reset source signal sw_rst1 being asserted (e.g., high), or both sw_rst1_wr and sw_rst1 being asserted (in other words, in response to either sw_rst1_wr or sw_rst1 being asserted). By doing so, the gated clock signal clk1_gated can be safely disabled as long as the reset signal rst1_n remains active (e.g., low) before the reset signal rst1_n switches to an active (e.g., low) level. If necessary, the time window can even be extended by delaying the release time of the clock gate (for example, by adding more chained triggers 308 inside module 306).

[0048] Specifically, in Figure 4 In the example, the gated clock signal clk1_gated can be generated at the output of clock gating unit 422 (e.g., including latches and AND gates in a manner known per se, and logically operating as an AND gate). Clock gating unit 422 can have a first input (e.g., a clock input) configured to receive the first clock signal clk1 and a second input (e.g., an enable input) configured to receive the output signal from NOR gate 424. NOR gate 424 can have a first input configured to receive a reset initiator signal sw_rst1_wr and a second input configured to receive a reset source signal sw_rst1, such that in response to either sw_rst1_wr or sw_rst1 being asserted (e.g., high), the output of NOR gate 424 is deasserted (e.g., low).

[0049] Advantageously, in Figure 4 In the architecture, all signal propagation arcs (e.g., paths) can be inspected by the STA tool during circuit design, including, for example, arcs in the SW reset path (e.g., from the output of register 306 through NOR logic gate 424 to clock gate 422, and from the output of register 306 through AND logic gate 312, flip-flop 316 to flip-flop 318). The reset register (306), the first logic gate (312), and the gate circuits (422, 424) can together form the reset control circuit of the digital circuit (40).

[0050] Figure 5 It includes Figure 4 The timing diagram of the signal waveforms in circuit 40 shows that the firmware-triggered reset is received via APB, and the signals are specifically: the first clock signal clk1, the signal APB indicating the current stage of the APB transaction, the reset initiator signal sw_rst1_wr, the source reset signal sw_rst1, the signal nor at the output of NOR logic gate 424, the first reset signal rst1_n, and the gate clock signal clk1_gated. It can be noted that the firmware-triggered reset generates a pulse in the signal sw_rst1_wr during the access phase ACC of the APB transaction (after the setup phase SET), and this pulse of the signal sw_rst1_wr is combined with the output signal sw_rst1 of register 306 through the NOR logic gate to generate the gate signal nor. This gate signal is used by the clock gating unit 422 to gate the clock signal of the destination reset domain 32 (the signal clk1_gated is disabled during reset assertions and releases).

[0051] Figure 6 It includes Figure 4 The timing diagram of the signal waveforms in circuit 40 shows that the firmware-triggered reset is received via AHB, and the specific signals are: the first clock signal clk1, the signal AHB indicating the current stage of the AHB transaction, the reset initiator signal sw_rst1_wr, the source reset signal sw_rst1, the signal nor at the output of the NOR logic gate 424, the first reset signal rst1_n, and the gate clock signal clk1_gated. It can be noted that during the data phase DAT of the AHB transaction (after the address phase ADD), the firmware-triggered reset generates a pulse in the signal sw_rst1_wr, and the usage of this pulse in the signal sw_rst1_wr is consistent with the reference. Figure 5 The descriptions are similar.

[0052] Therefore, one or more embodiments described herein present a simple and robust architecture for addressing reset setup / hold timing issues in digital circuits comprising multiple reset domains. Specifically, one or more embodiments may provide one or more of the following advantages: an architecture independent of PVT variant delay units; the possibility of checking all signal paths by STA tools, thus avoiding RDC or timing issues in the design; a hardware-based robust architecture for gating the clock signal of the destination reset domain; clock gating at reset assertion and reset release avoids reset-related timing issues, and the hardware implementation eliminates the steps of configuring and disabling the clock from firmware; a clear and optimized implementation (e.g., including a single NOR logic gate and a single clock gating unit), resulting in small area and low power consumption; an easily integrated solution; and a solution scalable to the AHB bus interface (decoding is practiced during the data phase of bus transactions) or any other system bus (e.g., OCP1.0, OCP2.0, etc.).

[0053] Without prejudice to the fundamental principles, details and embodiments may vary significantly from what has been described by way of example only without departing from the limits of protection.

[0054] The extent of protection is determined by the appended claims. Although the invention has been described with reference to exemplary embodiments, this description is not intended to be limiting. By referring to the description, those skilled in the art will understand various modifications and combinations of the exemplary embodiments and other embodiments of the invention. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A digital circuit, comprising: A communication bus interface configured to receive and decode one or more bus signals and generate a reset initiator signal based on the one or more bus signals, the reset initiator signal being asserted to indicate a reset request; At least one first flip-flop, the at least one first flip-flop being configured to be timed by a first clock signal and reset by a first reset signal; At least one second flip-flop, the at least one second flip-flop being configured to be timed by a second clock signal and reset by a second reset signal, the at least one second flip-flop being configured to receive a data signal from the at least one first flip-flop; A reset register, configured to be reset by the second reset signal, and configured to receive the reset initiator signal and generate a reset source signal based on the reset initiator signal; A first logic gate is configured to receive a complement signal of the second reset signal and the reset source signal, and is further configured to assert the first reset signal in response to the second reset signal being asserted or the reset source signal being asserted. as well as A gating circuit, configured to receive the reset initiator signal, the reset source signal, and the first clock signal, and further configured to generate a second clock signal at the output of the gating circuit by the following steps: In response to the reset initiator signal and the reset source signal being deasserted, the first clock signal is passed to the output of the gating circuit, and In response to the assertion of the reset initiator signal or the reset source signal, the output of the gating circuit is disabled.

2. The digital circuit according to claim 1, wherein, The first logic gate is also configured to assert the first reset signal in response to the second reset signal being asserted and the reset source signal being asserted.

3. The digital circuit according to claim 1, wherein, The reset register is configured to be timed by the first clock signal.

4. The digital circuit according to claim 1, wherein, The gate circuit includes: A NOR logic gate, configured to receive the reset initiator signal and the reset source signal, and based thereon generate an intermediate output signal; and A clock gating unit is configured to receive the intermediate output signal and the first clock signal, and generate the second clock signal based thereon.

5. The digital circuit of claim 1 further includes a reset synchronizer circuit, the reset synchronizer circuit being configured to be timed by the first clock signal and reset by an asynchronous reset signal to generate the second reset signal.

6. The digital circuit according to claim 1, wherein, The reset register includes a register flip-flop, which is configured to: The first clock signal is received at the corresponding clock terminal of the register flip-flop. The second reset signal is received at the corresponding reset terminal of the register flip-flop. The reset initiator signal is received at the corresponding data input terminal of the register flip-flop, and The reset source signal is generated at the corresponding data output terminal of the register flip-flop.

7. The digital circuit according to claim 1, wherein, The communication bus interface includes a slave interface configured to receive and decode signals encoded according to the Advanced Microcontroller Bus Architecture (AMBA) protocol, which is selected from the Advanced Peripheral Bus (APB) protocol or the Advanced High Performance Bus (AHB) protocol.

8. The digital circuit according to claim 7, wherein, The communication bus interface is configured to assert the reset initiator signal during the access phase of an APB transaction.

9. The digital circuit according to claim 7, wherein, The communication bus interface is configured to assert the reset initiator signal during the data phase of an AHB transaction.

10. A method of operating an electronic circuit, the method comprising: The digital circuit is provided with a communication bus interface, a reset register, a first logic gate, and a gate control circuit. Receive and decode one or more bus signals at the communication bus interface, and generate a reset initiator signal based on the one or more bus signals, asserting the reset initiator signal to indicate a reset request; The reset initiator signal is received at the reset register, and a reset source signal is generated based on the reset initiator signal. The first logic gate receives the second reset signal and the complement signal of the reset source signal, and asserts the first reset signal in response to the second reset signal being asserted or the reset source signal being asserted. The gate circuit receives the reset initiator signal, the reset source signal, and the first clock signal, and generates a second clock signal at the output of the gate circuit, the generation including: In response to the reset initiator signal and the reset source signal being deasserted, the first clock signal is passed to the output of the gated circuit; as well as In response to the assertion of the reset initiator signal or the reset source signal, the output of the gating circuit is disabled.

11. The method according to claim 10, wherein, In response to the second reset signal being asserted and the reset source signal being asserted, the first reset signal is asserted, and wherein, in response to the reset initiator signal and the reset source signal being asserted, the output of the gating circuit is disabled.

12. The method according to claim 10, wherein, The reset register is timed by the first clock signal.

13. The method according to claim 10, wherein, The gated circuit includes NOR logic gates and clock gate units, and the method further includes: At the NOR logic gate, an intermediate output signal is generated based on the reset initiator signal and the reset source signal; and At the clock gating unit, the second clock signal is generated based on the intermediate output signal and the first clock signal.

14. The method of claim 10, wherein, The digital circuit further includes a reset synchronizer circuit, and the method further includes: The asynchronous reset signal and the first clock signal are received at the reset synchronizer circuit, and the second reset signal is generated based on them.

15. A reset control circuit for a digital circuit having a first reset domain and a second reset domain, the reset control circuit comprising: A reset register, configured to receive a reset initiator signal from the communication bus interface of the digital circuit and generate a reset source signal based on the reset initiator signal, the reset register being further configured to be timed by a first clock signal and reset by a second reset signal associated with the second reset domain; A first logic gate is configured to receive a complement signal of the second reset signal and the reset source signal, and is further configured to assert a first reset signal associated with the first reset domain in response to assertion of the second reset signal or assertion of the reset source signal. as well as A gating circuit, configured to receive the reset initiator signal, the reset source signal, and the first clock signal, and further configured to generate a gating clock signal at the output of the gating circuit through the following steps: In response to the reset initiator signal and the reset source signal being deasserted, the first clock signal is passed to the output of the gated circuit; and In response to the assertion of the reset initiator signal or the assertion of the reset source signal, the output of the gating circuit is disabled.

16. The reset control circuit according to claim 15, wherein, The first reset domain is configured to be reset based on a reset trigger from the second reset signal and the reset source signal, and the second reset domain is configured to be reset independently of the reset source signal based on a reset trigger from the second reset signal.

17. The reset control circuit according to claim 15, wherein, The gated clock signal is provided to at least one flip-flop in the second reset domain, the at least one flip-flop being configured to receive a data signal from at least one additional flip-flop in the first reset domain.

18. The reset control circuit according to claim 15, wherein, The gate circuit includes: A NOR logic gate, configured to receive the reset initiator signal and the reset source signal, and based thereon generate an intermediate output signal; and A clock gating unit is configured to receive the intermediate output signal and the first clock signal, and generate the gated clock signal based thereon.

19. The reset control circuit of claim 15 further includes a reset synchronizer circuit, the reset synchronizer circuit being configured to be timed by the first clock signal and reset by an asynchronous reset signal to generate the second reset signal.

20. The reset control circuit according to claim 15, wherein, The communication bus interface includes a slave interface configured to receive and decode signals encoded according to the Advanced Microcontroller Bus Architecture (AMBA) protocol, which is selected from the Advanced Peripheral Bus (APB) protocol or the Advanced High Performance Bus (AHB) protocol.

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