Three-dimensional stacked thin-film battery multi-core processor system and energy consumption optimization method

Abstract

The application provides a three-dimensional stacked thin-film battery multi-core processor system, comprising: a processor computing layer containing a plurality of processor cores belonging to independent power domains, a wafer front interconnection layer and a wafer back interconnection layer; a back distributed thin-film battery array composed of a plurality of independent solid-state thin-film battery units arranged in a matrix, directly integrated on the processor computing layer and electrically connected with the wafer back interconnection layer through micro-silicon through holes penetrating the wafer; and an on-chip power router (OPR) integrated at least in the processor computing layer, electrically connected at least with the back distributed thin-film battery array and used for implementing dynamic scheduling energy distribution according to real-time load and spatial position of the processor cores. A corresponding energy consumption optimization control method is also provided. The application makes the power supply path of the thin-film battery to the processor core short, thereby improving energy utilization efficiency, reducing energy consumption and solving heat dissipation.

Description

Technical Field

[0001] This invention belongs to the fields of semiconductor integrated circuits, advanced packaging and micro power supply technology, and specifically relates to a multi-core processor system, especially a multi-core processor system using solid-state thin-film batteries. Specifically, it relates to a system and control method for three-dimensional heterogeneous integration of solid-state thin-film batteries with multi-core processors and peripheral devices, and realizing on-chip intelligent dynamic power routing and adaptive matching of load impedance. Background Technology

[0002] With the rapid deployment of large-scale, multimodal AI technologies, scenarios such as cloud-based model training, high-concurrency inference, and edge-side intelligent sensing are generating massive demands for computing power. Neural network operations possess large-scale parallel computing characteristics, including numerous homogeneous computational tasks such as convolution and matrix multiplication / addition, placing extremely high demands on the parallel processing capabilities of processors. Due to physical process limitations, single-core processors cannot simply rely on increasing clock speed to continuously increase computing power, failing to meet the demands of large-scale parallel computing for AI tasks. Against this backdrop, multi-core processor architecture has become the mainstream technology and is widely used. Multi-core processors integrate multiple independent computing cores within a single chip, relying on parallel execution mechanisms to simultaneously schedule multiple computing tasks, effectively improving overall computing throughput and optimizing task concurrency processing capabilities. Simultaneously, the multi-core architecture allows for flexible allocation of computing resources, adapting to application scenarios such as cloud-based intelligent computing centers, edge devices, and terminal intelligent hardware.

[0003] Modern high-performance multi-core processors (CPU / GPU) and microsystems face at least three core challenges in energy efficiency management: 1. Severe parasitic losses in power transmission networks (PDNs): Traditional electronic systems mainly use board-level batteries for power supply, and the power management integrated circuit (PMIC) is far from the logic chip and sensor. The power transmission path crosses traditional PCB traces, packaging substrates and multiple front-side metal layers, introducing significant parasitic resistance and inductance, resulting in extremely severe AC / DC overlap losses and voltage drop (IR Drop) under high-frequency and high-current conditions.

[0004] 2. Transient response lag and limited micro-voltage regulation: The computational load of each logic core in a multi-core processor changes rapidly within nanoseconds. Traditional centralized power supply response speeds are typically in the microsecond range, making it impossible to achieve nanosecond-level transient power consumption response, and it is also difficult to achieve fine-grained dynamic voltage and frequency regulation (DVFS) at the level of individual logic cores.

[0005] 3. Ripple interference caused by high pulse currents from peripheral devices: Miniature sensors, wireless communication modules, and other peripheral devices in IoT and highly integrated systems typically require transient high pulse currents when waking from sleep mode or performing high-frequency sampling. Traditional centralized power networks, due to long power supply distances and input impedance mismatches, cannot effectively suppress such transient ripples, leading to low overall system efficiency and, in severe cases, even interfering with the normal operation of the logic core.

[0006] While on-chip thin-film / micro-capacitors can be used for transient decoupling, their areal energy density is extremely low (typically only in the range of 0.01~1 μWh / cm²) due to their dielectric polarization or electrostatic energy storage principles. Even with a 3D trench topology, their highest areal energy density typically does not exceed 0.03 mWh / cm², only able to handle power consumption surges within microseconds (μs), after which severe voltage collapse occurs due to energy depletion. Furthermore, traditional coin cells (thickness > 1 mm) and pouch cells (lacking rigid support and posing a risk of thermal expansion) cannot withstand the high temperatures and high vacuum environments of semiconductor back-end packaging, and therefore cannot meet the stringent requirements of on-chip heterogeneous integration.

[0007] Based on existing technologies, we hope to provide multi-core processor systems with higher energy efficiency and corresponding energy consumption optimization methods. Summary of the Invention

[0008] The purpose of this invention is to solve the problems of high path loss and low transient power consumption matching efficiency under multiple loads in existing semiconductor systems. This invention proposes a system that integrates a reconfigurable solid-state thin-film battery array with a multi-core processor / peripheral device in a three-dimensional heterogeneous package. Utilizing a "pincer" spatial layout and on-chip power routing algorithms, it eliminates long-distance trace loss (IR Drop). Due to the shortened vertical power supply distance, IR Drop is reduced by more than 90%. The solid-state thin-film battery cells, in conjunction with on-chip capacitors, achieve nanosecond-level transient decoupling and provide continuous high-power smoothing buffers from milliseconds to seconds, suppressing voltage ripple and collapse across the entire frequency band.

[0009] According to one aspect of the present invention, a three-dimensional stacked thin-film battery multi-core processor system is provided, characterized in that it comprises: The processor computing layer includes at least one processor core belonging to an independent power domain, a wafer front interconnect layer, and a wafer back interconnect layer; The rear-side distributed thin-film battery array, which consists of multiple independent solid-state thin-film battery cells (μ-TFB) arranged in a matrix, is directly integrated on the processor computing layer and electrically connected to the back-side interconnect layer of the wafer through through-silicon vias (μ-TSV) penetrating the wafer, is used to provide low-loss power supply for the local area of ​​the processor core; An on-chip power router (OPR) is integrated at least in the processor computing layer and is electrically connected at least to the rear-mounted distributed thin-film battery array. The OPR is used to dynamically schedule energy allocation based on the real-time load and spatial location of the processor core.

[0010] Preferably, the processor computing layer includes multiple processor cores belonging to independent power domains.

[0011] Preferably, the rear-distributed thin-film battery array is composed of multiple independent micro solid-state thin-film battery cells (μ-TFB) arranged in a matrix.

[0012] Preferably, the solid-state thin-film battery cells in the back-distributed thin-film battery array are directly integrated on the back side of the processor computing layer wafer.

[0013] Preferably, the processor system further includes an interposer, on which the processor computing layer is stacked, and the interposer integrates at least a high-capacity thin-film battery pack, a global power management bus, and a signal transmission network.

[0014] Preferably, the on-chip energy router is integrated in the intermediary layer.

[0015] Preferably, the on-chip energy router is electrically connected to the high-capacity thin-film battery pack in the interposer layer.

[0016] Preferably, the high-capacity thin-film battery pack within the interposer layer is connected to the wafer front interconnect layer of the processor computing layer or the on-chip power router via a large-size through-silicon via, in order to cope with sudden high-load power consumption demands of the cluster.

[0017] Preferably, the orthographic projection of the solid-state thin-film battery cell onto the processor computing layer corresponds to at least one local high-power hotspot area of ​​a processor core.

[0018] Preferably, the orthographic projection relationship between the solid-state thin-film battery cell and the local high-power hotspot area is set in a manner that minimizes power transmission path loss.

[0019] Preferably, the high-capacity thin-film battery pack within the back-distributed thin-film battery array and / or the interlayer is grown in situ on the substrate via physical vapor deposition.

[0020] Preferably, the high-capacity thin-film battery pack in the back-side distributed thin-film battery array and / or the interlayer is an all-solid-state inorganic thin-film battery, whose positive electrode layer is at least one of LiCoO2, lithium manganese oxide, high-nickel ternary, lithium iron phosphate, lithium-rich manganese-based, high-voltage spinel or Prussian blue system, and whose electrolyte layer is at least one of LiPCON, lithium lanthanum zirconium oxide, titanium aluminum oxide phosphate, lithium chlorine phosphorus sulfur, lithium germanium phosphorus sulfur, and lithium chlorine zirconium.

[0021] Preferably, the wafer of the processor computing layer has a thinning region, and the micro-silicon via penetrates the thinning region of the wafer and is directly aligned with the power gate or reference power supply pad of the processor core in an array.

[0022] Preferably, the on-chip power router is connected to the solid-state thin-film battery cell via a transistor switch matrix composed of low on-resistance MOSFETs, and the transistor switch matrix is ​​integrated in the front metal layer or interposer layer of the processor computing layer.

[0023] According to another aspect of the present invention, a method for optimizing and controlling the power consumption of a processor system according to claims 1 to 12 is also provided, characterized by comprising the following steps: a. The on-chip power router is used to monitor and predict the computing load status of each processor core in the multi-core processor and the triggering interrupt signals of peripheral devices in real time; b. The on-chip energy router reads the power, ripple and temperature data of each solid-state thin-film battery cell in the rear distributed thin-film battery array in real time; c. The on-chip energy router executes a spatial proximity routing algorithm based on the spatial location of the target load, and calculates the optimal battery series-parallel topology based on the transient input impedance of the target load; d. Drive the corresponding transistor switch array to dynamically adjust the series and parallel connection relationship between the solid-state thin-film battery cells, so as to realize the distribution of electrical energy to the target load through the shortest path.

[0024] Preferably, the target load is one or more processor cores.

[0025] Preferably, the target load is a peripheral device.

[0026] Preferably, in step d, electrical energy is distributed flexibly to the target load via the shortest vertical path.

[0027] Preferably, step d includes the following steps: When a processor core is detected to enter a high-load, high-power state, the on-chip energy router controls the switching network to reconfigure the corresponding solid-state thin-film battery cells into a parallel mode in order to reduce the internal resistance of the power supply and match the transient high current demand of the load. When a high-voltage wake-up signal is detected for an external device, the on-chip energy router controls the switching network to reconfigure the corresponding solid-state thin-film battery cells into a series configuration to increase the output voltage; and When the local energy consumption rate of the rear distributed thin-film battery array exceeds a preset threshold, the on-chip energy router initiates a two-level collaborative replenishment mechanism, controlling the intermediate layer high-capacity thin-film battery pack to smoothly charge and replenish the rear solid-state thin-film battery unit through the global power bus.

[0028] The thin-film battery multi-core processor system based on three-dimensional stacking and the corresponding energy consumption optimization control method provided by this invention place the thin-film battery on the path closest to the processor core, shortening the energy transmission path. Furthermore, the specific energy consumption optimization control method further shortens the power supply path from the thin-film battery to the processor core, thereby improving energy utilization efficiency and reducing energy consumption. The thin-film battery multi-core processor system and corresponding energy consumption optimization control method provided by this invention can be used for mass production at a controllable cost. In practical applications, it can save energy, improve the computing performance of multi-core processor systems, and reduce technical bottlenecks that cannot be overcome due to heat dissipation issues. It is easy to apply to actual production lines and can yield considerable economic benefits. Attached Figure Description

[0029] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A schematic diagram of the architecture of a three-dimensional stacked thin-film battery multi-core processor system according to a first embodiment of the present invention is shown. Figure 2 A schematic diagram of the physical structure of an all-solid-state thin-film battery in a three-dimensional stacked thin-film battery multi-core processor system is shown according to a preferred embodiment of the present invention. Figure 3 A schematic diagram of the charge-discharge curves of an Al / LiCoO2 / LiCPON / Li / Cu all-solid-state thin-film battery in a three-dimensional stacked thin-film battery multi-core processor system according to a preferred embodiment of the present invention is shown. Figure 4 This diagram illustrates a circuit topology of a reconfigurable thin-film battery array and an on-chip energy router in a three-dimensional stacked thin-film battery multi-core processor system according to a first embodiment of the present invention; and Figure 5A schematic diagram of an energy consumption optimization control method for a three-dimensional stacked thin-film battery multi-core processor system according to a first embodiment of the present invention is shown. Detailed Implementation

[0030] To better illustrate the technical solution of the present invention, the present invention will be further described below with reference to the accompanying drawings.

[0031] Combination Figures 1 to 4 The embodiments shown are as understood by those skilled in the art.

[0032] Those skilled in the art will understand that, in a preferred embodiment, the overall three-dimensional integrated architecture of the multi-core processor system provided by the present invention can be referenced. Figure 1 Specifically, the multi-core processor system includes a processor layer, a peripheral device layer (micromechanical MEMS sensor / wireless radio frequency communication module), a distributed thin-film battery array layer directly connected to the back of the processor, and a distributed high-capacity thin-film battery array nested within the silicon interposer. Electrical interconnections are achieved between and within each layer via micro-bumps, C4 solder balls, or through-silicon vias (μ-TSVs) penetrating the silicon substrate.

[0033] More specifically, specific implementation methods are provided to illustrate different embodiments.

[0034] Example 1: Physical characteristics and fabrication process of all-solid-state thin-film battery cell (μ-TFB) This embodiment employs an all-solid-state thin-film battery with an Al (current collector) / LiCoO2 (cathode) / LiPCON (electrolyte) / Li (anode) / Cu (current collector) configuration. A typical three-dimensional stacked physical structure is shown in the attached figure. Figure 2 As shown.

[0035] Its typical preparation process and parameters are as follows: Back current collector fabrication: A back current collector layer (such as Ti / Au, Cr / Cu / Ti, etc.) can be deposited first using magnetron sputtering / thermal evaporation technology on the back side of the thinned processor silicon wafer as the substrate, followed by the deposition of a positive electrode film on its surface. Alternatively, an ultra-thin inorganic flexible high-conductivity metal such as Al foil (less than 50 micrometers thick) can be used as the substrate, with its geometry customizable by adaptive topology tailoring based on the independent power domain boundaries on the back side of the processor. After fabrication on the independent substrate, the battery is heterogeneously integrated to the back side of the silicon wafer using three-dimensional bonding technology and electrically connected to the silicon wafer via μ-TSV. Other metals such as Ti and Cu can also be used.

[0036] Cathode Thin Film Deposition: A LiCoO2 cathode thin film is deposited on the substrate using magnetron sputtering. A lithium cobalt oxide target with a purity of 99.9% is selected, and the oxygen to argon flow rate ratio in the working gas is controlled to be 0.1–10:1. The preferred sputtering power is 500 W, maintaining a substrate-target spacing of 10 cm. The vacuum chamber gas pressure is maintained within the range of 2–5 × 10⁻² Pa during fabrication, precisely depositing to a film thickness of 1–100 μm. Besides LiCoO2, other cathode materials that can be used include lithium manganese oxide, high-nickel ternary lithium, lithium iron phosphate, lithium-rich manganese-based lithium, high-voltage spinel, or Prussian blue.

[0037] Solid-state electrolyte film deposition: On the surface of the already formed positive electrode film, a lithium nitrogen phosphate composite (LiPCON) inorganic all-solid-state electrolyte film is continuously deposited in situ using magnetron sputtering. A mixed target of lithium phosphate and lithium carbonate is selected, and the flow rate ratio of nitrogen to argon in the working gas is controlled at 0.1~10:1. The sputtering power is also set to 500W, the substrate-target distance is 10cm, and the working gas pressure is maintained at 2-5*10-2Pa. The deposition thickness is 0.5-5μm. Other oxides and halides can also be used to expand the deposition process, such as lithium lanthanum zirconium oxide, titanium aluminum oxide, lithium chlorine phosphorus sulfide, lithium germanium phosphorus sulfide, and lithium chlorine zirconium oxide.

[0038] Negative electrode and top current collector construction: On the all-solid electrolyte layer, a lithium metal or lithium alloy negative electrode film with a thickness of 0.5-20μm and a highly conductive copper metal top current collector film with a thickness of 1-5μm are sequentially deposited using thermal evaporation technology.

[0039] The charge-discharge behavior curves of the all-solid-state thin-film battery prepared by this process are attached. Figure 3 As shown, it exhibits extremely high reversible chemical capacity and a stable electrochemical voltage plateau at a discharge rate of 0.5C.

[0040] This battery exhibits the following core technological features in semiconductor heterogeneous integration: Size compatibility: The physical thickness of the entire unit is strictly controlled within 1mm (typical thickness can be less than 20μm), which can be easily transplanted to the back of the silicon wafer and the interposer through chemical mechanical thinning technology, and directly connected to the front metal layer of the CPU using μ-TSV.

[0041] Significant Energy Density Advantages: Its area energy density is adjustable within the range of 0.1 to 20 mWh / cm². In contrast, traditional on-chip thin-film capacitors, based on electrostatic energy storage, typically have an energy density in the range of 0.01 to 1 μWh / cm², and even with the most advanced 3D micro-trench topology, it does not exceed 0.03 mWh / cm². The energy density of this invention's battery is 2 to 4 orders of magnitude higher than that of thin-film capacitors, providing continuous high-power buffering at the millisecond to second level, and the operating voltage fluctuation during discharge is less than 2% (achieving plateau-level zero-ripple output), overcoming the inherent defect of capacitor voltage collapsing exponentially over time (consistent with the formula V(t) = V0 et / RC).

[0042] Reflow soldering resistance: The all-solid-state inorganic structure completely eliminates the risk of organic chemical expansion or thermal runaway. It can perfectly withstand multiple soldering peak temperature shocks of 260~290° in flip-chip and 3D stacked packaging, and there is no chemical evolution at the heterogeneous interfaces of the internal film layers, and no performance degradation.

[0043] Environmental stability: No deformation or material volatilization occurs under the high vacuum conditions of semiconductor manufacturing at <0.01Pa, and after being stored continuously for 1000 hours in the extreme heat environment of logic chips at 150°C, the overall structure of the battery still maintains chemical inertness and electrochemical integrity.

[0044] Example 2: Topology and Dynamic Cooperative Control Logic of On-Chip Energy Router (OPR) The circuit topology of the control system described in this embodiment is shown in the attached figure. Figure 4 As shown, the corresponding dynamic adaptive energy distribution and impedance matching control flow is attached. Figure 5 As shown.

[0045] The entire control loop operates in a closed loop within the three-dimensional integrated energy efficiency management chip. The specific steps are as follows: Demand Awareness and Transient Assessment: The control flow is triggered from "Start". The OPR core integrated on the right side captures the pipeline send command status of each logic core and interrupt wake-up requests from peripheral devices such as sensors and RF communication modules in real time through the on-chip core power demand interface. When a local core (such as core Ci) is detected to be about to experience a power surge (such as entering Turbo overclocking state), the system immediately activates the status assessment loop.

[0046] Status Monitoring and Topology Decision-Making: The battery status monitor reads the remaining charge, real-time output voltage, and temperature data of each μ-TFB cell in the left-side reconfigurable array in real time via a green signal line. If the battery status parameters are within the normal safety window, the impedance matching calculation unit will immediately calculate the dynamic complex conjugate input impedance of the target load. At the same time, the global power routing control logic locks the thin-film battery cell μ-TFBi directly opposite the back of the core based on the principle of "shortest spatial geometric distance".

[0047] Array drive and switch reconfiguration: The OPR converts the logic instruction into a high-level gate drive signal and sends it to the switch matrix driver to control the transistor switch array on the left, which is composed of low on-resistance MOSFETs, to switch on and off.

[0048] When calculations show that the core requires low voltage and high current (such as high-throughput deep learning multiply-accumulate operations), the control switch matrix instantly switches several adjacent μ-TFB cells on the back side to parallel reconfiguration mode to reduce the equivalent internal resistance of the power network by a factor of two and match the high current requirements. When the external high-voltage sensor sends a sampling trigger, the control switch matrix switches to series reconstruction mode to provide a high-voltage wake-up signal.

[0049] The on-chip power OPR also integrates a level shifter and a buck DC-DC micro-converter. When the μ-TFB array is reconfigured into a high-voltage series mode, the voltage is reduced to the rated voltage required by the processor core through the converter, or the high voltage is directly routed to the power domain of peripheral devices that require high voltage wake-up, thereby achieving electrical isolation between power domains.

[0050] Two-stage energy replenishment and closed-loop iteration: The optimized electrical energy is transmitted through an ultrashort vertical μ-TSV path (corresponding to the attached...) Figure 1 The physical architecture directly injects power into the target logic domain, completely avoiding the trace losses of traditional planar circuits and effectively eliminating voltage drops. In the closed-loop monitoring loop, if an abnormal power consumption rate (insufficient local power) is detected in the back-side μ-TFB, the OPR automatically initiates a two-stage collaborative replenishment mechanism. This involves activating the power input selector and controlling the distributed high-capacity thin-film battery pack integrated within the lower silicon interposer to smoothly replenish power to the back-side μ-TFB via a large-size TSV and a global power bus, thereby maintaining the AC / DC power balance of the entire on-chip micro power network.

[0051] Furthermore, referring to the above Figures 1 to 5As will be understood by those skilled in the art in the illustrated embodiments, in a preferred embodiment, the wafer may be made of materials such as silicon, ceramic, or gallium nitride, and these variations are all within the scope of protection of this invention. Further, in a preferred embodiment, the wafer is used to carry the processor core; in a variation, other carriers may be used to carry the processor core, and the wafer is replaced by these other carriers; these variations are all within the scope of protection of this invention.

[0052] Furthermore, those skilled in the art will understand that the rear-distributed thin-film battery array is used to provide a localized, dynamically low-loss power supply for the processor core.

[0053] Furthermore, those skilled in the art will understand that, in a variation, the On-Chip Power Router (OPR) is integrated into the processor computing layer or intermediary layer. The OPR is electrically connected to the rear-mounted distributed thin-film battery array and the high-capacity thin-film battery pack in the intermediary layer, respectively, and is used to dynamically schedule energy allocation using a switch matrix / transistor switch array based on the real-time load and spatial location of each processor core. This illustrates the electrical connection and dynamic scheduling relationship between the rear-mounted micro-thin-film battery array, the intermediary layer integrating the high-capacity thin-film batteries, and the OPR.

[0054] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A multi-core processor system for thin-film batteries based on three-dimensional stacking, characterized in that, include: The processor computing layer includes at least one processor core belonging to an independent power domain, a wafer front interconnect layer, and a wafer back interconnect layer; The rear-side distributed thin-film battery array, which consists of multiple independent solid-state thin-film battery cells (μ-TFB) arranged in a matrix, is directly integrated on the processor computing layer and electrically connected to the back-side interconnect layer of the wafer through through-silicon vias (μ-TSV) penetrating the wafer, is used to provide low-loss power supply for the local area of ​​the processor core; An on-chip power router (OPR) is integrated at least in the processor computing layer and is electrically connected at least to the rear-mounted distributed thin-film battery array. The OPR is used to dynamically schedule energy allocation based on the real-time load and spatial location of the processor core.

2. The processor system according to claim 1, characterized in that, It also includes an interposer, on which the processor computing layer is stacked, and the interposer integrates at least a high-capacity thin-film battery pack, a global power management bus, and a signal transmission network.

3. The processor system according to claim 2, characterized in that, The on-chip energy router is integrated in the intermediary layer.

4. The processor system according to claim 2, characterized in that, The on-chip energy router is electrically connected to the high-capacity thin-film battery pack in the interposer layer.

5. The processor system according to any one of claims 2 to 4, characterized in that, The high-capacity thin-film battery pack within the interposer layer is connected to the wafer front interconnect layer of the processor computing layer or the on-chip power router via a large-size through-silicon via, in order to cope with sudden high-load power consumption demands of the cluster.

6. The system according to any one of claims 1 to 5, characterized in that: The orthographic projection of the solid-state thin-film battery cell onto the processor computing layer corresponds to at least one local high-power hotspot area of ​​a processor core.

7. The processor system according to claim 6, characterized in that, The orthographic projection relationship between the solid-state thin-film battery unit and the local high-power hotspot area is set in a way that minimizes power transmission path loss.

8. The processor system according to any one of claims 1 to 7, characterized in that, The high-capacity thin-film battery pack within the back-distributed thin-film battery array and / or the interlayer is grown in situ on the substrate via physical vapor deposition.

9. The processor system according to any one of claims 1 to 8, characterized in that, The high-capacity thin-film battery pack in the back-side distributed thin-film battery array and / or the intermediate layer is an all-solid-state inorganic thin-film battery. Its positive electrode layer is at least one of LiCoO2, lithium manganese oxide, high-nickel ternary, lithium iron phosphate, lithium-rich manganese-based, high-voltage spinel or Prussian blue system, and its electrolyte layer is at least one of LiPCON, lithium lanthanum zirconium oxide, titanium aluminum oxide phosphate, lithium chlorine phosphorus sulfur, lithium germanium phosphorus sulfur, and lithium chlorine zirconium.

10. The processor system according to any one of claims 1 to 9, characterized in that, The wafer of the processor computing layer has a thinning region, and the micro-silicon vias penetrate the thinning region of the wafer and are directly aligned with the power gate or reference power supply pad of the processor core in an array.

11. The processor system according to any one of claims 1 to 10, characterized in that: The on-chip power router is connected to the solid-state thin-film battery cell via a transistor switch matrix composed of low on-resistance MOSFETs. The transistor switch matrix is ​​integrated in the front metal layer or interposer layer of the processor computing layer.

12. A method for optimizing and controlling the energy consumption of a processor system according to claims 1 to 12, characterized in that, Includes the following steps: a. The on-chip power router can monitor and predict the computational load status of each processor core in the multi-core processor and the triggering interrupt signals of peripheral devices in real time; b. The on-chip energy router reads the charge, ripple, and temperature data of each solid-state thin-film battery cell in the rear-mounted distributed thin-film battery array in real time; c. The on-chip energy router executes a spatial proximity routing algorithm based on the spatial location of the target load, and calculates the optimal battery series-parallel topology based on the transient input impedance of the target load; d. Drive the corresponding transistor switch array to dynamically adjust the series and parallel connection relationship between the solid-state thin-film battery cells, so as to realize the distributed flexible distribution of electrical energy to the target load through the shortest vertical path.

13. The control method according to claim 12, characterized in that, Steps c and d include the following steps: When a processor core is detected to enter a high-load, high-power state, the on-chip energy router controls the switching network to reconfigure the corresponding solid-state thin-film battery cells into a parallel mode in order to reduce the internal resistance of the power supply and match the transient high current demand of the load. When a high-voltage wake-up signal is detected for an external device, the on-chip power router controls the switch network to reconfigure the corresponding solid-state thin-film battery cells into a series mode to increase the output voltage. as well as When the local energy consumption rate of the rear distributed thin-film battery array exceeds a preset threshold, the on-chip energy router initiates a two-level collaborative replenishment mechanism, controlling the intermediate layer high-capacity thin-film battery pack to smoothly charge and replenish the rear solid-state thin-film battery unit through the global power bus.

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