A parameter determination method of a storage card, an electronic device, and a storage medium

Abstract

The application discloses a parameter determination method of a storage card, an electronic device and a storage medium. The method comprises the following steps: acquiring an original address range of the storage card based on a nominal capacity of the storage card; performing read-write detection for several times in the original address range, so as to search out a capacity boundary address from the original address range, wherein, in the original address range, addresses smaller than the capacity boundary address are all valid read-write addresses, and at least one address larger than the capacity boundary address is an invalid read-write address; and determining a real capacity of the storage card based on the capacity boundary address. In the foregoing manner, the real capacity of the storage card can be determined, and data damage or system abnormality caused by data writing into a virtual label area can be avoided.

Description

Technical Field

[0001] This application relates to the field of memory card technology, and in particular to a method for determining the parameters of a memory card, an electronic device, and a storage medium. Background Technology

[0002] When a memory card leaves the factory, its actual physical media capacity is usually slightly larger than the marked nominal capacity. However, the memory card's internal firmware performs block alignment during power-on initialization, which may cause a discrepancy between the actual usable capacity and the actual physical media capacity. If the system performs read and write operations according to the nominal capacity, it may not be able to access the physical media in the high address range of the memory card, leading to data corruption or system malfunction. Summary of the Invention

[0003] The main technical problem addressed by this application is to provide a method for determining the parameters of a memory card, an electronic device, and a storage medium that can determine the true capacity of the memory card and avoid data corruption or system malfunction caused by writing data to a falsely labeled area.

[0004] To address the aforementioned technical problems, the first aspect of this application provides a method for determining the parameters of a memory card, comprising: obtaining the original address range of the memory card based on its nominal capacity; performing several read / write tests within the original address range to search for capacity boundary addresses within the original address range, wherein addresses smaller than the capacity boundary addresses within the original address range are valid read / write addresses, and at least one address larger than the capacity boundary addresses is an invalid read / write address; and determining the actual capacity of the memory card based on the capacity boundary addresses.

[0005] In this context, all addresses in the smallest storage unit at the boundary where the capacity boundary address is located are valid read / write addresses, and at least one address in the next smallest storage unit at the boundary is an invalid read / write address.

[0006] The process of performing read / write detection within the original address range to search for capacity boundary addresses includes: using the original address range as the initial search range and selecting an initial detection address from the original address range; performing read / write detection on the detection address to obtain the read / write detection result, where the read / write detection result indicates whether the detection address is a valid or invalid read / write address; determining a new search range based on the read / write detection result of the detection address; if the current preset conditions are not met, selecting a new detection address from the new search range and re-executing the read / write detection and subsequent steps for the detection address until the preset conditions are met; if the current preset conditions are met, selecting the capacity boundary address from the latest search range.

[0007] The process of selecting an initial detection address from the original address range includes: obtaining the difference between the upper address in the original address range and a preset offset, and using it as the initial detection address.

[0008] Specifically, determining a new search range based on the read / write detection results of the detection address includes: in response to the read / write detection results indicating that the detection address is a valid read / write address, using the detection address as the lower address of the new search range and using the upper address of the current search range as the upper address of the new search range; and / or, in response to the read / write detection results indicating that the detection address is an invalid read / write address, using the lower address of the current search range as the lower address of the new search range and using the detection address as the upper address of the new search range.

[0009] The preset conditions include at least one of the following: the difference between the upper and lower addresses of the new search range is less than or equal to the capacity of the smallest storage unit, or the number of iterations exceeds the preset number.

[0010] The read / write detection within the original address range includes: for each detection address within the original address range, after writing preset test data to the detection address, performing a read operation to obtain the read data; in response to the read data being the same as the preset test data, determining that the read / write detection result is that the detection address is a valid read / write address; in response to the read data being different from the preset test data, determining that the read / write detection result is that the detection address is an invalid read / write address.

[0011] The process of determining the actual capacity of a memory card based on its capacity boundary address includes: obtaining the reserved capacity; and using the difference between the capacity corresponding to the capacity boundary address and the reserved capacity as the safe capacity of the memory card.

[0012] Among them, the reserved capacity is greater than the maximum address deviation that can be generated by the internal firmware of the memory card performing block alignment operation, and / or the reserved capacity is an integer power of the preset value in bytes.

[0013] The method for determining the parameters of the memory card further includes: obtaining the response status of the memory card in multiple historical read operations; and updating the response base time of the memory card for read operations based on the response status of multiple historical read operations, wherein the response base time is used to determine whether the memory card's response to the read operation has timed out.

[0014] Specifically, based on the response status of multiple historical read operations, the response baseline time of the memory card for read operations is updated, including: if the response status of multiple historical read operations is at least a first number of consecutive normal responses, the response weight is reduced; if the response status of multiple historical read operations is at least a second number of consecutive timeouts without response, the response weight is increased; the response baseline time is weighted using the response weight to obtain the updated response baseline time.

[0015] To address the aforementioned technical problems, a second aspect of this application provides an electronic device comprising a memory and a processor. The memory stores program instructions, and the processor executes the program instructions to implement the method provided in the first aspect.

[0016] To address the aforementioned technical problems, a third aspect of this application provides a computer-readable storage medium storing program instructions that can be executed by a processor to implement the method provided in the first aspect.

[0017] The beneficial effects of this application are as follows: Unlike existing technologies, it performs several read / write tests within the original address range to search for capacity boundary addresses within that range. This proactively identifies address deviations caused by firmware block alignment operations within the memory card. Furthermore, based on these capacity boundary addresses, the true capacity of the memory card can be determined, preventing data corruption or system malfunctions caused by writing data to falsely labeled areas. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this application, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Among them: Figure 1 This is a flowchart illustrating one implementation method of the memory card parameter determination method provided in this application; Figure 2 This is a flowchart illustrating another embodiment of the method for determining the parameters of a memory card provided in this application; Figure 3 This is a schematic diagram of the framework structure of one embodiment of the memory card parameter determination device provided in this application; Figure 4 This is a schematic diagram of the framework structure of one embodiment of the electronic device provided in this application; Figure 5 This is a schematic diagram of the framework structure of one embodiment of the computer-readable storage medium provided in this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] It should be noted that the embodiments of this application contain descriptions involving "first," "second," etc., which are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0021] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the figures). If the specific posture changes, the directional indication will also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "many" in this document means two or more. Moreover, the term "at least one" in this document means any combination of at least two of any one or more of a plurality of objects. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0024] This application provides the following embodiments, and each embodiment will be described in detail below.

[0025] Please see Figure 1 , Figure 1 This is a flowchart illustrating one embodiment of the method for determining the parameters of a memory card provided in this application. The method includes: S11: Obtain the original address range of the memory card based on its nominal capacity.

[0026] This embodiment is used to determine the true capacity of a memory card by actively detecting read and write operations to find the true boundaries of the physical media of the memory card, rather than passively trusting the nominal value. Memory cards include, but are not limited to, MMC cards, SM cards, and SD cards. In one specific embodiment, the memory card is an SD card. The original address range refers to the logical address interval with the nominal capacity of the memory card as the upper limit. For example, the logical address interval is 0-2GB.

[0027] S12: Perform several read / write checks within the original address range to search for the capacity boundary address within the original address range.

[0028] In one embodiment, each read / write test involves performing a write-then-read operation on a target detection address within the original address range. The target detection address for the next read / write test is determined based on the result of the previous read / write test. The read / write test result for the target detection address indicates whether the target detection address is an invalid or valid read / write address. Specifically, for each target detection address, preset test data is written to that target detection address, a read operation is performed, and the read data is obtained. If the read data is the same as the preset test data, the read / write test result is determined to be a valid read / write address; if the read data is different from the preset test data, the read / write test result is determined to be an invalid read / write address. The initial target detection address can be any detection address within the original address range.

[0029] In one specific embodiment, determining the target detection address for the next read / write detection based on the previous read / write detection result includes: selecting a detection address that is smaller or larger than the previous target detection address as the target detection address for the next read / write detection, based on the previous read / write detection result. For example, in response to the previous read / write detection result indicating that the previous target detection address was an invalid read / write address, a detection address smaller than the previous target detection address is selected as the target detection address for the next read / write detection. Conversely, in response to the previous read / write detection result indicating that the previous target detection address was a valid read / write address, a detection address larger than the previous target detection address is selected as the target detection address for the next read / write detection. Wherein, the smaller the detection address, the smaller the capacity corresponding to the detection address; the larger the detection address, the larger the capacity corresponding to the detection address.

[0030] Based on several test results, the capacity boundary address is determined. Within the original address range, addresses smaller than the capacity boundary address are considered valid read / write addresses, while at least one address larger than the capacity boundary address is considered an invalid read / write address. The preset test data can be a fixed pattern of 0xAA55 or a pseudo-random sequence.

[0031] In one specific embodiment, finding the capacity boundary address can be achieved by selecting several detection addresses with a preset step size, and sequentially performing read and write checks at each detection address until the capacity boundary address is found. The preset step size can be a multiple of the capacity of the smallest storage unit; for example, if the capacity of the smallest storage unit is 4KB, the preset step size can be 40KB.

[0032] For example, the order of original addresses from smallest to largest is used as the forward direction, and the order of original addresses from largest to smallest is used as the backward direction. Starting from the uppermost address in the original address range, a new original address is selected as the detection address at a preset step size. For example, if the original address range is 0-2GB, the first original address 400KB away from 2GB is selected as the first detection address, and the first detection address is smaller than the first original address. It is determined whether the first detection address is a valid read / write address. If not, a second original address 400KB away from the first detection address is selected as the new first detection address, following the order of addresses from largest to smallest. If yes, in one embodiment, the first detection address can be directly used as the capacity boundary address. In another embodiment, it can be determined whether the original address adjacent to the first detection address in the forward direction is a valid read / write address. If not, the first detection address is used as the capacity boundary address; if yes, the preset step size can be reduced, and a new original address is selected again from the uppermost address in the original address range at a preset step size as the new first detection address. Read / write detection is performed on the new first detection address. The above steps are repeated until the capacity boundary address is found.

[0033] In another specific embodiment, a binary search strategy can also be adopted. First, intermediate addresses are tested, and the search interval is narrowed based on the verification results until a preset condition is met, thereby quickly converging to the capacity boundary. Specifically, the original address range is used as the initial search range, and an initial detection address is selected from the original address range; read / write detection is performed on the detection address to obtain the read / write detection result, where the read / write detection result indicates whether the detection address is a valid or invalid read / write address; based on the read / write detection result of the detection address, a new search range is determined; if the preset condition is not currently met, a new detection address is selected from the new search range, and the read / write detection and subsequent steps for the detection address are re-executed until the preset condition is met; if the preset condition is currently met, the capacity boundary address is selected from the latest search range.

[0034] In one embodiment, the initial detection address can be randomly selected, or the difference between the upper address in the original address range and a preset offset can be used as the initial detection address. For example, the preset offset can be set to the capacity of the smallest storage unit (e.g., 4KB) or a multiple of the smallest storage unit's capacity. The new detection address can be any address within the new search range; in a specific embodiment, the new detection address is the middle address within the new search range. By using the difference between the upper address and the preset offset as the initial detection address, the initial detection position can be accurately located near the high-order valid region of the original address range, while effectively avoiding the tail metadata or reserved areas of the file system, thus improving the success rate and efficiency of the first detection.

[0035] In one embodiment, determining a new search range based on the read / write detection results of the detected address includes: responding to the read / write detection result indicating that the detected address is a valid read / write address, using the detected address as the lower address of the new search range, and using the upper address of the current search range as the upper address of the new search range; the lower address is less than the upper address. Responding to the read / write detection result indicating that the detected address is an invalid read / write address, using the lower address of the current search range as the lower address of the new search range, and using the detected address as the upper address of the new search range. In the first round of searching, the current search range is the original address range.

[0036] For example, the current search range is [400MB, 800MB], and the detection address is 600MB. If the detection address is a valid read / write address, then [600MB, 800MB] will be used as the new search range; if the detection address is an invalid read / write address, then [400MB, 600MB] will be used as the new search range.

[0037] In this embodiment, the lower or upper address of the search range is updated based on the read / write detection results, which accurately narrows the search interval. This ensures that each iteration eliminates half or more of the invalid address space, thereby significantly improving the convergence speed of capacity boundary localization. This dynamic adjustment mechanism avoids blind searching, ensuring that the search range always closely surrounds the actual physical capacity boundary. This facilitates the rapid determination of the accurate capacity boundary within a limited number of iterations, reduces the number of invalid read / write operations on the memory card's physical medium, and thus protects the memory card's lifespan.

[0038] The detection process stops when preset conditions are met, and the capacity boundary address is selected from the latest search range. The preset conditions include at least one of the following: the difference between the upper and lower addresses of the new search range is less than or equal to the capacity of the smallest storage unit, or the number of iterations exceeds a preset number.

[0039] In one embodiment, any address within the latest search range can be used as the capacity boundary address, for example, the next lower address within the latest search range can be used as the capacity boundary address; or the middle address of the latest search range can be used as the capacity boundary address. Preferably, the next lower address within the latest search range is used as the capacity boundary address.

[0040] In one embodiment, the preset condition is that the difference between the upper and lower addresses of the new search range is less than or equal to the capacity of the smallest storage unit. For example, the second search range is [672KB, 688KB], with a range width greater than the capacity of the smallest storage unit (4KB). The second search address is determined to be 680KB. Assuming the second search address is a valid read / write address, the third search range is determined to be [680KB, 688KB], with a range width greater than 4KB. The third search address is determined to be 684KB. Assuming the third search address is an invalid read / write address, the fourth search range is determined to be [680KB, 684KB]. At this point, the range width is equal to 4KB, satisfying the preset condition. The iteration stops, and 680KB is used as the capacity boundary address. In this embodiment, at least one address in the next smallest storage unit after the boundary smallest storage unit is an invalid read / write address. If there is another smallest storage unit after the next smallest storage unit, then all addresses in that smallest storage unit are invalid read / write addresses.

[0041] In one embodiment, if the number of iterations exceeds a preset number, the next lower address in the newly determined search range is used as the capacity boundary address. In this embodiment, the next smallest storage unit after the boundary smallest storage unit may contain at least one invalid read / write address, or all addresses may be valid read / write addresses.

[0042] In one embodiment, the preset conditions include the difference between the upper and lower addresses of the new search range being less than or equal to the capacity of the smallest storage unit and the number of iterations exceeding a preset number. Iteration stops when either of these conditions is met.

[0043] By setting the relationship between the search range width and the capacity of the smallest storage unit as a termination condition, the accuracy of capacity boundary positioning can match the granularity of hardware physical characteristics. This avoids meaningless micro-segmentation within a single physical block, thereby improving search efficiency and reducing unnecessary flash memory read / write operations, which helps extend the lifespan of the storage medium. By setting a maximum number of iterations as a fallback termination condition, the system can promptly exit the search process when encountering non-standard capacity cards or abnormal responses, avoiding prolonged system suspension or deadlock, further ensuring the stability and real-time performance of the storage management process.

[0044] Understandably, the methods for determining capacity boundary addresses provided above are only some examples, and other methods can also be used, which are not listed here.

[0045] S13: Determine the actual capacity of the memory card based on the capacity boundary address.

[0046] In one embodiment, the capacity corresponding to the capacity boundary address can be directly used as the actual capacity of the memory card. In other embodiments, the capacity boundary address can be shifted to the next address, and the resulting address can be used as the actual boundary address. The actual capacity of the memory card can then be obtained based on the capacity corresponding to the actual boundary address. Specifically, data is written according to the smallest storage unit. All data in the smallest storage unit must be erased before writing. Therefore, all addresses in the smallest boundary storage unit where the capacity boundary address is located are valid read / write addresses. After determining the capacity boundary address, if the capacity boundary address is located in the middle of the smallest boundary storage unit, either address at one end of the smallest boundary storage unit can be used as the actual boundary address. That is, the address in the smallest boundary storage unit that is closest to or furthest from the upper address in the original address range is selected as the actual boundary address, and the capacity corresponding to the actual boundary address is used as the actual capacity. If the capacity boundary address is at one end of the smallest boundary storage unit, the capacity corresponding to the capacity boundary address is used as the actual capacity. Preferably, the address in the smallest boundary storage unit that is furthest from the upper address in the original address range can be used as the actual boundary address.

[0047] In other implementations, a reserved capacity can be set, and the difference between the capacity corresponding to the capacity boundary address and the reserved capacity can be used as the safe capacity of the memory card; or, the difference between the actual boundary address and the reserved capacity can be used as the safe capacity of the memory card.

[0048] In one embodiment, the reserved capacity is greater than the maximum address deviation that can be generated by the internal firmware of the memory card performing block alignment operations, and / or the reserved capacity is an integer power of a preset value in bytes. For example, the value of the reserved capacity can range from 4KB to 64KB, with a preferred value of 32KB. By ensuring that the reserved capacity is greater than the maximum address deviation, the write logical address does not fall on the physical erase boundary of the flash memory, preventing address overflow after firmware alignment offset.

[0049] Since firmware address offset, block alignment, and wear leveling all use power-of-2 lengths for boundary division, the default value can be 2. This avoids situations where the reserved space is not a power of 2, and the tail boundary gets stuck on a non-power-of-2 boundary during firmware offset alignment, easily leading to issues such as crossing reserved areas and address out-of-bounds errors. Reserved capacity is set to 2. nThe tail boundary coincides exactly with the flash erase block boundary, ensuring that the maximum firmware offset will not exceed the reserved area. The reserved capacity can also serve as a buffer area for firmware garbage collection (GC) inside the memory card, reducing the write and erase operations on available data areas during GC, improving GC efficiency and extending the life of the memory card.

[0050] The above scheme sequentially selects multiple target detection addresses within the original address range, performing a write-then-read operation at each target detection address. The target detection address for the next read / write detection is determined based on the result of the previous read / write detection, thus enabling rapid search for capacity boundary addresses. Performing a write-then-read operation at the target detection address yields the read / write detection result. Based on this result, it can be determined whether the target detection address is a valid or invalid read / write address. This proactively identifies address deviations caused by firmware block alignment operations within the memory card. Furthermore, based on the capacity boundary address, the true capacity of the memory card can be determined, preventing data corruption or system anomalies caused by writing data to falsely labeled areas.

[0051] Please see Figure 2 , Figure 2 This is a flowchart illustrating another embodiment of the method for determining the parameters of a memory card provided in this application. The method includes: S21: Obtain the response status of the memory card during multiple historical read operations.

[0052] After sending a single command (CMD) read operation instruction, the system starts a timer to monitor the memory card's response. The memory card's response status includes response time and whether a response was received. If the memory card does not return a valid response within the response baseline time, it is considered a timeout. Multiple historical read operations can be adjacent to the current acquisition time.

[0053] S22: Update the memory card's response base time for read operations based on the response status of multiple historical read operations.

[0054] In one embodiment, the response baseline time is used to determine whether the memory card's response to a read operation times out. If the response to multiple historical read operations is at least a first number of consecutive normal responses, the response weight is decreased; if the response to multiple historical read operations is at least a second number of consecutive timeouts without a response, the response weight is increased. The response baseline time is weighted using the response weights to obtain an updated response baseline time. The first and second numbers can be set as needed and are not specifically limited here; the response weight is greater than 1. In other embodiments, the response baseline time can also be updated to a preset time associated with the response status based on the response status of multiple historical read operations.

[0055] In one embodiment, to prevent the response weight from decreasing or increasing indefinitely, a constraint range for the response weight is set, for example, it can be set to 1.5~5.0. Understandably, before each read operation, the response baseline time for the current read operation can be updated based on the response status of multiple historical read operations, thus achieving dynamic updating of the response baseline time.

[0056] Steps S21 and S22 can be executed before, after, or simultaneously with any of steps S11-S13, and their execution order is not limited.

[0057] In this embodiment, by adjusting the response base time, false timeouts caused by memory card response delays can be effectively reduced, and the system's compatibility in low-quality or high-load memory card environments can be improved.

[0058] It is understood that in the above method of specific implementation, the order in which each step is written does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0059] Please see Figure 3 , Figure 3 This is a schematic diagram of the framework structure of one embodiment of the memory card parameter determination device provided in this application.

[0060] The memory card parameter determination device 30 includes a first acquisition module 31, a boundary determination module 32, and a capacity determination module 33. The acquisition module 31 is used to acquire the original address range of the memory card based on its nominal capacity. The boundary determination module 32 is used to perform several read / write tests within the original address range to search for capacity boundary addresses within the original address range. Each read / write test involves writing to a target detection address within the original address range and then reading it. The target detection address for the next read / write test is determined based on the result of the previous read / write test. The read / write test result of the target detection address indicates whether the target detection address is an invalid or valid read / write address. Within the original address range, addresses smaller than the capacity boundary address are valid read / write addresses, and at least one address larger than the capacity boundary address is an invalid read / write address. The capacity determination module 33 determines the actual capacity of the memory card based on the capacity boundary addresses.

[0061] The parameter determination device 30 for the memory card may further include a second acquisition module and a time update module. The second acquisition module is used to acquire the response status of the memory card in multiple historical read operations. The time update module is used to update the response reference time of the memory card for the read operation based on the response status of multiple historical read operations. The response reference time is used to determine whether the memory card's response to the read operation has timed out.

[0062] The above scheme performs read / write tests within the original address range to search for capacity boundary addresses. This proactively identifies address deviations caused by firmware block alignment operations within the memory card. Furthermore, based on these capacity boundary addresses, the true capacity of the memory card can be determined, preventing data corruption or system malfunctions caused by writing data to falsely labeled areas.

[0063] It should be noted that the memory card parameter determination device and the memory card parameter determination method provided in the above embodiments belong to the same concept. The specific operation methods of each module and unit have been described in detail in the method embodiments and will not be repeated here. In practical applications, the memory card parameter determination device provided in the above embodiments can allocate the above functions to different functional modules as needed, that is, divide the internal structure of the device into different functional modules to complete all or part of the functions described above. This is not a limitation here.

[0064] Please see Figure 4 , Figure 4 This is a schematic diagram of the framework structure of one embodiment of the electronic device provided in this application.

[0065] The electronic device 40 includes a memory 41 and a processor 42, which are coupled to each other. The memory 41 stores program instructions, and the processor 42 executes the program instructions stored in the memory 41 to implement the steps of any of the above method embodiments. In a specific implementation scenario, the electronic device 40 may include, but is not limited to, a microcomputer or a server. In addition, the electronic device 40 may also include mobile devices such as laptops and tablets, which are not limited here.

[0066] Specifically, processor 42 controls itself and memory 41 to implement the steps in any of the above method embodiments. Processor 42 may also be referred to as a CPU (Central Processing Unit). Processor 42 may be an integrated circuit chip with signal processing capabilities. Processor 42 may also be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. A general-purpose processor may be a microprocessor or any conventional processor. Furthermore, processor 42 may be implemented using integrated circuit chips.

[0067] Please see Figure 5 , Figure 5 This is a schematic diagram of the framework structure of one embodiment of the computer-readable storage medium provided in this application.

[0068] The computer-readable storage medium 50 stores program instructions 51 that can be executed by a processor, the program instructions 51 being used to implement the steps in any of the above method embodiments.

[0069] The storage media mentioned in this article include: USB flash drives, external hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media that can store program code.

[0070] This application also provides a computer program product comprising a computer program that, when executed by a processor, can implement the steps described in any of the foregoing method embodiments. Specifically, the computer program product can be a software or program product containing a computer program, capable of running on a computing device or stored on any available medium.

[0071] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0072] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0073] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0074] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0075] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods in the various embodiments of this application.

[0076] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, and thus stored in a computer-readable storage medium for execution by a computing device, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Therefore, this application is not limited to any particular hardware and software combination.

[0077] If the technical solution of this application involves personal information, the product using this technical solution has clearly informed the user of the personal information processing rules and obtained the user's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using this technical solution has obtained the user's separate consent before processing the sensitive personal information, and also meets the requirement of "express consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set up to inform users that they have entered the scope of personal information collection and that personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed that they have agreed to the collection of their personal information; or on the personal information processing device, with clear signs / information informing users of the personal information processing rules, authorization is obtained from the individual through pop-up information or by asking the individual to upload their personal information; wherein, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.

[0078] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A method for determining parameters of a memory card, characterized in that, include: Based on the nominal capacity of the memory card, obtain the original address range of the memory card; Several read / write checks are performed within the original address range to search for capacity boundary addresses within the original address range. In the original address range, addresses smaller than the capacity boundary address are valid read / write addresses, and at least one address larger than the capacity boundary address is an invalid read / write address. The actual capacity of the memory card is determined based on the capacity boundary address.

2. The method according to claim 1, characterized in that, Each read / write test involves performing a write-then-read operation on the target detection address within the original address range, and the target detection address corresponding to the next read / write test is determined based on the result of the previous read / write test. The read / write test result of the target detection address indicates whether the target detection address is an invalid read / write address or a valid read / write address. And / or, each address in the smallest storage unit of the boundary where the capacity boundary address is located is a valid read / write address, and at least one address in the next smallest storage unit of the boundary minimum storage unit is an invalid read / write address.

3. The method according to claim 1, characterized in that, The step of performing read / write detection within the original address range to search for capacity boundary addresses within the original address range includes: The original address range is used as the initial search range, and the initial detection address is selected from the original address range; The detection address is subjected to read / write detection to obtain the read / write detection result of the detection address, wherein the read / write detection result indicates whether the detection address is a valid read / write address or an invalid read / write address; Based on the read / write detection results of the detected address, a new search range is determined; If the preset conditions are not met, a new detection address is selected from the new search range, and the read / write detection of the detection address and subsequent steps are re-executed until the preset conditions are met. Under the current conditions that are met, the capacity boundary address is selected from the latest search range.

4. The method according to claim 3, characterized in that, The step of selecting the initial detection address from the original address range includes: The difference between the upper address in the original address range and the preset offset is obtained and used as the initial detection address.

5. The method according to claim 3, characterized in that, The determination of a new search range based on the read / write detection results of the detected address includes: In response to the read / write detection result indicating that the detected address is a valid read / write address, the detected address is used as the lower address of the new search range, and the upper address of the current search range is used as the upper address of the new search range. And / or, in response to the read / write detection result indicating that the detected address is an invalid read / write address, the lower address of the current search range is used as the lower address of the new search range, and the detected address is used as the upper address of the new search range.

6. The method according to claim 3, characterized in that, The preset conditions include at least one of the following: the difference between the upper and lower addresses of the new search range is less than or equal to the capacity of the smallest storage unit, and the number of iterations exceeds a preset number.

7. The method according to claim 1, characterized in that, The read / write detection within the original address range includes: For each detection address within the original address range, after writing preset test data to the detection address, a read operation is performed to obtain the read data; In response to the fact that the read data is the same as the preset test data, the read / write detection result is determined to be that the detection address is a valid read / write address; In response to the fact that the read data is different from the preset test data, the read / write detection result is determined to be that the detected address is an invalid read / write address.

8. The method according to claim 1, characterized in that, Determining the actual capacity of the memory card based on the capacity boundary address includes: Obtain reserved capacity; The difference between the capacity corresponding to the capacity boundary address and the reserved capacity is taken as the safe capacity of the memory card.

9. The method according to claim 8, characterized in that, The reserved capacity is greater than the maximum address deviation that can be generated by the internal firmware of the memory card performing block alignment operations, and / or the reserved capacity is an integer power of a preset value in bytes.

10. The method according to claim 1, characterized in that, The method further includes: Obtain the response status of the memory card during multiple historical read operations; Based on the response status of multiple historical read operations, the response baseline time of the memory card for read operations is updated, wherein the response baseline time is used to determine whether the memory card's response to a read operation has timed out.

11. The method according to claim 10, characterized in that, The process of updating the memory card's response time base for read operations based on the response status of multiple historical read operations includes: If the response to the multiple historical read operations is at least a first number of consecutive normal responses, the response weight is reduced. If the response to the multiple historical read operations is that there are at least a second number of consecutive timeouts without a response, the response weight is increased. The response baseline time is weighted using the response weights to obtain the updated response baseline time.

12. An electronic device, characterized in that, The method includes a memory and a processor, wherein the memory stores program instructions and the processor executes the program instructions to implement the method according to any one of claims 1 to 11.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores program instructions that can be executed by a processor to implement the method of any one of claims 1 to 11.

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