A data processing method of a high-bandwidth flash memory controller and related products

Abstract

The application provides a data processing method of a high-bandwidth flash memory controller and related products, monitors a physical state of a high-bandwidth flash memory chip, obtains multi-dimensional medium state parameters, and acquires historical running data of the high-bandwidth flash memory chip; based on the multi-dimensional medium state parameters and the historical running data, the medium state of the high-bandwidth flash memory chip at a future time is predicted, a predicted medium state and an uncertainty index of the predicted medium state are obtained; based on the predicted medium state and the uncertainty index, a multi-objective solution is performed on an error correction code rate and a cache partition weight of the high-bandwidth flash memory chip at the future time, a target error correction code rate and a target cache partition weight are obtained; based on the target error correction code rate and the target cache partition weight, joint adjustment is performed on error correction configuration and cache configuration of the high-bandwidth flash memory chip, so as to realize error correction and cache collaborative control, the error correction failure rate and the cache access invalidation rate can be reduced, and therefore the system service quality is improved.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a data processing method and related products for a high-bandwidth flash memory controller. Background Technology

[0002] High-bandwidth flash (HBF) chips achieve extremely high data throughput through three-dimensional stacking and high-speed interfaces, and have gradually become the core storage medium for data centers and edge computing devices. As storage density increases, storing multiple bits of data per unit (such as four-layer QLC or five-layer PLC) has become mainstream, but this has also led to a sharp worsening of data retention errors and read interference problems, placing higher demands on the data processing capabilities of storage controllers.

[0003] However, existing flash memory controllers typically employ a fixed low-density parity-check (LDPC) bitrate and a static cache partitioning strategy. The offline-configured fixed LDPC bitrate and static cache partitioning cannot dynamically respond to workload changes and media degradation. Under media degradation or read-intensive loads, error correction failure rates can easily increase and read hit rates can decrease, affecting the quality of service of the system. Summary of the Invention

[0004] This invention provides a data processing method and related products for a high-bandwidth flash memory controller, in order to solve the problem that related technologies using fixed LDPC code rates and static cache partitions for HBF management are prone to increased error correction failure rates and decreased read hit rates, which affect the quality of system services.

[0005] In a first aspect, embodiments of the present invention provide a data processing method for a high-bandwidth flash memory controller, comprising: The physical state of high-bandwidth flash memory chips is monitored to obtain multi-dimensional media state parameters, and historical operating data of high-bandwidth flash memory chips are acquired. Based on multidimensional media state parameters and historical operating data, the media state of high-bandwidth flash memory chips at future moments is predicted, resulting in the predicted media state and the uncertainty index of the predicted media state. Based on the predicted medium state and uncertainty indicators, a multi-objective solution is performed to calculate the error correction code rate and cache partition weight of a high-bandwidth flash memory chip at future moments, so as to obtain the target error correction code rate and target cache partition weight. Based on the target error correction code rate and the target cache partition weight, the error correction configuration and cache configuration of the high-bandwidth flash memory chip are jointly adjusted to achieve collaborative control of error correction and cache.

[0006] In a second aspect, embodiments of the present invention provide a high-bandwidth flash memory controller, comprising: The monitoring module is used to monitor the physical state of the high-bandwidth flash memory chip, obtain multi-dimensional media state parameters, and acquire historical operating data of the high-bandwidth flash memory chip. The prediction module is used to predict the media state of a high-bandwidth flash memory chip at a future time based on multi-dimensional media state parameters and historical operating data, and to obtain the predicted media state and the uncertainty index of the predicted media state. The solution module is used to perform multi-objective solutions for the error correction code rate and cache partition weight of a high-bandwidth flash memory chip at future moments based on the predicted medium state and uncertainty indicators, so as to obtain the target error correction code rate and target cache partition weight. The adjustment module is used to jointly adjust the error correction configuration and cache configuration of the high-bandwidth flash memory chip based on the target error correction code rate and the target cache partition weight, so as to achieve collaborative control of error correction and cache.

[0007] Thirdly, embodiments of the present invention provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described method.

[0008] Fourthly, embodiments of the present invention provide a readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described method.

[0009] Fifthly, embodiments of the present invention provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the above-described method.

[0010] In one solution provided by the aforementioned high-bandwidth flash memory controller data processing method and related products, the physical state of the high-bandwidth flash memory chip is monitored in real time, and the future media state is predicted by combining historical operating data. This allows the control process to anticipate the degradation trend of the flash memory media due to changes in usage time and workload, avoiding response lag caused by static configuration based solely on the current state. Then, based on the predicted media state and the uncertainty indicators of the prediction results, the error correction code rate and cache partitioning strategy are dynamically optimized for future moments. This enables the error correction capability configuration and cache resource allocation to adaptively adjust according to changes in media reliability and business needs. It improves data reliability when the media degradation is high and optimizes cache resource utilization efficiency when data access pressure changes. Therefore, this solution enhances the adaptability of the high-bandwidth flash memory controller to changes in media state and load, improves flash memory data reliability and cache resource utilization efficiency, reduces error correction failure rate and cache access failure rate, thereby improving system service quality. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the data processing system of a high-bandwidth flash memory controller according to an embodiment of the present invention; Figure 2 This is a schematic flowchart of a data processing method for a high-bandwidth flash memory controller according to an embodiment of the present invention; Figure 3 yes Figure 2 A schematic diagram of the implementation process of step S20; Figure 4 yes Figure 2 A schematic diagram of the implementation process of step S30; Figure 5 This is a schematic diagram of the structure of a Bayesian optimization collaborative decision-making module in one embodiment of the present invention; Figure 6 yes Figure 2 A schematic diagram of the implementation process of step S40; Figure 7 This is a schematic diagram of the layered architecture of the system in one embodiment of the present invention; Figure 8 This is a comparative schematic diagram of one embodiment of the present invention with other solutions; Figure 9 yes Figure 1 A schematic diagram of a medium-to-high bandwidth flash memory controller; Figure 10 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. It should also be understood that, as used in this specification and the appended claims, the term "and / or" refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0015] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0016] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0017] To illustrate the technical solution of the present invention, specific embodiments are described below.

[0018] In existing flash memory controller designs, fixed LDPC bitrates and static cache partitioning strategies are typically used. However, the fixed LDPC bitrates and static cache partitioning set offline cannot dynamically respond to changes in workload and media degradation. Under media degradation or read-intensive loads, the fixed bitrate leads to an increase in error correction failure rate, and the static cache allocation leads to a decrease in read hit rate. This results in increased overall system latency and wasted power, which seriously affects the system's Quality of Service (QoS).

[0019] Therefore, a dynamic adjustment mechanism based on set thresholds is considered to dynamically adjust the LDPC bitrate or cache resources, improving the adaptability of coding error correction and cache partitioning strategies. However, this type of dynamic adjustment scheme is based solely on threshold comparison, ignoring the randomness and uncertainty of flash memory cell states changing with multi-dimensional parameters such as temperature and aging (represented by P / E cycles, i.e., programming / erase cycles), and cannot predict quantification risks. Moreover, the adjustment strategy is lagging and coarse, often triggering error correction upgrades only after a large number of errors have occurred, failing to achieve proactive resource scheduling and leading to fluctuations in service quality.

[0020] Furthermore, in the existing flash controller architecture, the error correction engine and cache manager operate independently, lacking a collaborative optimization mechanism. Increasing the strength of LDPC error correction will consume more decoding latency and power consumption, and the decrease in cache hit rate will also increase access latency. Optimizing the two in isolation cannot achieve the global system optimization, which can easily lead to an imbalance in the allocation of system resources (such as power consumption, latency, and bandwidth), resulting in overall performance being limited by the weakest link.

[0021] In summary, existing technologies have limitations in error correction and cache management for high-bandwidth flash memory controllers, being static, passive, and isolated, making it difficult to continuously provide stable and efficient data processing services in complex environments where flash memory media dynamically degrades.

[0022] To address these issues, this invention provides a data processing method for a high-bandwidth flash memory controller, a high-bandwidth flash memory controller, an electronic device, a storage medium, and a program product. For example, by real-time monitoring of the physical state of the high-bandwidth flash memory chip and acquiring historical operating data, the future media state and its uncertainty indicators are predicted based on multi-dimensional media state parameters and historical operating data. Then, based on the prediction results, a multi-objective solution is performed for the error correction code rate and cache partition weight at the future time. Finally, the error correction configuration and cache configuration are jointly adjusted based on the solved target error correction code rate and target cache partition weight. By introducing a forward-looking prediction of the future media state, the error correction and cache configurations can proactively adapt to the dynamic degradation trend of the media, overcoming the shortcomings of existing technologies where fixed LDPC code rates and static cache partitioning strategies cannot dynamically respond to workload changes and media degradation. This effectively reduces the risk of decreased error correction failure rate and cache read hit rate under media degradation or read-intensive loads, significantly improving system service quality.

[0023] The data processing method for a high-bandwidth flash memory controller provided in this embodiment of the invention can be applied to applications such as... Figure 1 The data processing system (hereinafter referred to as the system) of the high-bandwidth flash memory controller shown includes a high-bandwidth flash memory chip and a high-bandwidth flash memory controller, wherein the high-bandwidth flash memory chip communicates with the high-bandwidth flash memory controller via a cable.

[0024] The high-bandwidth flash memory controller integrates at least one flash memory channel, and each flash memory channel corresponds to at least one high-bandwidth flash memory chip. During actual operation, the high-bandwidth flash memory controller monitors the physical state of the high-bandwidth flash memory chip, such as chip temperature and read voltage distribution, to obtain multi-dimensional media state parameters and acquire historical operating data of the high-bandwidth flash memory chip. This historical operating data includes at least the multi-dimensional media state parameters and bit error rate during the historical operation of the high-bandwidth flash memory chip.

[0025] Based on acquired multi-dimensional media state parameters and historical operating data, the high-bandwidth flash memory controller predicts the media state of the high-bandwidth flash memory chip at future moments, such as predicting the bit error rate and its uncertainty index, thus obtaining the predicted media state and the uncertainty index of the predicted media state; this uncertainty index is used to measure the degree of uncertainty of the predicted bit error rate value.

[0026] Then, based on the predicted media state and uncertainty indicators, the high-bandwidth flash memory controller performs multi-objective solutions for the error correction code rate and cache partition weight of the high-bandwidth flash memory chip at future moments to obtain the target error correction code rate and target cache partition weight. Then, based on the target error correction code rate and target cache partition weight, the error correction configuration and cache configuration of the high-bandwidth flash memory chip are jointly adjusted to achieve collaborative control of error correction and cache.

[0027] In this solution, the high-bandwidth flash memory controller monitors the physical state of the high-bandwidth flash memory chip in real time and predicts future media conditions by combining historical operating data. This allows the control process to anticipate the degradation trend of the flash memory media due to changes in usage time and workload, avoiding the response lag caused by static configuration based solely on the current state. Then, based on the predicted media state and the uncertainty indicators of the prediction results, the error correction code rate and cache partitioning strategy are dynamically optimized for future moments. This enables the error correction capability configuration and cache resource allocation to adaptively adjust according to changes in media reliability and business needs. It improves data reliability when media degradation is high and optimizes cache resource utilization efficiency when data access pressure changes. Simultaneously, by jointly adjusting the error correction configuration and cache configuration, the flash memory controller can comprehensively coordinate error recovery capabilities and data access efficiency, avoiding the problem of overall system performance degradation caused by optimizing error correction or caching in isolation. Therefore, this solution can improve the adaptability of high-bandwidth flash memory controllers to changes in media state and load, improve flash data reliability and cache resource utilization efficiency, reduce error correction failure rate and cache access failure rate, and solve the problem that existing flash memory controllers, which use fixed error correction code rates and static caching strategies, cannot adapt to media degradation and dynamic workload changes, thus affecting the quality of service of the system.

[0028] In one embodiment, such as Figure 2 As shown, a data processing method for a high-bandwidth flash memory controller is provided, which is applied to... Figure 1 Taking a high-bandwidth flash memory controller as an example, the following steps are included: S10: Monitor the physical state of the high-bandwidth flash memory chip, obtain multi-dimensional media state parameters, and acquire historical operating data of the high-bandwidth flash memory chip.

[0029] During the operation of a high-bandwidth flash memory chip, the high-bandwidth flash memory controller monitors the physical state of the chip to obtain multi-dimensional media state parameters. For example, the multi-dimensional media state parameters include at least the current chip temperature and the number of programming or erasing cycles (i.e., P / E cycles). In other embodiments, the multi-dimensional media state parameters may also include the current number of programming / erasing cycles of the high-bandwidth flash memory chip, the chip temperature, the read voltage distribution offset, and the read error count slope in the most recent time period.

[0030] For example, at a certain moment, the on-chip monitoring circuit collects data showing that the current programming / erase cycle count is 2500, the chip temperature is 48°C, the read voltage distribution offset is 0.8V (relative to the initial reference value), and the recent read error count slope is 15 errors / s (calculated based on a 1-minute sliding window).

[0031] Meanwhile, the high-bandwidth flash memory controller also records the operating data of the high-bandwidth flash memory chip to obtain the historical operating data of the high-bandwidth flash memory chip. This historical operating data includes not only the multi-dimensional media state parameters monitored at different times, but also other data, such as the historical bit error rate collected at different times over a period of time.

[0032] S20: Based on multi-dimensional media state parameters and historical operating data, the media state of high-bandwidth flash memory chips is predicted at future moments, and the predicted media state and its uncertainty index are obtained.

[0033] This method uses current multidimensional media state parameters (such as chip temperature and number of programming / erasing cycles) and historical operating data as inputs. A sliding window averaging method combined with historical similarity state matching is employed to predict the bit error rate (BER) at future moments. Specifically, historical state points closest to the current temperature and cycle number are selected from the historical operating data. The BER at subsequent moments corresponding to these historical state points is then weighted and averaged to obtain the predicted BER as the predicted media state. Simultaneously, the variance or standard deviation is calculated based on the fluctuation range of the BER at these historical state points, serving as an uncertainty indicator for the predicted media state. A larger variance or standard deviation indicates greater uncertainty in the prediction result under the current state, requiring more conservative subsequent decisions.

[0034] For example, based on 10 similar state points in historical data with temperatures between 45-50°C and cycle counts between 2400-2600, the average bit error rate (BER) of these points 5 minutes later is calculated to be 2.5 × 10⁻⁶. -3 As the prediction bit error rate, the standard deviation is calculated to be 0.5 × 10⁻⁶. -3 As an indicator of uncertainty.

[0035] In other embodiments, multidimensional media state parameters and historical operating data can be used as inputs, and a pre-trained Gaussian Process Regression (GPR) model can be employed to predict the bit error rate of the high-bandwidth flash memory chip at future moments, thereby obtaining the predicted media state and the uncertainty index of the predicted media state.

[0036] S30: Based on the predicted medium state and uncertainty indicators, the error correction code rate and cache partition weight of the high-bandwidth flash memory chip at future moments are solved in multiple objectives to obtain the target error correction code rate and target cache partition weight.

[0037] High-bandwidth flash memory controllers can perform multi-objective solutions to the error correction code rate and cache partition weight of high-bandwidth flash memory chips at future moments based on predicted media state and uncertainty indicators, thereby obtaining the target error correction code rate and target cache partition weight.

[0038] For example, with a prediction bit error rate of 2.3 × 10⁻⁶ -3 The variance of the prediction bit error rate is 0.3 × 10⁻⁶. -3 As input, an optimization problem is constructed with the weighted sum of system latency and power consumption as the objective function. With the prediction bit error rate meeting the preset condition as a constraint, the Bayesian optimization algorithm is used to iteratively search for the error correction bit rate and cache partition weight at future time steps, thereby finding the optimal error correction bit rate and cache partition weight at future time steps. The corresponding outputs are the target error correction bit rate and the target cache partition weight.

[0039] Among them, the Bayesian optimization algorithm is a global optimization algorithm based on a probabilistic surrogate model, suitable for scenarios where the objective function is a black box (i.e., an explicit analytical expression cannot be obtained). It uses a Gaussian process as a surrogate model to fit the objective function, and uses the expected improvement (EI) as a sampling function to balance exploration and utilization. After multiple iterative searches, the target error correction bitrate and the target cache partition weights can be obtained.

[0040] In other embodiments, the predicted medium state and uncertainty indicators, such as the predicted bit error rate (BER) and predicted variance, can be used as inputs to construct an optimization problem with dual objectives of optimizing system latency and system power consumption. The Non-Dominated Sorting Genetic Algorithm (NSGA-II) is employed as the multi-objective solution method, using the code rate and buffer partition weight of the low-density parity-check code as decision variables. The search range for the code rate is set to [0.75, 0.95], and the search range for the buffer partition weight (i.e., the proportion allocated to the read buffer) is set to [0.1, 0.9]. With the predicted BER being less than or equal to a preset target BER threshold as a constraint, the population is iteratively evolved through selection, crossover, and mutation operations of the genetic algorithm. After 50 generations of evolution, the solution that achieves the optimal balance between latency and power consumption is selected from the Pareto optimal solution set. The code rate and weight corresponding to this solution are used as the target error correction code rate and target buffer partition weight. For example, the target error correction code rate is calculated to be 0.85, and the target buffer partition weight is 0.60.

[0041] S40: Based on the target error correction code rate and target cache partition weight, the error correction configuration and cache configuration of the high-bandwidth flash memory chip are jointly adjusted to achieve collaborative control of error correction and cache.

[0042] The high-bandwidth flash memory controller adjusts the error correction configuration of the high-bandwidth flash memory chip based on the target error correction code rate and the target cache partition weight, and correspondingly adjusts the cache configuration of the high-bandwidth flash memory chip. Then, based on the configuration, it performs LDPC code error correction and cache control to achieve coordinated control of error correction and cache.

[0043] For example, the target error correction bitrate of 0.85 and the target cache partition weight of 0.60 can be calculated and used to configure the error correction engine and cache manager of the high-bandwidth flash memory chip, respectively. For the error correction engine, the bitrate parameter of the LDPC decoder is set to 0.85, and the maximum number of decoding iterations is set to 12 according to the preset mapping relationship between bitrate and decoding iteration count. For the cache manager, the total cache space of the high-bandwidth flash memory chip is multiplied by the target cache partition weight of 0.60 to obtain the space allocated to the read cache, and the remaining 40% of the total cache space is allocated to the write cache. Through the above joint configuration, the error correction engine and the cache manager operate under the same set of collaborative parameters, achieving overall optimization of error correction intensity and cache resources.

[0044] In this embodiment, by monitoring the physical state of the high-bandwidth flash memory chip and acquiring historical operating data, the future media state and its uncertainties are predicted based on the current state and historical data. Then, based on the prediction results, the error correction code rate and cache partition weight are solved jointly by multiple objectives. Finally, error correction and caching are configured collaboratively according to the solution results. This achieves global overall optimization of error correction intensity and cache resources, overcomes the shortcomings of fixed error correction code rate and static cache partitioning strategy in dynamically responding to media degradation, effectively reduces the risk of error correction failure rate and cache hit rate decline under media degradation or load changes, and improves the system service quality.

[0045] In one embodiment, step S10, which involves monitoring the physical state of the high-bandwidth flash memory chip to obtain multi-dimensional media state parameters, specifically includes the following steps: S11: Real-time monitoring of the temperature and erase / write cycle count of high-bandwidth flash memory chips to obtain the current chip temperature and programming or erase cycle count.

[0046] The physical state of a high-bandwidth flash memory chip can be monitored by an on-chip monitoring circuit, thereby obtaining multi-dimensional media state parameters, namely, the programming / erasing cycle, chip temperature, voltage distribution offset, and read error count slope within a preset time window. The termination time of the preset time window is the current time.

[0047] Specifically, the chip temperature can be acquired in real time using an on-chip temperature sensor, and the number of programming or erasing operations can be recorded using a programming / erasing cycle counter. For example, if the chip temperature is acquired to be 48°C at a certain moment, the number of programming / erasing cycles is 2500.

[0048] S12: Sample the read voltage distribution of the high-bandwidth flash memory chip to obtain the current read voltage distribution, and calculate the mean difference between the current read voltage distribution and the preset reference voltage distribution as the current read voltage distribution offset.

[0049] Specifically, in the flash memory read operation, the reference voltage of the high-bandwidth flash memory chip is adjusted to read the read voltage distribution multiple times, and the threshold voltage distribution curve of each memory cell is sampled. This curve is then compared with the initial reference voltage distribution curve calibrated when the chip leaves the factory. The difference between the mean positions of the two curves is calculated to obtain the read voltage distribution offset.

[0050] S13: Monitor and calculate the read error situation of the high-bandwidth flash memory chip, obtain the read error count at different times, and calculate the rate of change of the read error count within a preset time window to obtain the read error count slope.

[0051] Read errors in high-bandwidth flash memory chips are monitored and calculated. An error correction engine records the number of erroneous bits detected in each read operation. Using a preset time window (e.g., 1 minute) as a sliding window, the slope of the linear fit of the read error count over time within this window is calculated to obtain the read error count slope. This slope reflects the trend of read error changes; a positive value indicates an increasing error rate, and a negative value indicates a decreasing error rate.

[0052] For example, a linear fit within a 1-minute window yields a read error count slope of 15 errors / s, indicating that the current read errors are increasing at a rate of 15 per second.

[0053] S14: Output the current programming / erase cycle number, chip temperature, read voltage distribution offset, and read error count slope as multi-dimensional media state parameters.

[0054] In this embodiment, by introducing two microscopic feature parameters, namely the read voltage distribution offset and the read error count slope, compared with the scheme that only collects the number of programming / erase cycles and chip temperature, it can more finely characterize the microscopic state changes of the flash memory medium, significantly improve the ability to perceive sudden degradation (such as the instantaneous spike in bit error rate caused by read interference), provide richer and more sensitive input features for subsequent prediction steps, predict and quantify future system risks, and then perform forward-looking resource scheduling based on quantified risks, so that the system has a stronger early warning capability for sudden degradation.

[0055] In one embodiment, such as Figure 3 As shown, step S20, which involves predicting the media state of a high-bandwidth flash memory chip at future moments based on multi-dimensional media state parameters and historical operating data, yields the predicted media state and its uncertainty index. This specifically includes the following steps: S21: Based on multidimensional media state parameters and historical operating data, predict the bit error rate of a high-bandwidth flash memory chip at future moments to obtain the predicted bit error rate and the predicted bit error rate variance.

[0056] The high-bandwidth flash memory controller normalizes the collected multi-dimensional media state parameters to form a multi-dimensional state feature vector. This feature vector is then input into a pre-trained Gaussian process regression model. This model is used to predict the media state of the high-bandwidth flash memory chip at future times, yielding the predicted media state and its uncertainty index. This Gaussian process regression model is a non-parametric Bayesian regression probabilistic model used to calculate the similarity (e.g., covariance) between data points through a kernel function, thereby predicting the distribution of unknown points and outputting a complete probability distribution of the predicted values ​​rather than a single numerical value.

[0057] S22: Use the predicted bit error rate as the predicted medium state and the predicted bit error rate variance as the uncertainty index, and output the predicted medium state and the corresponding uncertainty index.

[0058] For example, this Gaussian process regression model updates the posterior distribution online based on historical operating data, calculates the predicted bit error rate 5 minutes later, outputs the predicted bit error rate as the state of the predicted medium, and outputs the predicted bit error rate variance as an uncertainty index.

[0059] In this embodiment, the state of the medium is probabilistically modeled using a Gaussian process regression model, which outputs a complete probability distribution containing the mean and variance rather than a single numerical value. The variance directly quantifies the uncertainty of the prediction, providing a reliable risk basis for subsequent decision-making steps.

[0060] In one embodiment, step S21, which involves predicting the bit error rate of a high-bandwidth flash memory chip at future moments based on multi-dimensional media state parameters and historical operating data, to obtain the predicted bit error rate and the predicted bit error rate variance, specifically includes the following steps: S211: Normalize the parameters of different dimensions in the multidimensional medium state parameters to obtain a multidimensional state feature vector.

[0061] Among them, the parameters of different dimensions in the multidimensional medium state parameters can be normalized, and the number of programming / erase cycles, chip temperature, read voltage distribution offset and read error count slope can be mapped to a unified numerical range. After eliminating the dimensional differences of the parameters in each dimension, they are combined to obtain a multidimensional state feature vector.

[0062] S212: Update the covariance matrix of the preset Gaussian process regression model based on historical operating data within the most recent time period.

[0063] Simultaneously, based on historical operating data from the most recent time period, the covariance matrix and its inverse matrix of the preset Gaussian process regression model are updated. This covariance matrix is ​​calculated by the kernel function of the preset Gaussian process regression model based on all historical bit error rates from the historical operating data.

[0064] In one embodiment, the kernel function of the preset Gaussian process regression model is a weighted sum of the radial basis function (RBF) kernel function and the periodic kernel function. During model training, the hyperparameters in the kernel function of the Gaussian process regression model are optimized using maximum likelihood estimation. These hyperparameters include the length scale and signal variance of the RBF kernel function, and the period and signal variance of the periodic kernel function. During model update, the optimized hyperparameters are fixed, and the covariance matrix of the preset Gaussian process regression model is incrementally updated based on historical operating data, including historical bit error rates at different times.

[0065] Specifically, the kernel function of this pre-defined Gaussian process regression model can be represented by the following combination function: ; in, Indicates the predicted value; This represents the model input, i.e., the multidimensional state feature vectors at different times; Represents the kernel function; Represents the radial basis kernel function; This represents a periodic kernel function.

[0066] in, The coefficients represent the radial basis function, i.e., the signal variance of the radial basis kernel, which is used to control the overall influence of the long-term drift trend. The larger the value, the more significant the impact of flash memory aging (increased bit error rate) on the overall change. It represents the length scale of the radial basis kernel function and controls the smoothness of long-term drift. The larger the value, the smoother the trend of the bit error rate changing with the P / E cycle (slow aging). The smaller the value, the more drastic the change (extremely sensitive to the P / E cycle).

[0067] in, The coefficients of the periodic kernel function, i.e., the signal variance, are used to control the magnitude of the influence of the periodic fluctuation component. The larger the value, the more significant the fluctuation in bit error rate caused by temperature or load cycling. This indicates the period controlling the cyclical fluctuations; this value is fixed. This represents the periodic smoothing scale of the periodic kernel function, used to control the sharpness of fluctuations within the periodic kernel. The larger the value, the closer the periodic fluctuation is to a smooth sine wave; The smaller the value, the sharper the fluctuations appear, like sudden load spikes.

[0068] The initial value of the length scale of the radial basis kernel function can be 1.0, and the signal variance... The initial value for the period can be 0.5; the period kernel's initial value can be 24 hours, and the signal variance... It can be 0.2.

[0069] In this embodiment, the kernel function used is a weighted sum of the radial basis function (RBF) and the periodic kernel function. The RBF kernel function uses the Euclidean distance between two data points as its independent variable; the closer the distance, the larger the output value. It is used to capture the long-term drift trend of media state aging as programming or erasing cycles increase. The periodic kernel function can capture recurring periodic patterns in the data, used to capture the periodic fluctuations of media state with changes in temperature or workload.

[0070] S213: The updated Gaussian process regression model is updated by using the multidimensional state feature vector as the query point input to predict the bit error rate corresponding to the query point, and the output is the predicted bit error rate and the predicted bit error rate variance of the high bandwidth flash memory chip.

[0071] Then, the normalized multidimensional state feature vector is used as the input of the query point into the updated Gaussian process regression model to predict the bit error rate corresponding to the query point, and the predicted bit error rate and the predicted bit error rate variance are output.

[0072] Specifically, the prediction process includes: calculating the joint Gaussian distribution between the predicted value corresponding to the query point and the historical bit error rate in the historical operating data based on the updated covariance matrix and kernel function; performing Bayesian inference based on the joint Gaussian distribution, and deriving the posterior conditional distribution of the predicted value corresponding to the query point using the historical bit error rate in the historical operating data as a condition; calculating the posterior conditional mean and posterior conditional variance of the bit error rate corresponding to the query point based on the posterior conditional distribution; outputting the posterior conditional mean and posterior conditional variance as the predicted bit error rate and predicted bit error rate variance, and then using the predicted bit error rate as the state of the prediction medium and the predicted bit error rate variance as the uncertainty index.

[0073] For example, after inputting the normalized feature vector into the model, the calculated prediction bit error rate for the next 5 minutes is 2.3 × 10⁻⁶. - ³, the variance of the prediction bit error rate is (0.3 × 10⁻⁶). - ³)², meaning the standard deviation of the prediction bit error rate is 0.3 × 10⁻⁶. -3 .

[0074] In this embodiment, a Gaussian process regression model is used to probabilistically model the state of the medium, outputting a complete probability distribution including the mean and variance rather than a single numerical value. The variance directly quantifies the uncertainty of the prediction, providing a reliable risk basis for subsequent decision-making steps. Combined with the dual capture capability of the combined kernel function for long-term drift and periodic fluctuations, this scheme achieved a root mean square error (RMSE) of only 0.08 for the bit error rate prediction after 1 hour in a 128-layer QLC flash memory test, far superior to the 0.25 of the traditional moving average method, significantly improving prediction accuracy.

[0075] In one embodiment, such as Figure 4 As shown, in step S30, based on the predicted medium state and uncertainty index, a multi-objective solution is performed on the error correction code rate and cache partition weight of the high-bandwidth flash memory chip at future time points to obtain the target error correction code rate and target cache partition weight. Specifically, this includes the following steps: S31: Using the predicted medium state and uncertainty index as inputs, construct an objective function to characterize the overall performance cost.

[0076] Before performing multi-objective solutions, an objective function for quantifying the overall system performance is first constructed. Specifically, the objective function is constructed by taking the error correction code rate and cache partition weight after the system executes the configuration as two core variables, and defining the weighted sum of the system latency and system power consumption after executing the configuration (including error correction configuration and cache configuration) as the overall system performance cost, thereby constructing the objective function.

[0077] The objective function can be expressed by the following formula: ; in, This represents the overall performance cost of the system; Indicates system latency; Indicates system power consumption; The first weight representing system latency and the second weight representing system power consumption are respectively preset constant values. The values ​​can be 0.6 and 0.4.

[0078] System latency includes decoding latency caused by the error correction engine executing the configured error correction code rate, and access latency caused by the cache manager executing the configured cache partition weight; system power consumption includes decoding power consumption caused by the error correction engine executing the configured error correction code rate, and read / write power consumption caused by the cache manager executing the configured cache partition weight.

[0079] For example, a first weight can be set to 0.6 and a second weight to 0.4. The objective function can be expressed as the overall performance cost J = 0.6 × system latency + 0.4 × system power consumption. The first weight of 0.6 is greater than the second weight coefficient of 0.4, indicating that in the current system design priority, latency optimization is slightly more important than power consumption optimization. This weight can be adjusted according to different application scenarios. For example, in power-constrained edge computing devices, the power consumption weight coefficient can be appropriately increased. The smaller the value of this objective function, the better the overall system performance.

[0080] S32: With the goal of minimizing the overall performance cost and the constraint that the predicted bit error rate meets the preset conditions, the error correction bit rate and cache partition weight of the high-bandwidth flash memory chip at future moments are iteratively solved based on the predicted medium state and uncertainty indicators to obtain the target error correction bit rate and target cache partition weight.

[0081] Then, with the goal of minimizing the overall performance cost and the constraint that the predicted bit error rate meets the preset conditions, and with the predicted medium state and uncertainty index as inputs, a solver is used to solve for the error correction code rate and cache partition weight, so as to obtain the optimal error correction code rate and cache partition weight of the high bandwidth flash memory chip in the future, and the target error correction code rate and target cache partition weight are output.

[0082] The search space for the error correction rate can be [0.75, 0.95], and the search space for the cache partition weight (i.e., the proportion allocated to the read cache) can be [0.1, 0.9]. The preset condition can be that the predicted bit error rate is greater than a preset bit error rate threshold.

[0083] In this embodiment, the predicted mean and predicted variance output by the Gaussian process regression model are used to jointly iteratively solve the two parameters under the Bayesian optimization framework, with the bit error rate as a constraint and the weighted sum of latency and power consumption as the comprehensive performance cost. This quantifies uncertainty into an exploratory driving force, achieving an adaptive global optimal configuration of error correction capability and cache performance throughout the entire life cycle of flash memory, and significantly improving the comprehensive performance of the high-bandwidth flash memory controller under reliability constraints.

[0084] In one embodiment, the process of determining whether the predicted bit error rate meets the constraint conditions includes: multiplying the predicted standard deviation output by the preset Gaussian process regression model by a preset risk avoidance coefficient, and then adding it to the predicted mean of the preset Gaussian process regression model to obtain a bit error rate risk estimate; comparing the bit error rate risk estimate with a preset target bit error rate threshold; when the bit error rate risk estimate is less than or equal to the target risk threshold, it is determined that the predicted bit error rate meets the preset conditions, and the current candidate configuration is still within the acceptable reliability range after considering the prediction uncertainty; when the bit error rate risk estimate is greater than the target risk threshold, it is determined that the predicted bit error rate does not meet the preset conditions, and the reliability risk of the current candidate configuration is too high, and it needs to be filtered out.

[0085] For example, a risk aversion coefficient of 1.5 is set, and the target risk threshold is 1 × 10⁻⁶. -3 For a given candidate configuration, the preset Gaussian process regression model predicts its mean bit error rate to be 2.3 × 10⁻⁶. -3 The standard deviation is 0.3 × 10⁻⁶. -3 The estimated bit error rate risk is 2.3 × 10⁻⁶. -3 +1.5×0.3×10 -3 =2.75×10 -3 It is greater than 1×10 -3 Therefore, this candidate configuration does not meet the constraints and is excluded during the solution process. The value of the risk aversion coefficient determines the conservatism of the constraints; the larger the risk aversion coefficient, the stricter the constraints, and the more likely the decision will favor a conservative configuration with higher error correction strength and a larger read cache ratio. Experiments show that when the risk aversion coefficient is 1.5, the system achieves the best balance between performance and reliability.

[0086] In this embodiment, the prediction uncertainty output by the Gaussian process regression model is incorporated into the constraints by introducing a risk aversion coefficient, making the decision-making process inherently risk-sensitive. Compared to traditional solutions that only use a single bit error rate threshold for judgment, this solution can dynamically adjust the strictness of the constraints according to the degree of prediction uncertainty. It automatically tends towards a more conservative configuration when the prediction is uncertain, and allows for a more aggressive configuration when the prediction is certain, thereby achieving an adaptive balance between system reliability and performance.

[0087] In one embodiment, step S32, which involves iteratively solving for the error correction code rate and cache partition weight of the high-bandwidth flash memory chip at future moments based on the predicted medium state and uncertainty indicators, specifically includes the following steps: S321: Input the predicted medium state and uncertainty index into the surrogate model corresponding to the objective function to calculate the mean and standard deviation of the comprehensive performance cost prediction for high-bandwidth flash memory chips under different candidate error correction code rates and candidate cache partition weights.

[0088] The surrogate model corresponding to the objective function can be a Gaussian process regression model. This surrogate model can be a pre-defined Gaussian process regression model or another Gaussian process regression model with a different kernel function. During the prediction process, Bayesian optimization can be used for iterative optimization. This algorithm utilizes the Gaussian process surrogate model to optimize parameters by maximizing the expected improvement.

[0089] S322: Calculate the expected improvement of the candidate solution based on the prediction mean and prediction standard deviation, and use the prediction bit error rate meeting the preset condition as a constraint to select effective candidate solutions.

[0090] In each round of prediction, the expected improvement of the candidate configuration is calculated based on the current best observation value, the prediction mean, and the prediction standard deviation, using the current best observation value as a baseline. The expected improvement measures the expected degree of improvement in overall performance cost that the candidate solution can achieve relative to the current best candidate solution. The initial best observation value is the set overall performance cost; after one iteration, the current best observation value becomes the calculated measured overall performance cost.

[0091] Simultaneously, the predicted bit error rate (BER) meeting a preset condition is used as a constraint to filter valid candidate solutions. That is, candidate solutions whose predicted BER meets the preset condition (including the selected error correction code rate and candidate buffer partition weight) are selected as valid candidate solutions. Each candidate solution corresponds to a set of parameter values ​​for the candidate error correction code rate and the candidate buffer partition weight; that is, each candidate solution includes the candidate error correction code rate and the candidate buffer partition weight.

[0092] S323: Select the effective candidate solution with the largest expected improvement as the next measured parameter to obtain the measured comprehensive performance cost, and update and iteratively calculate the surrogate model when the convergence condition is not met.

[0093] S324: When the convergence condition is met, the candidate error correction code rate and candidate cache partition weight corresponding to the minimum value among all the measured comprehensive performance costs will be output as the target error correction code rate and target cache partition weight.

[0094] That is, in each iteration, the expected improvement amount is calculated for all candidate configurations, and the effective candidate configurations are selected with the prediction bit error rate meeting the preset condition as a constraint. The effective candidate configuration with the largest expected improvement amount is selected as the next measured parameter, and it is actually configured to run on the reference chip or simulated to obtain the measured comprehensive performance cost. The measured comprehensive performance cost is compared with the current best observation value. If it is smaller, the current best observation value is updated, and the surrogate model is updated using the measured data.

[0095] Repeat the above iterative process. When the preset maximum number of iterations (e.g., 15) is reached, or the expected improvement tends to zero in multiple consecutive iterations, the convergence condition is determined to be met. The error correction code rate and cache partition weight corresponding to the minimum value among all recorded measured comprehensive performance costs are output as the target error correction code rate and target cache partition weight. For example, after 15 iterations, the target error correction code rate is 0.82, and the target cache partition weight is 0.65.

[0096] like Figure 5 As shown, the high-bandwidth flash memory controller includes a Bayesian optimization collaborative decision-making module, which performs a collaborative solution based on a Bayesian optimization algorithm for the chip's error correction code rate and cache partition weights. This Bayesian optimization collaborative decision-making module includes a surrogate model unit (storing a surrogate model), a data acquisition function unit, and a constraint processing unit.

[0097] After obtaining the predicted mean μ (i.e., predicted bit error rate, representing the state of the predicted medium) and the predicted variance σ² (i.e., predicted bit error rate variance, representing the uncertainty index), these values ​​are input into the Bayesian optimization collaborative decision-making module for iterative solution of the error correction rate and cache partition weights. Specifically, after the predicted mean μ and predicted variance σ² are input, the surrogate model unit calls the surrogate model to calculate the predicted mean and predicted standard deviation of the chip's overall performance cost under different candidate error correction rates and candidate cache partition weights. The acquisition function unit calculates the expected improvement amount for each sampling point (i.e., candidate solution) based on the predicted mean and predicted standard deviation, and performs a balance exploration and utilization based on the expected improvement amount to recommend the next sampling point. The constraint processing unit uses the predicted bit error rate meeting preset conditions as constraints to screen effective candidate solutions and filter infeasible candidate solutions. These three components work together to achieve the globally optimal search for error correction rate and cache weight parameters.

[0098] In this embodiment, by automatically balancing the expected improvement amount during the search, a fine-grained search is performed focusing on the current optimal region, enabling efficient searching of the global optimum within a limited number of iterations. Compared to simple strategies such as traditional lookup table methods or PID control, this scheme can systematically explore the combination space of error correction code rate and cache partition weights globally, avoiding the trap of local optima and achieving true global collaborative optimization.

[0099] In one embodiment, step S322, which involves calculating the expected improvement of the candidate solution based on the predicted mean and predicted standard deviation, specifically includes the following steps: S3221: The minimum measured overall performance cost currently recorded is taken as the current optimal observation value, and the initial value of the current optimal observation value is the set cost threshold.

[0100] In each iteration, the minimum measured comprehensive performance cost among all currently recorded measured comprehensive performance costs is taken as the current optimal observation value. The initial value of the current optimal observation value is a set cost threshold. That is, in the first iteration, the set cost threshold is taken as the current optimal observation value; in subsequent iterations, the minimum measured comprehensive performance cost recorded in the previous iteration is taken as the current optimal observation value.

[0101] S3222: Calculate the potential improvement of the predicted mean relative to the current best observation, and calculate the uncertainty of the potential improvement based on the predicted standard deviation.

[0102] Here, the predicted mean is the predicted mean of the overall performance cost, and the predicted standard deviation represents the standard deviation of the predicted overall performance cost. The calculation process for the potential improvement magnitude includes: subtracting the current best observed value from the predicted mean, and then subtracting a preset balancing parameter to obtain the potential improvement magnitude.

[0103] The calculation process for the uncertainty of the potential improvement magnitude includes: dividing the potential improvement magnitude by the predicted standard deviation to obtain a standardized value; inputting the standardized value into a standard normal distribution to construct a probability density function; and using the product of the predicted standard deviation and the probability density function as the uncertainty of the potential improvement magnitude.

[0104] S3223: Calculate the expected improvement amount of the candidate solution based on the potential improvement magnitude and the corresponding uncertainty.

[0105] Then, the standardized value is input into the standard normal distribution to construct the cumulative distribution density function. The product of the potential improvement magnitude and the cumulative distribution density function is added to the uncertainty of the potential improvement magnitude to obtain the expected improvement of the candidate solution.

[0106] The calculation process for the expected improvement is expressed by the following formula: ; ; in, This represents the expected improvement of a candidate solution; This represents the average predicted comprehensive performance cost for a given candidate solution. This represents the current best observation value; This represents the preset balance parameter, which can be 0.01; This represents the standard deviation of the overall performance cost prediction for a given candidate solution. This represents the standardized value, which is the value obtained by dividing the potential improvement by the predicted standard deviation. Represents the cumulative distribution density function; This represents the cumulative distribution density function.

[0107] In other words, the calculation process of the expected improvement includes: subtracting the current best observation value from the predicted mean and then subtracting the preset balance parameter to obtain the potential improvement magnitude; dividing the potential improvement magnitude by the predicted standard deviation to obtain the standardized value; inputting the standardized value into a standard normal distribution to construct a function, obtaining the cumulative distribution function and the probability density function; and adding the product of the potential improvement magnitude and the cumulative distribution function to the product of the predicted standard deviation and the probability density function to obtain the expected improvement of the candidate solution.

[0108] For example, if the current best observed value is 0.85, the predicted mean of a candidate configuration is 0.70, the predicted standard deviation is 0.10, and the balance parameter is 0.01, then the correction bias is 0.70 - 0.85 - 0.01 = -0.16, the first standardized value is -0.16 / 0.10 = -1.6, and the cumulative distribution density function obtained from the standard normal distribution is 0.0548 and 0.1109. The expected improvement is (-0.16) × 0.0548 + 0.10 × 0.1109 = -0.0088 + 0.0111 = 0.0023.

[0109] In this embodiment, the difference between the predicted mean of a candidate solution and the current best observation is used as the potential improvement magnitude. This improvement magnitude is then normalized using the prediction standard deviation to adaptively unify the performance improvement metric among different candidate solutions. Based on this, the normalized standardized value is mapped to a standard normal distribution, and its cumulative distribution function and probability density function are calculated, thus transforming the improvement potential in the original prediction space into a mathematical expectation in the probability space. Finally, a unified decision index, the expected improvement amount, is constructed by weighting and summing the product of the potential improvement magnitude and the cumulative distribution function (representing the deterministic improvement contribution) and the product of the prediction standard deviation and the probability density function (representing the uncertainty contribution of the improvement magnitude). This allows the optimizer to proactively adjust the intensity of development of known advantageous regions and exploration of high-uncertainty regions based on the surrogate model output during iteration. It adaptively balances global search and local refinement without manually setting heuristic rules, thereby approximating the global optimal configuration with the fewest measured samples and effectively reducing the parameter tuning cost and time overhead of high-bandwidth flash controllers on actual chips.

[0110] In one embodiment, such as Figure 6 As shown, in step S40, based on the target error correction code rate and the target cache partition weight, the error correction configuration and cache configuration of the high-bandwidth flash memory chip are jointly adjusted to achieve collaborative control of error correction and cache. Specifically, this includes the following steps: S41: Configure the bitrate parameters of the error correction engine and the maximum number of decoding iterations based on the target error correction bitrate.

[0111] Specifically, the bitrate parameter of the LDPC decoder can be set to the target error correction bitrate, and based on the pre-built mapping table between the error correction bitrate and the maximum number of decoding iterations, the maximum number of decoding iterations of the decoder can be configured to the target error correction bitrate corresponding to the decoder, so that the decoder can perform information transmission and update at most the corresponding number of iterations when executing the belief propagation decoding algorithm.

[0112] The maximum number of decoding iterations is inversely proportional to the target error correction code rate. A lower target error correction code rate indicates more redundant parity bits and stronger error correction capability; correspondingly, more decoding iterations are set to fully utilize the error correction potential of the strong error correction code. Conversely, a higher target error correction code rate indicates a higher proportion of effective data and relatively weaker error correction capability; correspondingly, fewer decoding iterations are set to reduce unnecessary decoding latency and power consumption.

[0113] For example, the preset mapping relationship between bitrate and decoding iterations is as follows: bitrate 0.95 corresponds to 8 iterations, bitrate 0.88 corresponds to 12 iterations, bitrate 0.82 corresponds to 15 iterations, and bitrate 0.75 corresponds to 20 iterations. When the target error correction bitrate obtained from multi-objective solution is 0.82, the bitrate parameter of the low-density parity-check decoder is set to 0.82, and the maximum number of decoding iterations is configured to 15, so that the decoder performs a maximum of 15 rounds of information transmission and update when executing the belief propagation decoding algorithm.

[0114] This process establishes an inverse mapping relationship between the error correction bitrate and the number of decoding iterations, enabling the error correction engine to run with matching number of iterations at different bitrates. When the bitrate is low (strong error correction capability), more decoding computing resources are allocated to fully utilize the error correction potential, while when the bitrate is high (weak error correction capability), unnecessary decoding computing is reduced to save latency and power consumption, thus achieving a dynamic balance between error correction strength and computational overhead.

[0115] S42: Configure the space allocation ratio of read cache and write cache for the cache manager based on the target cache partition weight.

[0116] The target cache partition weight is a value between 0 and 1, representing the proportion of the total cache space allocated to the read cache. The total cache space of the high-bandwidth flash memory chip is multiplied by the target cache partition weight to obtain the space allocated to the read cache; the space allocated to the read cache is subtracted from the total cache space, and the remaining portion is allocated to the write cache.

[0117] For example, if the total cache space of a high-bandwidth flash memory chip is 256MB, and the target cache partition weight obtained from multi-objective solution is 0.65, then the read cache allocation size is 256MB × 0.65 = 166.4MB, and the write cache allocation size is 256MB - 166.4MB = 89.6MB. Through this mapping method, the cache manager divides the total cache space into read and write cache areas according to the target ratio, and in subsequent data read and write operations, directs read data requests to the read cache area and write data requests to the write cache area.

[0118] This process achieves continuous and adjustable control over cache resources by directly mapping cache partition weights to the space allocation ratio between read and write caches. When the load switches from read-intensive to write-intensive or vice versa, the system can adaptively optimize the cache hit rate by adjusting the cache partition weights. This avoids the drawbacks of static partitioning strategies, such as excessively large read cache space wasting write performance or excessively large write cache space reducing read hit rate, thus improving the utilization efficiency of cache resources.

[0119] S43: Based on the configured bitrate parameters, maximum number of decoding iterations, and the space allocation ratio of read cache and write cache, perform coordinated control of decoding and caching operations on high-bandwidth flash memory chips.

[0120] Specifically, when the high-bandwidth flash memory chip receives a data read request from the host, the cache manager first determines whether the requested data exists in the read cache based on the space allocation ratio of the read cache and write cache. If the data hits the read cache, it is returned directly from the read cache without triggering a flash read operation, thus avoiding flash read latency and error correction decoding overhead. If the data misses the read cache, the original data is read from the flash medium and sent to the error correction engine for LDPC decoding. The error correction engine executes the belief propagation decoding algorithm according to the configured bitrate parameters and the maximum number of decoding iterations, attempting to correct data errors within the maximum number of decoding iterations. If decoding is successful, the corrected data is returned to the host and simultaneously written to the read cache to update the cache content. When the high-bandwidth flash memory chip receives a data write request, the data is first cached in the write cache space corresponding to the write cache allocation ratio. It is then written to the flash medium in batches only after the flush conditions are met (such as the write cache being full or the timer expiring).

[0121] For example, in a typical mixed read / write operation sequence, suppose 10 read requests and 5 write requests arrive consecutively. The cache manager divides the total cache space of 256MB into a 166.4MB read cache and an 89.6MB write cache, based on a 65% read cache ratio and a 35% write cache ratio. For the 10 read requests, if the data for 7 of these requests is already in the read cache, the data is returned directly, with a latency of only about 50ns (cache access latency). The remaining 3 missed requests need to be read from flash memory, decoded by the error correction engine in 15 iterations, with each decoding iteration taking approximately 2μs, for a total decoding latency of approximately 30μs. Adding the flash read latency of approximately 75μs, the total latency is approximately 105μs. For the 5 write requests, the data is first written to the 89.6MB write cache. Once the write cache accumulates to a threshold, it is flushed to flash memory all at once, reducing wear and tear on the flash media caused by frequent small-block write operations.

[0122] In this collaborative control process, there is a coupling relationship between the number of decoding iterations of the error correction engine and the hit rate of the cache manager: if the bit rate is reduced (enhancing error correction), the number of decoding iterations increases, decoding latency and power consumption rise, but the improved error correction success rate can reduce reread operations, thereby indirectly increasing effective bandwidth; if the read cache ratio is increased, the read hit rate increases and the number of flash reads decreases, but the write cache space is compressed, which may lead to an increase in write flushing frequency. The configured bit rate of 0.82 and read cache ratio of 65% is the optimal trade-off found in the above trade-offs through Bayesian optimization in the previous steps, so that when the error correction engine and the cache manager run collaboratively under this set of parameters, the average latency, power consumption and throughput of the system reach a globally optimal state.

[0123] In one embodiment, after step S40, that is, after jointly adjusting the error correction configuration and cache configuration of the high-bandwidth flash memory chip based on the target error correction code rate and the target cache partition weight, the method further includes the following steps: S50: Collect the actual bit error rate after executing the target error correction bit rate configuration and target cache partition weight, and calculate the actual overall performance cost of the system.

[0124] After error correction and caching configurations are completed, the actual operating data of the high-bandwidth flash memory chip is continuously collected during the next monitoring cycle. The error correction engine records the actual detected bit error rate, the latency monitoring circuit collects the actual system latency, and the power consumption monitoring circuit collects the actual system power consumption.

[0125] For example, within a 5-minute monitoring period configured with a target error correction code rate of 0.85 and a target cache partition weight of 0.60, the actual average bit error rate was recorded as 2.4 × 10⁻⁶. -3 The system latency is 225μs and the system power consumption is 2.9W. The above latency and power consumption are weighted and summed according to preset weights, and the actual comprehensive performance cost is calculated to be 0.60×225+0.40×2.9=136.16 (normalized to 0.64).

[0126] S60: Combine the currently collected multidimensional media state parameters, actual bit error rate, and actual overall performance cost into the latest historical operating data to form new training samples.

[0127] The multidimensional media state parameters collected at the current moment are compared with the actual bit error rate of 2.4 × 10⁻⁶. -3 This is combined with the actual overall performance cost of 0.64 to form a complete new training sample; this new training sample contains the current input state and the corresponding actual output result. This new training sample is written to the historical data storage area and added to the existing historical dataset, increasing the number of samples in the historical dataset by one.

[0128] S70: Based on the newly added training samples, the covariance matrix of the preset Gaussian process regression model is incrementally updated; the preset Gaussian process regression model is used to predict the media state of high-bandwidth flash memory chips at future times.

[0129] Then, the new training samples are added to the training dataset of the preset Gaussian process regression model, and the column and row elements related to the new samples in the covariance matrix are recalculated. The posterior mean and posterior covariance matrix of the model are updated through the incremental learning algorithm so that the model can absorb the latest actual running information.

[0130] like Figure 7 As shown, the system in this embodiment includes a perception layer, a prediction layer, a decision layer, and an execution layer. The perception layer uses an upper-side monitoring circuit to perform multi-dimensional media state perception on the high-bandwidth flash memory chip. The monitored physical state parameters (i.e., multi-dimensional media state data) are input into the prediction layer for bit error rate (BER) prediction based on Gaussian process regression. The predicted BER mean and BER variance are used as inputs to the decision layer for Bayesian optimization collaborative decision-making to find the optimal error correction rate and cache partition weights. These optimal error correction rate and cache partition weights are then input into the execution layer for adaptive error correction and cache configuration. Based on the configuration parameters, collaborative control of decoding and cache operations is performed. Finally, the actual BER after configuration execution is used as feedback to update the preset Gaussian process regression model for use in the next round of prediction.

[0131] This update process does not require retraining on all historical data, thus minimizing computational overhead. The pre-defined Gaussian process regression model will be used in the next cycle to predict the state of the medium at future times. By continuously absorbing newly added measured data, the model's fitting accuracy to the medium degradation pattern gradually improves, forming a continuously optimized adaptive closed loop.

[0132] In this embodiment, based on the latest configuration, the actual bit error rate and actual overall performance cost after configuration execution are collected. The current state and actual results are combined into new training samples to incrementally update the prediction model, forming an adaptive closed-loop mechanism from perception, prediction, decision-making, execution to feedback. This closed-loop mechanism enables the system to learn online and adapt to dynamic changes in media degradation and workload. As the running time increases, the accuracy of the prediction model in fitting the media state continuously improves, and the decision quality also improves, ensuring that the optimal error correction and caching co-configuration is maintained throughout the entire lifecycle of the flash memory chip, from new to worn out.

[0133] like Figure 8As shown, in existing technologies, when using a fixed error correction code rate and a static caching strategy (i.e., the caching strategy is static and the code rate is fixed) for flash memory control, the error correction strategy and caching are isolated from each other, lacking an adaptive mechanism for risk quantification and collaborative configuration adjustment based on quantified risk. This leads to the system being prone to high tail latency issues. In this embodiment, multi-dimensional media state perception is used, and a Gaussian process regression (GPR) model is employed to predict the chip's bit error rate. Then, based on the predicted bit error rate and its uncertainty index, Bayesian optimization collaborative decision-making is used to collaboratively optimize the optimal error correction code rate and cache partition weights. Finally, based on the optimal error correction code rate and cache partition weights, the code rate parameters and cache parameters are dynamically configured and executed. The GPR model is updated based on the actual bit error rate after the configuration is executed, achieving closed-loop adaptive adjustment of the prediction scheme.

[0134] It is important to understand that existing chip control methods optimize error correction and caching independently, and employ simple strategies such as lookup tables or proportional-integral-derivative PID control, which cannot balance exploration and utilization globally. This invention, through Gaussian process regression, predicts media state and uncertainty online, and utilizes Bayesian optimization to jointly decide on error correction and caching strategies. Compared to traditional static or single-variable adjustment schemes, it improves system throughput by 22% and reduces 99.9% percentile tail latency by 38% under mixed read / write loads (comparison benchmark is a static caching scheme with a fixed LDPC code rate). Furthermore, by introducing read voltage distribution offset and read error count slope as new features, combined with Gaussian process regression using a combined kernel function, the prediction accuracy for QLC flash read interference errors is improved from 72% in traditional schemes to 91%, significantly enhancing the system's early warning capability against sudden degradation.

[0135] Furthermore, the aforementioned closed-loop feedback mechanism enables the model to learn online and adapt to dynamic changes in media degradation and workload, maintaining stable service quality throughout the entire flash memory lifecycle and avoiding the problem of drastic performance degradation in the later stages of media wear in traditional offline optimization schemes. By treating error correction intensity and cache resources as coupled variables for collaborative optimization, the resource allocation imbalance caused by isolated optimization of these two technologies is overcome, achieving global optimization of latency, power consumption, and bandwidth utilization. Compared to isolated optimization schemes, bandwidth utilization is improved by 15%.

[0136] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0137] In one embodiment, a high-bandwidth flash memory controller is provided, which corresponds one-to-one with the data processing method of the high-bandwidth flash memory controller in the above embodiments. For example... Figure 9 As shown, the functional modules in this parameter aggregation device are described in detail below: The monitoring module 901 is used to monitor the physical state of the high-bandwidth flash memory chip, obtain multi-dimensional media state parameters, and acquire historical operating data of the high-bandwidth flash memory chip. The prediction module (i.e. Gaussian process regression module) 902 is used to predict the medium state of a high-bandwidth flash memory chip at a future time based on multi-dimensional medium state parameters and historical operating data, and to obtain the predicted medium state and the uncertainty index of the predicted medium state. The solution module (i.e. the Bayesian optimization collaborative decision module) 903 is used to perform multi-objective solutions for the error correction code rate and cache partition weight of the high-bandwidth flash memory chip at future moments based on the predicted medium state and uncertainty index, so as to obtain the target error correction code rate and target cache partition weight. The adjustment module 904 is used to jointly adjust the error correction configuration and cache configuration of the high-bandwidth flash memory chip based on the target error correction code rate and the target cache partition weight, so as to achieve collaborative control of error correction and cache.

[0138] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of the present invention. For details on their specific functions and technical effects, please refer to the method embodiments section, which will not be repeated here.

[0139] Those skilled in the art will understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the functions described above can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this invention. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0140] This invention also provides an electronic device, which may be a high-bandwidth flash memory controller. For example... Figure 10 As shown, the electronic device includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor. When the processor executes the computer program, it implements the steps in any of the above method embodiments, or when the processor executes the computer program, it implements the functions of each module / unit in the above device embodiments.

[0141] For example, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the electronic device.

[0142] Those skilled in the art will understand that Figure 10 The electronic device described is merely an example and does not constitute a limitation on the electronic device. It may include more or fewer components than shown, or combine certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, etc.

[0143] The aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0144] The memory can be an internal storage unit of the electronic device, such as a hard drive or RAM. The memory can also be an external storage device of the electronic device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory can include both internal and external storage units of the electronic device.

[0145] This invention also provides a readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0146] This invention provides a computer program product that, when run on an electronic device, enables the electronic device to perform the steps described in the various method embodiments above.

[0147] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0148] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0149] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0150] In the embodiments provided by this invention, it should be understood that the disclosed apparatus / device and method can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0151] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0152] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A data processing method for a high-bandwidth flash memory controller, characterized in that, include: The physical state of the high-bandwidth flash memory chip is monitored to obtain multi-dimensional media state parameters, and the historical operating data of the high-bandwidth flash memory chip is acquired. Based on the multidimensional media state parameters and the historical operating data, the media state of the high-bandwidth flash memory chip at future moments is predicted to obtain the predicted media state and the uncertainty index of the predicted media state. Based on the predicted medium state and the uncertainty index, the error correction code rate and cache partition weight of the high-bandwidth flash memory chip at future time are solved by multiple objectives to obtain the target error correction code rate and target cache partition weight. Based on the target error correction code rate and the target cache partition weight, the error correction configuration and cache configuration of the high-bandwidth flash memory chip are jointly adjusted to achieve collaborative control of error correction and cache.

2. The method according to claim 1, characterized in that, The method of predicting the media state of the high-bandwidth flash memory chip at future moments based on the multi-dimensional media state parameters and the historical operating data, and obtaining the predicted media state and the uncertainty index of the predicted media state, includes: Based on the multidimensional media state parameters and the historical operating data, the bit error rate of the high-bandwidth flash memory chip at future moments is predicted to obtain the predicted bit error rate and the predicted bit error rate variance. The predicted bit error rate is used as the predicted medium state, and the predicted bit error rate variance is used as the uncertainty index. The predicted medium state and the corresponding uncertainty index are then output.

3. The method according to claim 2, characterized in that, The step of predicting the bit error rate (BER) of the high-bandwidth flash memory chip at future moments based on the multidimensional media state parameters and the historical operating data, and obtaining the predicted BER and the predicted BER variance, includes: The parameters of different dimensions in the multidimensional medium state parameters are normalized to obtain a multidimensional state feature vector. Based on the historical operating data, the covariance matrix of the preset Gaussian process regression model is updated. The covariance matrix is ​​calculated by the kernel function of the preset Gaussian process regression model based on all historical bit error rates in the historical operating data. The multidimensional state feature vector is used as the query point input to the updated Gaussian process regression model to predict the bit error rate corresponding to the query point, and the predicted bit error rate and predicted bit error rate variance of the high bandwidth flash memory chip are output.

4. The method according to claim 1, characterized in that, Based on the predicted medium state and the uncertainty index, a multi-objective solution is performed on the error correction code rate and cache partition weight of the high-bandwidth flash memory chip at future time points to obtain the target error correction code rate and target cache partition weight, including: Using the predicted medium state and the uncertainty index as inputs, an objective function is constructed to characterize the overall performance cost; With the goal of minimizing the overall performance cost and constrained by the prediction bit error rate meeting a preset condition, the error correction bit rate and cache partition weight of the high-bandwidth flash memory chip at future moments are iteratively solved based on the predicted medium state and the uncertainty index to obtain the target error correction bit rate and the target cache partition weight.

5. The method according to claim 4, characterized in that, The step of constructing an objective function characterizing the overall performance cost, using the predicted medium state and the uncertainty index as inputs, includes: Using the system latency and system power consumption generated after the system executes the configured error correction code rate and cache partition weight as variables, the weighted sum of the system latency and system power consumption after the configuration is executed is used as the overall system performance cost to construct the objective function; The system latency includes the decoding latency caused by the error correction engine executing the configured error correction code rate, and the access latency caused by the cache partition weights configured by the cache manager; the system power consumption includes the decoding power consumption generated by the error correction engine executing the configured error correction code rate, and the read / write power consumption generated by the cache partition weights configured by the cache manager.

6. The method according to any one of claims 1 to 5, characterized in that, The monitoring of the physical state of the high-bandwidth flash memory chip yields multi-dimensional media state parameters, including: The temperature and number of erase / write cycles of the high-bandwidth flash memory chip are monitored in real time to obtain the current chip temperature and the number of programming or erasing cycles. The read voltage distribution of the high-bandwidth flash memory chip is sampled to obtain the current read voltage distribution, and the mean difference between the current read voltage distribution and the preset reference voltage distribution is calculated as the current read voltage distribution offset. The read error situation of the high-bandwidth flash memory chip is monitored and calculated to obtain the read error count at different times, and the rate of change of the read error count within a preset time window is calculated to obtain the read error count slope; The current number of programming / erase cycles, the chip temperature, the read voltage distribution offset, and the read error count slope are output as the multidimensional media state parameters.

7. The method according to any one of claims 1 to 5, characterized in that, The step of jointly adjusting the error correction configuration and cache configuration of the high-bandwidth flash memory chip based on the target error correction code rate and the target cache partition weight to achieve coordinated control of error correction and cache includes: Based on the target error correction bitrate, configure the bitrate parameters of the error correction engine and the maximum number of decoding iterations; Based on the target cache partition weight, configure the space allocation ratio of the read cache and write cache of the cache manager; Based on the configured bitrate parameters, the maximum number of decoding iterations, and the space allocation ratio of the read cache and write cache, the high-bandwidth flash memory chip is subjected to coordinated control of decoding and caching operations.

8. A high-bandwidth flash memory controller, characterized in that, include: The monitoring module is used to monitor the physical state of the high-bandwidth flash memory chip, obtain multi-dimensional media state parameters, and acquire historical operating data of the high-bandwidth flash memory chip. The prediction module is used to predict the media state of the high-bandwidth flash memory chip at a future time based on the multi-dimensional media state parameters and the historical operating data, and to obtain the predicted media state and the uncertainty index of the predicted media state. The solution module is used to perform multi-objective solutions for the error correction code rate and cache partition weight of the high-bandwidth flash memory chip at future moments based on the predicted medium state and the uncertainty index, so as to obtain the target error correction code rate and target cache partition weight. The adjustment module is used to jointly adjust the error correction configuration and cache configuration of the high-bandwidth flash memory chip based on the target error correction code rate and the target cache partition weight, so as to achieve collaborative control of error correction and cache.

9. A readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the data processing method of the high-bandwidth flash controller according to any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the data processing method of the high-bandwidth flash controller according to any one of claims 1 to 7.

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