SOE reading and storing method, device and storage medium

Abstract

The application discloses a SOE reading and storage method and device and a storage medium, and belongs to the technical field of automatic industrial control. The application adopts a layered asynchronous cache architecture, writes real-time generated SOE events into an SRAM ring FIFO cache queue first, and then periodically carries the SOE events to sector batch cache space in SPI NOR FLASH by a background task; when power is initialized, valid records are identified by traversing sector first bytes, and SOE data stored before power-off is recovered; in the writing process, a multi-sector wear leveling mechanism is adopted, and all sectors are evenly worn by being erased in a cycle. Without replacing high-priced FRAM chips, the application realizes long-term reliable storage of SOE events by using low-cost SPI NOR FLASH, and effectively prolongs the service life of the storage medium.

Description

Technical Field

[0001] This invention relates to a method, apparatus, and storage medium for reading and storing SOE, belonging to the field of automation industrial control technology. Background Technology

[0002] Currently, power relay protection, measurement and control devices and DCS systems generally adopt a two-level hierarchical storage architecture when storing SOE (Sequence of Events), that is, real-time data is first written to a high-speed RAM ring cache, and then transferred to a non-volatile persistent storage medium by a background task.

[0003] In the selection of persistent storage media, the industry currently mainly follows two technical routes:

[0004] 1. FRAM (Ferroelectric Random Access Memory) is used. FRAM has a theoretical upper limit of 100 trillion read / write erase cycles. Even with high-frequency SOE events during the entire lifespan of a power device (typically 20-30 years), its erase / write lifespan far exceeds practical requirements, eliminating the risk of memory failure due to erase wear. However, the hardware cost of FRAM is significantly higher. Taking chips of the same capacity (4Mbit) and the same package (SPI SOIC-8 industrial grade) as an example, the material cost of FRAM is approximately 8-17 times that of SPI NOR FLASH, and the average price in conventional mass production is about 12 times higher, with a price difference of about 50-100 yuan per chip. For large-scale mass production equipment, the material cost pressure of storage is substantial.

[0005] 2. SPI NOR FLASH is used. This storage medium is inexpensive and has strong hardware versatility, but its inherent drawback is its limited erase lifespan, typically supporting only about 100,000 erase operations. In typical high-frequency SOE applications, if one SOE event is generated every 10ms, and every 256 SOE events constitute a 4KB sector and an erase operation is performed, the erase lifespan of a single sector can be exhausted in about 3 days, resulting in bad blocks and failing to meet the long-term stable operation requirements of power installations with a service life of 20-30 years.

[0006] In summary, how to achieve long-term reliable storage of SOE sequential events in industrial-grade power devices while balancing storage lifespan and hardware costs is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a SOE reading and storage method, device and storage medium. Under the premise of ensuring an average lifespan of 20 to 30 years for power embedded devices, this invention takes into account the high cost of FRAM hardware of the same capacity, and chooses to use low-cost SPI NOR Flash hardware. Through a hierarchical asynchronous cache architecture and a multi-sector wear leveling method, it achieves economical long-term stable storage of SOE sequential events.

[0008] To achieve the above objectives, the present invention is implemented using the following technical solution:

[0009] In a first aspect, the present invention provides a method for reading and storing SOE, comprising:

[0010] Initialize the real-time SRAM ring FIFO cache queue and the sector batch cache space in the SPI NOR FLASH, and copy the SOE sequential event record stored in the sector batch cache space at the last power failure to the real-time SRAM ring FIFO cache queue.

[0011] In the background storage task scheduling layer, the SOE sequential event records in the real-time SRAM ring FIFO cache queue are copied to the sector batch cache space periodically in the background. During the copying process, a multi-sector wear leveling mechanism is used to perform sector erase and write scheduling control.

[0012] According to the multi-sector wear leveling mechanism, each sector of the SPI NOR FLASH is erased in a cyclical manner, and after erasing is completed, the data to be written is written to the corresponding sector in sequence, thereby realizing the storage of SOE sequential events on the SPI NOR FLASH.

[0013] Furthermore, the initialization of the real-time SRAM ring FIFO cache queue and the sector batch cache space in the SPI NOR FLASH, and the copying of the SOE sequential event records stored in the sector batch cache space at the time of the last power failure to the real-time SRAM ring FIFO cache queue, includes:

[0014] Initialize the real-time SRAM ring FIFO buffer queue, with a buffer size of [size missing]. And initialize the sector batch cache space in the SPI NORFLASH, the sector batch cache space size is The size of each sector of the SPI NOR FLASH is fixed. ;

[0015] Store the data from the previous power outage in the sector's batch cache space. Each SOE sequential event record is copied to the real-time SRAM ring FIFO buffer queue, wherein each SOE sequential event... byte, ;

[0016] Traverse the first byte of each SOE sequential event in the sector batch cache space, determine the position of the valid SOE record based on whether the first byte is the special character 0xFF, and copy the valid SOE record to the real-time SRAM ring FIFO cache queue as the starting data for subsequent disk flushing operations.

[0017] Furthermore, the first byte of each SOE sequential event in the sector batch cache space is traversed, and the location of the valid SOE record is determined based on whether the first byte is the special character 0xFF. The valid SOE record is then copied to the real-time SRAM ring FIFO cache queue, including:

[0018] Traverse the batch cache space of the sectors If the first byte of a sequence of SOE events is the special character 0xFF, then the subsequent consecutive events are evaluated. Is each byte 0xFF?

[0019] If so, divide this location address by Obtain the sequence number of the SOE sequential event record. Search for the sequence number before The sector containing each SOE sequential event record is denoted as _(Sector Number)_. ;

[0020] judge If it is true, then take it. In each sector Each sector is copied entirely to the real-time SRAM circular FIFO cache queue; otherwise, it will be copied to the real-time SRAM circular FIFO cache queue. Each sector is copied as a whole to the real-time SRAM circular FIFO cache queue; if the first character is not the special character 0xFF, the traversal position is shifted down one position to continue the search.

[0021] Furthermore, in the multi-sector wear leveling mechanism, the maximum number of SOEs stored in a sector of the SPI NOR FLASH is denoted as the avalanche coefficient. It is used to limit the maximum number of SOEs saved within a flush cycle and to control sector writes based on the difference between the SOE sequence number of the current flush cycle and the previous flush cycle.

[0022] Furthermore, in the background storage task scheduling layer, the periodic copying of SOE sequential event records from the real-time SRAM ring FIFO cache queue to the sector batch cache space includes:

[0023] The sector number storing the latest SOE sequential event record in the sector batch cache space is calculated and rounded down to obtain... This sector will be used as the sector to be written. And obtain the end of the previous disk flushing cycle. Number of SOE sequential events not flushed to cache ;

[0024] Record the end of the previous disk flushing cycle The real-time SRAM ring FIFO cache queue has its most recent SOE sequence number decremented. for End of current disk flushing cycle The most recent SOE sequence number of the real-time SRAM ring FIFO buffer queue is ;

[0025] judge Is it true? If so, then... Plus Post-assignment to Otherwise, proceed to the next step of the judgment;

[0026] judge If the condition is true, recalculate the SOE sequence number at the end of the previous flush cycle; otherwise, proceed according to... and The difference determines the number of SOE records to be written in the current week, and the storage space of the real-time SRAM ring FIFO cache queue containing the corresponding record is stored in the SPI NOR FLASH with the sequence number [number missing]. The sector.

[0027] Furthermore, the aforementioned according to and The difference determines the number of SOE records to be written in the current week, and the storage space of the real-time SRAM ring FIFO cache queue containing the corresponding record is stored in the SPI NOR FLASH with the sequence number [number missing]. The sectors include:

[0028] remember for Divide by The remainder, that is ;

[0029] judge If it is true, then take it. The 4KB space of the real-time SRAM ring FIFO buffer queue where the SOE sequential event record is located is stored in the SPI NOR FLASH with the sequence number [number missing]. The sector; updated at the end of the previous flush cycle. The number of SOE sequential events that were not flushed to the cache is ,and ;

[0030] Otherwise take The 4KB space of the real-time SRAM ring FIFO buffer queue where the SOE sequential event record is located is stored in the SPI NOR FLASH with the sequence number [number missing]. The sector, and .

[0031] Furthermore, after completing the writing of the current sector, the sequence number of the sector to be written is incremented by 1, denoted as . ,judge If the condition is not met, proceed to the next disk flushing cycle; if it is met, then... Then, it will proceed to the next disk refresh cycle to continue execution.

[0032] Secondly, the present invention provides an SOE reading and storage device for implementing the SOE reading and storage method described in any one of the foregoing claims, comprising:

[0033] The cache initialization and data recovery module is used to initialize the real-time SRAM ring FIFO cache queue and the sector batch cache space in SPI NORFLASH, and copy the SOE sequential event records stored in the sector batch cache space at the time of the last power failure to the real-time SRAM ring FIFO cache queue.

[0034] The background scheduling storage module is used to periodically copy the SOE sequential event records in the real-time SRAM ring FIFO cache queue to the sector batch cache space through the background. During the copying process, a multi-sector wear leveling mechanism is used for sector erase and write scheduling control.

[0035] The wear leveling control module is used to perform cyclic erasure of each sector of the SPI NOR FLASH in units of the multi-sector wear leveling mechanism, and write the data to be written to the corresponding sector in sequence after the erasure is completed, so as to realize the storage of SOE sequential events on the SPI NOR FLASH.

[0036] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described above.

[0037] Fourthly, the present invention provides an electronic device, comprising:

[0038] Memory, used to store computer programs / instructions;

[0039] A processor for executing the computer program / instructions to implement the steps of any of the methods described above.

[0040] Fifthly, the present invention provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.

[0041] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0042] This invention provides a method, apparatus, and storage medium for SOE reading and storage. Using low-cost SPI NOR Flash as the storage hardware, it addresses the shortcomings of traditional SPI NOR Flash in high-frequency SOE scenarios, such as insufficient erase lifespan and susceptibility to bad blocks, through a hierarchical asynchronous cache architecture and a multi-sector wear leveling method. While meeting the requirements of a 20-30 year service life for power equipment and complete time-series storage of high-frequency SOE events, it significantly reduces storage material costs, eliminates the need to replace expensive FRAM chips, does not occupy additional hardware resources, and does not affect the real-time control and protection performance of the device. The hardware is highly versatile and suitable for large-scale mass production applications in power relay protection, measurement and control, and DCS equipment. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the layered asynchronous caching architecture provided in an embodiment of the present invention;

[0044] Figure 2 This is a flowchart of SOE sequential event reading and storage provided in an embodiment of the present invention. Detailed Implementation

[0045] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0046] Example 1:

[0047] This embodiment describes a method for reading and storing SOE data, including:

[0048] Initialize the real-time SRAM ring FIFO cache queue and the sector batch cache space in the SPI NOR FLASH, and copy the SOE sequential event record stored in the sector batch cache space at the last power failure to the real-time SRAM ring FIFO cache queue.

[0049] In the background storage task scheduling layer, the SOE sequential event records in the real-time SRAM ring FIFO cache queue are copied to the sector batch cache space periodically in the background. During the copying process, a multi-sector wear leveling mechanism is used to perform sector erase and write scheduling control.

[0050] According to the multi-sector wear leveling mechanism, each sector of the SPI NOR FLASH is erased in a cyclical manner, and after erasing is completed, the data to be written is written to the corresponding sector in sequence, thereby realizing the storage of SOE sequential events on the SPI NOR FLASH.

[0051] The SOE reading and storage method provided in this embodiment involves the following steps in its application process:

[0052] S1. Initialize the real-time SRAM ring FIFO buffer queue, with a buffer size of [size missing]. SPI NOR FLASH bulk sector cache space, the bulk sector cache space size is The size of each sector is fixed. Then, the data stored in the SPI NOR FLASH sector batch cache space during the last power outage... Each SOE sequential event record is copied to a real-time SRAM ring FIFO buffer, where each SOE sequential event... byte, Since the default value for erasing unwritten data in SPI NOR FLASH is the special character 0xFF, the specific method is as follows:

[0053] S11. Traverse the batch sector cache space If the first byte of a sequential event is a special character 0xFF, proceed to S12; otherwise, proceed to S14.

[0054] S12, Continuous judgment after the judgment If the given byte is 0xFF, then divide the address of this location by 0xFF. Get the sequence number of the sequential event record Search for the sequence number before The sector containing each SOE sequential event record is denoted as _(Sector Number)_. If not, proceed to S13; otherwise, proceed to S14.

[0055] S13, Judgment If it is true, then take it. In each sector The entire sector is copied to the real-time SRAM circular FIFO buffer queue and enters S2; otherwise, if so, it is... Each sector is copied as a whole to the real-time SRAM ring FIFO buffer queue and enters S2.

[0056] S14. Shift the traversal position down one position and proceed to S11;

[0057] S2. In the background storage task scheduling layer, the SOE sequential event records in the circular SRAM FIFO cache are periodically copied to the SPI NOR FLASH sector batch cache space. The data copying process adopts a multi-sector wear leveling mechanism, and the maximum number of SOEs stored in a sector is denoted as the avalanche coefficient. In order to suppress SOE avalanche, the maximum number of SOEs allowed to be saved during the disk flushing cycle is specified as follows:

[0058] S21. Calculate the sector number storing the latest SOE sequential event record in the batch sector cache space and round it down to get... This sector will be used as the sector to be written. Record the end of the previous disk flushing cycle. Number of SOE sequential events not flushed to cache Enter S22;

[0059] S22, Record the end of the previous disk flushing cycle. The most recent SOE sequence number of the real-time SRAM ring FIFO buffer queue is subtracted. for End of current disk flushing cycle The sequence number of the nearest queue (SOE) in the real-time SRAM ring FIFO buffer is ,judge Is it true? If so, then Plus Amplitude assigned Otherwise proceed to S23;

[0060] S23, Judgment Is this condition met? If yes, proceed to S22; otherwise, proceed to S24.

[0061] S24, Note for Divide by The remainder, that is ,judge Is it true? If so, then take it. The SOE sequential event record is stored in 4KB of SRAM space, with the sequence number being [number missing]. If the sector is not specified, proceed to S25; otherwise, retrieve... The SOE sequential event record is stored in 4KB of SRAM space, with the sequence number being [number missing]. The sector, and Enter S26;

[0062] S25, Update the last flush cycle. Number of SOE sequential events not flushed to cache ,and Enter S26;

[0063] S26. Increment the index of the sector to be written by 1, and denote it as... ,judge Is it true? If not, proceed to S22; if yes, take... Enter S22.

[0064] This embodiment uses low-cost SPI NOR Flash as the storage hardware. Through a hierarchical asynchronous cache architecture and a multi-sector wear leveling method, it solves the defects of traditional SPI NOR Flash in high-frequency SOE scenarios, such as insufficient erase life and easy generation of bad blocks in a short period of time. Under the premise of meeting the requirements of a 20-30 year ultra-long service life of power equipment and complete time-series storage of high-frequency SOE events, it significantly reduces the cost of storage materials, does not require the replacement of expensive FRAM chips, does not occupy additional hardware resources, does not affect the real-time control and protection performance of the device, has strong hardware versatility, and is suitable for large-scale mass production applications of power relay protection, measurement and control, and DCS equipment.

[0065] The following description, in conjunction with a preferred embodiment, illustrates the content involved in the above embodiments.

[0066] Get the smallest erase unit of the SPI NOR Flash sector The construction process of the layered asynchronous caching architecture is as follows:

[0067] S1. Initialize the real-time SRAM ring FIFO buffer queue, with a buffer size of [size missing]. The starting address is 0x10000000; SPI NOR FLASH batch sector cache space, the size of which is... The starting address is 0x00000000, and the ending address is 0x013FFFFF, with each sector having a fixed size. Then, the data stored in the SPI NOR FLASH sector batch cache space during the last power outage... Each SOE sequential event record is copied to a real-time SRAM ring FIFO buffer, where each SOE sequential event... byte, Since SPINOR FLASH erases unwritten data space by default using the special character 0xFF, the specific method is as follows:

[0068] S11. Traverse the batch sector cache space If the first character of the sequence event is 0x00100840 and is a special character 0xFF, proceed to S12;

[0069] S12, Continuous judgment after the judgment If bytes 0x00100840 to 0x0010085F are FF, then dividing this address by 32 gives the sequence number of the sequential event record. Locate the sector containing the 1024 SOE sequential event records preceding this sequence number. The space ranges from 0x000F8840 to 0x00100840-1, corresponding to sector numbers 249 to 257. According to Table 1, the number of sectors is... Enter S13;

[0070] S13, Judgment Then, the last 8 sectors out of the 9 sectors, corresponding to the sequence numbers 250 to 257, are copied as a whole to the real-time SRAM ring FIFO cache queue and enter S2;

[0071] S2. In the background storage task scheduling layer, the SOE sequential event records in the circular SRAM FIFO cache are periodically copied to the SPI NOR FLASH sector batch cache space. The data copying process adopts a multi-sector wear leveling mechanism, and the maximum number of SOEs stored in a sector is denoted as the avalanche coefficient. In order to suppress SOE avalanche, the maximum number of SOEs allowed to be saved during the disk flushing cycle is specified as follows:

[0072] S21. Calculate the sector sequence number in the batch sector cache space that stores the latest SOE sequential event record. To round down This sector will be used as the sector to be written. Since the device is starting its first cycle, record the end of the previous brush cycle. Number of SOE sequential events not flushed to cache Enter S22;

[0073] S22, Record the end of the previous disk flushing cycle. Subtract the most recent SOE sequence number from the real-time SRAM ring FIFO buffer queue for From Table 1, we can see that... End of current disk flushing cycle The sequence number of the nearest queue (SOE) in the real-time SRAM ring FIFO buffer is ,judge ,but Enter S23;

[0074] S23, Judgment Enter S24,

[0075] S24, Note ,judge Then take The 4k space of the SRAM where the SOE sequential event record is located is stored into sector number 256, and then enters S25;

[0076] S25, Update the last flush cycle. Number of SOE sequential events not flushed to cache Then Enter S26;

[0077] S26. Increment the index of the sector to be written by 1 to 257, and record it as... ,judge Then proceed to S27, the next disk refresh cycle;

[0078] S27, Record the end of the previous disk flushing cycle. Subtract the most recent SOE sequence number from the real-time SRAM ring FIFO buffer queue for , End of current disk flushing cycle The real-time SRAM ring FIFO buffer's nearest queue SOE sequence number is p2=10. (The question is incomplete and requires further context.) Enter S28;

[0079] S28, Judgment Enter S29;

[0080] S29, Note for Divide by remainder ,judge ,Pick The SOE sequential event record is stored in 4KB of SRAM, in sector number 257, and... Enter S30.

[0081] S30. Increment the sequence number of the sector to be written by 1, and record it as... ,judge Then proceed to S27; at this point, the next disk flushing cycle begins.

[0082] Table 1 SOE Sequential Event Sequence Number Address Table

[0083]

[0084] Example 2:

[0085] The SPI NOR FLASH batch sector cache space described in Example 1 has a size of [size missing]. , and The time interval is 30 seconds, and 128 SOE sequential events are generated within this time interval, meaning that one 4K sector is erased every 30 seconds. Following the multi-sector wear leveling method, the SPI NOR FLASH erase lifetime is calculated as follows:

[0086] Calculate the total number of available sectors The 320 sectors are erased in a cyclical manner. Each sector is erased once to complete one cycle. The total time for a single cycle is as follows: If the total number of erasable cycles is 100,000 erasures per sector, then the total theoretical lifespan is... This meets the requirements of an ultra-long service life of 20 to 30 years for power installations.

[0087] Example 3:

[0088] This embodiment provides an SOE reading and storage device, including:

[0089] The cache initialization and data recovery module is used to initialize the real-time SRAM ring FIFO cache queue and the sector batch cache space in SPI NORFLASH, and copy the SOE sequential event records stored in the sector batch cache space at the time of the last power failure to the real-time SRAM ring FIFO cache queue.

[0090] The background scheduling storage module is used to periodically copy the SOE sequential event records in the real-time SRAM ring FIFO cache queue to the sector batch cache space through the background. During the copying process, a multi-sector wear leveling mechanism is used for sector erase and write scheduling control.

[0091] The wear leveling control module is used to perform cyclic erasure of each sector of the SPI NOR FLASH in units of the multi-sector wear leveling mechanism, and write the data to be written to the corresponding sector in sequence after the erasure is completed, so as to realize the storage of SOE sequential events on the SPI NOR FLASH.

[0092] The specific functions of each module described above are explained in the relevant content of the method in Embodiment 1, and will not be repeated here.

[0093] Example 4:

[0094] This embodiment provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in Embodiment 1.

[0095] Example 5:

[0096] This embodiment provides an electronic device, including:

[0097] Memory, used to store computer programs / instructions;

[0098] A processor for executing the computer program / instructions to implement the steps of the method described in Embodiment 1.

[0099] Example 6:

[0100] This embodiment provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the method described in Embodiment 1.

[0101] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

[0102] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0103] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0104] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0105] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure and not to limit its protection scope. Although this disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that after reading this disclosure, they can still make various changes, modifications or equivalent substitutions to the specific implementation of the invention, but these changes, modifications or equivalent substitutions are all within the protection scope of the pending claims.

Claims

1. A method for reading and storing SOE data, characterized in that, include: Initialize the real-time SRAM ring FIFO cache queue and the sector batch cache space in the SPI NOR FLASH, and copy the SOE sequential event record stored in the sector batch cache space at the last power failure to the real-time SRAM ring FIFO cache queue. In the background storage task scheduling layer, the SOE sequential event records in the real-time SRAM ring FIFO cache queue are copied to the sector batch cache space periodically in the background. During the copying process, a multi-sector wear leveling mechanism is used to perform sector erase and write scheduling control. According to the multi-sector wear leveling mechanism, each sector of the SPI NOR FLASH is erased in a cyclical manner, and after erasing is completed, the data to be written is written to the corresponding sector in sequence, thereby realizing the storage of SOE sequential events on the SPI NOR FLASH.

2. The SOE reading and storage method according to claim 1, characterized in that, The initialization of the real-time SRAM ring FIFO cache queue and the sector batch cache space in the SPI NOR FLASH, and the copying of the SOE sequential event records stored in the sector batch cache space at the time of the last power failure to the real-time SRAM ring FIFO cache queue, includes: Initialize the real-time SRAM ring FIFO buffer queue, with a buffer size of [size missing]. And initialize the sector batch cache space in the SPI NOR FLASH, the size of which is The size of each sector of the SPI NOR FLASH is fixed. ; Store the data from the previous power outage in the sector's batch cache space. Each SOE sequential event record is copied to the real-time SRAM ring FIFO buffer queue, wherein each SOE sequential event... byte, ; Traverse the first byte of each SOE sequential event in the sector batch cache space, determine the position of the valid SOE record based on whether the first byte is the special character 0xFF, and copy the valid SOE record to the real-time SRAM ring FIFO cache queue as the starting data for subsequent disk flushing operations.

3. The SOE reading and storage method according to claim 2, characterized in that, Traverse the first byte of each SOE sequential event in the sector batch cache space, determine the location of the valid SOE record based on whether the first byte is the special character 0xFF, and copy the valid SOE record to the real-time SRAM ring FIFO cache queue, including: Traverse the batch cache space of the sectors If the first byte of a sequence of SOE events is the special character 0xFF, then the subsequent consecutive events are evaluated. Is each byte 0xFF? If so, divide this location address by Obtain the sequence number of the SOE sequential event record. Search for the sequence number before The sector containing each SOE sequential event record is denoted as _(Sector Number)_. ; judge Is it true? If so, then take it. In each sector Each sector is copied entirely to the real-time SRAM circular FIFO cache queue; otherwise, it will be copied to the real-time SRAM circular FIFO cache queue. Each sector is copied as a whole to the real-time SRAM circular FIFO cache queue; if the first character is not the special character 0xFF, the traversal position is shifted down one position to continue the search.

4. The SOE reading and storage method according to claim 1, characterized in that, In the multi-sector wear leveling mechanism, the avalanche coefficient is defined as the maximum number of SOEs stored in a sector of the SPI NOR FLASH. It is used to limit the maximum number of SOEs saved within a flush cycle and to control sector writing based on the difference between the SOE sequence number of the current flush cycle and the previous flush cycle.

5. The SOE reading and storage method according to claim 4, characterized in that, In the background storage task scheduling layer, the SOE sequential event records in the real-time SRAM ring FIFO cache queue are periodically copied to the sector batch cache space, including: The sector number storing the latest SOE sequential event record in the sector batch cache space is calculated and rounded down to obtain... This sector will be used as the sector to be written. And obtain the end of the previous disk flushing cycle. Number of SOE sequential events not flushed to cache ; Record the end of the previous disk flushing cycle The real-time SRAM ring FIFO cache queue has its most recent SOE sequence number decremented. for End of current disk flushing cycle The most recent SOE sequence number of the real-time SRAM ring FIFO buffer queue is ; judge Is it true? If so, then... Plus Post-assignment to Otherwise, proceed to the next step of the judgment; judge If the condition is true, recalculate the SOE sequence number at the end of the previous flush cycle; otherwise, proceed according to... and The difference determines the number of SOE records to be written in the current week, and the storage space of the real-time SRAM ring FIFO cache queue containing the corresponding record is stored in the SPI NOR FLASH with the sequence number [number missing]. The sector.

6. The SOE reading and storage method according to claim 5, characterized in that, According to and The difference determines the number of SOE records to be written in the current week, and the storage space of the real-time SRAM ring FIFO cache queue containing the corresponding record is stored in the SPI NOR FLASH with the sequence number [number missing]. The sectors include: remember for Divide by The remainder, that is ; judge Is it true? If so, then take it. The 4KB space of the real-time SRAM ring FIFO buffer queue where the SOE sequential event record is located is stored in the SPI NOR FLASH with the sequence number [number missing]. The sector; and update the last sector of the previous flush cycle. The number of SOE sequential events that were not flushed to the cache is ,and ; Otherwise take The 4KB space of the real-time SRAM ring FIFO buffer queue where the SOE sequential event record is located is stored in the SPI NOR FLASH with the sequence number [number missing]. The sector, and .

7. The SOE reading and storage method according to claim 6, characterized in that, After completing the writing of the current sector, increment the sequence number of the sector to be written by 1, and record it as . ,judge If the condition is not met, proceed to the next disk flushing cycle; if it is met, then... Then, it will proceed to the next disk refresh cycle to continue execution.

8. A SOE reading and storage device, characterized in that, include: The cache initialization and data recovery module is used to initialize the real-time SRAM ring FIFO cache queue and the sector batch cache space in SPI NORFLASH, and copy the SOE sequential event records stored in the sector batch cache space at the time of the last power failure to the real-time SRAM ring FIFO cache queue. The background scheduling storage module is used to periodically copy the SOE sequential event records in the real-time SRAM ring FIFO cache queue to the sector batch cache space through the background. During the copying process, a multi-sector wear leveling mechanism is used for sector erase and write scheduling control. The wear leveling control module is used to perform cyclic erasure of each sector of the SPI NOR FLASH in units of the multi-sector wear leveling mechanism, and write the data to be written to the corresponding sector in sequence after the erasure is completed, so as to realize the storage of SOE sequential events on the SPI NOR FLASH.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When executed by a processor, the computer program implements the steps of the method described in any one of claims 1-7.

10. An electronic device, characterized in that, include: Memory, used to store computer programs / instructions; A processor for executing the computer program / instructions to implement the steps of the method according to any one of claims 1-7.

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