Data tiering storage method, memory controller, and computer program product

Abstract

The present disclosure provides a data tiered storage method, a memory controller and a computer program product. The method divides a logical block address space of a storage device into multiple regions; in response to a read command from a host, determines a target region accessed by the read command, and updates read statistics information of the target region; determines a read heat of the target region based on the read statistics information, the read heat decaying over time in a case where the target region is not read again; determines a heat state of the target region according to the read heat; and performs data migration of target data in the target region between a high-speed storage region and a regular storage region according to the heat state and a storage region where the target data is located, so that data of a region with frequent read access is placed in the high-speed storage region with higher read performance, and data of a region with cold-to-hot transition is migrated back to the regular storage region, thereby supporting bidirectional tiered storage of hot and cold data.

Description

Technical Field

[0001] This disclosure relates to the field of data storage technology, and more particularly to a data hierarchical storage method, memory controller, and computer program product suitable for storage devices. Background Technology

[0002] Storage devices typically include a memory controller and memory modules. Memory modules, for example, consist of NAND flash memory where each cell stores multiple bits. This type of flash memory has advantages in storage density, but its read performance and lifespan are weaker than flash memory storing fewer bits per cell. To improve read response speed, storage devices can configure some flash memory as high-performance storage areas and separate frequently accessed data into hot and cold data areas. In practical applications, scenarios such as application startup, file loading, and photo browsing involve a large number of data read operations, making users highly sensitive to read response speed. However, existing hot and cold data separation schemes mostly use write frequency as the basis for determining hot and cold data, or use fixed thresholds for coarse-grained division, lacking fine-grained statistics and dynamic tracking of read operations, making it difficult to reflect changes in data access over time. Traditional statistical methods require maintaining an independent counter for each logical block address or each physical page, and memory overhead increases linearly with storage capacity, making it difficult to implement under limited memory resources of storage devices. Furthermore, the migration of data between different storage areas itself generates additional writes, and when the device temperature is high or the number of erase / write cycles of the flash memory reaches a high level, frequent migration may accelerate flash memory wear and thermal failure.

[0003] Therefore, accurately identifying hot and cold data read / access variations with limited memory overhead, and placing data in appropriate storage areas while protecting the flash memory medium, are currently unresolved technical problems. Summary of the Invention

[0004] In view of this, the present disclosure provides a data hierarchical storage method, a memory controller, and a computer program product. By statistically analyzing read accesses on a region-by-region basis, determining the read frequency that decreases over time, and determining the frequency status accordingly, the method then performs bidirectional data migration between high-speed storage areas and regular storage areas based on the frequency status and the storage area where the data is located. This allows frequently accessed data to be placed in high-speed storage areas with higher read performance, thereby improving read response speed.

[0005] According to a first aspect of this disclosure, a hierarchical data storage method is provided, applicable to a storage device configured with a memory controller and a memory module, wherein the memory module includes a conventional storage area and a high-speed storage area with higher read performance than the conventional storage area. The method includes: dividing the logical block address space of the storage device into multiple regions; in response to a read command from a host, determining the target region to which the logical block address accessed by the read command belongs, and updating read statistics of the target region; determining the read popularity of the target region based on the read statistics of the target region, wherein the read popularity decays over time if the target region is not read again; determining the popularity status of the target region based on the read popularity; and performing data migration of the target data between the high-speed storage area and the conventional storage area based on the popularity status of the target region and the storage area where the target data is located in the target region.

[0006] According to a second aspect of this disclosure, a memory controller is provided, suitable for a storage device configured with a memory module, the memory module including a conventional storage area and a high-speed storage area with higher read performance than the conventional storage area. The memory controller includes: a host interface control circuit for electrically connecting to a host; a memory interface control circuit for electrically connecting to the memory module; and a processor electrically connected to the host interface control circuit and the memory interface control circuit, wherein the processor is configured to: divide the logical block address space of the storage device into multiple regions; in response to a read command from the host, determine the target region to which the logical block address accessed by the read command belongs, and update read statistics of the target region; determine the read heat of the target region based on the read statistics of the target region, wherein the read heat decays over time if the target region is not read again; determine the heat state of the target region based on the read heat; and perform data migration of the target data between the high-speed storage area and the conventional storage area based on the heat state of the target region and the storage area where the target data of the target region is located.

[0007] According to a third aspect of this disclosure, a computer program product is provided, comprising a computer program that, when loaded and executed by a memory controller of a storage device, causes the memory controller to perform the following steps, wherein the storage device is configured with a memory module, the memory module including a conventional storage area and a high-speed storage area with higher read performance than the conventional storage area: dividing the logical block address space of the storage device into multiple regions; in response to a read command from a host, determining the target region to which the logical block address accessed by the read command belongs, and updating read statistics of the target region; determining the read heat of the target region based on the read statistics of the target region, wherein the read heat decays over time if the target region is not read again; determining the heat status of the target region based on the read heat; and performing data migration of the target data between the high-speed storage area and the conventional storage area based on the heat status of the target region and the storage area where the target data of the target region is located.

[0008] Based on the above, the technical solution provided in this disclosure determines the read heat based on the read statistics of the target area. The read heat decreases over time when the target area is not read again, and the read heat of areas that have not been read for a long time decreases accordingly. Therefore, the heat statistics can reflect the dynamic changes in read access over time, rather than relying on a single fixed count. The heat status of the target area is determined based on the read heat, and data migration is performed based on the heat status and the storage area where the data is located. This allows data in areas with frequent read access to be migrated to high-speed storage areas with higher read performance, improving host read response speed. Data in areas that have transitioned to a second heat status can be migrated back to regular storage areas, freeing up space in high-speed storage areas for other areas, thereby supporting bidirectional hierarchical storage between high-speed and regular storage areas. Furthermore, performing read statistics on a region-by-region basis, compared to maintaining an independent counter for each logical block address or each physical page, helps reduce the memory overhead required for statistics. Attached Figure Description

[0009] Figure 1A This is a block diagram illustrating a host system and storage device according to an embodiment of the present disclosure;

[0010] Figure 1B This is a software functional module architecture diagram of a memory controller shown according to an embodiment of the present disclosure;

[0011] Figure 2A This is a main flowchart of a hierarchical data storage method according to embodiments of the present disclosure;

[0012] Figure 2B This is a flowchart illustrating data migration determination according to embodiments of the present disclosure;

[0013] Figure 3A data structure diagram of the heat table reading according to an embodiment of the present disclosure;

[0014] Figure 4 This is a flowchart illustrating heat trend prediction and bidirectional data migration according to embodiments of the present disclosure;

[0015] Figure 5 A flowchart illustrating a data migration protection mechanism according to embodiments of this disclosure;

[0016] Figure 6 This is an interactive timing diagram illustrating the execution of data migration according to embodiments of the present disclosure. Detailed Implementation

[0017] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0018] Figure 1A This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 1A The host system 10 is, for example, a personal computer, laptop computer, server, smartphone, or tablet computer. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is electrically connected to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be located on the motherboard of the host system 10.

[0019] Storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), a connection interface circuit 230, and a temperature sensor 240. The memory controller 210 includes a host interface control circuit 215, a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214. The memory module 220 includes a high-speed storage area 221 and a conventional storage area 222.

[0020] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0021] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, an embedded storage device, a solid-state drive (SSD), a USB flash drive, a memory card, or a wireless storage device. The embedded storage device can be, for example, a storage device conforming to the Universal Flash Storage (UFS) specification or a storage device conforming to the embedded MultiMediaCard (eMMC) specification. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy (BLE) storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various input / output devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, and a speaker.

[0022] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the General Flash Memory Specification. The host system 10 and the storage device 20 use the communication protocol defined by the General Flash Memory Specification to transmit commands and data. In another embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 may also be interface circuits compatible with the Embedded Multimedia Card Specification, or interface circuits compatible with the Peripheral Component Interconnect Express (PCIe) standard and use the Non-Volatile Memory Express (NVMe) communication protocol to transmit data.

[0023] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside the chip including the memory controller 210.

[0024] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0025] The memory controller 210 executes multiple logic gates or control instructions implemented in hardware or firmware, and performs data writing, reading, and erasing operations in the memory module 220 according to instructions from the host system 10, and executes the data hierarchical storage method provided in this disclosure. More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is configured with multiple control instructions or program code, and these control instructions or program code are executed during the operation of the storage device 20 to perform data writing, reading, and erasing operations.

[0026] In this embodiment, the host interface control circuit 215 is electrically connected to the host system 10 via the connection interface circuit 230, serving as the interface for the memory controller 210 to receive read commands, write commands, and logical block addresses (LBAs) and other commands and data issued by the host system 10. The host interface control circuit 215 is electrically connected to the processor 211 and transmits the received commands and data to the processor 211.

[0027] Furthermore, the processor 211 is configured to execute the data hierarchical storage method provided in this disclosure. Specifically, the processor 211 divides the logical block address space of the storage device 20 into multiple regions; in response to a read command from the host system 10, the processor 211 determines the target region to which the logical block address accessed by the read command belongs, and updates the read statistics of the target region; based on the read statistics of the target region, the processor 211 determines the read heat of the target region, wherein the read heat decreases over time if the target region is not read again; the processor 211 determines the heat state of the target region according to the read heat, wherein the heat state of the target region is determined to be a first heat state when the read heat is not less than a preset heat threshold, and the heat state of the target region is determined to be a second heat state when the read heat is less than a low heat determination threshold, wherein the low heat determination threshold is not greater than the preset heat threshold; and the processor 211 performs data migration of the target data between the high-speed storage area 221 and the regular storage area 222 according to the heat state of the target region and the storage area where the target data of the target region is located. In one embodiment, when the heat state of the target area is a first heat state and the target data is stored in the regular storage area 222, the processor 211 migrates the target data from the regular storage area 222 to the high-speed storage area 221. When the heat state of the target area is a second heat state and the target data is stored in the high-speed storage area 221, the processor 211 migrates the target data from the high-speed storage area 221 to the regular storage area 222.

[0028] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0029] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself. The data management circuit 212 is electrically connected to the processor 211 and is used to receive instructions from the processor 211 to perform data transmission. For example, data is read from the host system 10 via the host interface control circuit 215 and the connection interface circuit 230, and the read data is written to the memory module 220 via the memory interface control circuit 213. Alternatively, a read operation is performed according to a read instruction from the host system 10, data is read from one or more physical units of the memory module 220 via the memory interface control circuit 213, and the read data is written to the host system 10 via the host interface control circuit 215 and the connection interface circuit 230. In one embodiment, the data management circuit 212 also works with the processor 211 and the memory interface control circuit 213 to move data during data migration. For example, the target data is read from the conventional storage area 222 to the buffer memory 214 via the memory interface control circuit 213, and then the data temporarily stored in the buffer memory 214 is written to the high-speed storage area 221 via the memory interface control circuit 213.

[0030] In another embodiment, the data management circuit 212 may also be integrated into the processor 211. The memory interface control circuit 213 is electrically connected to the processor 211 to receive instructions from the processor 211 and, in conjunction with the data management circuit 212, perform write (also known as programming), read, or erase operations on the memory module 220. Furthermore, data to be written to the memory module 220 is converted by the memory interface control circuit 213 into a format acceptable to the memory module 220. Specifically, if the processor 211 needs to access the memory module 220, the processor 211 transmits a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations. These instruction sequences may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as the identification code to be read, the memory address, and the physical address.

[0031] Furthermore, the memory controller 210 establishes a Logical to Physical Address Mapping Table (L2P) and a Physical to Logical Address Mapping Table (P2L) to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses of physical units (e.g., physical erase units or physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can look up the physical unit mapped to a logical unit through the L2P mapping table, and the memory controller 210 can look up the logical unit mapped to a physical unit through the P2L mapping table. In this disclosure, the processor 211 updates the L2P mapping table after performing data migration, pointing the logical block address of the target region to the migrated physical address; related details will be provided later. Figure 6 The embodiments are described below.

[0032] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and instructions from host system 10, data from memory module 220, and various system data for managing storage device 20. In this embodiment, buffer memory 214 is also used to store read heat tables required by this disclosure and to temporarily store target data to be migrated when processor 211 performs data migration.

[0033] The memory module 220 is electrically connected to the memory controller 210 (specifically, electrically connected to the memory interface control circuit 213) and is used to store user data sent by the host system 10. In this disclosure, the memory module 220 is the object of data hierarchical storage performed by the processor 211. Specifically, the memory module 220 includes a high-speed storage area 221 and a regular storage area 222, wherein the read performance of the high-speed storage area 221 is higher than that of the regular storage area 222.

[0034] In this embodiment, the high-speed storage area 221 is, for example, a storage area configured in a single-level cell (SLC) mode within the memory module 220, and the conventional storage area 222 is, for example, a storage area configured in a triple-level cell (TLC) mode. Storage areas configured in a triple-level cell mode have advantages in storage density, while storage areas configured in a single-level cell mode have higher read performance and durability. It should be noted that this disclosure is not limited to this; the high-speed storage area 221 and the conventional storage area 222 can also be implemented by storage areas of other storage modes with different read performance, and neither the high-speed storage area 221 nor the conventional storage area 222 is limited to a single physical block.

[0035] In one embodiment, the memory cell structure of the memory module 220 can be understood as a multi-layered physical organization architecture. Specifically, the memory module 220 includes multiple chips, each chip has multiple planes, each plane includes multiple physical blocks, and each physical block consists of multiple physical pages. It should be noted that this disclosure does not limit the specific size of each physical page and logical page.

[0036] Furthermore, temperature sensor 240 is a built-in temperature sensor of storage device 20 used to sense the current temperature of storage device 20 (e.g., the operating temperature of memory module 220 during operation). In this embodiment, temperature sensor 240 is located next to memory module 220 and outside memory controller 210. Temperature sensor 240 is electrically connected to memory controller 210, enabling processor 211 to read the current temperature sensed by temperature sensor 240. In this disclosure, processor 211 reads the current temperature sensed by temperature sensor 240 before performing data migration as a basis for determining whether to pause data migration; related details will follow. Figure 5 The embodiments are described below.

[0037] Based on the above Figure 1A The block diagram of the host system and storage device shown illustrates that the storage device performs data migration based on read heat on the memory modules, which include high-speed storage area and conventional storage area, through a memory controller including host interface control circuit and processor and memory interface control circuit. The current temperature is provided by a temperature sensor, so that the memory controller acts as the main body for performing hierarchical data storage between the host system and the memory modules, thus constituting the execution environment of the hierarchical data storage method of this disclosure.

[0038] Figure 1B This is a software functional block architecture diagram of a memory controller according to embodiments of the present disclosure. Please refer to... Figure 1B In one embodiment, the data hierarchical storage method of this disclosure executed by the processor 211 can be implemented by multiple functional modules. These functional modules are implemented in the form of firmware or software program code and are loaded and executed by the processor 211, including LBA area management module 310, reading statistics module 320, heat determination module 330, heat table management module 340, status detection module 350 and migration execution module 360. Figure 1B The host interface control circuit 215 is also shown. The host interface control circuit 215 is... Figure 1A The host interface control circuit 215 shown is used to receive read commands issued by the host system 10 and the logical block address carried by the read command. That is, Figure 1B It can be understood as Figure 1AThe memory controller 210 shown is a functional view at the firmware level.

[0039] In this embodiment, the host interface control circuit 215 transmits the logical block address of the received read command to the LBA region management module 310 (as shown by arrow A11). The LBA region management module 310 divides the logical block address space of the storage device 20 into multiple regions according to a preset granularity and assigns a unique region identifier (Region ID) to each region. The LBA region management module 310 maps the logical block address accessed by the read command to its corresponding region. The mapped region is the target region to which the logical block address accessed by the read command belongs, and the target region is identified by the region identifier. For example, the LBA region management module 310 divides the logical block address space of the 256GB storage device 20 into 256 regions with a preset granularity of 1GB. Any logical block address accessed by the host system 10, after mapping, uniquely corresponds to one of the above 256 regions.

[0040] In one embodiment, the LBA region management module 310 passes the region identifier of the target region to the read statistics module 320 (as shown by arrow A12). The read statistics module 320 is used to accumulate the number of reads of the target region and record the most recent read time of the target region. The statistical results are used as the basis for subsequent calculation of read popularity.

[0041] In one embodiment, the read statistics module 320 transmits statistical values ​​such as the cumulative number of reads and the most recent read time of the target area to the popularity determination module 330 (as shown by arrow A13). The cumulative number of reads and the most recent read time of the target area constitute the read statistics information of the target area. The popularity determination module 330 calculates the read popularity based on the read statistics information of the target area. If the target area is not read again, the read popularity decreases over time, and the popularity determination module 330 determines the popularity status of the target area based on the read popularity. The specific calculation method of read popularity and the determination criteria for popularity status will be discussed later. Figure 2A The embodiments are described below.

[0042] In one embodiment, the heat determination module 330 transmits the calculated read heat and the determined heat status to the heat table management module 340 (as shown by arrow A14). The heat table management module 340 updates the record corresponding to the target area in the read heat table based on the read statistics of the target area. This record includes the target area's region identifier, cumulative read count, most recent read time, read heat, and heat status. At the end of each statistical period, it performs periodic decay and update of the read heat. The specific structure of the read heat table will be discussed later. Figure 3 The embodiments are described below.

[0043] In one embodiment, the heat table management module 340 traverses and reads each region in the heat table, and passes the regions whose heat status and the storage area where the data is located meet the data migration conditions as migration candidates to the status detection module 350 (as shown by arrow A15). The status detection module 350 is used to detect whether the current temperature of the storage device 20 has reached a preset temperature threshold before performing data migration, and to detect whether the number of erase / write cycles in the high-speed storage area 221 and the number of erase / write cycles in the regular storage area 222 exceed the corresponding dynamic erase / write thresholds, and to detect whether the storage device 20 is in an idle state. Related detection conditions and pause / resume mechanisms will be discussed later. Figure 5 The embodiments are described below.

[0044] In one embodiment, the state detection module 350 notifies the migration execution module 360 ​​to perform data migration after all detections pass (as shown by arrow A16). The migration execution module 360 ​​performs data migration between the high-speed storage area 221 and the regular storage area 222 based on the heat status of the target area and the storage area where the target data is located. Target data with a first heat status and stored in the regular storage area 222 is migrated from the regular storage area 222 to the high-speed storage area 221, and target data with a second heat status and stored in the high-speed storage area 221 is migrated from the high-speed storage area 221 to the regular storage area 222. The L2P mapping table is updated after the data migration is completed. The specific execution process of the data migration and the update sequence of the L2P mapping table will be discussed later. Figure 6 The embodiments are described below.

[0045] It should be noted that, Figure 1B The functional modules shown are divided into one exemplary implementation. In another embodiment, the functions of the above-mentioned functional modules may also be implemented in fewer modules, or further divided into more modules, and this disclosure is not limited thereto. The above-mentioned functional modules are implemented, for example, by the processor 211 executing corresponding control instructions or program code, and the operations performed by each functional module can also be regarded as operations performed by the processor 211 or the memory controller 210.

[0046] Based on the above Figure 1BThe software functional module architecture diagram of the memory controller shown shows that the read commands received by the host interface control circuit are processed sequentially through the region mapping of the LBA region management module, the read statistics of the read statistics module, the heat calculation and status determination of the heat determination module, the read heat table maintenance of the heat table management module, the pre-migration detection of the status detection module, and the bidirectional migration of the migration execution module. Thus, each step of the data hierarchical storage method is executed collaboratively within the memory controller by functional modules with clearly defined functions, constituting the functional view of the data hierarchical storage method of this disclosure at the firmware level.

[0047] Figure 2A This is a main flowchart illustrating a hierarchical data storage method according to embodiments of this disclosure. Please refer to... Figure 2A In one embodiment, the data hierarchical storage method of this disclosure is comprised of... Figure 1A The memory controller 210 of the shown storage device 20 executes, more specifically, it is executed by the processor 211. The following is in conjunction with... Figure 2A Explain each step of the method.

[0048] In step S210, the processor 211 divides the logical block address space of the storage device 20 into multiple regions. Specifically, in one embodiment, the processor 211 divides the logical block address space of the storage device 20 into multiple regions according to a preset granularity, and assigns a unique region identifier to each region, as described above. Figure 1B In the embodiments, the region division performed by the LBA region management module 310 has a preset granularity of, for example, 1GB, but this disclosure is not limited thereto.

[0049] Next, in step S220, the processor 211, in response to a read command from the host system 10, determines the target region to which the logical block address accessed by the read command belongs, and updates the read statistics of the target region. In this embodiment, the read statistics of the target region include the cumulative number of reads and the most recent read time of the target region; that is, the processor 211 accumulates the number of reads of the target region and records the most recent read time of the target region. For example, when the host system 10 reads data corresponding to a logical block address falling within the address range of 1GB to 2GB, the processor 211 increments the number of reads of that region (which is the target region to which the logical block address accessed by the read command belongs) by one, and records the time of this read as the most recent read time of that region.

[0050] In step S230, the processor 211 determines the read frequency of the target area based on the read statistics of the target area. The read frequency decreases over time if the target area is not read again. Specifically, in one embodiment, the processor 211 determines the read frequency by multiplying the cumulative number of reads by a decay factor, where the decay factor is a power of the natural constant with the negative of the product of the decay constant and the time difference as the exponent. The formula for calculating the read frequency is as follows:

[0051]

[0052] in The read frequency of this target area. The cumulative number of reads for the target area is given, Δt is the time difference between the current time and the most recent read time for the target area, e is the natural constant, and λ is the decay constant, used to control the rate at which the read activity decreases over time. This decay constant is equal to the ratio of the natural logarithm of 2 to the preset time constant, i.e. ,in A preset time constant, for example, is set to 3600 seconds, meaning that if the target area is not read after 3600 seconds (i.e., 60 minutes), its read activity will decrease to half of its original value. In one embodiment, the cumulative number of reads will not increase further after reaching a preset saturation value, such as 0xFFFFFFFF, to prevent the cumulative number of reads from growing indefinitely.

[0053] In step S240, the processor 211 determines whether the read heat of the target area is not less than a preset heat threshold. If the determination result of step S240 is yes, the process proceeds to step S260; if the determination result of step S240 is no, the process proceeds to step S250. In step S250, the processor 211 determines whether the read heat is less than a low heat determination threshold, which is not greater than the preset heat threshold. In one embodiment, the low heat determination threshold is the product of the preset heat threshold and a preset hysteresis coefficient, and the preset hysteresis coefficient is greater than 0 and less than 1. The preset hysteresis coefficient is, for example, 0.8, meaning the low heat determination threshold is, for example, 0.8 times the preset heat threshold. If the determination result of step S250 is yes, the process proceeds to step S270; if the determination result of step S250 is no, the process proceeds to step S280.

[0054] In step S260, the processor 211 determines the thermal state of the target area as the first thermal state.

[0055] In step S270, the processor 211 determines the thermal state of the target area as the second thermal state.

[0056] In step S280, the processor 211 maintains the current heat state of the target area. Specifically, when the read heat is less than a preset heat threshold and not less than a low heat determination threshold, the read heat is within the hysteresis interval defined by the low heat determination threshold and the preset heat threshold. The processor 211 does not switch the heat state of the target area, thereby avoiding the target data with read heat fluctuating around the preset heat threshold from migrating back and forth between the high-speed storage area 221 and the regular storage area 222, which would consume too many erase and write cycles.

[0057] In step S290, the processor 211 performs data migration of the target data between the high-speed storage area 221 and the regular storage area 222 based on the heat status of the target area and the storage area where the target data is located. This allows the target data, which is frequently accessed, to be accessed by the host system 10 with higher read performance, while freeing up space in the high-speed storage area 221 for the target data that is being moved from hot to cold storage. Details of the data migration direction determination will be provided later. Figure 2B The embodiments are described below.

[0058] Assuming a preset heat threshold of 600 and a preset hysteresis coefficient of 0.8, the low-heat determination threshold is: Assume the cumulative number of reads for a certain target area. The number of reads is 1000. The read heat is calculated immediately after the target area is read (time difference Δt is close to 0 seconds). If the value is close to 1000 and not less than the preset heat threshold of 600, processor 211 determines this in step S240, and the process proceeds to step S260; when the target area has been in this state for 3600 seconds (i.e., a preset time constant), When not being read, the read activity decays to [value]. If the temperature reading is 500, which is less than the preset heat threshold of 600 and not less than the low heat determination threshold of 480, the processor 211 determines "no" in step S240 and "no" in step S250, and the process proceeds to step S280 to maintain the current heat state of the target area; when the time difference continues to increase to 7200 seconds, the heat reading further decreases to... If 250 is less than the preset heat threshold of 600 and less than the low heat determination threshold of 480, the processor 211 determines whether it is negative in step S240 and whether it is positive in step S250, and the process proceeds to step S270.

[0059] In one embodiment, the processor 211 further updates the read popularity and popularity status of each region in the read popularity table according to a preset statistical period, as described above. Figure 1BIn this embodiment, the heat table management module 340 performs periodic decay and updates. Furthermore, before the data migration in step S290 is executed, the current temperature, erase / write cycle count, and idle state of the storage device 20 can be detected. These detection conditions will be addressed in subsequent steps. Figure 5 The specific implementation process of data migration and the update of the L2P mapping table will be discussed in subsequent embodiments. Figure 6 The embodiments are described below; furthermore, in addition to triggering data migration based on the current read popularity, the processor 211 can also predict the predicted popularity of the next statistical period based on the changing trend of read popularity, determine the predicted popularity status based on the predicted popularity, and determine whether to perform data migration in the corresponding direction by combining the current popularity status with the storage area where the target data is located. Related details will be provided later. Figure 4 The embodiments are described below.

[0060] In another embodiment, the heat status of the target area can also be expanded from two heat statuses, namely the first heat status and the second heat status, to more levels of heat status, such as three levels of heat status including high heat status, medium heat status and low heat status. The processor 211 defines the boundary between adjacent levels by setting multiple heat thresholds that decrease sequentially, and configures different data migration priorities for different levels of heat status, such as prioritizing the migration of data in the area with the highest heat status, so as to make the scheduling granularity of data migration finer.

[0061] In another embodiment, the preset heat threshold and preset hysteresis coefficient may not be limited to fixed values. The processor 211 may dynamically adjust the preset heat threshold and preset hysteresis coefficient according to the operating status of the storage device 20. For example, when the access load of the host system 10 is high, the preset heat threshold may be increased to reduce the triggering frequency of data migration. Or, for example, when the remaining space of the high-speed storage area 221 is small, the preset heat threshold may be increased so that only data in areas with higher read heat is migrated to the high-speed storage area 221.

[0062] Based on the above Figure 2A The main flowchart of the data hierarchical storage method shown is as follows: the processor characterizes the read access heat of each area by using the read heat that decreases over time through steps S210 to S230; it defines the hysteresis interval by using a preset heat threshold and a low heat determination threshold through steps S240 and S250; and it performs data migration between the high-speed storage area and the regular storage area according to the heat status and the storage area where the data is located through step S290. This allows the storage location of the data to be adaptively adjusted according to the hot and cold changes of read access, so that the data that turns from hot to cold gives up the space of the high-speed storage area and avoids the data with the heat at the threshold from migrating back and forth.

[0063] Figure 2B This is a flowchart illustrating the data migration determination according to embodiments of this disclosure. Please refer to... Figure 2B , Figure 2B The aforementioned correspondence is shown. Figure 2A In the embodiment, the details of the data migration direction determination in step S290 are as follows: the processor 211 determines whether to perform data migration and the direction of data migration based on the heat status of the target area and the storage area where the target data of the target area is located.

[0064] In step S291, the processor 211 determines whether the heat state of the target area is the first heat state. If the determination result of step S291 is yes, the process proceeds to step S292; if the determination result of step S291 is no, that is, the heat state of the target area is the second heat state, the process proceeds to step S294.

[0065] In step S292, the processor 211 determines whether the target data is stored in the regular storage area 222. If the determination result of step S292 is yes, the process proceeds to step S293; if the determination result of step S292 is no, that is, the target data is already stored in the high-speed storage area 221, then there is no need to perform data migration, and the process ends.

[0066] In step S293, the processor 211 migrates the target data from the regular storage area 222 to the high-speed storage area 221, so that the target data that is frequently accessed can be accessed by the host system 10 with higher read performance.

[0067] In step S294, the processor 211 determines whether the target data is stored in the high-speed storage area 221. If the determination result of step S294 is yes, the process proceeds to step S295; if the determination result of step S294 is no, that is, the target data is already stored in the regular storage area 222, then no data migration is required, and the process ends.

[0068] In step S295, the processor 211 migrates the target data from the high-speed storage area 221 to the regular storage area 222, freeing up space in the high-speed storage area 221 for use by data in other frequently accessed areas.

[0069] In one embodiment, Figure 2B The direction of data migration shown is determined by the aforementioned corresponding... Figure 1B In this embodiment, the migration execution module 360 ​​performs the migration; furthermore, before the data migration in steps S293 and S295 is executed, the current temperature, erase / write cycle count, and idle state of the storage device 20 can be detected, and the relevant detection conditions will be determined later. Figure 5 The specific implementation process of data migration and the update of the L2P mapping table will be discussed in subsequent embodiments. Figure 6 The embodiments are described below.

[0070] Based on the above Figure 2B The flowchart of data migration judgment shown shows that the processor judges the heat status of the target area in step S291, judges the storage area where the target data of the target area is located in steps S292 and S294, and performs forward migration from the regular storage area to the high-speed storage area and reverse migration from the high-speed storage area to the regular storage area in steps S293 and S295. This makes the target area with inconsistent heat status and data storage location adjusted in both directions, and does not perform unnecessary migration for the target area where the data is already located in the appropriate storage area.

[0071] Figure 3 This is a data structure diagram illustrating the reading of a heat table according to an embodiment of this disclosure. Please refer to... Figure 3 In one embodiment, the processor 211 updates the record corresponding to the target region in the read popularity table T31 based on the read statistics of the target region, as described above. Figure 1B In the embodiment, the heat table management module 340 performs heat table maintenance, and the heat table T31 is maintained in the buffer memory 214 by firmware executed by the processor 211.

[0072] In one embodiment, the read popularity table T31 records the region identifier, cumulative read count, most recent read time, read popularity, and popularity status for each of the multiple regions. For example... Figure 3 As shown on the left, the heat table T31 includes records ET1, ET2 to ETN, where record ET1 corresponds to region 1 in the multiple regions, record ET2 corresponds to region 2, and so on, with record ETN corresponding to region N. That is, each record in the heat table T31 corresponds to one of the multiple regions.

[0073] Figure 3 The right side shows a magnified view of record ET1, framed with a dashed line. (See attached image.) Figure 3 As shown on the right, record ET1 includes five fields: region identifier FD1, cumulative number of reads FD2, most recent read time FD3, read popularity FD4, and popularity status FD5. Records ET2 to ETN have the same field structure as record ET1.

[0074] In one embodiment, the region identifier FD1 is used to record the region identifier of the region corresponding to the record, i.e., the aforementioned corresponding region identifier. Figure 1B In this embodiment, the LBA region management module 310 assigns a unique identifier to each region when dividing it into multiple regions. The region identifier FD1 is, for example, 2 bytes long. The cumulative read count FD2 records the cumulative number of times the region corresponding to this record has been read, and its accumulation method is as described above. Figure 2AIn the embodiment shown in step S220, the length of the cumulative read count FD2 is, for example, 8 bytes.

[0075] The most recent read time (FD3) records the time when the area corresponding to this record was last read. The length of FD3 is, for example, 8 bytes. The read popularity (FD4) records the read popularity of this area calculated based on the cumulative read count (FD2) and the most recent read time (FD3), and its calculation method is as described above. Figure 2A In the embodiment, step S230 shows that the length of the read heat FD4 is, for example, 4 bytes.

[0076] The heat status FD5 is used to record the current heat status of the area corresponding to the record. The length of the heat status FD5 is, for example, 1 byte. For example, a value of 1 represents the first heat status and a value of 0 represents the second heat status. The determination method is as described above. Figure 2A In the embodiment, steps S240 to S280 are shown.

[0077] In one embodiment, the processor 211 updates and ages the read heat table T31 at the end of each statistical period through the heat table management module 340. Specifically, the heat table management module 340 recalculates the read heat of each region based on the cumulative read count FD2 of each region and the time difference between the current time and the most recent read time FD3, and updates the read heat FD4 accordingly. It also updates the heat status FD5 based on the updated read heat, so that the read heat and heat status recorded in the read heat table T31 can reflect the latest read access situation of each region.

[0078] Furthermore, in one embodiment, the heat table T31 can be supplemented with fields for predicting heat trends for each region. The added fields and the prediction method based on these fields will be discussed later. Figure 4 The embodiments are described below.

[0079] Based on the above Figure 3 The data structure diagram of the read heat table shown shows that the processor maintains five fields in the read heat table in a centralized manner, with one record for each region: region identifier, cumulative number of reads, most recent read time, read heat, and heat status. This allows the region-level information required for heat calculation, status determination, and data migration to be queried and updated in a unified data structure, providing a data foundation for the execution of the hierarchical data storage method.

[0080] Figure 4 This is a flowchart illustrating heat trend prediction and bidirectional data migration according to embodiments of this disclosure. Please refer to... Figure 4In one embodiment, the processor 211 predicts the predicted popularity of the target area in the next statistical period based on the changing trend of the target area's read popularity, and determines the predicted popularity status based on a preset popularity threshold and a low popularity determination threshold. When both the current popularity status and the predicted popularity status of the target area are in the first popularity status and the target data is stored in the regular storage area 222, the processor 211 performs forward data migration; when both the current popularity status and the predicted popularity status of the target area are in the second popularity status and the target data is stored in the high-speed storage area 221, the processor 211 performs reverse data migration; if the above conditions are not met, the processor 211 does not perform data migration. The following is combined with... Figure 4 This section explains the steps involved in predicting popularity trends and two-way data migration.

[0081] In step S410, the processor 211 maintains a horizontal component and a trend component for the target area. Specifically, the horizontal component represents the current base heat level of the target area, and the trend component represents the direction and magnitude of change in the reading heat of the target area. In one embodiment, the processor 211 adds a field to the reading heat table T31 for each area to record the horizontal component, the trend component, and the reading heat value of the previous period, i.e., the aforementioned corresponding... Figure 3 The field for predicting popularity trends as indicated in the embodiments includes, for example, a horizontal component with a length of 2 bytes, a trend component with a length of 2 bytes, and a previous period's reading popularity value with a length of 4 bytes. The initial value of the horizontal component is, for example, equal to the previous period's reading popularity value, and the initial value of the trend component is, for example, equal to 0.

[0082] In step S420, processor 211 updates the horizontal component based on the read heat and the horizontal and trend components before the update. The update formula for the horizontal component is as follows:

[0083]

[0084] in The read frequency of the target region in the current period, i.e., the aforementioned corresponding Figure 2A In the embodiment, the read heat calculated in step S230, and These are the horizontal and trend components before the update (i.e., the previous period), respectively. For the updated (i.e., current period) horizontal component, α is the horizontal smoothing coefficient, used to control the response speed of the horizontal component to the current read heat. For example, α is set to 0.0625.

[0085] In step S430, processor 211 updates the trend component based on the difference between the updated and unupdated horizontal components. The update formula for the trend component is as follows:

[0086]

[0087] in The updated trend component is represented by β, which is the trend smoothing coefficient used to control the response speed of the trend component to trend changes. For example, β is set to 0.03125.

[0088] In step S440, the processor 211 determines the predicted heat as the sum of the updated horizontal component and the updated trend component. The formula for calculating the predicted heat is as follows:

[0089]

[0090] in This represents the predicted popularity of the target area in the next statistical period. Since the trend component records the direction and magnitude of changes in reading popularity, the predicted popularity is higher than the current level component when reading popularity is continuously rising, and lower than the current level component when reading popularity is continuously falling, allowing the predicted popularity to reflect the reading and access trends of the target area in the next statistical period.

[0091] In one embodiment, the processor 211 may also use the sum of twice the updated horizontal component and the updated trend component as the predicted heat of the target area in the next statistical period, so as to predict the change in reading heat more statistical periods in advance.

[0092] In step S450, the processor 211 determines the predicted heat status of the target area in the next statistical period based on a preset heat threshold and a low heat determination threshold. In step S460, the processor 211 determines whether the current heat status and the predicted heat status of the target area are both in the first heat status, and whether the target data is stored in the regular storage area 222. If the determination result of step S460 is yes, the process proceeds to step S470, and the processor 211 migrates the target data from the regular storage area 222 to the high-speed storage area 221; if the determination result of step S460 is no, the process proceeds to step S480. In step S480, the processor 211 determines whether the current heat status and the predicted heat status of the target area are both in the second heat status, and whether the target data is stored in the high-speed storage area 221. If the judgment result of step S480 is yes, the process proceeds to step S491, and the processor 211 migrates the target data from the high-speed storage area 221 to the regular storage area 222; if the judgment result of step S480 is no, the process proceeds to step S492, and the processor 211 does not perform data migration.

[0093] Assume the horizontal smoothing coefficient α is 0.0625 (i.e., 1 ÷ 16), the trend smoothing coefficient β is 0.03125 (i.e., 1 ÷ 32), the preset heat threshold is 600, and the low-heat judgment threshold is 480. Assume the horizontal components of a target area before the update. For 640, the trend component before the update The value is 0, and the read activity of the target area in the current period is... The value is 1664. In step S420, the updated horizontal component... In step S430, the updated trend components In step S440, the heat level is predicted. In step S450, since 706 is not less than the preset heat threshold 600, the predicted heat state is determined to be the first heat state; and since the current period's read heat 1664 is not less than the preset heat threshold 600, the current heat state is also the first heat state. If the target data is stored in the regular storage area 222 at this time, the processor 211 determines yes in step S460 and migrates the target data from the regular storage area 222 to the high-speed storage area 221 in step S470; if the target data is already stored in the high-speed storage area 221, the processor 211 determines no in both steps S460 and S480, and does not perform data migration in step S492. Correspondingly, when the current heat state and the predicted heat state of the target area are both the second heat state and the target data is stored in the high-speed storage area 221, the processor 211 determines yes in step S480 and migrates the target data from the high-speed storage area 221 to the regular storage area 222 in step S491.

[0094] In one embodiment, before executing the forward data migration in step S470 or the reverse data migration in step S491, the processor 211 may first detect the temperature, erase / write cycle count, and idle state of the storage device 20, and execute the corresponding data migration when all detections pass. This ensures that the data migration determined based on the consistency judgment between the current and predicted thermal states is still limited by the storage medium protection conditions, and the relevant detection conditions will be addressed in subsequent steps. Figure 5 The embodiments are described below.

[0095] In another embodiment, the calculation of the predicted popularity may not be limited to double exponential smoothing. The processor 211 may use other time series smoothing methods to predict the predicted popularity of the target area in the next statistical period based on the historical value of the reading popularity. For example, the average value of the reading popularity of the most recent statistical periods may be taken as the predicted popularity by using the sliding window mean. Another example is to use a first-order low-pass filter to smooth the historical value of the reading popularity and then use the smoothing result as the predicted popularity. This disclosure does not limit the specific calculation method of the predicted popularity.

[0096] In another embodiment, the horizontal smoothing coefficient and the trend smoothing coefficient may not be limited to fixed values. The processor 211 may adaptively adjust the horizontal smoothing coefficient and the trend smoothing coefficient according to the read access mode of the storage device 20. For example, when the read access mode changes rapidly, the horizontal smoothing coefficient may be increased so that the predicted heat responds more quickly to the change of the current read heat. Or, when the read access mode is relatively stable, the trend smoothing coefficient may be decreased to suppress the over-response of the trend component to occasional read fluctuations.

[0097] Based on the above Figure 4 The flowchart shown illustrates the heat trend prediction and bidirectional data migration process. The processor, through steps S410 to S440, performs double exponential smoothing on the read heat using horizontal and trend components to predict the predicted heat of the target region in the next statistical period. Step S450 determines the predicted heat state, and steps S460 and S480 determine the current heat state, the predicted heat state, and the storage area where the target data is located. When both the current and predicted heat states are in the first heat state and the target data is stored in the regular storage area, the processor performs forward data migration in step S470. When both the current and predicted heat states are in the second heat state and the target data is stored in the high-speed storage area, the processor performs reverse data migration in step S491. In other cases, no data migration is performed in step S492. Thus, data migration in the corresponding direction is performed only when the current read access state matches the predicted state for the next statistical period, reducing unnecessary data migration caused by short-term heat fluctuations or inconsistent state predictions.

[0098] Figure 5 This is a flowchart illustrating a data migration protection mechanism according to embodiments of this disclosure. Please refer to... Figure 5 In one embodiment, before performing data migration, the processor 211 first checks the current temperature, erase / write cycle count, and idle state of the storage device 20. Data migration is only performed after all checks pass, as described above. Figure 1B In the embodiment, the pre-migration detection is performed by the state detection module 350. Figure 5 The protection mechanism shown applies to the aforementioned corresponding Figure 2A In the embodiment, step S290 involves data migration, i.e., the aforementioned corresponding Figure 2B The data migration in steps S293 and S295 of the embodiment also applies to the aforementioned corresponding steps. Figure 4 In the embodiment, the data migration in steps S470 and S491 is described below. Figure 5 Explain the steps involved in the data migration protection mechanism.

[0099] In step S510, the processor 211 obtains the current temperature of the storage device 20 and determines whether the current temperature is not lower than a preset temperature threshold. Specifically, the processor 211 reads... Figure 1A The temperature sensor 240 detects the current temperature of the storage device 20 and compares it with a preset temperature threshold, such as 70°C. If the determination result of step S510 is yes, the process proceeds to step S520, where the processor 211 suspends data migration and resumes data migration after the current temperature drops below the preset temperature threshold, and then the process ends. If the determination result of step S510 is no, the process proceeds to step S530. In one embodiment, the processor 211 sets a timer when suspending data migration and detects the current temperature according to the timer. Data migration is resumed after the current temperature drops below the preset temperature threshold. By using steps S510 and S520, data migration is suspended when the storage device 20 is in a high-temperature state, preventing the additional writes generated by data migration from further increasing the temperature of the storage device 20.

[0100] In step S530, the processor 211 obtains the erase / write cycle count of the high-speed storage area 221 and the erase / write cycle count of the regular storage area 222, respectively. In one embodiment, the erase / write cycle count of the high-speed storage area 221 is, for example, the average erase / write cycle count of each storage block in the high-speed storage area 221, and the erase / write cycle count of the regular storage area 222 is, for example, the average erase / write cycle count of each storage block in the regular storage area 222. The erase / write cycle count reflects the degree of wear of the storage area; the higher the erase / write cycle count, the more severe the wear of the storage area.

[0101] In step S540, the processor 211 determines the dynamic erase / write threshold corresponding to the high-speed storage area 221 and the dynamic erase / write threshold corresponding to the conventional storage area 222 based on the write amplification factor and temperature. The dynamic erase / write thresholds corresponding to the high-speed storage area 221 and the conventional storage area 222 decrease as the write amplification factor increases and as the temperature increases, respectively. The write amplification factor is the ratio of the actual amount of data written by the storage device 20 to the amount of data requested to be written by the host system 10. In one embodiment, the formula for calculating the dynamic erase / write threshold is as follows:

[0102]

[0103]

[0104] in For dynamic erase / write threshold, The preset initial threshold for the erase / write cycle corresponds to the high-speed storage area 221. For example, 100000 corresponds to a regular storage area of ​​222. For example, 3000, where k is a dynamic correction factor. This is a reference value for the magnification factor, for example, 1.2. The current write amplification factor for storage device 20. This is a reference value for the operating temperature, for example, 30°C. The current operating temperature of storage device 20 is used. A higher current write amplification factor or a higher current operating temperature results in a smaller dynamic correction factor, which in turn lowers the dynamic erase / write threshold. This allows storage device 20 to enter protection mode earlier, preventing further temperature increases and write amplification factor increases due to data migration. It should be noted that this disclosure is not limited to the specific calculation method of the dynamic correction factor.

[0105] In step S550, the processor 211 determines whether either the number of erase / write cycles in the high-speed storage area 221 or the number of erase / write cycles in the regular storage area 222 exceeds the corresponding dynamic erase / write threshold. If the determination result of step S550 is yes, that is, the number of erase / write cycles in the high-speed storage area 221 exceeds the corresponding dynamic erase / write threshold, or the number of erase / write cycles in the regular storage area 222 exceeds the corresponding dynamic erase / write threshold, then the process proceeds to step S560, the processor 211 suspends data migration, and then the process ends; if the determination result of step S550 is no, then the process proceeds to step S570.

[0106] In step S570, the processor 211 determines whether the storage device 20 is in an idle state. An idle state is defined as the state where the host system 10 has not sent any input / output commands to the storage device 20 within a preset time period. If the determination result of step S570 is yes, the process proceeds to step S580, where the processor 211 performs data migration when the storage device 20 is in an idle state. If the determination result of step S570 is no, the process ends. In one embodiment, when the storage device 20 is not in an idle state, the processor 211 waits for the next detection cycle to execute again. Figure 5 The detection process shown allows data migration to be performed at a time that does not interfere with the foreground read / write operations of the host system 10.

[0107] Assuming the preset temperature threshold is 70°C and the reference value for the amplification factor is written... The reference value for operating temperature is 1.2. The temperature is 30°C, which corresponds to the initial threshold of the erase / write cycle for the high-speed storage area 221 and the regular storage area 222. The values ​​are 100,000 and 3,000 respectively. Assuming the current operating temperature of storage device 20 is 30°C, which is lower than the preset temperature threshold of 70°C, processor 211 determines "no" in step S510, and the process proceeds to step S530. Assuming that the erase / write cycle count of high-speed storage area 221 obtained in step S530 is 75,000 and the erase / write cycle count of regular storage area 222 is 2,000, and the current write amplification factor... If the value is 1.2, then in step S540, the dynamic correction factor... The dynamic erase / write threshold corresponding to high-speed storage area 221 is The dynamic erase / write threshold corresponding to the regular storage area 222 is If 75000 does not exceed 80000 and 2000 does not exceed 2400, processor 211 determines "no" in step S550, and the process proceeds to step S570. If the host system 10 does not send an input / output command to the storage device 20 within a preset time period, processor 211 determines "yes" in step S570 and performs data migration in step S580. Conversely, if the current write amplification factor increases to 2.4 and the current operating temperature increases to 60°C, the dynamic correction factor... The dynamic erase / write threshold corresponding to high-speed storage area 221 is reduced to If the erase / write cycle count of the high-speed storage area 221 exceeds 25,000 (75,000), the processor 211 determines this in step S550 and suspends data migration in step S560.

[0108] In another embodiment, Figure 5 The detection cycle and the heat reading statistics cycle of the detection process shown are not limited to a fixed duration. The processor 211 can adaptively adjust the detection cycle and statistics cycle according to the state of the storage device 20. For example, when the current temperature is high, the detection cycle can be shortened so that the storage device 20 can respond to temperature changes more quickly to perform protection. Or, when the storage device 20 is idle for a long time, the statistics cycle can be extended to reduce the processing resources occupied by heat statistics.

[0109] Based on the above Figure 5 The flowchart of the data migration protection mechanism shown illustrates that the processor performs gating on the current temperature of the storage device through steps S510 and S520, and performs gating on the number of erase / write cycles for the high-speed storage area and the regular storage area based on the dynamic erase / write threshold linked to the write amplification factor and temperature through steps S530 to S560. Furthermore, through steps S570 and S580, the processor ensures that data migration is performed only when the storage device is idle. This automatically pauses or postpones data migration in situations of high temperature, high wear, or heavy host access, preventing data migration from accelerating wear and thermal failure of the storage medium and reducing interference with host input / output operations.

[0110] Figure 6 This is an interactive timing diagram illustrating the execution of data migration according to embodiments of this disclosure. Please refer to... Figure 6 , Figure 6 The interactive timing of the host system 10, processor 211, buffer memory 214 and memory module 220 when executing the data hierarchical storage method of this disclosure is shown, with a forward data migration example of target data being migrated from the conventional storage area 222 to the high-speed storage area 221. Figure 6 The interactive sequence shown is divided into two stages: stage S61 (statistics and judgment) and stage S62 (high-temperature positive migration).

[0111] In stage S61, processor 211 responds to the read command to complete read statistics, heat calculation, and heat status determination. Specifically, in step S611, host system 10 issues a read command to processor 211. The read command carries the address of the logical block to be accessed. The read command is transmitted to processor 211 via connection interface circuit 230 and host interface control circuit 215.

[0112] In step S612, processor 211 determines the target region to which the logical block address accessed by the read command belongs. In step S613, processor 211 accumulates the number of reads of the target region and records the most recent read time of the target region. The processing in steps S612 and S613 corresponds to the aforementioned corresponding steps. Figure 2A The processing of step S220 in the embodiment.

[0113] In step S614, the processor 211 calculates the read heat that decreases over time based on the read statistics of the target region (including the cumulative number of reads and the most recent read time of the target region), and the calculation method corresponds to the aforementioned corresponding Figure 2A The processing of step S230 in the embodiment.

[0114] In step S615, the processor 211 determines the heat status of the target area based on the read heat. Figure 6 In the example shown, if the read popularity of the target area is not less than a preset popularity threshold, the popularity status of the target area is determined to be the first popularity status, and the determination method corresponds to the aforementioned corresponding... Figure 2A In the embodiment, the determination of the thermal state in steps S240 and S260.

[0115] In stage S62, when the target region's heat state is the first heat state and the target data is stored in the regular storage area 222, the processor 211 performs forward data migration. In one embodiment, before performing forward data migration, the processor 211 may first perform the aforementioned corresponding... Figure 5 The embodiments show the detection of current temperature, erase / write cycle count, and idle state.

[0116] In step S621, the processor 211 issues a read instruction to the memory module 220 to read the target data from the conventional storage area 222. Specifically, the processor 211 first, according to the aforementioned corresponding... Figure 1AIn the embodiment, the L2P mapping table established obtains the physical storage location of the target data in the regular storage area 222, allocates one or more free storage blocks in the high-speed storage area 221 as the destination for migration, and then issues the read instruction based on the physical storage location.

[0117] In step S622, the memory module 220 temporarily stores the read target data in the buffer memory 214, as described above. Figure 1A The buffer memory 214 shown in the embodiment temporarily stores data to be migrated during data migration.

[0118] In step S623, the processor 211 issues a write instruction based on the temporary data to the memory module 220; and in step S624, the target data temporarily stored in the buffer memory 214 is written to the free storage block allocated in the high-speed storage area 221.

[0119] In step S625, processor 211 updates the mapping from logical block address to physical address (i.e., updates the L2P mapping table), so that the logical block address of the target region points to the new physical address in high-speed storage area 221, enabling subsequent read accesses of the target region by host system 10 to be served by high-speed storage area 221. In one embodiment, processor 211 also marks the original data pages of the target region in regular storage area 222 as invalid for subsequent garbage collection.

[0120] It should be noted that, Figure 6 The instruction and data transfer between the processor 211 and the memory module 220, and between the memory module 220 and the buffer memory 214, is executed via the memory interface control circuit 213. Specifically, the read instruction in step S621 and the write instruction in step S623 are transmitted by the processor 211 to the memory interface control circuit 213 in the corresponding instruction sequence, and the memory interface control circuit 213 converts them into a format acceptable to the memory module 220; the data transfer between the memory module 220 and the buffer memory 214 in steps S622 and S624 is executed, for example, by the data management circuit 212 in conjunction with the memory interface control circuit 213. Thus, when executing the hierarchical data storage method of this disclosure, the host interface control circuit 215 is responsible for the command and data transfer with the host system 10, the memory interface control circuit 213 is responsible for the instruction and data transfer with the memory module 220, and the processor 211 performs read statistics, heat determination, and data migration scheduling.

[0121] In one embodiment, when the target region's heat state is the second heat state and the target data is stored in the high-speed storage area 221, the processor 211 performs reverse data migration. The interaction timing of the reverse data migration is a mirror image of the forward data migration shown in stage S62: the processor 211 reads the target data from the high-speed storage area 221 and temporarily stores it in the buffer memory 214, then writes the temporarily stored data to the regular storage area 222, then updates the mapping from logical block address to physical address, and marks the original data page of the target region in the high-speed storage area 221 as invalid, thereby releasing the space of the high-speed storage area 221.

[0122] In another embodiment, when the amount of target data is large, the processor 211 can also divide the target data into multiple batches and perform data migration in batches during multiple idle periods of the storage device 20. For example, when the host system 10 issues an input / output command during the execution of a certain batch of data migration, the processor 211 pauses the data migration of subsequent batches and prioritizes processing the input / output command. After the storage device 20 is idle again, the remaining batches of data migration will continue to be executed. The processor 211 updates the mapping from logical block address to physical address after all batches of data migration are completed, so as to reduce the interference of data migration on the input / output operations of the host system 10.

[0123] Based on the above Figure 6 The interactive timing diagram shown illustrates the execution of data migration. In stage S61, the processor completes the target region determination, read statistics, heat calculation, and status determination through steps S611 to S615 of the read command issued by the host system. In stage S62, the processor schedules the memory module and buffer memory through steps S621 to S625 to complete the reading, temporary storage, writing, and mapping update of data. This allows the steps of the hierarchical data storage method to be executed collaboratively among the components of the memory controller in a clear sequence, fully presenting the working process of the memory controller as the main body of hierarchical data storage execution.

[0124] It should be noted that in the above embodiments, the various values, thresholds, parameter ranges, and condition settings mentioned are all exemplary and do not constitute a limitation on the scope of protection of the claims of this disclosure. Specifically, the preset granularity used to divide multiple regions, the preset heat threshold and preset hysteresis coefficient, the preset time constant used for the attenuation constant, the preset saturation value of the cumulative number of reads, the horizontal smoothing coefficient and the trend smoothing coefficient, the length of each field in the read heat table, the preset temperature threshold, the initial threshold of the erase / write cycle corresponding to the high-speed storage area and the conventional storage area, the reference value of the write amplification factor and the reference value of the operating temperature, the upper limit of the dynamic correction factor, the initial value of the trend component, the preset duration for determining the idle state, the duration of the statistical period and the detection period, and the various values ​​assumed in the calculation examples of each embodiment, etc., can all be adjusted according to the capacity of the storage device and the size of the logical block address space, the storage unit mode and particle size used by the memory module, the read access characteristics of the host system, the application scenario requirements of the storage device, and environmental conditions such as heat dissipation conditions.

[0125] In another embodiment, this disclosure also provides a computer program product, including a computer program. When the computer program is loaded and executed by the memory controller of a storage device, it causes the memory controller to execute the data hierarchical storage method provided in this disclosure. The computer program can be carried on a non-transitory computer-readable storage medium, such as read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk. Therefore, the technical solution of this disclosure can be implemented in the form of a computer program product.

[0126] Based on the above, the data hierarchical storage method, memory controller, and computer program product provided in this disclosure divide the logical block address space of the storage device into multiple regions. The read access frequency of each region is characterized by the read frequency that decreases over time. Based on the frequency state defined by a preset frequency threshold and a low-frequency determination threshold, bidirectional data migration is performed between the high-speed storage region with high read performance and the regular storage region: data in the region with frequent read access is migrated to the high-speed storage region for the host to access with higher read performance, and data in the region that changes from hot to cold is migrated out of the high-speed storage region to free up space for data in other regions with frequent read access. Regions with read frequency in the hysteresis interval maintain their current frequency state, avoiding data with frequency at the threshold edge from migrating back and forth between the two storage regions and consuming too many erase and write cycles.

[0127] Furthermore, by performing double exponential smoothing on the read activity using horizontal and trend components, the predicted activity for the next statistical period is predicted. Based on preset activity thresholds and low-activity thresholds, the predicted activity state is determined. Forward data migration is performed when both the current and predicted activity states are in the first activity state and the target data is stored in a regular storage area. Reverse data migration is performed when both are in the second activity state and the target data is stored in a high-speed storage area. This ensures that data migration only occurs when the current read access state matches the predicted state for the next statistical period and the storage area containing the target data needs adjustment, reducing unnecessary data migration caused by short-term activity fluctuations, inconsistent state predictions, or data already being in an appropriate storage area. Furthermore, by using current temperature, write amplification factor, and temperature-linked dynamic erase / write thresholds, as well as pre-migration detection of idle states, data migration is paused or delayed under conditions of high temperature, high wear, or heavy host access. This prevents data migration from accelerating storage media wear and thermal failure and reduces interference with host input / output operations. Thus, this disclosure achieves a relative balance between read performance, storage media lifespan, and impact on host access.

[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A hierarchical data storage method, applicable to a storage device configured with a memory controller and a memory module, wherein the memory module includes a conventional storage area and a high-speed storage area with read performance higher than the conventional storage area, characterized in that, The method includes: The logical block address space of the storage device is divided into multiple regions; In response to a read command from the host, determine the target region to which the logical block address accessed by the read command belongs, and update the read statistics of the target region; Based on the reading statistics of the target area, the reading popularity of the target area is determined, wherein the reading popularity decreases over time if the target area is not read again; The heat status of the target area is determined based on the read heat; and Based on the heat status of the target area and the storage area where the target data is located, perform data migration of the target data between the high-speed storage area and the regular storage area.

2. The data hierarchical storage method according to claim 1, characterized in that, The step of determining the heat state of the target area based on the read heat includes: When the read heat value is not less than a preset heat value threshold, the heat value state of the target area is determined as a first heat value state; and When the read heat value is less than the low heat determination threshold, the heat state of the target area is determined as the second heat state, wherein the low heat determination threshold is not greater than the preset heat threshold.

3. The data hierarchical storage method according to claim 2, characterized in that, The step of migrating the target data between the high-speed storage area and the regular storage area based on the heat status of the target area and the storage area where the target data is located includes: When the heat status of the target area is the first heat status and the target data is stored in the regular storage area, the target data is migrated from the regular storage area to the high-speed storage area; and When the heat status of the target area is the second heat status and the target data is stored in the high-speed storage area, the target data is migrated from the high-speed storage area to the regular storage area.

4. The data hierarchical storage method according to claim 2, characterized in that, The low-heat determination threshold is the product of the preset heat threshold and the preset hysteresis coefficient, and the preset hysteresis coefficient is greater than 0 and less than 1.

5. The data hierarchical storage method according to claim 4, characterized in that, When the read heat is less than the preset heat threshold and not less than the low heat determination threshold, the current heat state of the target area is maintained.

6. The data hierarchical storage method according to claim 1, characterized in that, The read statistics include the cumulative number of reads and the most recent read time for the target area, and the step of determining the read popularity of the target area based on the read statistics includes: The product of the cumulative number of reads and the attenuation factor is determined as the read popularity, wherein the time difference is the time difference between the current time and the most recent read time, and the attenuation factor is a power of the product of the attenuation constant and the time difference, with the natural constant as the base and the opposite of the product of the attenuation constant and the time difference as the exponent.

7. The data hierarchical storage method according to claim 1, characterized in that, The method further includes: Based on the read statistics of the target region, the record corresponding to the target region in the read popularity table is updated. The read popularity table records the region identifier, cumulative read count, most recent read time, read popularity and popularity status for each of the multiple regions.

8. The data hierarchical storage method according to claim 3, characterized in that, The method further includes: Based on the changing trend of the reading popularity of the target area, predict the predicted popularity of the target area in the next statistical period; Based on the preset heat threshold and the low heat determination threshold, the predicted heat status of the target area in the next statistical period is determined according to the predicted heat. The step of migrating the target data from the conventional storage area to the high-speed storage area is performed when both the heat status of the target area and the predicted heat status are the first heat status; and The step of migrating the target data from the high-speed storage area to the regular storage area is performed when both the heat status of the target area and the predicted heat status are the second heat status.

9. The data hierarchical storage method according to claim 8, characterized in that, The step of predicting the predicted popularity of the target area in the next statistical period based on the changing trend of the target area's reading popularity includes: Maintain horizontal and trend components for the target region; The horizontal component is updated based on the read popularity and the horizontal component and trend component before the update; The trend component is updated based on the difference between the updated horizontal component and the unupdated horizontal component; and The sum of the updated horizontal component and the updated trend component is determined as the predicted heat.

10. The data hierarchical storage method according to claim 1, characterized in that, The method further includes: Before performing the data migration, obtain the current temperature of the storage device; and When the current temperature is not lower than a preset temperature threshold, the data migration is paused, and the data migration is resumed after the current temperature drops below the preset temperature threshold.

11. The data hierarchical storage method according to claim 1, characterized in that, The method further includes: Before performing the data migration, the erase / write cycle count of the high-speed storage area and the erase / write cycle count of the regular storage area are obtained respectively; and The data migration is paused when the number of erase / write cycles in the high-speed storage area exceeds the dynamic erase / write threshold corresponding to the high-speed storage area, or when the number of erase / write cycles in the regular storage area exceeds the dynamic erase / write threshold corresponding to the regular storage area.

12. The data hierarchical storage method according to claim 11, characterized in that, The dynamic erase / write thresholds corresponding to the high-speed storage area and the dynamic erase / write thresholds corresponding to the conventional storage area are determined based on the write amplification factor and temperature, respectively, and decrease as the write amplification factor increases and as the temperature increases, respectively.

13. The data hierarchical storage method according to claim 1, characterized in that, The method further includes: Before performing the data migration, it is determined whether the storage device is in an idle state, wherein the idle state is defined as the state in which the host has not issued input / output commands to the storage device within a preset time period; and The data migration is performed when the storage device is in the idle state.

14. A memory controller suitable for a storage device configured with a memory module, the memory module comprising a conventional storage area and a high-speed storage area with read performance higher than the conventional storage area, characterized in that, The memory controller includes: Host interface control circuit, used for electrical connection to the host; A memory interface control circuit, for electrically connecting to the memory module; and A processor, electrically connected to the host interface control circuit and the memory interface control circuit, wherein the processor is configured to: The logical block address space of the storage device is divided into multiple regions; In response to a read command from the host, determine the target region to which the logical block address accessed by the read command belongs, and update the read statistics of the target region; Based on the reading statistics of the target area, the reading popularity of the target area is determined, wherein the reading popularity decreases over time if the target area is not read again; The heat status of the target area is determined based on the read heat; and Based on the heat status of the target area and the storage area where the target data is located, perform data migration of the target data between the high-speed storage area and the regular storage area.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is loaded and executed by the memory controller of the storage device, the memory controller performs the following steps, wherein the storage device is configured with a memory module, the memory module including a conventional storage area and a high-speed storage area with higher read performance than the conventional storage area: The logical block address space of the storage device is divided into multiple regions; In response to a read command from the host, determine the target region to which the logical block address accessed by the read command belongs, and update the read statistics of the target region; Based on the reading statistics of the target area, the reading popularity of the target area is determined, wherein the reading popularity decreases over time if the target area is not read again; The heat status of the target area is determined based on the read heat; and Based on the heat status of the target area and the storage area where the target data is located, perform data migration of the target data between the high-speed storage area and the regular storage area.

Images