SLC flash memory data equalization management method and system based on array topology perception

Abstract

The application relates to the technical field of data balancing management, and discloses an SLC flash memory data balancing management method based on array topology perception, which comprises the following steps: acquiring an array physical topology, establishing a three-dimensional space mapping matrix; reading the erasing and writing times of each node, clustering to obtain a first wear state set; calculating the difference value of the erasing and writing times of adjacent nodes, and if the difference value exceeds a threshold value, it is determined that there is a channel wear difference, and a target wear node list is generated. Then, the historical access frequency of the nodes in the list is acquired, cold and hot data are distinguished, a cold and hot distribution map is obtained, and the cold and hot distribution map is matched with the three-dimensional matrix to select a cold data residence candidate set. If the target wear node contains cold data, the cold data is written into a new physical position allocated by the candidate set, the distribution topology map is updated, the writing pointer is reset, subsequent hot data is guided to be written into a position outside the list, and the balancing management is completed. The method can realize accurate isolation and load redistribution for channel wear difference.

Description

Technical Field

[0001] This invention relates to the field of data balance management technology, and in particular to a method and system for SLC flash memory data balance management based on array topology awareness. Background Technology

[0002] Currently, in storage systems composed of intelligent integrated circuits, single-layer flash memory is widely used in embedded storage devices such as industrial control, automotive electronics, and network communications due to its high-speed read / write speed and high reliability. Flash memory arrays exhibit a complex topology with multiple parallel channels and multiple die mounts. Due to the locality of data load in the logical address space and the uneven distribution of garbage collection pressure among channels, wear rates differ between channels. Furthermore, storage nodes with similar wear levels exhibit spatial clustering related to their channel mount relationships, thus forming localized wear hotspots in the array's topology. Against this backdrop, the flash memory controller, as a core component of intelligent integrated circuits, needs to sense this spatial clustering pattern of wear differences to achieve balanced utilization of storage resources.

[0003] In existing technologies, data leveling management of single-cell flash memory often employs static wear leveling strategies based on global wear counts or dynamic data migration strategies based on access frequency. These strategies primarily focus on the overall erase / write count distribution of each storage block. A common practice is to move cold data out of younger blocks with low erase / write counts and relocate it to older blocks with high erase / write counts, thus reserving free capacity in younger blocks to handle hot data writes and balance the overall array wear. However, these methods only consider wear distribution at the logical address level, lacking awareness of the flash array topology and failing to utilize the spatial clustering of wear hotspots along the channel dimension. When a channel experiences significantly higher wear rates on its attached storage nodes due to localized data load concentration or concentrated garbage collection pressure compared to adjacent channels, traditional wear leveling strategies cannot identify this localized clustering of wear rate differences in the physical topology. They still schedule data writes according to global leveling logic, failing to prevent the continuous influx of hot data into localized wear hotspots at the physical topology level. This exacerbates wear differences between channels, limiting the overall array lifespan to the single channel with the fastest wear.

[0004] In summary, existing smart integrated circuits lack the ability to perceive the physical topology of the array and identify channel wear differences in flash memory data balancing management. They are unable to achieve precise isolation and load redistribution for channel wear differences in the three-dimensional topological space of the array, resulting in the problem that the overall lifespan of the flash memory array is limited by locally worn channels. Summary of the Invention

[0005] This invention provides a method and system for SLC flash memory data balancing management based on array topology awareness, so as to achieve accurate isolation and load redistribution for channel wear differences.

[0006] Firstly, to address the aforementioned technical problems, this invention provides a method for SLC flash memory data balancing management based on array topology awareness, comprising: Obtain the physical topology information of a single-layer cell flash array, extract the physical location coordinates of each storage node, and establish a three-dimensional spatial mapping matrix; The current erase / write count of each storage node is read using the three-dimensional spatial mapping matrix, and the first wear state set is obtained by clustering. For each storage node in the first wear state set, the current erase / write count is subtracted from the current erase / write count of the adjacent storage node to obtain a positive difference value. The maximum value of the positive difference value is taken as the erase / write count difference value. If the erase / write count difference value is greater than a preset difference value threshold, it is determined that the corresponding storage node has channel wear differences, and a target wear node list is obtained. The historical access frequency of each storage node in the target wear node list is obtained. Cold data and hot data are distinguished according to the historical access frequency to obtain a cold and hot data distribution map. The cold and hot data distribution map is matched with the three-dimensional spatial mapping matrix to obtain a cold data resident candidate set. If cold data exists in the target wear node list, the cold data is written to the target physical location allocated from the cold data residence candidate set to obtain an updated distribution topology map. The write pointer is then reset according to the updated distribution topology map to guide subsequent hot data to be written to physical locations outside the target wear node list, thus completing data balance management.

[0007] Secondly, the present invention provides an array topology-aware SLC flash memory data balancing management system, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the array topology-aware SLC flash memory data balancing management method as described above.

[0008] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the array topology-aware SLC flash memory data balancing management method as described above.

[0009] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention obtains the physical topology information of a single-layer cell flash memory array, extracts the physical location coordinates of each storage node, and establishes a three-dimensional spatial mapping matrix. This matrix extracts the horizontal and vertical physical coordinates of the die on the module substrate and the vertical axis coordinates of the block group within the die from the array hardware configuration data, accurately associating the logical address with the physical location. This allows all subsequent readings and determinations of wear states to be performed in the real physical space, solving the problem of blind spots caused by channel wear differences due to the traditional method's inability to perceive the wear distribution from the perspective of the logical address alone.

[0010] (2) This invention reads the current erase / write count of each storage node through a three-dimensional spatial mapping matrix and clusters it to obtain a first wear state set. For each storage node in this set, the difference between the erase / write count and that of adjacent storage nodes is calculated. If the difference is greater than a preset difference threshold, it is determined that the corresponding storage node has channel wear differences, and a list of target wear nodes is obtained. Cluster analysis groups all array storage nodes according to aging stages, making the statistics of wear states more stable and reliable. The calculation of the positive difference between adjacent nodes concretizes the channel wear difference from the abstract global distribution into a quantifiable local physical index. The most severe adjacent positive drop characterizes the degree of channel wear difference of the node, and only nodes on the high side of the wear gradient are included in the management, avoiding healthy neighboring nodes on the low side of the wear gradient being mistakenly included in the isolation range. This solves the problem that intelligent integrated circuits cannot identify local wear hotspots from the physical level due to the lack of a quantitative method for the wear drop between channels.

[0011] (3) This invention obtains the historical access frequency of each storage node in the target wear node list, distinguishes cold data from hot data based on the historical access frequency, obtains a cold and hot data distribution map, and matches the cold and hot data distribution map with a three-dimensional spatial mapping matrix to obtain a cold data residency candidate set. By quantifying the data activity and cold / hot attributes of each storage node in the target wear node list, it makes clear the criteria for which data in severely worn areas is suitable for migration. The generation of the cold data residency candidate set is to select physically adjacent and spatially sufficient areas from storage nodes with current write counts higher than the average level. The remaining write life of older nodes is no longer suitable for high-frequency hot writes, while cold data residency does not generate additional writes. Migrating cold data to older nodes utilizes their remaining static storage capacity and allows younger nodes with low write counts to retain free capacity to accept hot data writes. This provides a target address pool that conforms to the wear leveling direction for cold data migration, solves the problem of lack of physical topology constraints in cold and hot data identification and migration target selection, and ensures that the data distribution after migration meets the wear leveling requirements without destroying the physical continuity of the array.

[0012] (4) When cold data exists in the target wear node list, the present invention writes the cold data to the target physical location allocated from the cold data residence candidate set to obtain an updated distribution topology map. The write pointer is reset according to the updated distribution topology map to guide subsequent hot data to be written to a physical location outside the target wear node list, thus completing data balance management. The delineation of the isolation area boundary corresponding to the target wear node list physically separates the severely worn node group from the hot data writing path. The reset of the write pointer and the re-establishment of the addressing mapping relationship of the hot data ensure that all subsequent hot data are forcibly guided to a healthy physical location, so that the exhausted high wear node group no longer receives new hot data writing. This solves the problem that the lack of physical topology awareness of intelligent integrated circuits makes it impossible to block the continuous influx of hot data into local wear hot spots at the topology level, thus avoiding the failure mode of the overall array lifespan being limited by the fastest wear channel. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the SLC flash memory data balancing management method based on array topology awareness provided in the first embodiment of the present invention; Figure 2 This is a schematic diagram of the first wear state set provided in the first embodiment of the present invention; Figure 3 This is a schematic diagram of channel wear difference determination provided in the first embodiment of the present invention; Figure 4 This is a schematic diagram of hot data writing and allocation provided in the first embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Reference Figure 1 The first embodiment of the present invention provides a method for SLC flash memory data balancing management based on array topology awareness, including the following steps: Step S11: Obtain the physical topology information of the single-layer cell flash array, extract the physical location coordinates of each storage node, and establish a three-dimensional spatial mapping matrix; Step S12: Read the current erase / write count of each storage node through the three-dimensional spatial mapping matrix, and cluster to obtain the first wear state set; Step S13: For each storage node in the first wear state set, the current erase / write count is subtracted from the current erase / write count of the adjacent storage node to obtain a positive difference value. The maximum value of the positive difference value is taken as the erase / write count difference value. If the erase / write count difference value is greater than the preset difference value threshold, it is determined that the corresponding storage node has channel wear difference, and a target wear node list is obtained. Step S14: Obtain the historical access frequency of each storage node in the target wear node list, distinguish cold data from hot data according to the historical access frequency, obtain a cold and hot data distribution map, match the cold and hot data distribution map with the three-dimensional spatial mapping matrix, and obtain a cold data resident candidate set. Step S15: If cold data exists in the target wear node list, the cold data is written to the target physical location allocated from the cold data residence candidate set to obtain an updated distribution topology map. The write pointer is reset according to the updated distribution topology map to guide subsequent hot data to be written to a physical location outside the target wear node list, thus completing data balance management.

[0016] In step S11, the physical topology information of the single-layer cell flash memory array is obtained, the physical location coordinates of each storage node are extracted, and a three-dimensional spatial mapping matrix is ​​established. This includes: The physical topology information is analyzed to obtain channel mounting data and grain distribution data; Based on the channel mounting data, determine the channel identifier and chip select signal number mounted on each die, and summarize to obtain the channel identifier set and chip select signal set of each memory node; If the set of channel identifiers matches the set of chip select signals according to a preset addressing rule, the physical location coordinates of each storage node are extracted, and a three-dimensional spatial mapping matrix is ​​established.

[0017] Physical topology information refers to the array hardware configuration data built by the storage system manufacturer during the array module's production and commissioning phase. This data is permanently stored in the non-volatile memory of the flash memory controller and is in a structured text format. It contains two types of data tables: the first is a die distribution table, exported from the array module's substrate layout design file, which records the horizontal and vertical physical coordinates of each die on the module substrate, as well as the die's mounting relationship field. The second is a channel mounting table, which records the actual die identifier responded to by each combination of channel identifier and chip select signal number obtained from power-on enumeration scanning. The unit of physical coordinates in the tables is mm, and the layout coordinates are given by the array module's substrate layout design file, satisfying the requirements for distinguishing between channel and die positioning. The single-layer cell flash memory array in this embodiment consists of 8 channels, each channel carrying 8 dies, for a total of 64 dies. Each die contains 1024 physical blocks, which are divided into 4 block groups based on the physical block number modulo 4, resulting in a total of 256 storage nodes. In this embodiment, the storage nodes and block groups correspond one-to-one. Each physical block contains 64 physical pages, each page has a capacity of 16KB, the capacity of a single physical block is 1MB, the nominal storage capacity of a single storage node is 256MB, and the nominal storage capacity of the entire array is 64GB.

[0018] When parsing the physical topology information, the two types of data tables in the array hardware configuration data are read line by line according to the field name. The horizontal and vertical physical coordinate sequences of 64 chips are extracted from the chip distribution table to obtain the chip distribution data. The chip mounting records under the combination of each channel identifier and chip select signal number are extracted from the channel mounting table to obtain the channel mounting data.

[0019] The die distribution data shows that 64 dies are arranged in an 8x8 two-dimensional array with equal spacing on the substrate. With the lower left corner of the substrate as the origin, the horizontal and vertical physical coordinates are taken in increments of 0mm-14mm and 2mm respectively. That is, the horizontal axis number corresponds to the quotient of the horizontal axis physical coordinate divided by 2mm, and the vertical axis number corresponds to the quotient of the vertical axis physical coordinate divided by 2mm. In the channel mounting data, the 1024 physical blocks within each die are divided into 4 block groups based on their physical block numbers modulo 4. The vertical axis hierarchical numbers 0 to 3 correspond to block groups 0 to 3 respectively. Therefore, the physical location coordinates of each storage node can be described either by indexing by serial number or by physical coordinates with units, with a one-to-one correspondence between the two methods.

[0020] Subsequently, during the commissioning and debugging phase, a power-on enumeration scan was performed. For each of the 64 combinations consisting of 8 channel identifiers and 8 chip select signal numbers, a device identification command was issued through the flash memory controller's configuration interface. Based on the response of each combination, the actual die mounted under that combination was determined, thereby determining the channel identifier (value 0-7) and the chip select signal number (value 0-7) corresponding to that chip select pin for each die. The mounting relationships for each of the 64 dies were recorded, and the channel identifiers of all dies were summarized into a channel identifier set, and the chip select signal numbers were summarized into a chip select signal set. The enumeration results were then written into a channel mounting table for storage. In this embodiment, the die with substrate coordinates (12mm, 6mm) responded to the combination of channel 6 and chip select signal 3.

[0021] The preset addressing rules limit the range of legal channel and chip select combinations. Specifically, the channel identifier takes values ​​from 0 to 7, the chip select signal number takes values ​​from 0 to 7, and each combination of channel identifier and chip select signal number corresponds to at most one die in the entire array. The preset addressing rules are determined by the number of channels and the maximum number of devices per channel, as given in the product manual of the single-layer cell flash array. These rules are entered into the flash controller and stored during the production commissioning phase. During the validity verification, each element in the channel identifier set and the chip select signal set is compared with the preset addressing rules. If a match is found, the corresponding device relationship is deemed valid, and coordinate extraction is triggered. The horizontal and vertical physical coordinates of the die are read from the die distribution data, and the sequence number of the block group where the storage node is located is used as the vertical axis level number. These three coordinates constitute the physical location coordinates of the storage node. In this embodiment, the physical location coordinates of the storage node in block group 2 within the die of channel 6 and chip select signal 3 are (12mm, 6mm, 2). Conversely, if a match fails, for example, if the channel identifier exceeds the value range of 0 to 7, or if the same combination corresponds to multiple crystals, the corresponding enumeration record is determined to be invalid and discarded, and will not participate in the establishment of the three-dimensional spatial mapping matrix, thereby ensuring that the extracted physical location is true and valid.

[0022] The three-dimensional spatial mapping matrix is ​​constructed once during the production commissioning phase and permanently stored in the non-volatile memory of the flash memory controller. When the array undergoes physical structure changes due to bad block management, maintenance personnel reconstruct the matrix and re-solidify it during downtime maintenance based on the changed chip state. During construction, the matrix is ​​generated based on the physical location coordinates of all valid storage nodes. The matrix has a dimension of 8×8×4. The indices of the three dimensions correspond to the horizontal axis index i (i.e., channel identifier, value 0-7), the vertical axis index j (i.e., chip select signal number, value 0-7), and the vertical axis hierarchical index k (i.e., intra-chip block group index, value 0 to 3) of the storage node, respectively. The matrix element value is the logical address of the corresponding storage node. The logical address is encoded according to the row-major expansion rule, i.e., L=32×i+4×j+k, with a value range of 0 to 255. The horizontal axis index and vertical axis index correspond one-to-one with the horizontal axis physical coordinates and vertical axis physical coordinates of the chip in the chip distribution data, and the vertical axis hierarchical index corresponds one-to-one with the intra-chip block group division.

[0023] In step S12, the current erase / write count of each storage node is read using the three-dimensional spatial mapping matrix, and clustered to obtain a first wear state set. This includes: An addressing instruction is generated based on the logical address of each storage node in the three-dimensional spatial mapping matrix. The addressing instruction is sent to the metadata management unit of the flash conversion layer. The raw erase / write count value is received by the metadata management unit according to the physical block statistics. The original erase count values ​​are concatenated according to the coordinate order of the three-dimensional spatial mapping matrix to obtain a one-dimensional feature vector; Calculate the Euclidean distance between each element in the one-dimensional feature vector and the preset cluster center. If the Euclidean distance is less than the preset distance threshold, the corresponding element is assigned to the classification cluster where the preset cluster center is located. Extract the storage node in the classification cluster and the corresponding current erase / write count to obtain the first wear state set.

[0024] First, all 256 elements of the three-dimensional spatial mapping matrix are traversed. The element values, i.e., logical addresses, are decomposed into physical addressing triplets by inverse operation according to the encoding rules. The channel identifier is the integer part of the logical address divided by 32, the chip select signal number is the integer part of the quotient of the logical address divided by 32 and then divided by 4, and the vertical axis level number is the result of the logical address divided by 4. The physical addressing triplets are encapsulated into read commands that can be recognized by the flash memory controller, i.e., addressing instructions. These instructions are arranged in ascending order of logical address to form an addressing instruction sequence and sent to the metadata management unit of the flash memory translation layer. The flash memory conversion layer increments the cumulative erase count of the corresponding physical block by one each time an erase operation is completed, and maintains a block erase table with physical blocks as keys. The block erase table is queried according to the address instruction sequence. For each storage node, the arithmetic mean of the cumulative erase count of all physical blocks in its block group is taken as the original erase count of the storage node since initialization, i.e., the current erase count. This count reflects the overall aging degree of each storage node. In this embodiment, the original erase count returned by the storage node that reads logical address 209 (corresponding to the horizontal axis number 6, vertical axis number 4, and vertical axis level number 1 of the physical location coordinates) is 24800.

[0025] Subsequently, following the coordinate order of the three-dimensional spatial mapping matrix, i.e., row priority (horizontal axis number first, vertical axis number second, and vertical axis hierarchical number last), the 256 original erase and write count values ​​are sequentially concatenated into a continuous one-dimensional feature vector. The length of the vector is consistent with the total number of effective storage nodes. The nth element in the vector strictly corresponds to the current erase and write count of the storage node with logical address n-1, thereby structuring the discrete count values ​​for subsequent cluster analysis.

[0026] There are three preset cluster centers, representing the three aging stages of low wear, medium wear, and high wear, respectively. In this embodiment, 12,000, 20,000, and 28,000 cycles are respectively fixed. The rated programmable erase endurance of a single block of a single-layer cell flash memory is usually 30,000 to 100,000 cycles. The 28,000 cycles of the high-wear cluster center is about 90% of the lower limit of the rated endurance and is used to represent the aging stage nearing the end of its life. The acquisition process is as follows: before the initial deployment of the leveling management process, the original erase and write count values ​​of each storage node of three single-layer cell flash memory arrays of the same model are taken and run continuously for 720 days under the same business load. After merging, all count values ​​are sorted from smallest to largest and divided into three equal parts according to the number. The median of the low, medium, and high divisions are used as the initial values ​​of the three preset cluster centers and fixed and stored. Thereafter, the fixed values ​​are used in each leveling cycle, and the maintenance personnel recalibrate them every six months during the downtime maintenance period using the same statistical method.

[0027] During clustering, the Euclidean distance between each element in the one-dimensional feature vector and the preset cluster center is calculated. Since both the element and the cluster center are one-dimensional values, the Euclidean distance is the absolute value of the difference between the element value and the cluster center value. For each element, the distance to the three preset cluster centers is calculated, and the minimum distance is used for judgment. If the minimum distance is less than the preset distance threshold, the element is assigned to the cluster containing the cluster center with the minimum distance. If the minimum distance is tied among multiple preset cluster centers, the element is assigned to the cluster with the smallest cluster center value. If the distance between an element and all three preset cluster centers is greater than or equal to the preset distance threshold, the element is assigned to the cluster containing the nearest preset cluster center and marked as the boundary node of that cluster. The boundary node is also included in the first wear state set and participates in the difference calculation in subsequent steps to ensure that all storage nodes in the entire array are within the wear management range. The preset distance threshold is 2000 times. Trial clustering was performed on the three identical arrays using candidate thresholds of 1500, 2000, and 2500 times respectively. The selection criteria were: minimum standard deviation of the number of erase / write operations for storage nodes within a cluster, and the proportion of elements marked as boundary nodes not exceeding 5%. The final preset distance threshold was set at 2000 times. As the number of erase / write operations increases, storage nodes marked as boundary nodes will automatically become regular members of that cluster in subsequent equalization cycles when their distance to a preset cluster center falls within the preset distance threshold range.

[0028] After the first round of partitioning, the initial clusters are iteratively updated. The arithmetic mean of all elements in each cluster is used as the new cluster center. The distance calculation and element partitioning are then re-executed using the new cluster center, and this process is repeated iteratively. Iteration stops when the change in the value of each cluster center is less than a preset convergence threshold of 100 times in two consecutive iterations, or when the number of iterations reaches a preset maximum number of iterations of 20 times, whichever comes first. The preset convergence threshold of 100 times is determined by a clustering stability test, meaning that in the clustering results of the same type of array for 30 consecutive days, the daily fluctuation of the value of each cluster center does not exceed 100 times. After the iteration, the final clusters are extracted, and the cluster identifier, the physical location coordinates of each storage node in the cluster, and the corresponding current erase / write count are structured and encapsulated to obtain the first wear state set. This set records the physical node groups in the array that are at a specific wear level according to the aging stage. In this embodiment, the storage nodes with logical addresses 208 and 210 (current erase / write counts of 27600 and 28400 times, respectively) are both classified into the high wear cluster. Compared to the common practice of directly sorting and comparing the number of erase and write cycles, clustering uses a preset cluster center as a reference to group all array nodes according to aging stages. The first wear state set completely records the storage nodes of each wear level in the entire array according to the aging stage, and the cluster center is updated iteratively with the balancing cycle, which can track the overall evolution of the wear distribution of the entire array.

[0029] For example, Figure 2This is a schematic diagram of the first wear state set. The diagram shows the current erase / write counts of 256 memory nodes distributed by logical address, and clustered into low wear, medium wear, and high wear clusters. Some memory nodes in the logical address range of 192 to 211 are concentrated in the high wear cluster, reflecting the structured grouping results of the wear states.

[0030] In step S13, for each storage node in the first wear state set, the current erase / write count is subtracted from the current erase / write count of its adjacent storage nodes to obtain a positive difference value. The maximum value among these positive differences is taken as the erase / write count difference value. If the erase / write count difference value is greater than a preset difference threshold, it is determined that the corresponding storage node has channel wear differences, thus obtaining a target wear node list. This includes: Extract the physical location coordinates of each storage node from the first wear state set; Determine the coordinates of adjacent physical locations based on the physical location coordinates, and obtain the current erase / write count corresponding to the adjacent physical location coordinates; Subtract the current erase / write count corresponding to the adjacent physical location coordinates from the current erase / write count of the corresponding storage node to obtain the positive difference in each adjacent direction. Take the maximum value among the positive differences as the erase / write count difference. If the difference in the number of erase / write cycles is greater than a preset difference threshold, it is determined that the corresponding storage node has channel wear differences. The storage nodes with channel wear differences are then summarized to obtain a target wear node list.

[0031] First, the physical location coordinates (horizontal axis index i, vertical axis index j, vertical axis hierarchical index k) of each storage node are extracted one by one from the first wear state set. The adjacent physical location coordinates are determined using a six-neighborhood definition. For any physical location coordinate, it is offset by ±1 along each of the three matrix dimensions to obtain at most six adjacent coordinates: (i+1, j, k), (i-1, j, k), (i, j+1, k), (i, j-1, k), (i, j, k+1), and (i, j, k-1). When an offset direction exceeds the matrix boundary and no storage node exists, only the actually existing adjacent coordinates are taken. In this embodiment, the storage node with physical location coordinates (6, 4, 2) has six adjacent physical location coordinates: (5, 4, 2), (7, 4, 2), (6, 3, 2), (6, 5, 2), (6, 4, 1), and (6, 4, 3).

[0032] Subsequently, the current erase / write count corresponding to the coordinates of each adjacent physical location is read through the three-dimensional spatial mapping matrix. Here, the original erase / write count value read and stored in logical address in step S12 is directly reused, without needing to access the flash array again. The current erase / write count of the central storage node is subtracted from the current erase / write count of each adjacent storage node to obtain the positive difference in each adjacent direction. The maximum value among them is taken as the erase / write count difference of the central storage node. If all positive differences are negative, the erase / write count difference of the central storage node is 0. In this embodiment, the current erase / write count of storage node (6, 4, 2) is 28400 times, and the current erase / write count of its adjacent coordinate (6, 4, 1) is 24800 times. The positive difference in this direction is +3600 times, and this difference is the maximum value among the 6 adjacent directions. Therefore, the erase / write count difference of storage node (6, 4, 2) is 3600 times. The reason for using positive difference is that, for the same drop, only the central node on the side with high wear meets the judgment condition. As long as the central node is significantly higher than its adjacent nodes, it means that the local erasing environment of the node has been unbalanced. The most severe adjacent positive drop represents the degree of channel wear difference of the node, which can avoid the problem of averaging the sharp local imbalance when averaging the differences in multiple directions. On the contrary, the positive difference of healthy neighboring nodes located on the low side of the wear gradient is negative. The maximum value of the positive difference in each adjacent direction will not exceed the preset difference threshold. They will not be judged to have channel wear difference, nor will they be included in the target wear node list, thus avoiding the mistaken inclusion of healthy nodes in the isolation range.

[0033] The preset difference threshold is 2500 times. During the array commissioning and debugging phase, the same model of single-layer cell flash array is continuously run under the nominal write load for no less than 90 days. The difference in the number of erase and write operations of all adjacent storage node pairs in the entire array is counted every day. All difference samples are sorted from smallest to largest, and the 95th percentile is taken as the preset difference threshold. The statistical result is 2500 times. This value ensures that during the normal operation of the array and the natural diffusion of wear, only about 5% of adjacent node pairs are judged as wear differences. It will not frequently trigger data migration due to the threshold being too low, nor will it miss the real local wear imbalance due to the threshold being too high.

[0034] If the difference in the number of erase / write cycles between storage nodes exceeds a preset difference threshold of 2500, it is determined that the storage node exhibits channel wear differences, indicating a significant imbalance in the erase / write load of its local area. In this embodiment, 3600 cycles is greater than 2500, therefore storage nodes (6, 4, 2) are determined to have channel wear differences. Conversely, if the difference in the number of erase / write cycles is less than or equal to the preset difference threshold, it is determined that the wear rate of the storage node is consistent with that of its adjacent storage nodes, there are no channel wear differences, and it is not included in the target wear node list. The above calculations and judgments are performed on all storage nodes in the first wear state set. All storage nodes with channel wear differences are summarized. Each record contains four fields: the physical location coordinates of the storage node, the logical address, the current erase / write count, and the difference between the current erase / write count. This yields the target wear node list. In this embodiment, the target wear node list contains 18 storage nodes, which are concentrated in the address range of logical address 192 to 211 on channel 6. The adjacent nodes on the low wear gradient side of channels 5 and 7 have negative positive differences pointing to their high wear neighbors, and the positive differences in other directions are also much smaller than the preset difference threshold. Therefore, they are not included in the target wear node list. It should be noted that the target wear node list is dynamically generated in each balancing cycle. As the balancing management continues, the wear gradient gradually flattens. When there are no storage nodes with an erase / write count difference greater than the preset difference threshold in a certain balancing cycle, the target wear node list is empty. At this time, the migration processing of steps S14 and S15 is skipped in this round of the process, and the process waits for the next balancing cycle to be re-executed.

[0035] For example, Figure 3 This is a schematic diagram illustrating the channel wear difference determination. The diagram shows the difference in the number of erase / write cycles for each storage node relative to its adjacent storage nodes. Within the logical address range of 192 to 211, there are 18 storage nodes whose erase / write cycle differences exceed the preset difference threshold of 2500 times. These nodes are all concentrated in channel 6, thus forming a target wear node list.

[0036] In step S14, the historical access frequency of each storage node in the target wear node list is obtained, cold data and hot data are distinguished according to the historical access frequency to obtain a cold and hot data distribution map, and the cold and hot data distribution map is matched with the three-dimensional spatial mapping matrix to obtain a cold data residency candidate set.

[0037] In one implementation, the method includes: Obtain the read / write timestamps of each storage node in the target wear node list; perform access interval statistics on the read / write timestamps to obtain the historical access frequency; If the historical access frequency is greater than the preset frequency threshold, the data of the corresponding storage node will be assigned to the hot data set; otherwise, the data of the corresponding storage node will be assigned to the cold data set. A hot and cold data distribution map is generated based on the hot data set and the cold data set.

[0038] In one implementation, the method further includes: Extract the physical location coordinates of the cold data from the hot and cold data distribution map, and read the current erase / write count of each storage node from the three-dimensional spatial mapping matrix; If the current number of erase / write operations is higher than the preset average erase / write threshold, the corresponding physical location coordinates will be divided into an elderly residence area. The physical location coordinates in the elderly residence area are aggregated to obtain a cold data residence candidate set.

[0039] Read / write timestamps are automatically recorded by the metadata management unit of the flash memory conversion layer upon completion of each read / write operation. The timestamps are taken from the system clock with an accuracy of 1ms. For each storage node in the target wear node list, all read / write timestamps within a 24-hour statistical window are extracted. The historical access frequency in hours / hour is obtained by dividing the total number of read / write operations within the statistical window by the window duration of 24 hours. The statistical window duration is consistent with the preset balancing period and is updated synchronously with the balancing period setting. In this embodiment, the storage node at logical address 209 has accumulated 1200 read / write operations within the window, with a historical access frequency of 50 times / hour; the storage node at logical address 208 has accumulated 5 read / write operations within the window, with a historical access frequency of 0.2 times / hour.

[0040] The preset frequency threshold is 30 times / hour. This is achieved by replaying the daily operation records of the same array model under normal business load for 90 consecutive days. The manual criterion for determining cold data is based on the storage node having no read / write operations for 7 consecutive days starting from the next day. For all samples meeting this criterion, the historical access frequency calculated according to the aforementioned definition within the last 24 hours before entering the continuous no-read / write state is statistically analyzed. The 95th percentile of the frequency distribution is taken as the preset frequency threshold, resulting in a statistical result of 30 times / hour. If the historical access frequency is greater than the preset frequency threshold, the data of the corresponding storage node is classified into the hot data set. In this embodiment, logical address 209's 50 times / hour is greater than 30 times / hour, so its data is classified into the hot data set. Conversely, if the historical access frequency is less than or equal to the preset frequency threshold, the data of the corresponding storage node is classified into the cold data set. In this embodiment, logical address 208's 0.2 times / hour is less than 30 times / hour, so its data is classified into the cold data set. Each record in the hot and cold data sets contains four fields: the logical address of the storage node, the physical location coordinates, the total number of read and write operations within the statistics window, and the historical access frequency. These fields are used to generate the hot and cold data distribution map and are directly called upon in subsequent migration processes.

[0041] Subsequently, a hot and cold data distribution map is generated. Specifically, a three-dimensional distribution matrix is ​​established, with a grid division completely consistent with the three-dimensional spatial mapping matrix. The matrix dimension is 8×8×4, with each grid cell corresponding to a storage node. The grid spatial resolution is at the granularity of a single storage node, i.e., a single block group. The grid elements corresponding to storage nodes identified as hot data within the target wear node list have a value of 1, while those identified as cold data have a value of 0. The grid elements corresponding to storage nodes outside the target wear node list have a uniform value of 2, indicating that they did not participate in this round of hot and cold data statistics. This three-dimensional distribution matrix is ​​the hot and cold data distribution map, and its three-dimensional coordinate indices correspond one-to-one with the three-dimensional spatial mapping matrix. The hot and cold data markers and the number of erase / write operations are linked through the same coordinate system.

[0042] Since the mesh divisions of the two maps are completely identical, the cold and hot markers of the same physical location coordinates in the cold and hot data distribution map are aligned with the current erase / write count in the three-dimensional spatial mapping matrix to the same storage node, generating a matching result table. Each row in the table records four fields for a storage node: physical location coordinates, channel identifier, cold / hot marker, and current erase / write count. Two types of information can be directly extracted from the matching result table: first, the physical location coordinates of the cold data, i.e., the migration source coordinates of the cold data to be migrated later; second, the current erase / write count of each storage node in the entire array, which reuses the reading result from step S12. For example, the record in the row of logical address 72 in the matching result table is physical location coordinates (2, 2, 0), channel identifier 2, cold / hot marker 2, and current erase / write count 22000.

[0043] The preset average erase / write threshold is the arithmetic mean of the current erase / write counts of all valid storage nodes in the entire array. This value is preset and fixed during the deployment of the balancing management process. The threshold value is updated synchronously with the read results of step S12 at the beginning of each balancing cycle. In this embodiment, the preset average erase / write threshold for the current cycle is 18,000 times. If the current erase / write count of a storage node in the matching result table is higher than the preset average erase / write threshold, the physical location coordinates of that storage node are classified as an old-age residency area; conversely, storage nodes with a current erase / write count less than or equal to the preset average erase / write threshold are not included in the old-age residency area. The remaining erase / write lifetime of old-age nodes is no longer suitable for handling high-frequency hot writes, while cold data residency does not generate additional erase / writes. Migrating cold data to old-age nodes utilizes their remaining static storage capacity and allows young nodes with low erase / write counts to retain free capacity to handle hot data writes, which conforms to the balancing direction of cold data residing in old-age blocks and young blocks handling hot writes. In this embodiment, the storage node with logical address 72 (corresponding to physical location coordinates (2, 2, 0)) has been erased and written 22,000 times, which is higher than 18,000 times, and is therefore classified as an old-age residence area.

[0044] Finally, the physical location coordinates in the aged residency area are aggregated and grouped according to their respective channel identifiers. Storage nodes belonging to the target wear node list are removed, and nodes deemed to be in wear imbalance should no longer receive any migration data. The number of remaining aged residency coordinates in each channel is counted. If the number in a channel is greater than or equal to a preset minimum node count of 2, then that channel, along with its internal aged residency coordinates and corresponding remaining available capacity, is included in the cold data residency candidate set. The remaining available capacity is equal to the nominal capacity of the storage node (256MB) minus the already resided data capacity, calculated from the mapping table of the flash memory conversion layer. Conversely, if the number in a channel is less than the preset minimum node count of 2, then that channel is not included in the cold data residency candidate set. The preset minimum node count of 2 ensures that candidate channels have the capability to receive large swaths of cold data, avoiding new local imbalances caused by single-point reception. In this embodiment, the cold data residency candidate set includes two channels: channel 2 and channel 5. The storage node with logical address 72 in channel 2 has a remaining available capacity of 5MB, and this candidate set will serve as the target write area for subsequent cold data migration.

[0045] In step S15, if cold data exists in the target wear node list, the cold data is written to the target physical location allocated from the cold data residence candidate set to obtain an updated distribution topology map. The write pointer is reset according to the updated distribution topology map to guide subsequent hot data to be written to a physical location outside the target wear node list, thus completing data balance management.

[0046] In one implementation, the method includes: Obtain the read and write timestamps of each storage node in the target wear node list, and calculate the data activity based on the read and write timestamps; If the data activity level is lower than the preset activity level threshold, the data of the corresponding storage node is determined to be cold data, and the occupied capacity value of the cold data is extracted. Select a physical location from the cold data residency candidate set whose remaining available capacity matches the occupied capacity value as the target physical location; The cold data is written to the target physical location to generate a node status record. The original data distribution topology is updated based on the node status record to obtain an updated distribution topology.

[0047] In one implementation, the method further includes: Based on the updated distribution topology map, determine the boundary of the isolation area corresponding to the target wear node list; The set of usable physical coordinates is obtained by removing the physical location coordinates that fall within the boundary of the isolated region from the global physical block coordinates. The write pointer is reset to the set of available physical coordinates to establish an addressing mapping relationship between the hot data and the write pointer; Based on the addressing mapping relationship, subsequent thermal data is guided to be written to a physical location outside the target wear node list, thus completing data balance management.

[0048] First, the read / write timestamp sequence of each storage node in the target wear node list for the most recent 30 days is obtained. The statistical window of 30 days is a preset activity statistics window, the length of which is determined by the statistical requirements of the monthly access patterns of the covered data. The access interval sequence is obtained by subtracting adjacent timestamps. Exponential smoothing is then performed sequentially from earliest to latest time. The initial smoothing value is the first access interval in the sequence. For each new access interval read thereafter, the smoothing coefficient is multiplied by the new access interval, and the difference between 1 and the smoothing coefficient is multiplied by the previous weighted average access interval. The sum of these two values ​​is the new weighted average access interval. The value obtained after traversal is the weighted average access interval T of that node. The smoothing coefficient is set to 0.4. It is determined by minimizing the relative error between the weighted average access interval and the actual average access interval on historical access records of at least 90 days, using a grid search within the range of 0.1 to 0.9 with a step size of 0.1. Exponential smoothing assigns higher weight to recent access intervals, allowing changes in recent access behavior to be quickly reflected in the activity level, while preserving the smoothing effect of historical access patterns on the results.

[0049] Data activity A is calculated using the formula A = 100 × T0 / (T + T0), where T is the weighted average access interval of the node, and T0 is the preset baseline interval, which is 2 hours. The preset baseline interval is obtained by statistically analyzing and rounding down the median access interval of all storage nodes in the same type of array, and is used to characterize the overall access rhythm of the array. The value of data activity ranges from 0 to 100, with longer access intervals resulting in lower activity. In this embodiment, the storage node with logical address 208 has a weighted average access interval of 4.67 hours obtained through exponential smoothing. Substituting this into the formula, the data activity is calculated as 100 × 2 / (4.67 + 2) = 30.

[0050] The preset activity threshold is 50. The threshold is determined manually based on the assumption that a storage node has had no read / write operations for 14 consecutive days. Data activity is calculated for all storage nodes meeting this threshold in a 90-day continuous operation record of the same array model. The 95th percentile of this distribution is used as the preset activity threshold, resulting in a value of 50. If the data activity is lower than the preset activity threshold, the data on the corresponding storage node is classified as cold data and enters the migration process. In this embodiment, 30 is less than 50, so the data at logical address 208 is classified as cold data. Conversely, if the data activity is greater than or equal to the preset activity threshold, the corresponding data is classified as hot data or frequently accessed data, and it remains on the original storage node, not participating in this migration. In this embodiment, the data activity at logical address 209 is 99, and its data remains in its original position. It should be noted that step S14, based on the frequency determination within a 24-hour statistical window, and step S15, based on the activity determination within a 30-day statistical window, complement each other. Migration eligibility is based on the activity determination result of step S15 to avoid misjudgments caused by short-term fluctuations at the edge of the statistical window.

[0051] If multiple cold data points with activity levels below a preset activity threshold exist in the target wear node list, the occupied capacity extraction and target physical location allocation are performed sequentially according to data activity levels from low to high. The sparsest cold data is migrated first to quickly relieve the resident pressure on the most severely worn storage nodes. After each cold data migration is completed, the remaining available capacity of the corresponding storage node in the cold data resident candidate set is simultaneously deducted before the allocation of the next cold data is performed. This embodiment uses the migration of a single cold data point as an example. The number of effective physical pages occupied by the cold data is queried from the flash translation layer, and the occupied capacity value is calculated based on a page capacity of 16KB. The cold data at logical address 208 occupies 256 effective physical pages, which translates to a occupied capacity value of 4MB.

[0052] The target physical location is selected from the cold data residing candidate set using the best-fit allocation rule. The remaining available capacity of each storage node in the candidate set is traversed, and the storage node with the smallest difference between its remaining available capacity and the occupied capacity is selected as the target physical location. If multiple storage nodes have the same difference, the storage node with the smallest lexicographical order of its physical location coordinates (horizontal axis number, vertical axis number, and vertical axis hierarchical number) is selected to ensure uniqueness. In this embodiment, the storage node with logical address 72 in channel 2 has a remaining available capacity of 5MB, and the difference of 1MB between it and the occupied capacity is the smallest in the entire candidate set; therefore, it is determined as the target physical location. Conversely, if there is no storage node with a remaining available capacity greater than or equal to the occupied capacity in the cold data residing candidate set, the cold data is retained in its original storage node and marked as pending migration, awaiting re-selection after the cold data residing candidate set is updated in the next equalization cycle.

[0053] Subsequently, programming instructions are issued to the target physical location via the flash memory controller to write 4MB of cold data into the free physical page of the block group corresponding to logical address 72. After the write is completed, the cyclic redundancy check value is calculated for the source physical block data and the written data, and compared bit by bit. If the check passes, the source physical block is erased to free up space; if the check fails, the programming instructions are re-executed. This migration causes the source block to undergo an additional erase, but the storage node where the source block is located is removed from the hot data write path and will not accept new hot data writes in the subsequent balancing cycle. The cost of a single erase is exchanged for the continuous reduction of wear gradient hotspot write pressure. After the write is completed, the physical address, page offset, written data length, cold data identifier, and migration timestamp of the target physical location are extracted and concatenated in the order of the above fields to generate a node status record. This record fully describes the destination location and data scale of this data migration.

[0054] The original data distribution topology is a global graph structure data pre-maintained by the flash conversion layer. It is initialized to a completely empty state when the array is formatted and then incrementally updated with each data write and erase operation. Each node in the graph corresponds to a storage node, and the node attributes include physical location coordinates, logical address, resident data identifier, occupied capacity, cold / hot flag, and current erase / write count. Nodes are connected according to a six-neighbor relationship. When updating according to the node status record, the resident data identifier of the source node (logical address 208) is set to empty, the occupied capacity is cleared to zero, and the current erase / write count is updated synchronously according to the latest statistics of the block erase / write table after this erase. At the same time, the resident data identifier, occupied capacity, and cold / hot flag of the target node (logical address 72) are updated, and the updated distribution topology is reconstructed and generated. This graph reflects the latest physical resident status of the entire array after the cold data migration.

[0055] The physical location coordinates and logical addresses of each storage node in the target worn node list are extracted from the updated distribution topology map. Storage nodes with consecutive logical addresses are grouped into consecutive address segments, and the start and end boundaries of each consecutive address segment are the boundaries of the isolation region. If the storage nodes in the target worn node list are scattered into multiple non-consecutive segments in terms of logical address, then each consecutive sub-segment is designated as an isolation sub-region, and the boundary of the isolation region is the union of the boundaries of all sub-segments. In this embodiment, all 18 worn nodes are located in channel 6 and are grouped into a consecutive address segment from logical address 192 to 211 (some addresses within the segment are not listed), that is, the boundary of the isolation region is the range of physical location coordinates corresponding to logical addresses 192 to 211.

[0056] The global physical block coordinates are the physical location coordinates of all 256 storage nodes in the three-dimensional spatial mapping matrix. After removing the physical location coordinates that fall within the boundary of the isolation area, the remaining coordinates constitute the set of usable physical coordinates. Subsequently, a striped polling scheduling method is used to reset the write pointer, forcing it to the starting safe coordinate with the smallest logical address in the available physical coordinate set. In this embodiment, this is logical address 0 (corresponding to the 0th physical page of vertical axis number 0 and block group number 0 in channel 0). Subsequent writes proceed in a striped order with the channel identifier as the innermost rotation dimension within the available physical coordinate set. That is, for each set of vertical axis numbers and vertical axis level numbers, the corresponding storage nodes in channels 0 to 7 are traversed sequentially first, then the vertical axis level numbers are advanced, and then the vertical axis numbers are advanced. During the traversal, coordinates falling within the boundary of the isolation area are automatically skipped. After reaching the end of the set, the loop returns to the starting safe coordinate and continues. Continuously arriving write requests are thus distributed to different channels for parallel service, matching a multi-channel parallel architecture and avoiding channel-level serialization of writes. At any given time, the write pointer only points to coordinates within the available physical coordinate set, ensuring that high-wear areas no longer accept any new hot data writes.

[0057] It should be noted that the isolation zone boundary is dynamically updated with each balancing cycle. When the target worn node list no longer contains a certain storage node in a subsequent cycle, the physical location coordinates of that node automatically return to the set of available physical coordinates, resuming write operations. This isolation is a periodic reallocation of local worn hotspots rather than permanent retirement. The loss of the entire array's available capacity is only the remaining free pages of the isolated nodes in the current cycle. The write pointer is reset immediately after the cold data migration is completed, and thereafter recalibrated at the end of each balancing cycle according to the latest data distribution topology.

[0058] When a hot data write command is issued by the host, its logical block address is parsed. The logical block address is then bound to the physical location currently pointed to by the write pointer in the order of arrival, and written to the logical address to physical address mapping table of the flash translation layer. This establishes the addressing mapping relationship between the hot data and the write pointer. Subsequently, the hot data is written sequentially to the healthy physical pages pointed to by the striped sequence starting from logical address 0, according to the striped rotation order of the write pointer. Successive write requests are distributed to different channels for parallel service. The entire write process is strictly limited to physical locations outside the target wear node list, preventing exhausted high-wear node groups from receiving new hot data writes and completing the physical space allocation to mitigate local exhaustion risk. If there is no cold data in the target wear node list (i.e., the data activity of all storage nodes in the list is greater than or equal to a preset activity threshold), the cold data migration step is skipped. The write pointer reset and addressing mapping relationship are directly executed based on the current data distribution topology. This also guides subsequent hot data to avoid high-wear areas, achieving physical space allocation of write pressure.

[0059] In summary, this invention discloses a data balancing management method for SLC flash memory based on array topology awareness, comprising: acquiring the physical topology information of a single-layer cell flash array, extracting the physical location coordinates of each storage node, and establishing a three-dimensional spatial mapping matrix; reading the current erase / write count of each storage node through the three-dimensional spatial mapping matrix, and clustering to obtain a first wear state set; for each storage node in the first wear state set, subtracting its current erase / write count from the current erase / write count of its adjacent storage nodes to obtain a positive difference value, taking the maximum value of the positive difference value as the erase / write count difference value, and determining the corresponding storage node if the erase / write count difference value is greater than a preset difference threshold. Given differences in channel wear, a target wear node list is obtained. The historical access frequency of each storage node in the target wear node list is acquired, and cold data is distinguished from hot data based on the historical access frequency, resulting in a cold / hot data distribution map. This map is matched with a three-dimensional spatial mapping matrix to obtain a cold data residency candidate set. If cold data exists in the target wear node list, it is written to a target physical location allocated from the cold data residency candidate set, resulting in an updated distribution topology map. The write pointer is reset based on the updated distribution topology map, guiding subsequent hot data to be written to physical locations outside the target wear node list, thus completing data balancing management. This invention achieves precise isolation and load redistribution for differences in channel wear through data balancing management.

[0060] For example, Figure 4 This is a diagram illustrating the hot data write allocation. The diagram shows the allocation of 8192 hot data writes in the same batch before and after the write pointer is reset. Before the write pointer is reset, the logical address range 192 to 211 experienced concentrated hot data writes; after the write pointer is reset, the number of hot data writes in this isolated area drops to 0, and the hot data is guided to the available physical coordinate set, thus achieving a redistribution of the write load.

[0061] The second embodiment of the present invention provides an array topology-aware SLC flash memory data balancing management system, including: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the array topology-aware SLC flash memory data balancing management method as described above.

[0062] It should be noted that the array topology-aware SLC flash data balancing management system provided in this embodiment of the invention is used to execute all the process steps of the array topology-aware SLC flash data balancing management method in the above embodiment. The working principles and beneficial effects of the two are one-to-one, so they will not be described again.

[0063] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A method for SLC flash memory data balancing management based on array topology awareness, characterized in that, include: Obtain the physical topology information of a single-layer cell flash array, extract the physical location coordinates of each storage node, and establish a three-dimensional spatial mapping matrix; The current erase / write count of each storage node is read using the three-dimensional spatial mapping matrix, and the first wear state set is obtained by clustering. For each storage node in the first wear state set, the current erase / write count is subtracted from the current erase / write count of the adjacent storage node to obtain a positive difference value. The maximum value of the positive difference value is taken as the erase / write count difference value. If the erase / write count difference value is greater than a preset difference value threshold, it is determined that the corresponding storage node has channel wear differences, and a target wear node list is obtained. The historical access frequency of each storage node in the target wear node list is obtained. Cold data and hot data are distinguished according to the historical access frequency to obtain a cold and hot data distribution map. The cold and hot data distribution map is matched with the three-dimensional spatial mapping matrix to obtain a cold data resident candidate set. If cold data exists in the target wear node list, the cold data is written to the target physical location allocated from the cold data residence candidate set to obtain an updated distribution topology map. The write pointer is then reset according to the updated distribution topology map to guide subsequent hot data to be written to physical locations outside the target wear node list, thus completing data balance management.

2. The SLC flash memory data balancing management method based on array topology awareness according to claim 1, characterized in that, The process of acquiring the physical topology information of a single-layer cell flash array, extracting the physical location coordinates of each storage node, and establishing a three-dimensional spatial mapping matrix includes: The physical topology information is analyzed to obtain channel mounting data and grain distribution data; Based on the channel mounting data, determine the channel identifier and chip select signal number mounted on each die, and summarize to obtain the channel identifier set and chip select signal set of each memory node; If the set of channel identifiers matches the set of chip select signals according to a preset addressing rule, the physical location coordinates of each storage node are extracted, and a three-dimensional spatial mapping matrix is ​​established.

3. The SLC flash memory data balancing management method based on array topology awareness according to claim 1, characterized in that, The process of reading the current erase / write count of each storage node through the three-dimensional spatial mapping matrix and clustering it to obtain a first wear state set includes: An addressing instruction is generated based on the logical address of each storage node in the three-dimensional spatial mapping matrix. The addressing instruction is sent to the metadata management unit of the flash conversion layer. The raw erase / write count value is received by the metadata management unit according to the physical block statistics. The original erase count values ​​are concatenated according to the coordinate order of the three-dimensional spatial mapping matrix to obtain a one-dimensional feature vector; Calculate the Euclidean distance between each element in the one-dimensional feature vector and the preset cluster center. If the Euclidean distance is less than the preset distance threshold, the corresponding element is assigned to the classification cluster where the preset cluster center is located. Extract the storage node in the classification cluster and the corresponding current erase / write count to obtain the first wear state set.

4. The SLC flash memory data balancing management method based on array topology awareness according to claim 1, characterized in that, For each storage node in the first wear state set, the current erase / write count is subtracted from the current erase / write count of its adjacent storage nodes to obtain a positive difference value. The maximum value of the positive differences is taken as the erase / write count difference value. If the erase / write count difference value is greater than a preset difference threshold, it is determined that the corresponding storage node has channel wear differences, and a target wear node list is obtained, including: Extract the physical location coordinates of each storage node from the first wear state set; Determine the coordinates of adjacent physical locations based on the physical location coordinates, and obtain the current erase / write count corresponding to the adjacent physical location coordinates; Subtract the current erase / write count corresponding to the adjacent physical location coordinates from the current erase / write count of the corresponding storage node to obtain the positive difference in each adjacent direction. Take the maximum value among the positive differences as the erase / write count difference. If the difference in the number of erase / write cycles is greater than a preset difference threshold, it is determined that the corresponding storage node has channel wear differences. The storage nodes with channel wear differences are then summarized to obtain a target wear node list.

5. The SLC flash memory data balancing management method based on array topology awareness according to claim 1, characterized in that, The process of obtaining the historical access frequency of each storage node in the target wear node list, distinguishing between cold and hot data based on the historical access frequency, and obtaining a cold and hot data distribution map includes: Obtain the read and write timestamps of each storage node in the target wear node list; The access interval is statistically analyzed based on the read and write timestamps to obtain the historical access frequency; If the historical access frequency is greater than the preset frequency threshold, the data of the corresponding storage node will be assigned to the hot data set; otherwise, the data of the corresponding storage node will be assigned to the cold data set. A hot and cold data distribution map is generated based on the hot data set and the cold data set.

6. The SLC flash memory data balancing management method based on array topology awareness according to claim 1, characterized in that, The step of matching the hot and cold data distribution map with the three-dimensional spatial mapping matrix to obtain a candidate set of cold data residency includes: Extract the physical location coordinates of the cold data from the hot and cold data distribution map, and read the current erase / write count of each storage node from the three-dimensional spatial mapping matrix; If the current number of erase / write operations is higher than the preset average erase / write threshold, the corresponding physical location coordinates will be divided into an elderly residence area. The physical location coordinates in the elderly residence area are aggregated to obtain a cold data residence candidate set.

7. The SLC flash memory data balancing management method based on array topology awareness according to claim 1, characterized in that, If cold data exists in the target wear node list, the cold data is written to the target physical location allocated from the cold data residence candidate set to obtain an updated distribution topology map, including: Obtain the read and write timestamps of each storage node in the target wear node list, and calculate the data activity based on the read and write timestamps; If the data activity level is lower than the preset activity level threshold, the data of the corresponding storage node is determined to be cold data, and the occupied capacity value of the cold data is extracted. Select a physical location from the cold data residency candidate set whose remaining available capacity matches the occupied capacity value as the target physical location; The cold data is written to the target physical location to generate a node status record. The original data distribution topology is updated based on the node status record to obtain an updated distribution topology.

8. The SLC flash memory data balancing management method based on array topology awareness according to claim 1, characterized in that, The step of resetting the write pointer according to the updated distribution topology map to guide subsequent hot data to be written to a physical location outside the target wear node list, thereby completing data balancing management, includes: Based on the updated distribution topology map, determine the boundary of the isolation area corresponding to the target wear node list; The set of usable physical coordinates is obtained by removing the physical location coordinates that fall within the boundary of the isolated region from the global physical block coordinates. The write pointer is reset to the set of available physical coordinates to establish an addressing mapping relationship between the hot data and the write pointer; Based on the addressing mapping relationship, subsequent thermal data is guided to be written to a physical location outside the target wear node list, thus completing data balance management.

9. A topology-aware SLC flash memory data leveling management system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the array topology-aware SLC flash memory data balancing management method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the array topology-aware SLC flash memory data balancing management method as described in any one of claims 1 to 8.

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