Memory access bridging method and system

Abstract

The present disclosure relates to the technical field of storage, and specifically discloses a memory access bridging method and system, wherein the memory access bridging method is applied to a memory access bridging device, and includes the following steps: determining a memory to be accessed based on a memory access instruction sent by a memory controller; generating a memory refresh instruction corresponding to the memory to be accessed based on pre-stored memory configuration information and the memory access instruction, and sending the memory refresh instruction to the memory to be accessed; and in the case that the memory refresh instruction includes a first power consumption control instruction, controlling the memory to be accessed to enter a first power consumption running state. Through the technical solution provided by the present disclosure, the memory can be controlled to enter a low-power consumption running state based on the instruction generated by the memory controller.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a memory access bridging method and system. Background Technology

[0002] With the rapid development of integrated circuits, chip power consumption has become a key factor restricting device battery life, heat dissipation design, and operational reliability. Dynamic Random Access Memory (DRAM, such as LPDDR / DDR series) is the main memory of the system, and its power consumption accounts for a significant proportion of the total system power consumption. Optimizing the energy efficiency of the memory system plays a decisive role in improving overall system performance and battery life.

[0003] To reduce the power consumption of memory systems, the Joint Electron Device Engineering Council (JEDEC) has defined various low-power operating modes in different generations of memory standards, such as self-refresh and deep sleep. However, the low-power command formats, timing requirements, and state definitions differ across memory generations, increasing the difficulty of implementing unified power management in bridging scenarios based on memory access bridging devices. Summary of the Invention

[0004] The purpose of this disclosure is to provide a memory access bridging method and system that can generate a refresh instruction adapted to the memory to be accessed based on the memory access instruction and the pre-stored memory configuration information through a memory access bridging device, and control the memory to enter the corresponding power consumption state when the refresh instruction includes a power control instruction, thereby improving memory access compatibility while reducing system power consumption.

[0005] To address the aforementioned technical problems, the first aspect of this disclosure provides a memory access bridging method, which may specifically include the following steps: determining the memory to be accessed based on a memory access instruction sent by a memory controller; generating a memory refresh instruction corresponding to the memory to be accessed based on pre-stored memory configuration information and the memory access instruction, and sending the memory refresh instruction to the memory to be accessed; and controlling the memory to be accessed to enter a first power consumption operating state when the memory refresh instruction includes a first power consumption control instruction; wherein the memory generation version of the memory controller is different from the memory generation version of the memory to be accessed.

[0006] In one possible implementation of the first aspect above, the memory access bridging device is connected to at least one memory; the method further includes: sending a second power control instruction to a target memory in at least one memory that is in a first power consumption operating state; the second power control instruction includes an active / passive resistor adjustment instruction and / or a clock down frequency instruction.

[0007] In one possible implementation of the first aspect above, the method further includes: controlling the memory access bridging device to enter a second power consumption operating state based on the number of target memories in the first power consumption operating state.

[0008] In one possible implementation of the first aspect above, the memory access bridge device is controlled to enter a second power consumption operating state based on the number of target memory in the first power consumption operating state, including the following steps: when the number of target memory is the same as the number of memory connected to the memory access bridge device, the memory access bridge device is turned off.

[0009] In one possible implementation of the first aspect above, a memory refresh instruction corresponding to the memory to be accessed is generated based on pre-stored memory configuration information and memory access instructions, and the memory refresh instruction is sent to the memory to be accessed, including the following steps: a third power consumption control instruction corresponding to the memory to be accessed is generated based on pre-stored memory configuration information and memory access instructions, and the third power consumption control instruction is sent to the memory to be accessed; wherein, when the memory refresh instruction includes the third power consumption control instruction, the temperature of at least one memory connected to the memory access bridging device is obtained by temperature polling, and the refresh frequency of the memory to be accessed in the third power consumption operating state is controlled according to the memory temperature.

[0010] In one possible implementation of the first aspect described above, memory configuration information is stored in the non-volatile memory of the memory access bridging device.

[0011] In one possible implementation of the first aspect described above, the memory configuration information is obtained during the initialization configuration phase of the memory access bridge device, based on the initialization calibration process of the memory controller and the memory access bridge device.

[0012] In one possible implementation of the first aspect above, the initialization calibration process includes one or any combination of the following operations: configuring the impedance register of the memory access bridge device according to the impedance calibration information of the memory to be accessed; configuring the time phase register of the memory access bridge device according to the timing calibration information of the memory to be accessed; and configuring the communication link between the memory access bridge device and the memory to be accessed according to the link calibration information of the memory to be accessed.

[0013] In one possible implementation of the first aspect above, generating a memory refresh instruction corresponding to the memory to be accessed based on pre-stored memory configuration information and memory access instructions includes the following steps: extracting the memory model identifier contained in the memory access instruction; reading the pre-stored identifier configuration information corresponding to the memory model identifier according to the memory model identifier, and using the identifier configuration information as the memory configuration information of the memory to be accessed; generating a memory refresh instruction based on the memory configuration information and memory access instructions.

[0014] A second aspect of this disclosure provides a memory access bridging system, which may include: a memory controller, memory, and a memory access bridging device; the memory access bridging device is configured to perform any possible implementation of the first aspect above; the memory controller and the memory are communicatively connected through the memory access bridging device to enable instruction interaction and / or data interaction between the memory controller and the memory.

[0015] In one possible implementation of the second aspect above, a memory access bridging system may specifically include: a memory controller, multiple memory access bridging devices, and multiple memories; the memory generation versions of the multiple memories are not exactly the same as the memory generation version of the memory controller; each memory access bridging device corresponds to one or more memories.

[0016] The beneficial effects of this disclosure may include, but are not limited to: the technical solution provided in this disclosure creatively proposes a memory access bridging method applied to a memory access bridging device. The bridging device parses the memory access instructions issued by the memory controller and determines the memory to be accessed. It then generates and issues a memory refresh instruction adapted to the memory to be accessed, based on pre-stored memory configuration information. Furthermore, when the memory refresh instruction includes a first power control instruction, the memory to be accessed is controlled to enter a first power consumption operating state. On the one hand, this achieves compatible access to multiple generations of memory by a single memory controller, allowing the memory controller to flexibly access multiple generations of memory without needing to perceive generational differences in the backend memory. On the other hand, it achieves granular memory low-power mode switching control, enabling low-power operations to be performed only on the target memory while the remaining memory remains in a normal accessible state, balancing system performance and power consumption optimization. In addition, the memory access bridging device can monitor the low-power operating state of each memory in real time, providing a basis for the memory access bridging device itself to execute low-power operating states, further reducing the power consumption of the entire system. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 This is a flowchart illustrating a memory access bridging method provided according to an embodiment of the present disclosure; Figure 2 This is a schematic flowchart illustrating the generation of memory refresh instructions according to an embodiment of this disclosure; Figure 3 This is a memory refresh timing diagram provided according to an embodiment of the present disclosure; Figure 4 This is a schematic diagram of a memory access bridging system provided according to an embodiment of the present disclosure; Figure 5 This is a schematic diagram of an electronic device provided according to an embodiment of the present disclosure. Detailed Implementation

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the embodiments will be described in detail below with reference to the accompanying drawings. Obviously, the content described below are some examples or embodiments of this disclosure. For those skilled in the art, without creative effort, the technical solutions or means disclosed in this disclosure can be applied to other scenarios based on this technical content.

[0020] It should be understood that the terms "system," "device," "unit," and / or "module" used in this disclosure are a method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they may be replaced by other expressions.

[0021] Unless otherwise specified, the technical terms used to describe components, elements, etc. in this disclosure are not specifically singular, but may include plural. Generally speaking, terms such as "comprising" or "including" only indicate that explicitly identified steps, elements, or components are included, and these steps, elements, and components do not constitute an exclusive list, as the described method or apparatus may also include other steps or components.

[0022] This disclosure uses flowcharts to illustrate the operational steps performed by the apparatus or system of related embodiments. However, unless otherwise specified, the order in which these steps are described should not be construed as a limitation on the order of execution. Those skilled in the art can adjust the order of these steps based on the knowledge and information conveyed by the embodiments of this disclosure. Adjustments include, but are not limited to, reversing the order of steps, merging multiple steps, and splitting a step.

[0023] Based on the technical problems mentioned in the background art, this disclosure provides a memory access bridging method and system, which can generate a refresh instruction adapted to the memory to be accessed based on the memory access instruction and the pre-stored memory configuration information through the memory access bridging device, and control the memory to enter the corresponding power consumption state when the refresh instruction includes a power control instruction, thereby improving memory access compatibility while reducing system power consumption.

[0024] It is understood that in the specific implementation of this specification, the collection, use or processing of data (such as memory configuration information) is involved. When one or more embodiments of this disclosure are applied to the implementation of specific products or technologies, the permission or consent of the data subject is required. Moreover, the collection, use or processing of related data must strictly comply with the relevant laws, regulations and standards of the relevant countries and regions, such as the data source and implementation location. The de-identification technology ensures that the final data used is the de-identified data that has been securely processed, thereby protecting the rights and interests of the data subject and data security.

[0025] In some embodiments of this disclosure, Figure 1 A flowchart illustrating a memory access bridging method is shown. The memory access bridging method provided in this disclosure can be applied to a memory access bridging device. In some embodiments, the memory access bridging device can be disposed between a memory controller and at least one memory. One side of the memory access bridging device is connected to the memory controller, and the other side of the memory access bridging device is connected to at least one memory. Figure 1 As shown, process 100 may specifically include the following steps: Step 110: Determine the memory to be accessed based on the memory access instruction sent by the memory controller. In some embodiments, the memory generation version of the memory controller is different from the memory generation version of the memory to be accessed; when the memory generation version of the memory controller is the same as the memory generation version of the memory to be accessed, the memory controller can directly provide the memory access instruction for the chip to be accessed, which is not limited here. It should be noted that the number of memory access bridging devices in this disclosure can be one or more, wherein each memory access bridging device can execute the memory access bridging method provided in the embodiments of this disclosure. For example, the number of memory access bridging devices can be two, wherein one side of each memory access bridging device is connected to the memory controller, and the other side is connected to at least one memory.

[0026] In some examples, the memory access bridging device includes a shadow register, which stores relevant identifiers of the real-time operating status of the memory. The shadow register can update parameter values ​​in real time according to the actual operating status of the memory, ensuring the accuracy of instruction generation and power consumption control.

[0027] In some embodiments, the memory access bridging device may include a memory controller port, a memory port, an instruction transfer channel, and a data transfer channel. The memory controller port can be used to connect the memory access bridging device to a memory controller, receive and parse data and / or instructions provided by the memory controller, or provide data from the memory to the memory controller. The memory port can be used to connect the memory access bridging device to at least one memory, provide data and / or instructions provided by the memory controller to the memory in a data format that the memory can process, or receive data provided by the memory. The instruction transfer channel is used to transmit interaction instructions between the memory controller and the memory. The data transfer channel is used to transmit interaction data between the memory controller and the memory.

[0028] In some embodiments, the memory controller includes a module for receiving memory access requests from the processor and generating memory access instructions. The memory controller may include a memory control module integrated within a System on Chip (SoC) or a separate control chip; this embodiment does not limit the scope of the invention. The processor may be a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU).

[0029] Normally, the memory controller and memory are directly connected in a point-to-point manner. The memory controller can directly send data and instructions to the memory. However, when the memory controller and memory are of different generations, the memory cannot directly recognize and parse the instructions and data provided by the memory controller. Therefore, the memory access bridging device provided in this disclosure is required to bridge the gap, thereby enabling the memory controller to freely access memory of different generations.

[0030] Furthermore, when the memory access bridging device is connected to multiple memory versions of different generations, the memory access bridging device needs to parse and adapt the instructions from the memory controller to generate instructions that are adapted to the different generations of backend memory, so as to control the memory to complete operations such as temperature polling and self-refresh state switching according to the instructions.

[0031] In some examples, memory access instructions include power control instructions and / or data interaction instructions. Power control instructions instruct the memory to switch to low-power operating states such as self-refresh, deep sleep, or normal refresh to reduce overall system standby power consumption. Data interaction instructions instruct the execution of data read or write operations to the memory to be accessed. Before switching to a low-power operating state, the memory can be in an active state. In the active state, the memory responds to various read and write instructions issued by the memory controller and can complete data interaction operations at any time, switching to a low-power operating state.

[0032] It's important to note that memory relies on capacitors to store bit information. Capacitors are prone to leakage, necessitating periodic refresh operations to prevent data loss. During normal operation, the memory controller continuously issues power control commands to replenish charge. At this time, the memory clock, phase-locked loop (PLL), and I / O interfaces are all active, resulting in relatively high dynamic power consumption. When the system enters idle or standby mode, where frequent memory access is unnecessary, the memory can enter a low-power mode. Early versions of memory (such as LPDDR1-4) introduced a self-refresh mode: after the memory controller issues a command, the external clock is turned off, and the memory autonomously refreshes using its internal oscillator, no longer relying on an external controller. This significantly reduces static power consumption while retaining all memory data. Newer generations of memory, such as LPDDR5, further introduce a deep-sleep mode, which, on top of self-refresh, disables more internal analog and bias circuits, further reducing power consumption.

[0033] In some examples, the memory to be accessed is determined based on the memory access instructions sent by the memory controller. Specifically, the memory access instructions issued by the memory controller carry addressing information. After receiving the memory access instructions, the memory access bridging device extracts the addressing information from the instructions, queries a pre-stored mapping relationship, and matches the memory to be accessed corresponding to the addressing information in the mapping relationship. The addressing information can be a logical access address or an identifier used to identify the memory.

[0034] Step 120: Based on the pre-stored memory configuration information and memory access instructions, generate a memory refresh instruction corresponding to the memory to be accessed, and send the memory refresh instruction to the memory to be accessed.

[0035] In some examples, memory configuration information refers to a set of preset information used to identify the hardware parameters and access rules of each mounted memory. Different generations of memory to be accessed correspond to uniquely matching information. The memory access bridging device can call the matching memory configuration information to complete instruction adaptation and conversion based on the identified memory model. This converts the general memory access instructions issued by the memory controller into memory refresh instructions that can be correctly recognized and executed by the memory to be accessed, thereby achieving compatible access between the memory controller and memory of different specifications and solving access anomalies caused by incompatibility between different generations of memory.

[0036] In some examples, memory configuration information includes the memory generation identifier, capacity specifications, timing parameters, supported power states, instruction bus width (e.g., 6-bit CA lines for LPDDR4, 7-bit CA lines for LPDDR5), refresh cycle parameter tREFI, ODT configuration parameters, operating voltage parameters, and other configuration information related to the characteristics of the memory to be accessed. The memory access bridging device can pre-store the memory configuration information for different memory modules to be accessed. When it receives a memory access command from the memory controller, it can combine the memory configuration information to adapt and convert the original access command in terms of format, timing, and other dimensions, generating a memory refresh command that can be correctly identified and parsed by the memory to be accessed, ensuring the compatibility and correctness of memory access operations.

[0037] In some examples, memory configuration information is pre-stored in the non-volatile memory of the memory access bridging device. Alternatively, the memory configuration information may also be stored in the volatile memory of the memory access bridging device; this embodiment does not limit this to a specific type of memory.

[0038] In some examples, the memory access bridging device may not contain memory, or its memory may not store memory configuration information. In such cases, the memory configuration information is obtained during the initialization configuration phase of the memory access bridging device, based on the initialization calibration process of the memory controller and the memory access bridging device. The initialization configuration phase of the memory access bridging device is used to complete the bridging path configuration. This phase only configures the internal path parameters of the memory access bridging device and does not modify the refresh rate of the memory itself.

[0039] Optionally, the initialization calibration process includes impedance calibration, timing calibration, and / or link calibration. After the initialization calibration process is completed, memory configuration information is obtained. Impedance calibration includes ZQ calibration, timing calibration includes CBT calibration, and link calibration includes link read / write calibration. The initialization calibration process includes one or any combination of the following operations: configuring the impedance register of the memory access bridge device according to the impedance calibration information of the memory to be accessed; configuring the time phase register of the memory access bridge device according to the timing calibration information of the memory to be accessed; and configuring the communication link between the memory access bridge device and the memory to be accessed according to the link calibration information of the memory to be accessed.

[0040] The memory configuration information includes impedance calibration information, timing calibration information, and / or link calibration information. Impedance calibration matches the output impedance of the memory access bridging device with the input impedance of the memory to be accessed, reducing signal reflection and distortion during transmission and improving signal transmission integrity. Timing calibration adjusts the time phase of the output commands and data of the memory access bridging device, enabling the memory to sample the input signal within the correct time window and avoiding access failures caused by sampling errors. Link calibration optimizes the read / write communication link parameters between the memory access bridging device and the memory to be accessed, further improving the accuracy and stability of read / write operations and ensuring reliable operation of the memory access process.

[0041] For example, after the memory controller and memory access bridge device are started, the memory controller first confirms the number of memory modules connected to the memory access bridge device; it then performs branching processing based on whether non-volatile memory is available: if non-volatile memory is available, it directly loads the existing memory configuration information to complete the initialization configuration; if non-volatile memory is not available, it sequentially performs impedance calibration, timing calibration, and link calibration, and saves the impedance calibration information, timing calibration information, and link calibration information, and generates memory configuration information based on the impedance calibration information, timing calibration information, and link calibration information; after the initialization calibration is completed, the memory controller can perform memory access.

[0042] It should be noted that the memory configuration information pre-stored in the memory of the memory access bridging device can also be obtained using the above initialization calibration process.

[0043] In some embodiments of this disclosure, Figure 2 A flowchart illustrating the generation of memory refresh instructions is shown; for example... Figure 2 As shown, process 200 may specifically include the following steps: Step 210: Extract the memory model identifier contained in the memory access instruction.

[0044] In one example, the memory model identifier is specified in the identifier field of the memory access command issued by the memory controller. After the memory access bridging device receives the memory access command, it can directly read the specified identifier field to extract the memory model identifier and then match the configuration information of the corresponding memory to be accessed.

[0045] Step 220: Based on the memory model identifier, read the pre-stored identifier configuration information corresponding to the memory model identifier, and use the identifier configuration information as the memory configuration information of the memory to be accessed.

[0046] In some examples, each memory model identifier in the pre-stored memory configuration information is associated with a unique set of configuration parameters that are compatible with that type of memory. The memory access bridging device can use the memory model identifier as a search index to quickly retrieve and call the matching memory configuration information without having to traverse and search all the stored configuration information. This can effectively improve the processing efficiency of instruction adaptation and conversion and shorten the instruction generation waiting time.

[0047] Step 230: Generate memory refresh instructions based on memory configuration information and memory access instructions.

[0048] In some examples, to address the different requirements of different generations of memory for instruction format and timing parameters, the instruction encoding format and timing parameters of the original memory access instruction are adjusted based on the matched memory configuration information to generate a memory refresh instruction that can be parsed and executed normally for the memory to be accessed, thus completing the instruction adaptation and conversion process.

[0049] In some examples, the memory refresh instruction includes a first power control instruction and / or a third power control instruction. The first power control instruction can be a self-refresh instruction. Correspondingly, the first power operation state includes a self-refresh state, where the memory is decoupled from the external clock and autonomously refreshes using its internal clock. External refresh instructions are no longer needed, and the memory enters a low-power state, ceasing to respond to normal read / write operations until an exit self-refresh instruction is received. The third power control instruction can be a normal refresh instruction. Correspondingly, the third power operation state includes a normal refresh state, where the memory does not enter the self-refresh low-power mode. The memory controller continuously sends refresh commands to instruct the memory to perform storage unit refreshes, ensuring data is not lost. The memory still responds to read / write instructions and can be accessed normally.

[0050] The third power consumption control instruction may include a Bank refresh instruction and / or a full Bank refresh instruction. The Bank refresh instruction is used to control a specified Bank in the memory to perform a refresh operation, while the other Banks can still respond to read and write access normally; the full Bank refresh instruction is used to control all Banks in the memory to perform a complete refresh in sequence.

[0051] Optionally, before issuing the first power control instruction (self-refresh instruction) to the memory, the memory access bridging device can first perform a full bank refresh on the memory to be accessed. After refreshing all the storage units of the bank, the memory is then triggered to enter the self-refresh state, ensuring the data storage security of the memory chip.

[0052] For example, such as Figure 3As shown in the memory refresh timing diagram, memory can be refreshed by bank according to the timing shown in the diagram. Here, clk is the system clock; pad_CS_D4 is the chip select pin; pad_CA_D4 is the command address pin; Command represents the issued memory command; BANK identifies the target memory bank corresponding to the refresh operation; tRFCpb (per-bank refresh cycle time) is the per-bank refresh cycle time, which is the shortest time required from issuing the REFpb command to completing the refresh of that bank, also known as the refresh cycle between two adjacent REFpb commands; tRFCpbMIN represents the lower limit of tRFCpb, and the interval between two adjacent REFpb commands cannot be less than the lower limit of tRFCpb, meaning that after issuing one REFpb command, at least tRFCpbMIN must be waited before issuing the next one; ad marks the time interval corresponding to each bank refresh. Figure 3 The double slashes indicate a truncation of the timeline, omitting idle clock cycles. Specifically, the memory chip employs the following group-based refresh mechanism: the minimum refresh interval for a single Bank is tRFCpb, which is determined by the memory type; refreshes are scheduled in groups, and each refresh group must cover all Banks. The refresh order of Banks within a group is not limited, but the next group can only be started after all Banks have been refreshed; refreshes cannot be performed repeatedly on Banks that have already been refreshed while the same group is not being refreshed; each refresh group corresponds to the same row address for all Banks being refreshed, and the memory chip automatically increments the row address by 1 after the group refresh is completed, automatically cycling from 0 after all row addresses have been covered; the Bank to be refreshed must be in an IDLE state, and refresh commands are prohibited for Banks in an ACT active state.

[0053] In some examples, a memory refresh instruction corresponding to the memory to be accessed is generated based on pre-stored memory configuration information and memory access instructions, including: generating a third power control instruction corresponding to the memory to be accessed based on pre-stored memory configuration information and memory access instructions.

[0054] Specifically, when the memory refresh instruction includes a third power control instruction, the temperature of at least one memory connected to the memory access bridging device is obtained through temperature polling, and the refresh frequency of the memory to be accessed in the third power operation state is controlled based on the memory temperature. Alternatively, when the memory refresh instruction includes a first power control instruction, the temperature of at least one memory connected to the memory access bridging device can also be obtained through temperature polling, and the refresh frequency of the memory to be accessed in the third power operation state can be controlled based on the memory temperature.

[0055] Specifically, the memory access bridging device can read the memory temperature through the built-in temperature sensor interface or by reading the memory's mode register (MR). Temperature polling can be performed periodically, for example, every few milliseconds. Higher memory temperatures result in shorter data retention times in storage units, requiring a corresponding increase in the refresh rate (shortening the refresh interval); lower memory temperatures allow for a reduction in the refresh rate to save power. Based on the polled memory temperature, the memory access bridging device dynamically adjusts the frequency of refresh command transmission, achieving temperature-adaptive refresh control.

[0056] In some examples, after generating the memory refresh instruction corresponding to the memory to be accessed, the real-time running status table of each memory stored inside the memory access bridging device can also be updated to ensure that the next instruction adaptation conversion can generate a matching instruction based on the latest running status, avoiding instruction errors caused by inconsistent status.

[0057] Step 130: If the memory refresh instruction includes the first power control instruction, control the memory to be accessed to enter the first power operation state.

[0058] In some examples, to reduce system power consumption, after controlling the memory to be accessed to enter a first power consumption operating state, a second power consumption control instruction can be sent to at least one target memory in the first power consumption operating state. Optionally, the second power consumption control instruction includes active / passive resistor adjustment instructions and / or clock frequency reduction instructions. The passive resistor adjustment in the active / passive resistor adjustment instructions refers to the memory controller directly controlling and adjusting the ODT termination resistor of the signal path corresponding to the target memory. The active resistor adjustment refers to the memory access bridge device automatically adjusting the resistor according to the different power consumption modes of the target memory to reduce the static power consumption continuously consumed by the termination resistor; this is not limited here. The clock frequency reduction instruction can reduce the operating clock frequency of the path corresponding to the target memory, reducing the dynamic power consumption caused by digital logic circuit switching, and further reducing the power consumption of the memory access bridge device.

[0059] In some examples, the memory access bridging device provided in this disclosure supports mounting two memory modules; in other examples, the memory access bridging device provided in this disclosure can also mount three memory modules, with two of them entering a self-refresh state and the other one remaining active for normal read and write operations. In this case, the memory access bridging device can perform low-power management only for the two memory modules that need to enter the self-refresh state and reduce the clock frequency of the corresponding path; the path corresponding to the remaining active memory module remains enabled by ODT and runs at full clock frequency, without affecting normal access.

[0060] In some examples, to further reduce system power consumption, after controlling the memory to be accessed to enter a first power consumption operating state, the memory access bridging device can be controlled to enter a second power consumption operating state based on the number of target memories in the first power consumption operating state. The second power consumption operating state can be a self-shutdown state.

[0061] For example, when all three memory modules enter the self-refresh state, the memory access bridge device enters the second power consumption operating state (self-shutdown state), shutting down the clock and power supply of most of the internal circuits, leaving only the wake-up detection circuit.

[0062] In some examples, the memory access bridge device can be controlled to enter a second power consumption operating state in the following way: when the number of target memory is the same as the number of memory connected to the memory access bridge device, the memory access bridge device is turned off.

[0063] Disabling the memory access bridge device allows the entire system to achieve synchronous power management between the memory access bridge device and the memory after all memory enters a low-power state, further reducing the overall static and dynamic power consumption of the system.

[0064] When all the memory to be accessed connected to the memory access bridge device has entered the first power consumption operating state, the memory access bridge device can switch itself to the second power consumption operating state. At this time, except for the necessary wake-up detection circuit to maintain operation, the memory access bridge device can turn off the clock of the unused internal circuit module and shut down the power rails of all idle signal paths, reducing its overall power consumption to the lowest level, and working with the back-end memory to achieve the ultimate low power consumption operation of the entire memory system.

[0065] In some examples, even when all memory modules switch to a low-power state based on memory access instructions, the memory access bridge itself will continue to consume power if its internal circuitry remains operational. This is especially true in architectures with multiple memory modules, where multiple signal paths exist between the memory access bridge and the modules. When some memory modules enter a self-refresh state, the corresponding paths no longer transmit valid read / write data. If the circuitry of these paths continues to operate, it will consume unnecessary power. Therefore, simply controlling the backend memory to enter low-power mode is insufficient to achieve the lowest possible power consumption for the entire memory system. The memory access bridge must also consider the actual operating state of each backend memory module and synchronously execute its own low-power actions, such as self-shutdown, disabling ODT on idle paths, and clock downclocking, to achieve a reduction in the overall power consumption of the memory system.

[0066] Therefore, this disclosure provides a low-power memory access bridging method for memory access bridging devices. On the basis of achieving compatibility between multiple memory accesses and multiple generations of memory, it can generate power control instructions adapted to different generations of memory and perform power management on memory and memory access bridging devices, thereby effectively reducing the overall operating power consumption of the system.

[0067] In some examples, when the memory controller needs to resume memory access, it first wakes up the memory access bridge device and the target memory, and then issues an exit self-refresh instruction. The memory access bridge device parses the instruction and forwards it to the corresponding target memory, controlling the target memory to exit the first power consumption operating state (self-refresh state) and return to the active state. At the same time, the memory access bridge device synchronously exits its own low-power operation and restores its internal clock to the normal operating frequency. When the memory access bridge device is in the second power consumption operating state (self-shutdown state), it can be woken up by a wake-up instruction issued by the memory controller or by a specific signal detected by the wake-up detection circuit, exiting the self-shutdown state and restoring the normal operation of all circuits.

[0068] In some embodiments of this disclosure, exemplarily, Figure 4 A schematic diagram of a memory access bridging system is shown. In some embodiments, the memory access bridging system includes: a memory controller, memory, and a memory access bridging device; the memory access bridging device is configured to execute the memory access bridging method provided in the foregoing embodiments; the memory controller and the memory are communicatively connected through the memory access bridging device to realize instruction interaction and / or data interaction between the memory controller and the memory.

[0069] The memory access bridging device can run a condition management engine. The condition management engine is used to monitor the real-time operating status of each memory connected to the memory access bridging device, and at the same time receive and parse various access commands issued by the memory controller. It combines the pre-stored memory configuration information to complete the command adaptation and conversion, generate corresponding commands that can be correctly parsed and executed for backend memory of different generations and specifications, and manage memory access operations and power consumption control actions.

[0070] For example, Figure 4The memory access bridging system includes a GPU / CPU memory controller, memory access bridging device 1, memory access bridging device 2, and multiple memory groups. The GPU / CPU memory controller is connected to memory access bridging device 1 and memory access bridging device 2 respectively. Both memory access bridging device 1 and memory access bridging device 2 are equipped with a condition management engine and manage one group of memory respectively. In the memory managed by memory access bridging device 1, memory 1 is in an active state, while memory 2 and memory N are in a self-refresh state. In the memory managed by memory access bridging device 2, memory 1 and memory 2 are in an active state, while memory N is in a self-refresh state. The memory access bridging devices can manage the backend memory through the condition management engine and realize the switching of memory self-refresh states.

[0071] In some examples, a memory access bridging system includes: a memory controller, multiple memory access bridging devices, and multiple memory modules; the memory generation versions of the multiple memory modules are not exactly the same as the memory generation version of the memory controller; each memory access bridging device corresponds to one or more memory modules.

[0072] In some embodiments of this disclosure, Figure 5 A schematic diagram of the structure of an electronic device is shown, such as... Figure 5 The electronic device shown includes at least one processor 501; and a memory 502 communicatively connected to the at least one processor 501; wherein the memory 502 stores instructions executable by the at least one processor 501, the instructions being executed by the at least one processor 501 to enable the at least one processor 501 to perform the memory access bridging method in the above embodiments.

[0073] The memory 502 and processor 501 are connected via a bus, which can include any number of interconnecting buses and bridges. The bus connects various circuits of one or more processors 501 and memory 502 together. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by processor 501 is transmitted over a wireless medium via an antenna, which further receives data and transmits it to processor 501.

[0074] Processor 501 is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory 502 can be used to store data used by processor 501 during operation.

[0075] In some embodiments of this disclosure, a computer program product is also involved, including a computer program that, when executed by a processor, implements the steps of the memory access bridging method provided in the foregoing embodiments.

[0076] In some embodiments, the computer program product may involve only a computer program, which may be carried on a storage medium or a processing device. In other embodiments, the computer program product may also be a storage medium or processing device containing the aforementioned computer program. The processing device may include one or more processors, and the storage medium. Those skilled in the art will understand that the implementation of all or part of the steps in the memory access bridging method provided in the foregoing embodiments can be accomplished by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the memory access bridging method provided in the foregoing embodiments of this disclosure.

[0077] The basic concepts have been described above. It is obvious that the detailed disclosure above is merely illustrative and does not constitute a limitation of this specification. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to this specification by those skilled in the art. Such modifications, improvements, and corrections are taught in this specification and therefore remain within the spirit and scope of the exemplary embodiments described herein.

Claims

1. A memory access bridging method, characterized in that, Applied to a memory access bridging device, the method includes: The memory to be accessed is determined based on the memory access instructions sent by the memory controller; Based on pre-stored memory configuration information and the memory access instruction, a memory refresh instruction corresponding to the memory to be accessed is generated, and the memory refresh instruction is sent to the memory to be accessed; and If the memory refresh instruction includes a first power consumption control instruction, the memory to be accessed is controlled to enter a first power consumption operating state; The memory generation version of the memory controller is different from the memory generation version of the memory to be accessed.

2. The memory access bridging method according to claim 1, characterized in that, The memory access bridging device is connected to at least one memory; The method further includes: Send a second power control instruction to the target memory in the at least one memory that is in the first power consumption operating state; the second power control instruction includes an active / passive resistor adjustment instruction and / or a clock frequency reduction instruction.

3. The memory access bridging method according to claim 1 or 2, characterized in that, The method further includes the following steps: Based on the number of target memory units in the first power consumption operating state, the memory access bridging device is controlled to enter the second power consumption operating state.

4. The memory access bridging method according to claim 3, characterized in that, The step of controlling the memory access bridging device to enter the second power consumption operating state based on the number of target memory units in the first power consumption operating state includes the following steps: If the number of target memory is the same as the number of memory connected to the memory access bridge device, then the memory access bridge device is turned off.

5. The memory access bridging method according to claim 1, characterized in that, The step of generating a memory refresh instruction corresponding to the memory to be accessed based on pre-stored memory configuration information and the memory access instruction, and sending the memory refresh instruction to the memory to be accessed, includes: Based on the pre-stored memory configuration information and the memory access instruction, a third power consumption control instruction corresponding to the memory to be accessed is generated, and the third power consumption control instruction is sent to the memory to be accessed; Specifically, when the memory refresh instruction includes the third power consumption control instruction, the temperature of at least one memory accessed by the memory access bridging device is obtained by temperature polling, and the refresh frequency of the memory to be accessed in the third power consumption operating state is controlled according to the memory temperature.

6. The memory access bridging method according to claim 1, characterized in that, The memory configuration information is stored in the non-volatile memory of the memory access bridging device.

7. The memory access bridging method according to claim 1, characterized in that, The memory configuration information is obtained during the initialization configuration phase of the memory access bridging device, based on the initialization calibration process of the memory controller and the memory access bridging device.

8. The memory access bridging method according to claim 6, characterized in that, The initialization calibration process includes one or any combination of the following operations: Configure the impedance register of the memory access bridge device according to the impedance calibration information of the memory to be accessed. Configure the time phase register of the memory access bridging device according to the timing calibration information of the memory to be accessed; as well as Configure the communication link between the memory access bridging device and the memory to be accessed according to the link calibration information of the memory to be accessed.

9. The memory access bridging method according to claim 1, characterized in that, The step of generating a memory refresh instruction corresponding to the memory to be accessed based on pre-stored memory configuration information and the memory access instruction includes: Extract the memory model identifier contained in the memory access instruction; Based on the memory model identifier, read the pre-stored identifier configuration information corresponding to the memory model identifier, and use the identifier configuration information as the memory configuration information of the memory to be accessed; Based on the memory configuration information and the memory access instructions, the memory refresh instructions are generated.

10. A memory access bridging system, characterized in that, include: Memory controller, memory, and memory access bridging devices; The memory access bridging device is configured to perform the memory access bridging method according to any one of claims 1 to 9; The memory controller and the memory are communicatively connected through the memory access bridging device to enable instruction and / or data interaction between the memory controller and the memory.

11. The memory access bridging system according to claim 10, characterized in that, include: A memory controller, multiple memory access bridge devices, and multiple memory modules; The memory generation versions of the plurality of memory modules are not exactly the same as the memory generation version of the memory controller; each memory access bridge device corresponds to one or more of the memory modules.

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