Low power high signal to noise ratio signal processing system based on data processing

Abstract

The application discloses a low-power high-SNR signal processing system based on data processing, and relates to the technical field of data processing.The system comprises a post-conditioning analog signal output module, a processing source data obtaining module and a data processing module.The post-conditioning analog signal output module is used for constructing a full-differential signal conditioning link, performing fixed gain amplification and third-order cascade low-pass filtering on an analog signal output by an acoustic sensor, and outputting a post-conditioning analog signal.The processing source data obtaining module is used for performing analog-digital conversion and obtaining a digital signal sequence.The data processing module is used for inputting the digital signal sequence into a parallel delay memory unit processor to perform information interaction, obtaining a processed digital signal sequence, and taking the processed digital signal sequence as a processing result.The technical problems of poor common-mode interference suppression capability of a signal conditioning link, insufficient long-term memory capability for processing nonlinear dynamic acoustic signals, and high computing power consumption in the prior art are solved, and the technical effects of improving the signal-to-noise ratio of the system, the nonlinear signal feature extraction precision, and the processing energy efficiency ratio are achieved.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and more specifically to a low-power, high signal-to-noise ratio signal processing system based on data processing. Background Technology

[0002] In the field of acoustic signal processing, especially in applications such as speech recognition, underwater acoustic detection, industrial equipment condition monitoring, and medical auscultation, acquiring raw signals with high signal-to-noise ratio and low distortion is a prerequisite for accurate analysis and judgment. However, the actual acquisition environment is often accompanied by adverse factors such as strong background noise, electromagnetic interference, and multipath reflection, which pose a significant challenge to the extraction of weak acoustic signals. Traditional signal processing systems typically employ single-ended signal links and simple filtering structures, which are prone to introducing common-mode noise and are sensitive to power supply ripple and ground noise, limiting the improvement of the system's signal-to-noise ratio. Furthermore, the cascaded design of fixed-gain amplifiers and filters, if lacking systematic optimization, can easily lead to compression of the signal's dynamic range or loss of high-frequency information. With the increase in the sampling rate and resolution of analog-to-digital converters, data segmentation based on fixed time windows often struggles to simultaneously meet the requirements of time and frequency resolution in processing non-stationary acoustic signals (such as transient impact sounds or modulated sounds). In addition, finite impulse response filters, short-time Fourier transforms, or conventional recurrent neural networks face problems such as limited memory capacity, gradient vanishing, or excessive computational power consumption when processing acoustic signals with long-term dependencies or nonlinear dynamic characteristics. Existing research on the low-power implementation of Legendre polynomial basis memory units in parallel processing architectures, and its co-design with signal conditioning links, is still insufficient.

[0003] Therefore, current related technologies suffer from technical problems such as poor common-mode interference suppression capability in signal conditioning links, insufficient long-term memory capability and high computational power consumption when processing nonlinear dynamic acoustic signals. Summary of the Invention

[0004] This application provides a low-power, high signal-to-noise ratio signal processing system based on data processing, which solves the technical problems of poor common-mode interference suppression capability of the signal conditioning link, insufficient long-term memory capability and high computational power consumption in the prior art, thereby achieving the technical effect of improving the system's signal-to-noise ratio, the accuracy of nonlinear signal feature extraction and the processing energy efficiency ratio.

[0005] This application provides a low-power, high signal-to-noise ratio signal processing system based on data processing. The system includes: a conditioned analog signal output module, used to construct a fully differential signal conditioning link, through which the analog signal output from the acoustic sensor is amplified by a fixed gain and subjected to a three-stage cascaded low-pass filter to output a conditioned analog signal; a processing source data acquisition module, used to input the conditioned analog signal into an analog-to-digital converter for analog-to-digital conversion to obtain a digital signal sequence, and to segment the digital signal sequence according to a preset time window length to obtain multiple processing source data; and a data processing module, used to input the multiple processing source data into a parallel delayed memory unit processor containing Legendre memory units, adaptively adjust the state update path using a delay gating mechanism and perform data processing to obtain the processing result.

[0006] In a possible implementation, the digital signal sequence is input into a parallel delayed memory unit processor for data processing to obtain a processed digital signal sequence. This includes: traversing multiple processing source data and compressing it using the Legendre memory unit of the parallel delayed memory unit processor to obtain multiple window state vectors; acquiring multiple historical state queues, where each historical state queue stores multiple historical window state vectors of multiple time windows closest to the current time window; traversing the multiple window state vectors and inputting them, respectively, with the corresponding multiple historical state queues into a cross-scale interaction module to obtain multiple correspondence matrices; using the multiple correspondence matrices, weighting and fusing the historical information in the multiple historical state queues into the multiple window state vectors to obtain multiple processing window state vectors, concatenating them in chronological order, and outputting the processed digital signal sequence as the processing result.

[0007] In a possible implementation, multiple processing source data are traversed, and compressed using the Legendre memory unit of the parallel delayed memory unit processor to obtain multiple window state vectors. This includes: pre-setting the order of the Legendre polynomial, where the order is the dimension of the window state vector; mapping the sampling points within the time window corresponding to the multiple processing source data to a numerical range from negative one to positive one at equal intervals; calculating the Legendre polynomial values ​​of each order corresponding to the mapped value of each sampling point to obtain multiple basis matrices; multiplying the multiple basis matrices by the magnitude vectors of the sampling points within the time window corresponding to the multiple processing source data to obtain multiple initial window state vectors; and exponentially weighting and smoothing the multiple initial window state vectors with the window state vector output from the previous time window to obtain multiple window state vectors.

[0008] In a possible implementation, multiple window state vectors are traversed and input into the cross-scale interaction module with the multiple historical state queues respectively to obtain multiple correspondence matrices. This includes: traversing multiple window state vectors and performing inner product operations with each historical window state vector in the multiple historical state queues respectively to obtain multiple similarity groups; and performing normalization and matrix processing on the multiple similarity scores respectively to obtain multiple correspondence matrices.

[0009] In a possible implementation, the historical information in the multiple historical state queues is weighted and fused into multiple window state vectors using the multiple correspondence matrices to obtain multiple processing window state vectors. This includes: weighting and summing the multiple correspondence matrices with the multiple historical window state vectors of the multiple historical state queues to obtain multiple historical information fusion vectors; and calculating the mean of the multiple historical information fusion vectors with the multiple window state vectors to obtain multiple processing window state vectors.

[0010] In a possible implementation, the parallel delayed memory unit processor further includes a delay gating mechanism, comprising: calculating the ratio of short-time energy to long-time energy of the processing source data in the current time window to obtain the local activity intensity; when the local activity intensity is less than or equal to a first preset threshold, it is determined to be a low activity intensity, bypassing the state decay path, and directly copying all historical window state vectors in the historical state queue of the current time window to the next time window without decay; when the local activity intensity is greater than the first preset threshold, it is determined to be a high activity intensity, enabling the state decay path, removing the earliest historical window state vector in the historical state queue of the current time window, multiplying each remaining historical window state vector by a decay factor less than one, adding the window state vector of the current time window to the historical state queue, and completing the update of the historical state queue.

[0011] In a possible implementation, the fully differential signal conditioning link includes: a positive input coupling and biasing unit, including a first coupling capacitor CIN1, the first end of which is used to receive the single-ended input signal SIGNAL output by the acoustic sensor, and the second end of which is connected to the positive input terminal VIN+ of the fully differential amplifier U1 through a first resistor RG1, wherein the first resistor RG1 provides DC bias for the positive input terminal; and a negative input coupling and biasing unit, including a second coupling capacitor CIN2, the first end of which is grounded GND, and the second end of which is connected to the negative input terminal VIN- of the fully differential amplifier U1 through a second resistor RG2, wherein the second resistor RG2 provides DC bias for the negative input terminal; The circuit provides DC bias; the fully differential fixed gain amplifier unit includes a fully differential amplifier U1, whose inverting output terminal VOUT- is connected to the positive input terminal VIN+ through a first feedback network, and whose non-inverting output terminal VOUT+ is connected to the negative input terminal VIN- through a second feedback network; the output coupling unit includes a first output coupling capacitor COUT1 and a second output coupling capacitor COUT2, the first output coupling capacitor COUT1 is connected in series between the second terminal of the second feedback resistor RF2 and the first input terminal of the subsequent circuit, and the second output coupling capacitor COUT2 is connected in series between the second terminal of the fourth feedback resistor RF4 and the second input terminal of the subsequent circuit.

[0012] In a possible implementation, the low-power, high signal-to-noise ratio signal processing system based on data processing further includes: a first feedback network, comprising a first feedback capacitor CF1, a first feedback resistor RF1, and a second feedback resistor RF2. The first feedback capacitor CF1 is connected between the inverting output terminal VOUT- and the positive input terminal VIN+. The first terminal of the second feedback resistor RF2 is connected to the inverting output terminal VOUT-. The first feedback resistor RF1 is connected between the second terminal of the second feedback resistor RF2 and the positive input terminal VIN+. The inverting output terminal VOUT- is connected in series with a first grounding resistor through the second feedback resistor RF2. The capacitor C1 is grounded, forming a first-order low-pass filter; the second feedback network includes a second feedback capacitor CF2, a third feedback resistor RF3, and a fourth feedback resistor RF4. The second feedback capacitor CF2 is connected between the non-inverting output terminal VOUT+ and the negative input terminal VIN-. The first end of the fourth feedback resistor RF4 is connected to the non-inverting output terminal VOUT+. The third feedback resistor RF3 is connected between the second end of the fourth feedback resistor RF4 and the negative input terminal VIN-. The non-inverting output terminal VOUT+ is grounded through the fourth feedback resistor RF4 connected in series with the second grounding capacitor C2, forming a second first-order low-pass filter.

[0013] In a possible implementation, the low-power, high signal-to-noise ratio signal processing system based on data processing further includes: a first second-order multi-feedback low-pass filter consisting of a first feedback capacitor CF1, a first feedback resistor RF1, a second feedback resistor RF2, and a first resistor RG1, wherein the first second-order multi-feedback low-pass filter is cascaded with a first first-order low-pass filter to form a first third-order low-pass filter characteristic; and a second second-order multi-feedback low-pass filter consisting of a second feedback capacitor CF2, a third feedback resistor RF3, a fourth feedback resistor RF4, and a second resistor RG2, wherein the second second-order multi-feedback low-pass filter is cascaded with a second first-order low-pass filter to form a second third-order low-pass filter characteristic.

[0014] In a possible implementation, the low-power, high signal-to-noise ratio signal processing system based on data processing further includes: a first high-pass filter formed by the first coupling capacitor CIN1, the first resistor RG1, and the input impedance of the positive input terminal of the fully differential amplifier U1; a second high-pass filter formed by the second coupling capacitor CIN2, the second resistor RG2, and the input impedance of the negative input terminal of the fully differential amplifier U1; a third high-pass filter formed by the first output coupling capacitor COUT1 and the input impedance of the first input terminal of the analog-to-digital converter U2; and a fourth high-pass filter formed by the second output coupling capacitor COUT2 and the input impedance of the second input terminal of the analog-to-digital converter U2; wherein the first high-pass filter and the third high-pass filter together determine the low-frequency cutoff frequency of the positive input terminal path, and the second high-pass filter and the fourth high-pass filter together determine the low-frequency cutoff frequency of the negative input terminal path.

[0015] This application proposes a low-power, high signal-to-noise ratio (SNR) signal processing system based on data processing. The system comprises a conditioned analog signal output module, used to construct a fully differential signal conditioning link, which performs fixed-gain amplification and three-stage cascaded low-pass filtering on the analog signal output from the acoustic sensor to output a conditioned analog signal; a source data acquisition module, used to perform analog-to-digital conversion to obtain a digital signal sequence; and a data processing module, used to input the digital signal sequence into a parallel delayed memory unit processor for information interaction, obtaining a processed digital signal sequence as the processing result. This system solves the technical problems of poor common-mode interference suppression capability in signal conditioning links, insufficient long-term memory capacity for processing nonlinear dynamic acoustic signals, and high computational power consumption in existing technologies. It achieves the technical effects of improving the system's SNR, the accuracy of nonlinear signal feature extraction, and the processing energy efficiency ratio. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments of this disclosure will be briefly described below. Flowcharts are used in this application to illustrate the operations performed by the system according to the embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed precisely in sequence. Instead, various steps can be processed in reverse order or simultaneously as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0017] Figure 1 This is a schematic diagram of a low-power, high signal-to-noise ratio signal processing system based on data processing, provided in an embodiment of this application.

[0018] Figure 2 This is an overall block diagram of the signal conditioning circuit in a low-power, high signal-to-noise ratio acoustic signal processing system based on a fully differential structure, as provided in an embodiment of this application.

[0019] Figure 3 The following is a detailed circuit diagram of a fully differential amplifier in a low-power, high signal-to-noise ratio acoustic signal processing system based on a fully differential structure, as provided in the embodiments of this application.

[0020] Explanation of reference numerals in the attached figures: Conditioned analog signal output module 10, source data acquisition module 20, data processing module 30, first coupling capacitor CIN1, second coupling capacitor CIN2, first resistor RG1, second resistor RG2, fully differential amplifier U1, analog-to-digital converter U2, first feedback resistor RF1, second feedback resistor RF2, third feedback resistor RF3, fourth feedback resistor RF4, first feedback capacitor CF1, second feedback capacitor CF2, first grounding capacitor C1, second grounding capacitor C2, first output coupling capacitor COUT1, second output coupling capacitor COUT2. Detailed Implementation

[0021] To further illustrate the technical means and effects adopted by the present invention in order to achieve the intended purpose, the following detailed description is provided in conjunction with the accompanying drawings and preferred embodiments, based on the specific implementation methods, structures, features and effects of the present invention.

[0022] This application provides a low-power, high signal-to-noise ratio (SNR) signal processing system based on data processing. This low-power, high SNR acoustic signal processing system is applied to a corresponding signal conditioning circuit, such as... Figure 1 As shown, the system includes: The conditioned analog signal output module 10 is used to construct a fully differential signal conditioning link. The fully differential signal conditioning link amplifies the analog signal output by the acoustic sensor with fixed gain and performs a three-stage cascaded low-pass filtering to output the conditioned analog signal.

[0023] Preferred, such as Figure 2, 3 As shown, the fully differential signal conditioning link is an analog signal processing module completed collaboratively by multiple circuit units. Specifically, it is the signal conditioning circuit. The conditioned analog signal output module 10 is an analog front-end circuit module based on a fully differential amplifier, with fixed gain and integrated three-stage cascaded low-pass filtering function. It receives the weak single-ended analog signal from the acoustic sensor and outputs a differential analog signal that has been amplified and filtered, suitable for driving the analog-to-digital converter. Specifically, the fully differential signal conditioning link includes positive and negative input coupling and biasing units and a fully differential fixed-gain amplification unit. The core component is the fully differential amplifier, which is used to convert the single-ended signal that may be input from the acoustic sensor into a differential signal. The differential structure can effectively cancel common-mode noise, such as power frequency interference. The fixed-gain amplification refers to the closed-loop gain determined by the fully differential amplifier and its feedback network, which is used to convert the weak acoustic sensor signal (such as m) into a differential signal. The voltage is amplified to a suitable input voltage range for the analog-to-digital converter U2 (V-level). The three-stage cascaded low-pass filter is implemented by cascading two filters, including a second-order multi-feedback low-pass filter and a first-order low-pass filter. The second-order multi-feedback low-pass filter is a circuit network composed of a first feedback capacitor CF1, a first feedback resistor RF1, a second feedback resistor RF2, and a first resistor RG1, which is a typical multi-feedback (MFB) topology. The first-order low-pass filter is an RC filter network composed of a second feedback resistor RF2 and a first ground capacitor C1, which provides an additional -20dB / decathlon roll-off characteristic. Cascading the two filters forms a third-order low-pass filter with a total roll-off slope of -60dB / decathlon, which can effectively filter out high-frequency noise above the Nyquist frequency (half of the sampling rate of 20kHz, i.e., 10kHz) and prevent signal aliasing. Finally, the amplified, filtered, and conditioned analog signal converted to differential form is output from the fully differential fixed-gain amplifier unit and sent to the analog-to-digital converter U2 through the output coupling unit.

[0024] Furthermore, the fully differential signal conditioning link includes: a positive input coupling and biasing unit, including a first coupling capacitor CIN1, the first end of which is used to receive the single-ended input signal SIGNAL output by the acoustic sensor, and the second end of which is connected to the positive input terminal VIN+ of the fully differential amplifier U1 through a first resistor RG1, wherein the first resistor RG1 provides DC bias for the positive input terminal; and a negative input coupling and biasing unit, including a second coupling capacitor CIN2, the first end of which is grounded GND, and the second end of which is connected to the negative input terminal VIN- of the fully differential amplifier U1 through a second resistor RG2, wherein the second resistor RG2 provides DC bias for the negative input terminal. DC bias; a fully differential fixed-gain amplifier unit, including a fully differential amplifier U1, whose inverting output terminal VOUT- is connected to the positive input terminal VIN+ through a first feedback network, and whose non-inverting output terminal VOUT+ is connected to the negative input terminal VIN- through a second feedback network; an output coupling unit, including a first output coupling capacitor COUT1 and a second output coupling capacitor COUT2, the first output coupling capacitor COUT1 being connected in series between the second terminal of the second feedback resistor RF2 and the first input terminal of the subsequent circuit, and the second output coupling capacitor COUT2 being connected in series between the second terminal of the fourth feedback resistor RF4 and the second input terminal of the subsequent circuit.

[0025] Furthermore, the fully differential signal conditioning link also includes a first feedback network, comprising a first feedback capacitor CF1, a first feedback resistor RF1, and a second feedback resistor RF2. The first feedback capacitor CF1 is connected between the inverting output terminal VOUT- and the positive input terminal VIN+. The first end of the second feedback resistor RF2 is connected to the inverting output terminal VOUT-, and the first feedback resistor RF1 is connected between the second end of the second feedback resistor RF2 and the positive input terminal VIN+. The inverting output terminal VOUT- is grounded through the second feedback resistor RF2 connected in series with a first grounding capacitor C1, forming the first... A first-order low-pass filter; the second feedback network includes a second feedback capacitor CF2, a third feedback resistor RF3, and a fourth feedback resistor RF4. The second feedback capacitor CF2 is connected between the non-inverting output terminal VOUT+ and the negative input terminal VIN-. The first end of the fourth feedback resistor RF4 is connected to the non-inverting output terminal VOUT+. The third feedback resistor RF3 is connected between the second end of the fourth feedback resistor RF4 and the negative input terminal VIN-. The non-inverting output terminal VOUT+ is grounded through the fourth feedback resistor RF4 connected in series with a second grounding capacitor C2, thus forming a second first-order low-pass filter.

[0026] Furthermore, the fully differential signal conditioning link further includes: the first feedback capacitor CF1, the first feedback resistor RF1, the second feedback resistor RF2, and the first resistor RG1 forming a first second-order multi-feedback low-pass filter, wherein the first second-order multi-feedback low-pass filter is cascaded with the first first-order low-pass filter to form a first third-order low-pass filter characteristic; the second feedback capacitor CF2, the third feedback resistor RF3, the fourth feedback resistor RF4, and the second resistor RG2 forming a second second-order multi-feedback low-pass filter, wherein the second second-order multi-feedback low-pass filter is cascaded with the second first-order low-pass filter to form a second third-order low-pass filter characteristic.

[0027] Furthermore, the fully differential signal conditioning link also includes an input coupling unit, wherein the first coupling capacitor CIN1, the first resistor RG1, and the input impedance of the positive input terminal of the fully differential amplifier U1 together constitute a first high-pass filter; the second coupling capacitor CIN2, the second resistor RG2, and the input impedance of the negative input terminal of the fully differential amplifier U1 together constitute a second high-pass filter; and an output coupling unit, wherein the first output coupling capacitor COUT1 and the input impedance of the first input terminal of the analog-to-digital converter U2 together constitute a third high-pass filter; and the second output coupling capacitor COUT2 and the input impedance of the second input terminal of the analog-to-digital converter U2 together constitute a fourth high-pass filter; wherein the first high-pass filter and the third high-pass filter together determine the low-frequency cutoff frequency of the positive input terminal path, and the second high-pass filter and the fourth high-pass filter together determine the low-frequency cutoff frequency of the negative input terminal path.

[0028] Furthermore, the fully differential signal conditioning link also includes an analog-to-digital converter (ADC), comprising a 32-bit audio ADC, whose differential input terminals are respectively connected to the back ends of the first output coupling capacitor COUT1 and the second output coupling capacitor COUT2, and the sampling rate is set to 20kHz, used to convert analog signals into digital signals; the digital output terminal of the ADC is used to connect to an external processor.

[0029] Preferably, the first high-pass filter and the third high-pass filter together determine the low-frequency cutoff frequency, and the first third-order low-pass filter determines the high-frequency cutoff frequency, forming an overall bandpass response with a passband range of 10Hz to 5kHz. Similarly, the second high-pass filter, the fourth high-pass filter, and the second and third-order low-pass filters also form the same characteristics, thereby realizing the passband processing of the fully differential signal and suppressing power frequency interference without the need for a dedicated power frequency notch circuit. The capacitance values ​​of the first coupling capacitor CIN1 and the second coupling capacitor CIN2 are 0.1μF~10μF; the capacitance values ​​of the first output coupling capacitor COUT1 and the second output coupling capacitor COUT2 are 0.1μF~10μF; the resistance values ​​of the first resistor RG1 and the second resistor RG2 are 1kΩ~100kΩ; the resistance values ​​of the first feedback resistor RF1, the second feedback resistor RF2, the third feedback resistor RF3, and the fourth feedback resistor RF4 are 1kΩ~100kΩ; the capacitance values ​​of the first feedback capacitor CF1 and the second feedback capacitor CF2 are 10pF~1000pF; the capacitance values ​​of the first ground capacitor C1 and the second ground capacitor C2 are 10pF~1000pF; the transfer function of the second-order multi-feedback low-pass filter is:

[0030] By selecting the values ​​of resistors and capacitors, the quality factor Q of the second-order multi-feedback low-pass filter is made to be 0.5~1.0, and the natural frequency fn is made to be 5kHz~10kHz. These are the polynomial coefficients.

[0031] Preferably, the first-order low-pass filter consists of a second feedback resistor RF2 and a first grounding capacitor C1. Its cutoff frequency is higher than that of the second-order multi-feedback low-pass filter. After cascading, the overall -3dB cutoff frequency is designed to be 8kHz ± 1kHz, the passband gain flatness is less than ±0.5dB, and the stopband attenuation is greater than 60dB / decade to match the anti-aliasing requirements of a 20kHz sampling rate. The fully differential amplifier U1 is a THS4531 fully differential amplifier with a quiescent current of less than 500μA and a gain bandwidth of greater than 10MHz. The 32-bit audio ADC is a low-power audio analog-to-digital converter with a power consumption of less than 5mW at a 20kHz sampling rate. The low-power, high signal-to-noise ratio acoustic signal processing system includes four parallel signal conditioning circuits, forming a four-channel signal acquisition system. The total power consumption of the four-channel signal acquisition system is less than 1.65W, the equivalent input noise is less than 8µVrms, and the signal-to-noise ratio is greater than 85dB. Each channel has a sampling rate of 20kHz, a passband of 10Hz~5kHz, and a filter cutoff frequency of 8kHz.

[0032] Preferably, the signal conditioning circuit is connected as follows: Positive input path: SIGNAL (1Vpp) is connected to VIN+ of U1 via CIN1=1μF and RG1=1kΩ; VOUT- of U1 is connected to VIN+ via CF1=100pF, and VOUT- is connected to VIN+ via RF2=5kΩ and RF1=5kΩ in series; VOUT- is also grounded via RF2=5kΩ in series with C1=1nF; VOUT- is connected to ADC- via RF2=5kΩ in series with COUT1=1μF.

[0033] Negative input path: GND is connected to VIN- of U1 via CIN2=1μF and RG2=1kΩ; VOUT+ of U1 is connected to VIN- via CF2=100pF, and VOUT+ is connected to VIN- via RF4=5kΩ and RF3=5kΩ in series; VOUT+ is also grounded via RF4=5kΩ in series with C2=1nF; VOUT+ is connected to ADC+ via RF4=5kΩ in series with COUT2=1μF.

[0034] Analog-to-digital converter: U2 model PCM1808, differential input terminals connected to the back end of COUT1 and COUT2, sampling rate set to 20kHz by an external clock, output digital signal for use by an external processor via I2S interface. It has a single-channel power consumption of 0.4W, equivalent input noise of 10µVrms, signal-to-noise ratio of 85dB, gain flatness of ±0.3dB within the passband of 10Hz~5kHz, and no significant interference in a 50Hz power frequency environment.

[0035] Preferably, four signal conditioning circuits are connected in parallel, sharing the same clock source and power management module. The power management uses a low-ripple LDO to provide independent power to each channel, and a buffer is used for clock distribution to ensure synchronization. When all four channels are working simultaneously, the total power consumption is 1.6W, the crosstalk between channels is less than -90dB, and the synchronization error is <1μs. The overall performance meets the design requirements. While maintaining the overall bandpass characteristics, the coupling capacitors CIN1, CIN2, COUT1, and COUT2 can be changed to 0.47μF, the feedback resistors RF1=10kΩ, RF2=10kΩ, CF1=47pF, and C1=470pF (symmetrically identical). Simulation and actual measurements still achieve a 10Hz~5kHz passband and an 8kHz cutoff frequency, with a slight change in power consumption, but still lower than the total power consumption of 1.65W for the four channels.

[0036] The source data acquisition module 20 is used to input the conditioned analog signal into the analog-to-digital converter U2 for analog-to-digital conversion to obtain a digital signal sequence, and to divide the digital signal sequence into multiple source data according to a preset time window length to obtain multiple source data.

[0037] Preferably, the core of the source data acquisition module 20 is an analog-to-digital converter (ADC), which converts the conditioned analog signal generated by the conditioned analog signal output module 10 into a discrete digital signal sequence. Its main component is the ADC U2, preferably a 32-bit audio ADC with a sampling rate set to 20kHz. Its two differential input terminals are connected to the two output signals from the pre-amplifier. The ADC+ terminal is connected through the second output coupling capacitor COUT2, and the ADC- terminal is connected through the first output coupling capacitor COUT1. The differential connection preserves the high signal-to-noise ratio advantage of the fully differential circuit to the greatest extent. Specifically, at a fixed rate of 20kHz, the continuously changing analog signal voltage value is captured instantaneously. Each captured voltage value is assigned to one of the many quantization levels with 32-bit precision and given a digital code. Then, it is organized into a sequence according to a specific format (such as the I2S bus format) to obtain a digital signal sequence, which directly determines the upper limit of the signal-to-noise ratio that the entire system can achieve and the highest frequency of the signal that can be processed. By pre-setting the time window length, such as 256 sampling points or 512 sampling points, the continuous digital signal sequence is divided into multiple non-overlapping segments, thereby transforming the infinitely long continuous signal stream into finite-length independent processing units, obtaining multiple processing source data, that is, digital signal subsequences within each time window, the number of which depends on the original sequence length ÷ window length.

[0038] The data processing module 30 is used to input the multiple processing source data into a parallel delayed memory unit processor containing Legendre memory units, adaptively adjust the state update path using a delay gating mechanism, and perform data processing to obtain the processing result.

[0039] Preferably, the core of the data processing module 30 is a parallel delayed memory unit processor, which is essentially a specially designed digital signal processing algorithm or hardware accelerator. It is used to perform time series modeling, feature enhancement and information interaction on the original digital signal sequence output by the front-end analog-to-digital converter, and finally output a "cleaner" and more informative processed digital signal sequence as the final processing result. Specifically, it is executed by a digital signal processor, a field-programmable gate array or an application-specific integrated circuit.

[0040] Furthermore, the specific configuration of the data processing module 30 also includes: traversing multiple processing source data, compressing it through the Legendre memory unit of the parallel delayed memory unit processor to obtain multiple window state vectors; acquiring multiple historical state queues, wherein each of the multiple historical state queues stores multiple historical window state vectors of the multiple time windows closest to the current time window; traversing the multiple window state vectors, inputting them into the cross-scale interaction module with the corresponding multiple historical state queues to obtain multiple correspondence matrices; using the multiple correspondence matrices, weighting and fusing the historical information in the multiple historical state queues into the multiple window state vectors to obtain multiple processing window state vectors, concatenating them in chronological order, and outputting the processed digital signal sequence as the processing result.

[0041] Preferably, the continuous digital signal sequence of the ADC is used as input, such as a series of voltage digital values ​​arranged at a sampling rate of 20kHz. This data is divided into multiple non-overlapping processing source data, for example, each window containing 256 sampling points. A parallel delayed memory unit processor traverses these multiple processing source data and compresses them using a Legendre memory unit to obtain multiple window state vectors. The Legendre memory unit is a feature extractor based on Legendre polynomials. Multiple historical state queues are retrieved from the buffer. Each historical state queue stores multiple historical window state vectors from the multiple time windows closest to the current time window, for example, storing the state vectors of the last 10 windows. The process involves: first, traversing multiple window state vectors and inputting them into the cross-scale interaction module along with their corresponding historical state queues; comparing each segment in the "current segment" and the "historical segment library"; performing an inner product operation between the current window state vector and each historical vector to determine the similarity score; normalizing the similarity score using the softmax function; and then constructing multiple correspondence matrices using the similarity scores. These correspondence matrices are then used as weights to perform a weighted summation of the historical information in the multiple historical state queues, resulting in a historical information fusion vector that is merged with the current window state vector (e.g., by calculating the mean). This yields multiple processing window state vectors. Finally, all enhanced window features are reassembled in their original chronological order, outputting a complete processed digital signal sequence as the processing result.

[0042] Furthermore, the specific configuration of the data processing module 30 also includes: pre-setting the order of the Legendre polynomial, where the order is the dimension of the window state vector; mapping the sampling points within the time window corresponding to the multiple processing source data to a numerical range from negative one to positive one at equal intervals; calculating the Legendre polynomial values ​​of each order corresponding to the mapped value of each sampling point to obtain multiple basis matrices; multiplying the multiple basis matrices by the magnitude vectors of the sampling points within the time window corresponding to the multiple processing source data to obtain multiple initial window state vectors; and performing exponential weighted smoothing on the multiple initial window state vectors and the window state vector output by the previous time window to obtain multiple window state vectors.

[0043] Preferably, multiple sampling points within a time window are projected and transformed using Legendre polynomial basis functions to compress them into a low-dimensional window state vector. Exponential weighted smoothing is introduced to enhance temporal continuity. Specifically, the Legendre polynomial is a set of orthogonal basis functions in the interval [-1, 1]. The order of the Legendre polynomial is pre-set, using the first K orders, typically starting from order 0. The dimension of the window state vector is equal to K+1. Higher orders result in stronger expressive power of the feature vector, but also greater computational complexity. Multiple processing source data corresponding to... The sampling points within the time window are mapped at equal intervals to the numerical range from negative one to positive one, thereby matching the time coordinates with the domain [-1, 1] of the Legendre polynomial. The mapped coordinates of each sampling point are input, and the Legendre polynomial values ​​of each order corresponding to the mapped values ​​of each sampling point are calculated to obtain multiple basis matrices of size L×(K+1). Finally, the multiple basis matrices are multiplied by the amplitude vectors of the sampling points within the time window corresponding to the multiple processing source data to obtain the initial window state vector, transforming the time-domain signal into the space spanned by the Legendre orthogonal basis, thus achieving dimensionality reduction and compression.

[0044] Furthermore, the specific configuration of the data processing module 30 also includes traversing multiple window state vectors and performing inner product operations with each historical window state vector in multiple historical state queues to obtain multiple similarity groups; and performing normalization and matrix processing on multiple similarity scores to obtain multiple correspondence matrices.

[0045] Preferably, multiple window state vectors are traversed, and each is subjected to an inner product operation with the state vector of each historical window in multiple historical state queues to obtain multiple similarity groups. Each similarity group contains multiple similarity scores. The larger the inner product value, the more consistent the direction of the current window and the historical window in the state space, i.e., the stronger the correlation. Then, the multiple similarity scores are normalized by Softmax to determine the corresponding weights. All weight values ​​are in the interval (0, 1). Softmax converts the similarity scores into a standard probability distribution. The higher the similarity of the historical window, the closer the weight is to 1, and the lower the similarity, the closer the weight is to 0. Next, matrix processing is performed to arrange the weight values ​​into a matrix form to obtain multiple correspondence matrices, which represent the strength of the correspondence between the current window and each historical window.

[0046] Furthermore, the specific configuration of the data processing module 30 also includes: weighting and summing the multiple correspondence matrices with the multiple historical window state vectors of the multiple historical state queues to obtain multiple historical information fusion vectors; and calculating the mean of the multiple historical information fusion vectors with the multiple window state vectors to obtain multiple processing window state vectors.

[0047] Preferably, the historical state queue is weighted and summed using the weights in multiple correspondence matrices to obtain a historical information fusion vector, which represents the most relevant historical context. Among them, historical windows with high relevance contribute more information, while those with low relevance contribute less. The historical information fusion vector is then averaged with multiple window state vectors to generate an enhanced processing window state vector, which contains the features of the current window and incorporates the historical context, thus having a stronger information expression capability.

[0048] Furthermore, the specific configuration of the data processing module 30 also includes a delay gating mechanism, which includes calculating the ratio of short-time energy to long-time energy of the source data to be processed in the current time window to obtain the local activity intensity; when the local activity intensity is less than or equal to a first preset threshold, it is determined to be a low activity intensity, bypassing the state decay path, and directly copying all historical window state vectors in the historical state queue of the current time window to the next time window without decay; when the local activity intensity is greater than the first preset threshold, it is determined to be a high activity intensity, enabling the state decay path, removing the earliest historical window state vector in the historical state queue of the current time window, multiplying each remaining historical window state vector by a decay factor less than one, adding the window state vector of the current time window to the historical state queue, and completing the update of the historical state queue.

[0049] Preferably, the delay gating mechanism is an adaptive control unit in the parallel delayed memory unit processor, used to dynamically manage the update strategy of the historical state queue to improve computational efficiency and adapt to different signal activity intensities. It determines the local activity intensity of the signal by calculating the ratio of the short-time energy to the long-time energy of the currently processed source data, and selects different historical state queue update strategies based on the activity intensity. Specifically, it calculates the ratio of the short-time energy to the long-time energy of the processed source data in the current time window, outputs the local activity intensity, and a ratio greater than 1 indicates that the current signal is stronger than usual, while a ratio less than 1 indicates that the current signal is weaker than usual; if the local activity intensity is less than... If the activity level equals a first preset threshold (e.g., 1.5), it is considered low activity intensity. The state decay path is bypassed, and all historical window state vectors in the current time window's historical state queue are directly copied to the next time window without modification, multiplying the historical vectors by a decay factor, or removing any historical vectors. If the local activity intensity exceeds the first preset threshold, it is considered high activity intensity. The state decay path is then activated. The first historical window state vector in the current time window's historical state queue is removed, each remaining historical vector in the queue is multiplied by a decay factor, and the current window state vector is added to the end of the queue, outputting the updated historical state queue. This ensures that the update strategy is adaptively adjusted according to the dynamic characteristics of the input signal, maintaining memory stability during stable periods and rapidly updating memory during changes, thereby improving processing efficiency and enhancing the ability to respond to signal mutations.

[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A low-power, high signal-to-noise ratio signal processing system based on data processing, characterized in that, include: The conditioned analog signal output module is used to construct a fully differential signal conditioning link. The fully differential signal conditioning link amplifies the analog signal output by the acoustic sensor with fixed gain and performs a three-stage cascaded low-pass filtering to output the conditioned analog signal. The digital signal sequence acquisition module is used to input the conditioned analog signal into the analog-to-digital converter for analog-to-digital conversion to obtain a digital signal sequence, and to segment the digital signal sequence according to a preset time window length to obtain multiple processing source data; The data processing module is used to input the multiple processing source data into a parallel delayed memory unit processor containing Legendre memory units, adaptively adjust the state update path using a delay gating mechanism, and perform data processing to obtain the processing result.

2. The low-power, high signal-to-noise ratio signal processing system based on data processing as described in claim 1, characterized in that, The data processing module performs the following steps: Multiple processing source data are traversed and compressed through the Legendre memory unit of the parallel delayed memory unit processor to obtain multiple window state vectors; Obtain multiple historical state queues, where each historical state queue stores multiple historical window state vectors of the multiple time windows closest to the current time window; By traversing multiple window state vectors and inputting them into the cross-scale interaction module with the corresponding multiple historical state queues, multiple corresponding relationship matrices are obtained. Using the multiple correspondence matrices, the historical information in the multiple historical state queues is weighted and fused into multiple window state vectors to obtain multiple processing window state vectors. After being concatenated in chronological order, the processed digital signal sequence is output as the processing result.

3. The low-power, high signal-to-noise ratio signal processing system based on data processing as described in claim 2, characterized in that, The data processing module further includes the following steps: The order of the Legendre polynomial is pre-defined, where the order is the dimension of the window state vector; The sampling points within the time window corresponding to multiple processing source data are mapped at equal intervals to the numerical range from negative one to positive one. Calculate the Legendre polynomial values ​​of each order corresponding to the mapped values ​​of each sampling point to obtain multiple basis matrices; Multiple basis matrices are multiplied by the magnitude vectors of the sampling points within the time windows corresponding to the multiple processing source data to obtain multiple initial window state vectors; The multiple initial window state vectors are exponentially weighted and smoothed with the window state vector output from the previous time window to obtain multiple window state vectors.

4. The low-power, high signal-to-noise ratio signal processing system based on data processing as described in claim 2, characterized in that, The data processing module further includes the following steps: By iterating through multiple window state vectors and performing inner product operations with each historical window state vector in multiple historical state queues, multiple similarity groups are obtained. Multiple similarity scores are normalized and matrixed to obtain multiple correspondence matrices.

5. The low-power, high signal-to-noise ratio signal processing system based on data processing as described in claim 4, characterized in that, The data processing module further includes the following steps: The multiple correspondence matrices are weighted and summed with the multiple historical window state vectors of multiple historical state queues to obtain multiple historical information fusion vectors; The average of the multiple historical information fusion vectors and multiple window state vectors is calculated to obtain multiple processing window state vectors.

6. The low-power, high signal-to-noise ratio signal processing system based on data processing as described in claim 2, characterized in that, The data processing module further includes the following steps: Calculate the ratio of short-time energy to long-time energy of the source data being processed within the current time window to obtain the local activity intensity; When the intensity of the local activity is less than or equal to the first preset threshold, the state decay path is bypassed, and all historical window state vectors in the historical state queue of the current time window are directly copied to the next time window without decay. When the intensity of the local activity exceeds a first preset threshold, the state decay path is activated, the earliest historical window state vector in the historical state queue of the current time window is removed, and each remaining historical window state vector is multiplied by a decay factor less than one. The window state vector of the current time window is then added to the historical state queue, thus completing the update of the historical state queue.

7. The low-power, high signal-to-noise ratio signal processing system based on data processing as described in claim 1, characterized in that, The fully differential signal conditioning link includes: The positive input coupling and bias unit includes a first coupling capacitor CIN1, the first end of which is used to receive the single-ended input signal SIGNAL output by the acoustic sensor, and the second end of which is connected to the positive input terminal VIN+ of the fully differential amplifier U1 through a first resistor RG1, wherein the first resistor RG1 provides DC bias for the positive input terminal. The negative input coupling and biasing unit includes a second coupling capacitor CIN2, the first end of which is grounded to GND, and the second end of which is connected to the negative input terminal VIN- of the fully differential amplifier U1 through a second resistor RG2, wherein the second resistor RG2 provides DC bias for the negative input terminal; The fully differential fixed gain amplifier unit includes a fully differential amplifier U1, whose inverting output terminal VOUT- is connected to the positive input terminal VIN+ through a first feedback network, and whose non-inverting output terminal VOUT+ is connected to the negative input terminal VIN- through a second feedback network. The output coupling unit includes a first output coupling capacitor COUT1 and a second output coupling capacitor COUT2. The first output coupling capacitor COUT1 is connected in series between the second end of the second feedback resistor RF2 and the first input terminal of the subsequent circuit. The second output coupling capacitor COUT2 is connected in series between the second end of the fourth feedback resistor RF4 and the second input terminal of the subsequent circuit.

8. The low-power, high signal-to-noise ratio signal processing system based on data processing as described in claim 7, characterized in that, Also includes: The first feedback network includes a first feedback capacitor CF1, a first feedback resistor RF1, and a second feedback resistor RF2. The first feedback capacitor CF1 is connected between the inverting output terminal VOUT- and the positive input terminal VIN+. The first end of the second feedback resistor RF2 is connected to the inverting output terminal VOUT-. The first feedback resistor RF1 is connected between the second end of the second feedback resistor RF2 and the positive input terminal VIN+. The inverting output terminal VOUT- is grounded through the second feedback resistor RF2 connected in series with the first grounding capacitor C1, thus forming a first first-order low-pass filter. The second feedback network includes a second feedback capacitor CF2, a third feedback resistor RF3, and a fourth feedback resistor RF4. The second feedback capacitor CF2 is connected between the non-inverting output terminal VOUT+ and the negative input terminal VIN-. The first end of the fourth feedback resistor RF4 is connected to the non-inverting output terminal VOUT+. The third feedback resistor RF3 is connected between the second end of the fourth feedback resistor RF4 and the negative input terminal VIN-. The non-inverting output terminal VOUT+ is grounded through the fourth feedback resistor RF4 connected in series with the second grounding capacitor C2, thus forming a second first-order low-pass filter.

9. The low-power, high signal-to-noise ratio signal processing system based on data processing as described in claim 8, characterized in that, Also includes: The first feedback capacitor CF1, the first feedback resistor RF1, the second feedback resistor RF2 and the first resistor RG1 constitute a first second-order multi-feedback low-pass filter, wherein the first second-order multi-feedback low-pass filter is cascaded with the first first-order low-pass filter to form a first third-order low-pass filter characteristic. The second feedback capacitor CF2, the third feedback resistor RF3, the fourth feedback resistor RF4, and the second resistor RG2 constitute a second second-order multi-feedback low-pass filter. The second second-order multi-feedback low-pass filter is cascaded with the second first-order low-pass filter to form a second third-order low-pass filter characteristic.

10. The low-power, high signal-to-noise ratio signal processing system based on data processing as described in claim 9, characterized in that, The first coupling capacitor CIN1, together with the first resistor RG1 and the input impedance of the positive input terminal of the fully differential amplifier U1, constitute the first high-pass filter; The second coupling capacitor CIN2, together with the second resistor RG2 and the input impedance of the negative input terminal of the fully differential amplifier U1, constitute the second high-pass filter; The first output coupling capacitor COUT1 and the input impedance of the first input terminal of the analog-to-digital converter U2 together constitute the third high-pass filter; The second output coupling capacitor COUT2 and the input impedance of the second input terminal of the analog-to-digital converter U2 together constitute the fourth high-pass filter; The first high-pass filter and the third high-pass filter together determine the low-frequency cutoff frequency of the positive input path, and the second high-pass filter and the fourth high-pass filter together determine the low-frequency cutoff frequency of the negative input path.

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