A method for shared-seed floating-point function computation and a processor

Abstract

The application discloses a shared seed floating point function calculation method and a processor, belongs to the field of vector floating point processors and AI accelerators, and realizes reciprocal, reciprocal square root and square root function operations. The application adopts a shared channel to complete floating point classification, normalization and index parity adjustment of FP32 input; generates an iteration initial seed through segmented linear fitting, and reuses a processor original FP32 fusion multiplication and addition unit to execute Newton iteration, and the square root reuses an iteration intermediate result of the reciprocal square root. After index reconstruction and special value multi-path selection, only one FP32 to BF16 nearest rounding output is executed at the end; a double source vector result can be spliced into a full bit width BF16 destination vector in a vector mode. The application has high hardware reuse degree, reduces chip cost, eliminates intermediate format conversion loss, and is suitable for large model inference acceleration.

Description

Technical Field

[0001] This application relates to the fields of floating-point processors, vector operations, and artificial intelligence accelerators, and in particular to a floating-point function calculation method and processor with a shared seed. Background Technology

[0002] Reciprocal (RECIP), reciprocal square root (RSQRT), and square root (SQRT) are fundamental special functions of vector floating-point processors and AI accelerators, widely used in Softmax, Sigmoid, SiLU, RMSNorm, LayerNorm normalization, statistical operations, and distance calculations. In large model inference scenarios, strictly precise rounding of FP32 results is generally not required, but it is necessary to ensure that the FP32 input is not truncated prematurely to maintain the numerical stability of the BF16 output.

[0003] Software implementations relying on division or math libraries for computation consume significant instruction and register bandwidth, resulting in substantial computational latency. On the hardware side, setting up separate arithmetic units for RECIP, RSQRT, and SQRT involves redundant configuration of circuits for floating-point classification, normalization, exponent processing, and special value judgment, leading to higher chip area, power consumption, and verification costs. A lookup table approach combined with multi-order polynomial approximation requires large-capacity coefficient storage and multiplexers, resulting in higher hardware overhead.

[0004] Newton-Raphson iteration and table lookup for generating initial seeds are well-known numerical methods in the field. Some existing solutions disclose the instruction semantics of BF16 square root and reciprocal square root, but do not disclose the complete seed-iteration hardware path, nor do they implement a shared front-end for the three types of functions; some architectures require outputting intermediate FP32 results first, and then performing independent instruction conversion to obtain BF16, which brings register relocation and scheduling overhead.

[0005] Therefore, existing technologies lack a hardware architecture that can share the hardware front-end and back-end to support RECIP, RSQRT, and SQRT functions, use segmented seeds to generate initial values ​​for iteration, reuse the processor's inherent FP32 fused multiply-accumulate unit to complete iterative correction, and directly output BF16 results at the end, eliminating the overhead caused by intermediate format conversion. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this application provides a floating-point function calculation method and processor with a shared seed. It adopts a set of shared hardware front-end and back-end that simultaneously supports three special functions: RECIP, RSQRT, and SQRT. It generates initial values ​​by relying on segmented seeds, reuses the processor's inherent FP32 fused multiply-accumulate unit to complete iterative correction, and directly outputs BF16 at the end, eliminating intermediate format conversion overhead.

[0007] To achieve the above objectives, this application provides a floating-point function calculation method with a shared seed, comprising: Receives input data in FP32 format and a function request for selecting a reciprocal function, a reciprocal square root function, or a square root function; performs shared floating-point classification, mantissa normalization, and exponent processing on the input data, wherein leading zero detection, significant number left shift, and exponent compensation are performed on subnormal inputs, and the sign is saved and restored for negative inputs of reciprocal functions; An initial seed is generated by a shared seed generation path based on the adjusted normalized mantissa and the function request. The shared seed generation path includes shared seed generation hardware, segmented address formation interface, and seed output path. According to the function request, the FP32 fused multiply-accumulate operation resource is invoked to perform error iteration on the initial seed, forming a normalized approximate result; Based on the exponential information, the normalized approximation result is reconstructed to form a normal function approximation result; During the classification phase, candidate results for specific values ​​corresponding to specific inputs are generated. The selection is made between the candidate results of the special value and the approximate result of the normal function based on the classification label; The selected result is rounded to nearest by performing RNE from FP32 to BF16 only once, and the BF16 result is output.

[0008] Furthermore, the reciprocal function, the reciprocal square root function, and the square root function share the same sign, zero, infinity, NaN, negative finite number and subnormal number classification, mantissa normalization, exponent splitting, seed address formation and terminal BF16 rounding path.

[0009] Furthermore, when the function request selects the reciprocal function, the residual 1-m×y0 is calculated using the initial seed y0 and the normalized mantissa m, and the reciprocal normalized approximation result y1_recip=y0×(2-m×y0) is formed based on the residual.

[0010] Furthermore, when the function request selects the reciprocal square root function, the adjusted normalized mantissas m' and e' are first obtained according to x=m×2e: when e is even, m'=m, e'=e; when e is odd, m'=2m, e'=e-1, making e' even; t=m'×y0 is calculated, h=1.5-0.5×t×y0 is calculated, and then the normalized reciprocal square root y1_rsqrt=y0×h is calculated, and multiplied by 2-e' / 2 to restore the result.

[0011] Furthermore, when the function request selects the square root function, the normalized y1_rsqrt formed by the reciprocal square root function is reused to calculate s=m'×y1_rsqrt, and then multiplied by 2e' / 2 to form an approximate square root result.

[0012] Furthermore, the shared seed generation path maps the adjusted normalized mantissa to the segment variable u∈[0,1) of the i-th segment, and generates an initial seed according to y0=ai+bi×u, where (ai,bi) are segment parameters addressed according to the function mode; the segment parameters are generated and fixed by offline fitting or biased fitting.

[0013] Furthermore, the standard quality mode uses a seed of the first parameter precision and outputs BF16 after one iteration. Function control, quality control, subnormal control, and anomaly control are independent of each other.

[0014] Furthermore, the high-precision mode improves the internal computational quality by at least one of the following methods: expanding the effective number of bits of the segmentation parameters, or appending one error iteration; outputting BF16 at the end after the high-precision mode operation is completed; and using a quality control field to select between the standard quality mode and the high-precision mode.

[0015] Furthermore, let N = VLEN / 32, receive the first FP32 source vector and the second FP32 source vector, each source vector includes N FP32 elements and each generates N BF16 results; write the N BF16 results of the first FP32 source vector into the lower VLEN / 2 bits of the destination vector, and write the N BF16 results of the second FP32 source vector into the higher VLEN / 2 bits of the destination vector; when VLEN = 128, write the 4 BF16 results of the first FP32 source vector into the destination vector [63:0], write the 4 BF16 results of the second FP32 source vector into the destination vector [127:64], and concatenate to obtain a BF16 destination vector with a full VLEN bit width.

[0016] To achieve the above objectives, this application also provides a floating-point function processor with a shared seed, comprising: A shared classification and normalization module is configured to receive FP32 input and perform classification, mantissa normalization, and exponent processing according to a function request, wherein the shared classification and normalization module includes subnormal leading zero detection, normalization shift, and exponent compensation path; The shared seed generation module is configured to generate an initial seed based on the adjusted normalized tail and the feature request; The iterative control module, connected to the FP32 fused multiply-accumulate unit, is configured to produce a normalized approximation of the reciprocal, the square root of the reciprocal, or the square root. The exponent reconstruction module is configured to receive the normalized approximation result and exponent information and form a normal function approximation result; The special value candidate and selection module is configured to select between the special value candidate result and the normal function approximation result; The BF16 rounding output module is configured to perform RNE rounding from FP32 to BF16 only once after the selection and output the BF16 result.

[0017] Furthermore, for x = m × 2e, when e is even, m' = m, e' = e; when e is odd, m' = 2m, e' = e1, thus making e' even, and providing m' and e' to the reciprocal square root or square root path.

[0018] Furthermore, the shared seed generation module includes a ROM or a configuration register, which includes segmented regions addressed in RECIP and RSQRT modes respectively. The address is formed by the function mode and the segment index i. Each segment stores parameters (ai, bi) and calculates y0 = ai + bi × u based on the variable u within the segment.

[0019] Furthermore, the iterative control module is configured to: control the FP32 fusion multiply-accumulate unit to calculate the residual e0=1-m×y0 and calculate y1=y0+y0×e0 for the reciprocal function, wherein the multiplication can be performed by FMA(a,b,0); calculate t=m'×y0, h=1.5-0.5×t×y0 and y1=y0×h for the reciprocal square root function, wherein the multiplication can be performed by FMA(a,b,0); and calculate s=m'×y1 for the square root function and reconstruct it according to the exponential information.

[0020] Furthermore, the BF16 rounding output module supports a dual-source vector mode. In dual-source vector mode, it receives N BF16 results generated by the first FP32 source vector and the second FP32 source vector, writes the first FP32 source vector result into the lower VLEN / 2 bits of the full-width BF16 destination vector, and writes the second FP32 source vector result into the higher VLEN / 2 bits of the destination vector. The processor is configured with an independent subnormal control field and an independent exception control field. The subnormal input can be selected as normalized or nullified, and the exception scenario can be independently selected as outputting infinity, a maximum finite number, or a NaN candidate.

[0021] To achieve the above objectives, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor employs a floating-point function processor with a shared seed as described above, for executing the computer program stored in the memory to implement the floating-point function calculation method with a shared seed as described above.

[0022] To achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program, which is loaded and executed by a processor to implement the floating-point function calculation method with a shared seed as described above.

[0023] Compared with existing technologies, this application has the following advantages: This application shares the floating-point classification, normalization, special value processing, seed addressing, and end-rounding paths of RECIP, RSQRT, and SQRT functions in hardware, eliminating the need to configure a complete set of front-end circuits for each of the three types of functions; the square root operation reuses the iterative intermediate results of the reciprocal square root, eliminating the need for independent seed generation and iterative paths; the iterative operation reuses the processor's native FP32 fused multiply-accumulate unit, eliminating the need for a dedicated multiplication array; FP32-to-BF16 rounding is performed only once at the end of the path, eliminating intermediate format conversion and register write-back overhead; and in vector mode, it supports parallel operation of dual-source vectors, making full use of the vector register bandwidth and reducing read / write power consumption.

[0024] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of the floating-point function calculation method for a shared seed according to an embodiment of this application; Figure 2 This is a shared seed segmented linear parameter table for embodiments of this application; Figure 3 This is a schematic diagram of the floating-point function processor structure for the shared seed in an embodiment of this application; Figure 4 This is a schematic diagram illustrating the adjustment of m' with even exponents and the restoration of the exponential scale in an embodiment of this application; Figure 5 This is a schematic diagram of the FP32 fused multiply-accumulate iteration and the terminal BF16 RNE output path in an embodiment of this application; Figure 6 This is a schematic diagram illustrating the mapping of a VLEN dual-source FP32 vector to a BF16 destination vector according to an embodiment of the present invention. Figure 7 This is a schematic diagram of an electronic device structure according to an embodiment of the present invention.

[0026] The above figures are only used to illustrate the technical solution of this application and are not intended to limit the scope of protection of this application. Detailed Implementation

[0027] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application.

[0028] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0029] The term "comprising" and its variations as used in this application are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0030] It should be noted that the terms "first" and "second" may be used in this application only to distinguish different devices, components or parts, and are not used to define the order of functions performed by these devices, components or parts or their interdependence.

[0031] It should be noted that the terms "one" and "more" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "More" should be understood as two or more.

[0032] It should be noted that the vector processor described in this application refers to a processor that has an FP32 fused multiply-accumulate execution unit that can be called by ordinary vector operations, and that enables micro-operations inside special functions to call the execution unit through a shared execution interface; the processor also includes or is connected to BF16 result conversion and submission resources; the fused multiply-accumulate operation performs a floating-point rounding after the product and addend are combined according to the mathematical relationship a×b+c.

[0033] Example 1 This embodiment provides a floating-point function calculation method with a shared seed, which can be executed on a vector processor with a vector length of VLEN=128 bits. It can receive a first FP32 source vector and a second FP32 source vector, and supports three function operations: reciprocal RECIP, reciprocal square root RSQRT, and square root SQRT. This embodiment is configured in standard quality mode, with the subnormalization control field configured to enable the normalization path, and the exception control field using default floating-point semantics.

[0034] Figure 1 This is a flowchart of the floating-point function calculation method for a shared seed according to an embodiment of this application. The following will refer to... Figure 1 The methods of the embodiments of this application will be described in detail below.

[0035] First, in step S1, input data in FP32 format and function requests are received.

[0036] The system receives input data from two FP32 source vectors and a function request, which is used to select the reciprocal RECIP function, the reciprocal square root RSQRT function, or the square root SQRT function. It also receives independent control fields, including a function selection field, a quality control field, a subnormal control field, and an anomaly control field. In vector operation scenarios, it receives the first FP32 source vector and the second FP32 source vector.

[0037] In this embodiment, N=VLEN / 32=4, and the first FP32 source vector and the second FP32 source vector each contain 4 FP32 elements.

[0038] In step S2, shared floating-point classification, mantissa normalization, and exponent processing are performed on the input data.

[0039] Perform shared floating-point classification and normalization processing on each FP32 input element in the input data (first FP32 source vector and second FP32 source vector); 1) Floating-point classification: Identify the sign of each FP32 element, whether it is zero, infinite, NaN, negative finite number, or subnormal number, and generate classification labels; for special inputs, generate special value candidate results and anomaly flags simultaneously.

[0040] 2) Subnormality judgment: If the input is subnormal, perform leading zero detection and count the number of leading zeros in the mantissa; shift the mantissa to the left, align the first valid 1 to the highest bit of the mantissa, and compensate the exponent by subtracting the same number of bits from the exponent for the shift, thus converting the subnormal number into a normal floating-point number format; if the input itself is normal FP32, directly parse to obtain the normalized mantissa m and the original exponent e.

[0041] 3) Exponent parity adjustment: Express floating-point input as: x = m × 2 e Where, if the original exponent e is even: m'=m, e'=e; if the original exponent e is odd: m'=2m, e'=e-1; After adjustment, ensure that e' is always even, and output m, m', e, e', as well as the category label and special value candidate results.

[0042] For reciprocal function scenarios, the negative input sign is saved in this step, and sign restoration is performed after the exponent reconstruction is complete. This step, RECIP, RSQRT, and SQRT, fully share the classification, normalization, and exponent splitting logic.

[0043] In step S3, the shared seed generation path generates an initial seed based on the adjusted normalized tail number and the function request.

[0044] The shared seed generation path receives the normalized mantissa and the function request signal; it decodes the segment index i according to the normalized mantissa to obtain the segment number; and it maps the mantissa to obtain the segment variable u∈[0,1).

[0045] Based on the functional mode and segment index i, the fitting parameters (ai, bi) stored in the on-chip shared ROM or configuration register are read; the initial seed y0 is calculated according to the piecewise linear formula y0=ai+bi×u.

[0046] In this embodiment, the ROM internally stores 16 sets of Q2.14 format RECIP parameters and 16 sets of Q2.14 format RSQRT parameters; the maximum seed relative error of RECIP is 0.00091171614, and the maximum seed relative error of RSQRT is 0.0027708424. The number of segments, valid parameter bits, and address bits are determined by the quality mode and the number of iterations, without limiting the specific number of entries. The seed is not visible to the software, and SQRT can reuse the RSQRT seed region.

[0047] The parameters in this embodiment adopt the Q2.14 fixed-point format with 14 decimal places. This bit width is an exemplary selection obtained by balancing the target BF16 output ULP index and ROM storage area. The present invention is not limited to this bit width, and other fixed-point bit widths can be configured according to the quality mode.

[0048] Parameter storage supports two implementation methods: Method 1: ROM-based firmware method, offline fitting is performed before chip fabrication, and the fitted (a) i b i The chip is programmed into the on-chip ROM and cannot be modified during chip operation. Method 2: Configurable register group method. The parameters are stored in a writable configurable register array. The segment parameters can be rewritten and updated during chip power-on or operation to adapt to different precision requirements.

[0049] The fitting objective of the biased fitting described in this invention is to minimize the maximum relative error of the initial seed y0 relative to the ideal function value within each segmented interval, introduce a bias term aᵢ to offset the segment endpoint deviation, reduce the maximum relative error of the initial seed before Newton iteration, and thus reduce the requirement for the number of subsequent iterations.

[0050] Figure 2The shared seed piecewise linear parameter table used in this application embodiment is an example of a software model implementing 16 segments of Q2.14 parameters. In comparing the sampled input set of the software model with the BF16 RNE reference model, no samples exceeding 1 ULP were observed after a single correction of both RECIP and RSQRT. The above statistics are used to illustrate an implementable parameter configuration and do not replace RTL verification, formal verification, or mass production chip measurement results. Software model simulation yielded the following results: the maximum seed relative error for RECIP is 0.00091171614, and the maximum seed relative error for RSQRT is 0.0027708424. After one iteration of correction, no BF16 reference error exceeding 1 ULP was observed in the sample set. Figure 2 In the function, RECIP (reciprocal) / RSQRT (square root of reciprocal) are two sets of parameters; segment number i: segment index, obtained directly from the high-order bits of the normalized mantissa in hardware, 0-15, a total of 16 segments; left: the left endpoint of the segment interval (the starting value of the normalized mantissa m); width: the width of the segment interval; a_i (Q2.14): linear formula intercept, Q2.14 is a signed 16-bit fixed-point integer, the actual floating-point value A_i = a_i / 16384; b_i (Q2.14): linear formula slope, Q2.14 is a signed 16-bit fixed-point integer, the actual floating-point value B_i = b_i / 16384.

[0051] Understandably, Figure 2 This application is an example of a 16-segment Q2.14 format lookup table, but it is not limited to 16 segments and Q2.14 fixed-point format.

[0052] In step S4, based on the function request, an error iteration operation is performed on the initial seed to obtain a normalized approximate result.

[0053] The iteration control module calls the processor's built-in general-purpose FP32 fusion multiply-accumulate unit to perform the corresponding iterative operation according to the function request; among them, pure multiplication operations are all executed in the form of FMA(a,b,0); in this embodiment, the standard quality mode is used to perform one iteration.

[0054] When the function request is the reciprocal function: using the normalized mantissa m and the initial seed y0, execute e0= fma(-m,y0, 1.0), and then execute y1_recip=fma(y0,e0,y0) to obtain the reciprocal normalized approximation result y1_recip.

[0055] When the function request is the RSQRT reciprocal square root function: using the parity-adjusted m', execute t=fma(m',y0,0.0), ty=fma (t,y0,0.0), h=fma (-0.5,ty,1.5), y1_rsqrt=fma (y0,h,0.0) in sequence to obtain the normalized approximation result y1_rsqrt of the reciprocal square root.

[0056] When the function request is a square root SQRT function, the independent seed and independent iteration process are not reused; the reciprocal square root specification is reused instead. The approximate result y1_rsqrt is obtained. Executing s=fma (m',y_(1_rsqrt),0.0) yields the intermediate normalized result s of the square root.

[0057] This embodiment uses the standard quality mode, employing a seed with the first parameter precision, and performs one error iteration. Switching to high-precision mode improves the internal computational quality by increasing the effective bit width of the segmented parameters or adding an additional error iteration. Regardless of whether it's the standard or high-precision mode, the BF16 result is output after the computation is complete.

[0058] In the software simulation model, it can be simplified as h=fma (-0.5f multiplied by t, y_0, 1.5f). This is the simplified form of the software model. In hardware implementation, it needs to be broken down into multiple FP32 fused multiply-accumulate operations in this step, and all operations are completed using FP32 fused multiply-accumulate units without introducing independent multipliers.

[0059] In step S5, the normalized approximation result is reconstructed exponentially to obtain the normal function approximation result.

[0060] The exponential reconstruction module receives the normalized approximation result obtained through iteration and the e' exponent information, and completes the exponential scaling recovery according to the function type: The RECIP function negates the exponent as a whole. RSQRT function multiplied by a scaling factor of 2 -e' / 2 ; SQRT function multiplied by a scaling factor of 2 e' / 2 This generates approximate results for normal functions.

[0061] In step S6, special value candidate results for special inputs are generated during the classification process.

[0062] Based on the floating-point classification labels output in step S, each element undergoes a multi-way selection process between the special value candidate results pre-generated in the classification stage and the normal function approximation results output in step S5.

[0063] For example, when the input is NaN, NaN candidates are selected for propagation; when the input is +∞, the corresponding special value is selected for output according to the function semantics; for ordinary finite input, the normal function approximation result obtained by iteration is selected.

[0064] In step S7, the selected result is rounded from FP32 to BF16 using RNE, and the result is output in BF16 format.

[0065] In this embodiment, the result after multiplexing is processed only once by performing the nearest rounding RNE from FP32 to BF16, and the result is output in BF16 format without intermediate format write-back or secondary conversion.

[0066] In step S8, the dual-source vectors are packed and output using VLEN; The first FP32 source vector and the second FP32 source vector each generate N BF16 results; the N BF16 results corresponding to the first source vector are written into the lower VLEN / 2 bits of the destination vector, and the N BF16 results corresponding to the second source vector are written into the higher VLEN / 2 bits of the destination vector.

[0067] In this embodiment, VLEN=128 bits. The four BF16 results output from the first source vector are written into the destination vector bit field [63:0], and the four BF16 results output from the second source vector are written into the destination vector bit field [127:64]. The output is a BF16 destination vector with a full VLEN bit width.

[0068] In this embodiment, RECIP, RSQRT, and SQRT share the floating-point classification, subnormal processing, normalization, exponent parity processing, seed addressing, special value candidate selection, and BF16 rounding output path; all iterative operations reuse the processor's built-in FP32 fused multiply-accumulate unit, eliminating the need for three independent special function operation units; the square root reuses the iterative output result of the reciprocal square root; the dual source vectors are directly concatenated to output a full-width BF16 destination vector, saving additional FP32 to BF16 instructions and reducing register read / write bandwidth overhead.

[0069] Example 2 This embodiment provides a floating-point function processor with a shared seed, used to execute the floating-point function calculation method with a shared seed in the aforementioned embodiment 1, supporting three types of floating-point function operations: RECIP reciprocal, RSQRT reciprocal square root, and SQRT square root.

[0070] Figure 3 This is a schematic diagram of the floating-point function processor architecture for a shared seed in an embodiment of this application, as shown below. Figure 3As shown in the embodiment of this application, the floating-point function processor with a shared seed includes: a shared classification and normalization module 310, a shared seed generation module 320, an iteration control module 330, a general-purpose FP32 fusion multiply-accumulate unit 340, an exponent reconstruction module 350, a special value candidate and selection module 355, and a BF16 rounding output module 360, wherein... The processor receives FP32 input data and function request signals, and also receives independent control fields: function selection field, quality control field, subnormal control field, and exception control field; in vector operating mode, it receives the first FP32 source vector and the second FP32 source vector.

[0071] The shared classification and normalization module 310 is configured to receive FP32 input data and complete floating-point classification, mantissa normalization and exponent processing in conjunction with function requests; it internally integrates a subnormal number leading zero detection circuit, a shift normalization circuit and an exponent compensation path.

[0072] The shared classification and normalization module 310 outputs: classification label, special value candidate results, normalized mantissa m, parity-adjusted mantissa m', original index e, and parity-adjusted even index e'.

[0073] In this embodiment, the shared classification and normalization module 310 executes the exponential parity adjustment logic: for the input When the exponent e is even, m'=m, e'=e; when the exponent e is odd, m'=2m, e'=e-1, ensuring that the output e' is even, and outputting to the shared seed generation module 320 and the exponent reconstruction module 350.

[0074] Figure 4 This diagram illustrates the adjustment of m' with even exponents and the restoration of the exponent scale in an embodiment of this application, used to explain the exponent parity adjustment logic performed before the calculation of the reciprocal square root RSQRT and the square root SQRT. Figure 4 As shown, the input floating-point number is represented as When the original exponent e is even, m'=m, e'=e; when the original exponent e is odd, the mantissa is amplified to obtain m'=2m, and the exponent is reduced by 1 to obtain e'=e-1, ensuring that the adjusted exponent e' is even; subsequently, exponent scale 2 is applied. -e' / 2 Recovery. Through this adjustment, RSQRT and SQRT can share the same set of exponential halving recovery logic, achieving hardware path sharing.

[0075] Simultaneously, subnormal number processing is performed: based on the subnormal control field, the subnormal input can be converted into a normal number through leading zero detection, shifting, and exponent compensation before being sent to the subsequent path, or the corresponding special value candidate result can be directly output; for the negative input of the RECIP function, sign information is saved for sign recovery during the exponent reconstruction stage. The special value candidate results obtained from floating-point classification are directly output to the special value candidate and selection module 355.

[0076] In this embodiment, the shared classification and normalization module 310 outputs normalized mantissa and exponent information to the shared seed generation module 320 on the one hand; on the other hand, it feeds the special value candidate results directly to the special value candidate and selection module 355 in parallel, realizing the special value bypass path without going through the seed-iteration-exponent reconstruction link.

[0077] The shared seed generation module 320 is connected to the shared classification and normalization module 310 and is configured to receive the normalized tail number and function request signal to generate the initial seed y0.

[0078] In this embodiment, the shared seed generation module 320 includes a ROM memory (or a configurable register group), a segmented address formation interface, and a seed output path; the ROM is divided into a RECIP parameter partition and an RSQRT parameter partition, and the SQRT function reuses the RSQRT parameter partition; the memory read address is generated by jointly decoding the function mode signal and the segmented index i.

[0079] In this embodiment, the shared seed generation module 320 maps the normalized mantissa to the corresponding segment to obtain the segment variable u∈[0,1), reads the segment fitting parameters (ai, bi), calculates and outputs the initial seed y0 according to the formula y0=ai+bi×u, and outputs it to the iteration control module 330; wherein the fitting parameters (ai, bi) are offline fitting or fitting with bias and then fixed in ROM.

[0080] In terms of hardware, the segment index i is directly generated by decoding the high-order bit field of the normalized mantissa, without introducing division operations; ROM / configuration register dual-option deployment: if ROM mode is used, the parameter bias fitting is completed and solidified offline before chip fabrication; if configuration register array mode is used, each segment (a) can be rewritten externally upon power-on or during runtime. i b i ) Parameters. Hardware benefits with bias fitting: Reduces the maximum relative error of the initial seed, and improves the ULP index of the output BF16 result under the same number of iterations; the hardware can switch different parameter groups through the quality control field, indirectly and equivalently changing the number of segments and parameter bit width, adapting to standard quality mode / high precision mode. The 16 segments and Q2.14 bit width in this embodiment are only exemplary hardware configurations, and the hardware can support other numbers of segments and other fixed-point parameter bit widths.

[0081] The iterative control module 330 is connected to the shared seed generation module 320 and the general-purpose FP32 fusion multiply-accumulate unit 340. The iterative control module 330 obtains the mantissas m and m' from the shared classification and normalization module 310, and the initial seed y0 from the shared seed generation module 320. The iterative control module 330 is a control logic circuit that sends opcodes and operand selection control signals to the general-purpose FP32 fusion multiply-accumulate unit 340, and schedules the general-purpose FP32 fusion multiply-accumulate unit 340 to complete the Newton-Raphson error iterative calculations corresponding to RECIP, RSQRT, and SQRT. All iterative calculations reuse the processor's native general-purpose FP32 fusion multiply-accumulate unit 340, without the need for an additional independent multiplication array. Pure multiplication operations are all executed using FMA(a,b,0) semantics.

[0082] In this embodiment, the operation control logic of the iteration control module 330 is as follows: RECIP reciprocal function: Using the normalized mantissa m and the initial seed y0, execute e0= fma(-m,y0, 1.0), and then execute y1_recip=fma(y0,e0,y0) to obtain the reciprocal normalized approximation result y1_recip.

[0083] The RSQRT function, which calculates the reciprocal square root, uses the parity-adjusted m' and executes t=fma(m',y_0,0.0), ty=fma(t,y0,0.0), h=fma(-0.5,ty,1.5), and y1_rsqrt=fma(y0,h,0.0) in sequence to obtain the normalized approximation of the reciprocal square root, y1_rsqrt.

[0084] When using the SQRT function for square roots, independent seeds and independent iteration processes are not reused; instead, the reciprocal square root specification is reused. Approximate the result y1_rsqrt. Execute s=fma(m', y1_rsqrt, 0.0) to obtain the intermediate normalized result of the square root. .

[0085] The quality mode is configured by the quality control field: the standard quality mode performs one iteration; the high-precision mode improves precision by increasing the effective bit width of the segmentation parameters in the ROM, or by having the iteration control module 330 add an additional iteration calculation; in both modes, the final output is a BF16 format result. After the iteration calculation is completed, the normalized approximation result is output to the exponent reconstruction module 350.

[0086] The general-purpose FP32 fused multiply-accumulate unit 340 is a native hardware resource of the processor. It is scheduled by the iteration control module 330 to complete the FP32 fused multiply-accumulate operation of a×b+c. The entire iteration process is completed in this unit.

[0087] The exponential reconstruction module 350 receives the normalized approximation result from the iterative output, and simultaneously receives the exponential information e, e', and sign information from the shared classification and normalization module 310, completing the exponential scaling recovery and generating the normal function approximation result: RECIP function: Inverts the exponent and, combined with sign recovery, obtains an approximate result of the reciprocal normal function; RSQRT function: Multiplies the normalized approximation of the inverse square root y1_rsqrt by a scaling factor of 2. -e' / 2 This yields an approximate result of the normal function with the reciprocal square root. SQRT function: Multiplies the intermediate result s by a scale factor of 2. e' / 2 This yields an approximate result for the square root normal function.

[0088] In this embodiment, the exponential reconstruction module 350 outputs the generated normal function approximation result to the special value candidate and selection module 355.

[0089] The special value candidate and selection module 355 has two inputs: one from the special value candidate results output by the shared classification and normalization module 310; and the other from the normal function approximation results output by the exponential reconstruction module 350. It selects one of these two options element by element based on the classification label. In special cases such as zero, infinity, NaN, or invalid input, the corresponding special value candidate is selected; for ordinary finite numerical inputs, the normal function approximation results output by the exponential reconstruction module are selected, and the selected result is output to the BF16 rounding output module 360.

[0090] The BF16 rounding output module 360 ​​is configured to perform only one RNE rounding from FP32 to BF16 for the selected calculation result and output the BF16 result.

[0091] In vector mode, the processor receives two FP32 source vectors; defining N=VLEN / 32, the first FP32 source vector and the second FP32 source vector each output N BF16 results; the BF16 result corresponding to the first FP32 source vector is written into the lower VLEN / 2 bits of the destination vector; the BF16 result corresponding to the second FP32 source vector is written into the higher VLEN / 2 bits of the destination vector, and the resulting BF16 destination vector with a full bit width of VLEN is assembled and output.

[0092] For example, when VLEN=128 bits, the first FP32 source vector outputs 4 BF16 bytes and stores them in the destination vector bit field [63:0]; the second FP32 source vector outputs 4 BF16 bytes and stores them in the destination vector bit field [127:64]. The two are concatenated to form a full-width VLEN BF16 destination vector, as shown below. Figure 6 As shown.

[0093] The processor's subnormal control field and exception control field can be configured independently: subnormal inputs can choose to follow the full normalization path or be directly zeroed out; in exception scenarios, the output can be configured independently to be infinite, a maximum finite number, or a NaN candidate result.

[0094] Figure 5 This is a schematic diagram of the FP32 fused multiply-accumulate iteration and the terminal BF16 RNE output path in an embodiment of this application, as shown below. Figure 5 The diagram illustrates the complete data flow path of this application, from iterating intermediate variables to the BF16 output. The RECIP residual, and intermediate variables such as t, h, and y1 from RSQRT are fed into the FP32 fused multiply-accumulate iterative path; the square root SQRT reuses the RSQRT iterative output to complete the multiplication operation; the result is sent to the exponent reconstruction module to recover the exponent; finally, only one RNE operation is performed at the end of BF16 for rounding to the nearest value, outputting the BF16 result. All iterative operations reuse the existing FP32 fused multiply-accumulate unit within the processor, eliminating the need for a dedicated polynomial multiplication array.

[0095] The floating-point function processor hardware working data flow for the shared seed in this embodiment is as follows: the FP32 input is sent to the shared classification and normalization module 310, flows sequentially through the shared seed generation module 320, the iteration control and scheduling module 330, and the general FP32 fusion multiply-accumulate unit 340 to complete the iteration, and is then sent to the exponent reconstruction module 350; the special value candidates output by the shared classification and normalization module 310 are directly sent to the special value candidate and selection module 355, where they are multi-selected with the normal results output by the exponent reconstruction module 350, and then sent to the BF16 rounding output module 360 ​​to output the final BF16 operation result.

[0096] Example 3 In embodiments of the present invention, an electronic device is also provided. Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention, such as... Figure 7 As shown, the electronic device of the present invention includes a processor 701 and a memory 702, wherein, Processor 701 is a floating-point function processor for the shared seed in the above embodiment.

[0097] The memory 702 stores a computer program, which, when read and executed by the processor 701, performs the steps described above in the embodiment of the floating-point function calculation method with a shared seed.

[0098] Example 4 In embodiments of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, wherein the computer program is configured to execute the steps of the floating-point function calculation method embodiment with shared seed as described above when running.

[0099] In this embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0100] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for calculating floating-point functions with a shared seed, characterized in that, include: Receives FP32 format input data and a function request for selecting the reciprocal function, the reciprocal square root function, or the square root function; The input data is subjected to shared floating-point classification, mantissa normalization and exponent processing, wherein leading zero detection, significant number left shift and exponent compensation are performed on subnormal inputs, and the sign is saved and restored for negative inputs of the reciprocal function; An initial seed is generated by a shared seed generation path based on the adjusted normalized mantissa and the function request. The shared seed generation path includes shared seed generation hardware, segmented address formation interface, and seed output path. According to the function request, the FP32 fused multiply-accumulate operation resource is invoked to perform error iteration on the initial seed, forming a normalized approximate result; Based on the exponential information, the normalized approximation result is reconstructed to form a normal function approximation result; During the classification phase, candidate results for specific values ​​corresponding to specific inputs are generated. The selection is made between the candidate results of the special value and the approximate result of the normal function based on the classification label; The selected result is rounded to nearest BF16 using RNE only once. The BF16 result is then output.

2. The method according to claim 1, characterized in that, The reciprocal function, reciprocal square root function, and square root function share a sign, zero, infinity, NaN, negative finite number, and subnormal number classification, mantissa normalization, exponent splitting, seed address formation, and terminal BF16 rounding path.

3. The method according to claim 1, characterized in that, When the function request selects the reciprocal function, the residual 1-m×y0 is calculated using the initial seed y0 and the normalized mantissa m, and the reciprocal normalized approximation result y1_recip=y0×(2-m×y0) is formed based on the residual.

4. The method according to claim 1, characterized in that, When the function request selects the reciprocal square root function, the adjusted normalized mantissas m' and e' are first obtained according to x=m×2e: when e is even, m'=m, e'=e; when e is odd, m'=2m, e'=e-1, making e' even; t=m'×y0, h=1.5-0.5×t×y0, then the normalized reciprocal square root y1_rsqrt=y0×h is calculated, and multiplied by 2-e' / 2 to restore the result.

5. The method according to claim 4, characterized in that, When the function request selects the square root function, the normalized y1_rsqrt formed by the reciprocal square root function is reused to calculate s=m'×y1_rsqrt, and then multiplied by 2e' / 2 to form an approximate square root result.

6. The method according to claim 1, characterized in that, The shared seed generation path maps the adjusted normalized mantissa to the segment variable u∈[0,1) of the i-th segment, and generates an initial seed according to y0=ai+bi×u, where (ai,bi) are segment parameters addressed according to the function mode; the segment parameters are generated and fixed by offline fitting or biased fitting.

7. The method according to claim 1, characterized in that, The standard quality mode uses a seed with the first parameter precision and outputs BF16 after one iteration. Function control, quality control, subnormal control, and anomaly control are independent of each other.

8. The method according to claim 7, characterized in that, The high-precision mode improves the quality of internal computation by at least one of the following methods: expanding the effective number of bits of the segmented parameters, or appending one more error iteration; After the high-precision mode calculation is completed, BF16 is still output at the end; the quality control field is used to select the standard quality mode or the high-precision mode.

9. The method according to any one of claims 1 to 8, characterized in that, Let N = VLEN / 32. Receive the first FP32 source vector and the second FP32 source vector. Each source vector includes N FP32 elements and generates N BF16 results. Write the N BF16 results of the first FP32 source vector into the lower VLEN / 2 bits of the destination vector, and write the N BF16 results of the second FP32 source vector into the higher VLEN / 2 bits of the destination vector. When VLEN = 128, write the four BF16 results of the first FP32 source vector into the destination vector [63:0], and write the four BF16 results of the second FP32 source vector into the destination vector [127:64]. Concatenate to obtain a BF16 destination vector with a full VLEN bit width.

10. A floating-point function processor with a shared seed, characterized in that, include: A shared classification and normalization module is configured to receive FP32 input and perform classification, mantissa normalization, and exponent processing according to a function request, wherein the shared classification and normalization module includes subnormal leading zero detection, normalization shift, and exponent compensation path; The shared seed generation module is configured to generate an initial seed based on the adjusted normalized tail and the feature request; The iterative control module, connected to the FP32 fused multiply-accumulate unit, is configured to produce a normalized approximation of the reciprocal, the square root of the reciprocal, or the square root. The exponent reconstruction module is configured to receive the normalized approximation result and exponent information and form a normal function approximation result; The special value candidate and selection module is configured to select between the special value candidate result and the normal function approximation result; The BF16 rounding output module is configured to perform only one FP32 to BF16 RNE rounding and output the BF16 result after the selection.

11. The processor according to claim 10, characterized in that, The shared classification and normalization module, for x=m×2e, when e is even, m'=m, e'=e; when e is odd, m'=2m, e'=e-1, thus making e' even, and providing m' and e' to the reciprocal square root or square root path.

12. The processor according to claim 10, characterized in that, The shared seed generation module includes a ROM or a configuration register. The ROM or configuration register includes segmented regions addressed in RECIP and RSQRT modes respectively. The address is formed by the function mode and the segment index i. Each segment stores parameters (ai, bi) and calculates y0 = ai + bi × u based on the variable u within the segment.

13. The processor according to claim 10, characterized in that, The iterative control module is configured to: control the FP32 fusion multiply-accumulate unit to calculate the residual e0=1-m×y0 and calculate y1=y0+y0×e0 for the reciprocal function, where the multiplication can be performed by FMA(a,b,0); calculate t=m'×y0, h=1.5-0.5×t×y0 and y1=y0×h for the reciprocal square root function, where the multiplication can be performed by FMA(a,b,0); and calculate s=m'×y1 for the square root function and reconstruct it according to the exponential information.

14. The processor according to any one of claims 10 to 13, characterized in that, The BF16 rounding output module supports dual-source vector mode. In dual-source vector mode, it receives N BF16 results generated by the first FP32 source vector and the second FP32 source vector, writes the first FP32 source vector result into the lower VLEN / 2 bits of the full-width BF16 destination vector, and writes the second FP32 source vector result into the higher VLEN / 2 bits of the destination vector. The processor is configured with an independent subnormal control field and an independent exception control field. The subnormal input can be selected as normalized or nulled, and the exception scenario can be independently selected as outputting infinity, a maximum finite number, or a NaN candidate.

15. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor employs a floating-point function processor with a shared seed as described in any one of claims 10 to 14, for executing the computer program stored in the memory to implement the floating-point function calculation method with a shared seed as described in any one of claims 1 to 9.

16. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which is loaded and executed by a processor to implement the floating-point function calculation method with a shared seed as described in any one of claims 1 to 9.

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