Low-power full adder and chip based on fefet

Abstract

This invention discloses a low-power full adder and chip based on FeFET. The full adder includes FeFET transistors F1 and F2, an inverter INV, and CMOS transmission gates TG1, TG2, TG3, and TG4. The source of F1 is connected to input B, and the gate of F1 is connected to the first sub-input A1. The source of F2 is connected to the inverted input B, and the gate of F2 is connected to the second sub-input A2. A1 and A2 together represent input A. The drains of F1 and F2 are connected, and the output is an XNOR logic. The input of the inverter INV is connected to XNOR, and the output is XOR. The input of TG1 is connected to the input C, and the control terminal of TG1 is connected to XOR and XNOR respectively. The input of TG2 is connected to input C, and the control terminal of TG2 is connected to XNOR and XOR respectively. The outputs of TG1 and TG2 are connected and used to output bit S. The input of TG3 is connected to B, and the control terminal of TG3 is connected to XNOR and XOR respectively. The input of TG4 is connected to C, and the control terminal of TG4 is connected to XOR and XNOR respectively. The outputs of TG3 and TG4 are connected and used to output the carry Co. This invention simplifies the circuit structure and significantly reduces static power consumption and overall operational power consumption.

Description

Technical Field

[0001] This invention relates to a full adder in the field of integrated circuit technology, and more particularly to a low-power full adder based on FeFET, and also to a chip. Background Technology

[0002] The rapid development of artificial intelligence applications has led to a surge in computing power demand. The traditional von Neumann architecture, due to the separation of computing and storage units, has caused "memory walls" and "power walls" due to frequent data transfers, giving rise to in-memory computing technology. As the core basic computing unit of digital integrated circuits, the power consumption of the full adder directly determines the overall energy efficiency of the adder array, arithmetic logic unit, and chip.

[0003] Current mainstream full adders are mainly built on traditional CMOS devices. While the circuit structure is mature, it suffers from significant power consumption limitations: logic operations rely on complementary transistor switching, and the devices inherently have subthreshold leakage current, resulting in extremely high static power consumption. Furthermore, traditional CMOS devices lack non-volatile memory, requiring frequent read / write operations and data transfer during computation, leading to significant dynamic power consumption. These issues make it difficult for traditional CMOS full adders to meet the energy efficiency requirements of ultra-low-power integrated circuits and edge-lightweight computing applications. Meanwhile, existing FeFET-based full adder architectures are still immature, generally exhibiting redundant device counts and complex circuit topologies, generating substantial switching power consumption during computation. Summary of the Invention

[0004] To address the high power consumption problem of existing full adders, this invention provides a low-power full adder and chip based on FeFET.

[0005] This invention is achieved using the following technical solution: a low-power full adder based on FeFET, comprising: FeFET transistors F1 and F2; the source of F1 is connected to the input signal B, and the gate of F1 is connected to the first sub-input signal A1; the source of F2 is connected to the inverted signal of B. The gate of F2 is connected to the second sub-input signal A2. Signals A1 and A2 together represent the input signal A. The drains of F1 and F2 are connected and used to output the XNOR logic signal. The inverter INV has its input terminal connected to the signal XNOR and is used to output the signal XOR. CMOS transmission gates TG1, TG2, TG3, and TG4; the input of TG1 is connected to the inverted signal of the input signal C. The control terminals of TG1 are connected to signals XOR and XNOR respectively; the input terminal of TG2 is connected to the input signal C, and the control terminals of TG2 are connected to signals XNOR and XOR respectively; the output terminals of TG1 and TG2 are connected and used to output the bit signal S; the input terminal of TG3 is connected to the signal B, and the control terminals of TG3 are connected to signals XNOR and XOR respectively; the input terminal of TG4 is connected to the signal C, and the control terminals of TG4 are connected to signals XOR and XNOR respectively; the output terminals of TG3 and TG4 are connected and used to output the carry signal Co.

[0006] This invention utilizes the multi-threshold characteristics of two FeFET transistors, F1 and F2, to perform the XNOR logic operation on input signals A and B. It also uses the XNOR and XOR logic signals as control signals for four CMOS transmission gates to directly select and transmit different input signals to obtain the sum bit S and carry Co. This solves the technical problem of high power consumption in existing full adders and achieves the technical effects of simplified circuit structure and significantly reduced static power consumption and overall operational power consumption.

[0007] As a further improvement to the above scheme, signals A1 and A2 represent the input signal A in the following way: when signal A1 is low and signal A2 is high, it means A=0; when signal A1 is high and signal A2 is low, it means A=1.

[0008] As a further improvement to the above scheme, by applying different gate voltages to signals A1 and A2, high threshold or low threshold values ​​can be written to F1 and F2 respectively, thereby controlling the on or off state of F1 and F2 in the subsequent calculation stage.

[0009] As a further improvement to the above scheme, the working process of the full adder includes a writing phase, a holding phase, and a calculation phase; During the writing phase, a preset voltage is applied to the gates of F1 and F2 to write the corresponding threshold states, keeping signals B and C at a low level. and Keep low level; During the hold phase, all input signals are set to low level; During the calculation phase, a turn-on voltage is applied to the gates of F1 and F2, and F1 and F2 are turned on or off according to the written threshold state to realize the XOR logic operation of signals A and B, and signals S and Co are obtained through INV and each CMOS transmission gate respectively.

[0010] Furthermore, during the calculation phase, when the signal XOR is 1 and the signal XNOR is 0, TG1 and TG4 are turned on, and TG2 and TG3 are turned off; when the signal XOR is 0 and the signal XNOR is 1, TG1 and TG4 are turned off, and TG2 and TG3 are turned on.

[0011] Furthermore, during the write phase, a high-level voltage of 3V is applied to the gates of F1 and F2, and the write duration is 5ns; during the calculation phase, a high-level voltage of 0.9V is applied to the gates of F1 and F2, and the calculation duration is 2ns; during the holding phase, the calculation duration is 5ns.

[0012] As a further improvement to the above scheme, the formula for calculating the sum bit signal is as follows: The formula for calculating the carry signal is: .

[0013] As a further improvement to the above scheme, each CMOS transmission gate includes a first NMOS transistor and a first PMOS transistor connected in parallel; in the same CMOS transmission gate, the gates of the first NMOS transistor and the first PMOS transistor are respectively connected to control signals that are inversely related to each other: XOR and XNOR; INV includes a second NMOS transistor and a second PMOS transistor connected in series.

[0014] As a further improvement to the above scheme, F1 and F2 are both N-type FeFET transistors. The full adder performs low-threshold writing by applying a high level to the gates of F1 and F2, and performs high-threshold writing by applying a low level.

[0015] The present invention also provides a chip in which the above-described low-power full adder based on FeFET is integrated in its arithmetic circuit.

[0016] Compared to existing full adders, the low-power full adder and chip based on FeFET of the present invention have the following advantages: 1. This low-power full adder based on FeFET uses the multi-threshold characteristics of two FeFET transistors F1 and F2 to perform the XOR logic operation on input signals A and B. It uses the XOR logic signal XNOR and the XOR logic signal XOR as control signals for four CMOS transmission gates to directly select and transmit different input signals to obtain the sum bit S and carry Co. This solves the technical problem of high power consumption in existing full adders and achieves the technical effects of simplified circuit structure and significantly reduced static power consumption and overall operation power consumption.

[0017] 2. This low-power full adder based on FeFET utilizes the non-volatile storage characteristics of FeFET transistors. By presetting a threshold state during the write phase and directly turning on and selecting during the calculation phase, it eliminates the need to repeatedly read from the memory cell and move intermediate data as in traditional CMOS full adders. This effectively reduces the dynamic power consumption generated by data movement and achieves low-power computing in memory.

[0018] 3. This low-power full adder based on FeFET consists of only 2 FeFET transistors, 4 CMOS transmission gates and 1 inverter. Compared with existing FeFET full adders (such as 1FeFET+21MOS or 7FeFET+2MOS structures), it significantly reduces the number of transistors used, simplifies the circuit topology, and has a smaller hardware size, which is beneficial for reducing chip area, improving integration and manufacturing yield.

[0019] 4. This FeFET-based low-power full adder has a single complete calculation cycle of 12ns, an average energy consumption of only 0.283fJ, and an average power consumption of only 0.0236μW. It can complete full addition operations with extremely low power consumption and is particularly suitable for edge computing and IoT terminal devices with stringent energy efficiency requirements.

[0020] 5. The beneficial effects of this chip are the same as those of the low-power full adder based on FeFET mentioned above, and will not be repeated here. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of a low-power full adder based on FeFET according to Embodiment 1 of the present invention.

[0022] Figure 2 This is a timing diagram of the full adder in Embodiment 1 of the present invention when the input signals A=0, B=0, and C=1.

[0023] Figure 3 This is a timing diagram of the full adder in Embodiment 1 of the present invention when the input signals A=1, B=0, and C=1.

[0024] Figure 4 This is a timing diagram of the full adder in Embodiment 1 of the present invention when the input signals A=1, B=1, and C=1.

[0025] Figure 5 This is a comparison chart of the power consumption of the full adder in Embodiment 1 of the present invention and a conventional full adder. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0027] Example 1 Please see Figure 1This embodiment provides a low-power full adder based on FeFET. This full adder utilizes the non-volatile and low-leakage characteristics of FeFET, solving the problems of redundant device quantity and high power consumption during operation switching in full adders. Specifically, the full adder includes FeFET transistors F1 and F2, an inverter INV, and CMOS transmission gates TG1, TG2, TG3, and TG4.

[0028] The source of capacitor F1 is connected to input signal B, and the gate of F1 is connected to the first sub-input signal A1. The source of capacitor F2 is connected to the inverted signal of B. The gate of F2 is connected to the second sub-input signal A2. Signals A1 and A2 together represent the input signal A. The drains of F1 and F2 are connected and used to output the XNOR logic signal. In this embodiment, F1 and F2 are both N-type FeFET transistors. The full adder performs low-threshold writing by applying a high level to the gates of F1 and F2, and performs high-threshold writing by applying a low level.

[0029] In this embodiment, signals A1 and A2 represent the input signal A as follows: when signal A1 is low and signal A2 is high, it means A=0; when signal A1 is high and signal A2 is low, it means A=1. Finally, this embodiment uses the XOR (Exclusive OR) result as a control signal to open different transmission gates to determine the output, thereby obtaining the sum bit output and carry output of the full adder. This full adder applies different gate voltages to signals A1 and A2 to write high or low threshold values ​​to F1 and F2 respectively, thus controlling the on or off states of F1 and F2 in subsequent calculation stages.

[0030] The inverter INV has its input terminal connected to the signal XNOR and is used to output the signal XOR. The inverter INV includes a second NMOS transistor and a second PMOS transistor connected in series. Specifically, the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor, serving as the input terminal of the inverter, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, serving as the output terminal of the inverter. The source of the second PMOS transistor is connected to the power supply voltage VDD, and the source of the second NMOS transistor is connected to ground GND. When the input signal XNOR is high, the second NMOS transistor is turned on and the second PMOS transistor is turned off, pulling the output terminal low to GND, resulting in a low-level output. When the input signal XNOR is low, the second PMOS transistor is turned on and the second NMOS transistor is turned off, pulling the output terminal high to VDD, resulting in a high-level output, thus achieving the logic inversion function.

[0031] The input terminal of TG1 is connected to the inverted signal of the input signal C. The control terminals of TG1 are connected to signals XOR and XNOR, respectively. The input terminal of TG2 is connected to input signal C, and the control terminals of TG2 are connected to signals XNOR and XOR, respectively. The output terminals of TG1 and TG2 are connected and used to output the sum bit signal S. The input terminal of TG3 is connected to signal B, and the control terminals of TG3 are connected to signals XNOR and XOR, respectively. The input terminal of TG4 is connected to signal C, and the control terminals of TG4 are connected to signals XOR and XNOR, respectively. The output terminals of TG3 and TG4 are connected and used to output the carry signal Co. The formula for calculating the sum bit signal can be: The formula for calculating the carry signal is: .

[0032] Each CMOS transmission gate includes a first NMOS transistor and a first PMOS transistor, which are connected in parallel. Within the same CMOS transmission gate, the gates of the first NMOS transistor and the first PMOS transistor are connected to inverted control signals: XOR and XNOR, respectively. One end of the first NMOS transistor is connected to one end of the first PMOS transistor, serving as the input terminal of TG1, while the other end of the first NMOS transistor is connected to the other end of the first PMOS transistor, serving as the output terminal of TG1.

[0033] The operation of a full adder includes a write phase, a hold phase, and a calculation phase.

[0034] During the write phase, a preset voltage is applied to the gates of F1 and F2 to write the corresponding threshold states, keeping signals B and C at a low level. For N-type FeFET transistors, the threshold voltage of the FeFET is modified by applying different gate voltages. Applying a high level to the gate of the FeFET transistor performs a low-threshold write, while applying a low level performs a high-threshold write.

[0035] During the write phase, for F1 and F2 in this embodiment, A1 and A2 are the gate inputs of F1 and F2, respectively, and A1 and A2 together represent the input signal A. Specifically, in this embodiment, a high-level voltage of 3V is applied to the gates of F1 and F2, and the write duration is 5ns. When A1A2=10 (A1 connected to 3V voltage, A2 grounded), it indicates that the input signal A=1, at which time F1 writes to the low threshold and F2 writes to the high threshold; when A1A2=01 (A1 grounded, A2 connected to 3V voltage), it indicates that the input signal A=0, at which time F1 writes to the high threshold and F2 writes to the low threshold, and the rest are invalid. Input signals B and C remain low during the write phase. and It also remains at a low level (i.e., all signals except A1 and A2 are at a low level at this time).

[0036] During the hold phase, all input signals are set to low level, i.e., A, B, and C are all connected to low level, and the circuit does not work. The calculated duration is 5ns.

[0037] During the calculation phase, a turn-on voltage is applied to the gates of F1 and F2, and F1 and F2 are turned on or off according to the written threshold state to achieve the XOR logic operation of signals A and B, and signals S and Co are obtained through INV and each CMOS transmission gate respectively. When the signal XOR is 1 and the signal XNOR is 0, TG1 and TG4 are turned on, and TG2 and TG3 are turned off. When the signal XOR is 0 and the signal XNOR is 1, TG1 and TG4 are turned off, and TG2 and TG3 are turned on. In this embodiment, the high-level voltage applied to the gates of F1 and F2 is 0.9V, and the calculation duration is 2ns.

[0038] During the computation phase, this embodiment controls the on / off state of F1 and F2 by writing threshold values ​​to the FeFET. When the gate voltage is high (0.9V), the FeFET is turned on in the low threshold state and turned off in the high threshold state. Input signals B and C are applied with high (0.9V) or low levels according to different requirements. During the computation phase, A1 and A2 are both connected to high (0.9V). When input signal A=1, F1 is turned on and F2 is turned off; when input signal A=0, F1 is turned off and F2 is turned on. The XNOR operation of input signals A and B is achieved by different conduction states of the FeFET, and then the XOR result of A and B is obtained through an inverter. The four CMOS transmission gates are respectively connected to control signals XNOR and XOR, and different inputs are transmitted according to different control signals, thereby obtaining the sum S and carry Co of the full adder.

[0039] For the control signals of the CMOS transmission gate, when the XOR result of signals A and B is 1 (the XNOR result is 0), TG1 transmits the signal. TG2 is not working, TG3 is not working, and TG4 transmits signal C. When the XOR result of signal A and signal B is 0 (XNOR result is 1), TG1 is not working, TG2 transmits signal C, TG3 transmits signal B, and TG4 is not working.

[0040] For input signals A=0, B=0, C=1, during the write phase, A1A2=01, meaning a low level is applied to F1 and a high level to F2, resulting in F1 writing to the high threshold and F2 writing to the low threshold (i.e., F1 is off and F2 is on). During the hold phase, all input signals are low. During the calculation phase, input signal B is low and input signal C is high, so the XOR result of signals A and B is 0, and the XNOR result is 1. TG2 transmits signal C, and TG3 transmits signal B. For the bit... With S=1, for carry Co=0, which matches the calculation result of the full adder.

[0041] For input signals A=1, B=0, and C=1, during the write phase, A1A2=10, meaning a high level is applied to F1 and a low level to F2, resulting in F1 writing to the low threshold and F2 writing to the high threshold (i.e., F1 is on and F2 is off). During the hold phase, all input signals are low. During the calculation phase, input signal B is low and input signal C is high, so the XOR result of signals A and B is 1, and the XNOR result is 0. TG1 then transmits the signal. The TG4 transmits signal C, which has S=0 for the sum bit and Co=1 for the carry bit, consistent with the calculation result of the full adder.

[0042] For input signals A=1, B=1, C=1, during the write phase, A1A2=10, meaning a high level is applied to F1 and a low level to F2, resulting in F1 writing to the low threshold and F2 writing to the high threshold (i.e., F1 is on and F2 is off). During the hold phase, all input signals are low. During the calculation phase, input signals B and C are both high, so the XOR result of signals A and B is 0, and the XNOR result is 1. TG2 transmits signal C, and TG3 transmits signal B. For the sum bit, S=1, and for the carry bit, Co=1, which matches the calculation result of the full adder. The truth table of the full adder is as follows, and the timing diagram is as follows. Figure 2 , Figure 3 as well as Figure 4 Power consumption, for example Figure 5 As shown.

[0043] Table 1 Truth Table In summary, compared to existing full adders, the low-power full adder based on FeFET in this embodiment has the following advantages: 1. This low-power full adder based on FeFET uses the multi-threshold characteristics of two FeFET transistors F1 and F2 to perform the XOR logic operation on input signals A and B. It uses the XOR logic signal XNOR and the XOR logic signal XOR as control signals for four CMOS transmission gates to directly select and transmit different input signals to obtain the sum bit S and carry Co. This solves the technical problem of high power consumption in existing full adders and achieves the technical effects of simplified circuit structure and significantly reduced static power consumption and overall operation power consumption.

[0044] 2. This low-power full adder based on FeFET utilizes the non-volatile storage characteristics of FeFET transistors. By presetting a threshold state during the write phase and directly turning on and selecting during the calculation phase, it eliminates the need to repeatedly read from the memory cell and move intermediate data as in traditional CMOS full adders. This effectively reduces the dynamic power consumption generated by data movement and achieves low-power computing in memory.

[0045] 3. This low-power full adder based on FeFET consists of only 2 FeFET transistors, 4 CMOS transmission gates and 1 inverter. Compared with existing FeFET full adders (such as 1FeFET+21MOS or 7FeFET+2MOS structures), it significantly reduces the number of transistors used, simplifies the circuit topology, and has a smaller hardware size, which is beneficial for reducing chip area, improving integration and manufacturing yield.

[0046] 4. This FeFET-based low-power full adder has a single complete calculation cycle of 12ns, an average energy consumption of only 0.283fJ, and an average power consumption of only 0.0236μW. It can complete full addition operations with extremely low power consumption and is particularly suitable for edge computing and IoT terminal devices with stringent energy efficiency requirements.

[0047] Example 2 This embodiment provides a chip, which can be a memory computing chip, including a memory array and an arithmetic circuit. The arithmetic circuit integrates the low-power full adder based on FeFET as described in Embodiment 1. Specifically, the arithmetic circuit includes an adder array composed of multiple cascaded full adders, used to perform multi-bit binary addition operations. The memory array is used to store the data to be processed. Since the FeFET transistors in the full adder have non-volatile storage characteristics, intermediate data during the operation does not need to be frequently transferred between the memory array and the arithmetic circuit, significantly reducing the dynamic power consumption of data transfer and realizing high-efficiency computing in memory.

[0048] Example 3 This embodiment provides an arithmetic logic unit, including at least one low-power full adder based on FeFET as described in Embodiment 1. The arithmetic logic unit also includes a logic operation module, a shift module, and a control module. The full adder, as the core addition operation component of the arithmetic logic unit, is used to perform addition operations in arithmetic calculations. Since the full adder consists of only two FeFET transistors, four CMOS transmission gates, and one inverter, its hardware is small and its power consumption is low. This allows the arithmetic logic unit of this embodiment to significantly reduce chip area and overall power consumption while maintaining complete arithmetic logic functionality, making it suitable for use in low-power processors, microcontrollers, and other integrated circuit chips.

[0049] Example 4 This embodiment provides an electronic device, which includes a processor. The processor integrates an arithmetic logic unit as described in Embodiment 3, and the arithmetic logic unit includes at least one low-power full adder based on FeFET as described in Embodiment 1. The electronic device can be any one of a smartphone, tablet computer, wearable device, wireless sensor node, or Internet of Things (IoT) terminal device.

[0050] In this embodiment, the use of a low-power full adder based on FeFET significantly reduces the overall power consumption of the electronic device during data processing, effectively extending the battery life of the battery-powered device. Simultaneously, the simplified full adder circuit structure helps reduce the processor chip area, lower manufacturing costs, and enhance the integration and competitiveness of the end product.

[0051] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-power full adder based on FeFET, characterized in that, It includes: FeFET transistors F1 and F2; The source of F1 is connected to the input signal B, and the gate of F1 is connected to the first sub-input signal A1. The inverted signal of source F2 connected to B The gate of F2 is connected to the second sub-input signal A2. Signals A1 and A2 together represent the input signal A. The drains of F1 and F2 are connected and used to output the XNOR logic signal. The inverter INV has its input terminal connected to the signal XNOR and is used to output the signal XOR. CMOS transmission gates TG1, TG2, TG3, and TG4; the input of TG1 is connected to the inverted signal of the input signal C. The control terminals of TG1 are connected to signals XOR and XNOR respectively; the input terminal of TG2 is connected to the input signal C, and the control terminals of TG2 are connected to signals XNOR and XOR respectively; the output terminals of TG1 and TG2 are connected and used to output the bit signal S; the input terminal of TG3 is connected to the signal B, and the control terminals of TG3 are connected to signals XNOR and XOR respectively; the input terminal of TG4 is connected to the signal C, and the control terminals of TG4 are connected to signals XOR and XNOR respectively; the output terminals of TG3 and TG4 are connected and used to output the carry signal Co.

2. The low-power full adder based on FeFET as described in claim 1, characterized in that, Signals A1 and A2 represent input signal A in the following ways: when signal A1 is low and signal A2 is high, it means A=0; when signal A1 is high and signal A2 is low, it means A=1.

3. The low-power full adder based on FeFET as described in claim 1, characterized in that, By applying different gate voltages to signals A1 and A2, high or low threshold values ​​can be written to F1 and F2 respectively, thereby controlling the on or off states of F1 and F2 in subsequent calculation stages.

4. The low-power full adder based on FeFET as described in claim 1, characterized in that, The operation of the full adder includes a write phase, a hold phase, and a calculation phase. During the writing phase, a preset voltage is applied to the gates of F1 and F2 to write the corresponding threshold states, keeping signals B and C at a low level. and Keep low level; During the hold phase, all input signals are set to low level; During the calculation phase, a turn-on voltage is applied to the gates of F1 and F2, and F1 and F2 are turned on or off according to the written threshold state to realize the XOR logic operation of signals A and B, and signals S and Co are obtained through INV and each CMOS transmission gate respectively.

5. The low-power full adder based on FeFET as described in claim 4, characterized in that, During the calculation phase, when the signal XOR is 1 and the signal XNOR is 0, TG1 and TG4 are turned on, and TG2 and TG3 are turned off; when the signal XOR is 0 and the signal XNOR is 1, TG1 and TG4 are turned off, and TG2 and TG3 are turned on.

6. The low-power full adder based on FeFET as described in claim 4, characterized in that, During the write phase, a high-level voltage of 3V is applied to the gates of F1 and F2, and the write duration is 5ns; during the calculation phase, a high-level voltage of 0.9V is applied to the gates of F1 and F2, and the calculation duration is 2ns; during the hold phase, the calculation duration is 5ns.

7. The low-power full adder based on FeFET as described in claim 1, characterized in that, The formula for calculating the sum bit signal is: The formula for calculating the carry signal is: .

8. The low-power full adder based on FeFET as described in claim 1, characterized in that, Each CMOS transmission gate includes a first NMOS transistor and a first PMOS transistor connected in parallel; within the same CMOS transmission gate, the gates of the first NMOS transistor and the first PMOS transistor are respectively connected to control signals that are inversely related: XOR and XNOR; INV includes a second NMOS transistor and a second PMOS transistor connected in series.

9. The low-power full adder based on FeFET as described in claim 1, characterized in that, F1 and F2 are both N-type FeFET transistors. The full adder performs low-threshold writing by applying a high level to the gates of F1 and F2, and performs high-threshold writing by applying a low level.

10. A chip, characterized in that, Its operational circuit integrates a low-power full adder based on FeFET as described in any one of claims 1-9.

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