Reconfigurable analog compute-in-memory multiply-accumulate array

Abstract

The application discloses a reconfigurable analog memory-computing integrated multiply-accumulate array, and belongs to the technical field of analog integrated circuits and AI hardware accelerator, which comprises a floating gate transistor multiply-accumulate unit array, a programmable interconnection routing network and a configuration controller. The floating gate transistor multiply-accumulate unit stores programmable analog weights; the programmable interconnection routing network is located between an input / output bus and the array and is composed of configurable switches; and the configuration controller controls the on-off of the switches according to an external digital configuration word to change the interconnection relationship of the units. The application realizes adaptive support of multiple neural network computing modes such as convolution, full connection and residual connection by reconfiguring the interconnection topology, improves the versatility and energy efficiency of the analog memory-computing integrated array, and is suitable for AI hardware acceleration scenes.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuits and AI hardware accelerator technology, specifically relating to a reconfigurable analog in-memory computing multiply-accumulate array. Background Technology

[0002] In recent years, artificial intelligence technologies, represented by deep learning, have made groundbreaking progress, with the computational load and number of parameters in neural network models growing exponentially. In the traditional von Neumann computing architecture, data storage units and computing units are physically separated, and large amounts of data are frequently moved between memory and computing units, resulting in severe "memory walls" and "power walls," which have become core bottlenecks restricting the performance improvement of AI hardware. Computing-in-Memory (CIM) technology, by performing computational operations directly within the storage unit, fundamentally eliminates data movement and is considered a key technological path to overcome the limitations of traditional architectures.

[0003] In in-memory computing technologies, analog-domain computing has attracted significant attention due to its high parallelism and energy efficiency. Floating-gate transistors (FTMTs), as non-volatile memory devices, can store analog weights in the form of charge for extended periods within the floating gate. They utilize their inherent current-voltage characteristics to perform analog multiplication of the input signal and weights, and then use Kirchhoff's current law to accumulate current at the array level, thus achieving efficient analog multiply-accumulate (MAC) operations. Floating-gate transistor arrays based on NOR Flash structures have demonstrated significant application potential in this field.

[0004] However, existing analog in-memory computing arrays generally employ fixed-connection topologies. Once the chip is manufactured, the interconnections between the computing units are fixed and cannot be flexibly adjusted according to the needs of different neural network models. In practical applications, deep neural networks encompass various topologies: convolutional neural networks rely on weight-sharing structures with local receptive fields; fully connected layers require global interconnections; and deep networks such as ResNet introduce cross-layer residual connections to alleviate the gradient vanishing problem. When it is necessary to switch the neural network topology (such as from standard convolution to depthwise separable convolution or the introduction of residual connections), fixed-topology arrays cannot be directly adapted in the analog domain. Additional digital circuitry must be used for data rearrangement and format conversion, a process that significantly negates the original power consumption and latency advantages of analog computing.

[0005] To address the aforementioned issues, some existing technologies attempt to combine multiple fixed-topology subarrays to meet different computing needs. However, this approach increases chip area overhead, and data transfer between subarrays still incurs efficiency losses. Another approach is to employ a globally programmable digital routing network, but the latency and power consumption introduced by digital switches and buffers are particularly sensitive on analog signal paths, making it difficult to maintain the high energy efficiency of analog computing. Summary of the Invention

[0006] The purpose of this invention is to provide a reconfigurable analog-in-memory multiply-accumulate array to solve the technical problem that existing analog-in-memory arrays have fixed topologies and cannot flexibly adapt to various neural network computing modes. This invention introduces a programmable interconnect routing network and a configuration controller, enabling the same physical array to be reconfigured into connection relationships supporting various neural network topologies such as convolution, fully connected, and residual connections by loading different digital configuration words. This achieves adaptive support for multiple AI model architectures on a single chip.

[0007] The first aspect of this invention provides a reconfigurable analog in-memory multiply-accumulate array, comprising: The floating gate transistor multiply-accumulate unit array includes multiple floating gate transistor multiply-accumulate units, and each of the floating gate transistor multiply-accumulate units stores programmable analog weights; A programmable interconnect routing network is located between the input bus and the floating gate transistor multiply-accumulate unit array, and is also located between the floating gate transistor multiply-accumulate unit array and the output bus, and includes configurable switches; A configuration controller is used to control the on / off state of each switch in the programmable interconnect routing network according to an external digital configuration word, thereby changing the interconnection relationship between the floating gate transistor multiply-accumulate units.

[0008] Furthermore, it also includes: an input digital-to-analog converter; The input digital-to-analog converter is used to convert the input data into digital data to obtain the input data corresponding to the floating gate transistor multiply-accumulate unit array.

[0009] Furthermore, the floating gate transistor multiply-accumulate unit includes a floating gate transistor, a storage weight voltage terminal, a drain connected to the input signal terminal, a source connected to the output current summation line, and a programmable charge storage region; The floating gate of the floating gate transistor serves as the programmable charge storage region, used to store the amount of charge representing the analog weight; the stored weight voltage terminal is connected to the control gate of the floating gate transistor to provide the bias voltage required to read the weight; the drain connection input signal terminal is connected to the drain of the floating gate transistor to receive the analog voltage input signal; the source connection output current summation line is connected to the source of the floating gate transistor to output the product current of the weight and the input signal.

[0010] Furthermore, the analog weights stored in the floating gate transistor multiply-accumulate unit are programmed using the Fowler-Nordheim tunneling current, with a weight precision of 4-6 bits.

[0011] Furthermore, the size of the floating gate transistor multiply-accumulate cell array is set to 256×256.

[0012] Furthermore, the programmable interconnect routing network includes: An input-side routing network, configured before each column of input signal terminals in the array, is used to route analog voltage signals output from an external digital-to-analog converter to the input signal terminals of a specified column. The output-side routing network, configured after each row of the array's output current summary line, is used to route the output current of each row to a specified output accumulation line or subsequent processing circuitry. Inter-layer routing networks, configured within or between arrays, are used to interconnect signals between different rows or columns of cells to support complex topologies such as sliding window connections and residual connections for convolution operations.

[0013] Furthermore, the configurable switches in the programmable interconnect routing network are NMOS transistors, and the gates of each NMOS transistor are connected to the output of the configuration controller. The conduction / cutoff of the NMOS transistors is controlled by the high / low level of the control signal, thereby changing the physical routing path of the analog signal between the floating gate transistor multiply-accumulate unit array.

[0014] Furthermore, the programmable interconnected routing network is configured with convolutional neural network topology connections, fully connected neural network topology connections, and residual neural network topology connections.

[0015] Furthermore, the configuration controller is configured as an on-chip micro-sequencer.

[0016] Furthermore, the configuration controller is configured to parse the 32-bit configuration word received from the external SPI interface into the on / off state of each configurable switch in the programmable interconnect routing network.

[0017] The beneficial effects of this invention are as follows: This invention provides a reconfigurable analog-in-memory multiply-accumulate array, comprising a floating-gate transistor multiply-accumulate cell array, a programmable interconnect routing network, and a configuration controller. The floating-gate transistor multiply-accumulate cells store programmable analog weights; the programmable interconnect routing network, located between the input / output bus and the array, is composed of configurable switches; the configuration controller controls the on / off states of the switches based on an external digital configuration word, thereby changing the interconnect relationships between the cells. This invention, by reconfiguring the interconnect topology, achieves adaptive support for various neural network computing modes such as convolution, fully connected, and residual connections, improving the versatility and energy efficiency of the analog-in-memory array, and is suitable for AI hardware acceleration scenarios. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0019] Figure 1 A schematic diagram of a reconfigurable analog in-memory computing multiply-accumulate array provided in an embodiment of the present invention; Figure 2 A schematic diagram of a floating-gate transistor multiply-accumulate cell array provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the topology of a programmable interconnected routing network provided in an embodiment of the present invention; Among them, 101-input digital-to-analog converter, 102-floating gate transistor multiply-accumulate unit array, 103-programmable interconnect routing network, 104-configuration controller, 201-floating gate transistor, 202-storage weight voltage terminal, 203-drain connected input signal terminal, 204-source connected output current summator line, and 205-programmable charge storage area.

[0020] The accompanying drawings have illustrated specific embodiments of the invention, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the invention in any way, but rather to illustrate the concept of the invention to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0022] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0023] like Figure 1 As shown, this embodiment of the invention provides a reconfigurable analog in-memory computing multiply-accumulate array, comprising: The floating gate transistor multiply-accumulate unit array 102 includes a plurality of floating gate transistor multiply-accumulate units, and each of the floating gate transistor multiply-accumulate units stores programmable analog weights; The programmable interconnect routing network 103 is located between the input bus and the floating gate transistor multiply-accumulate unit array 102, and is also disposed between the floating gate transistor multiply-accumulate unit array 102 and the output bus, and includes configurable switches. The configuration controller 104 is used to control the on / off state of each switch in the programmable interconnect routing network 103 according to an external digital configuration word, thereby changing the interconnection relationship between the floating gate transistor multiply-accumulate units.

[0024] In some possible embodiments, it also includes: an input digital-to-analog converter 101; The input digital-to-analog converter 101 is used to convert the input data into digital data to obtain the input data corresponding to the floating gate transistor multiply-accumulate unit array 102.

[0025] For example, the input digital-to-analog converter 101 is connected between an external digital signal source and a programmable interconnect routing network 103 to convert externally input digital feature data into analog voltage signals, which are then used as inputs to the floating gate transistor multiply-accumulate unit array 102. The input digital-to-analog converter 101 preferably employs a successive approximation (SAR) or R-2R ladder resistor network structure, with resolution matching the weight accuracy of the floating gate units, preferably 6-8 bits.

[0026] like Figure 2 As shown, the floating gate transistor multiply-accumulate unit includes a floating gate transistor 201, a storage weight voltage terminal 202, a drain-connected input signal terminal 203, a source-connected output current summation line 204, and a programmable charge storage region 205. The floating gate of the floating gate transistor 201 serves as the programmable charge storage region 205, used to store the amount of charge representing the analog weight; the weight storage voltage terminal 202 is connected to the control gate of the floating gate transistor 201 to provide the bias voltage required to read the weight; the drain-connected input signal terminal 203 is connected to the drain of the floating gate transistor 201 to receive the analog voltage input signal; the source-connected output current summation line 204 is connected to the source of the floating gate transistor 201 to output the product current of the weight and the input signal.

[0027] In some possible embodiments, the analog weights stored in the floating gate transistor multiply-accumulate cell are programmed via Fowler-Nordheim tunneling current with a weight precision of 4-6 bits.

[0028] For example, the weights of each cell in the floating-gate transistor multiply-accumulate cell array 102 are programmed using the Fowler-Nordheim tunneling effect. During programming, a high-voltage pulse is applied between the control gate of the floating-gate transistor and the channel or substrate, causing charge carriers to tunnel through the oxide layer into or out of the floating gate, thereby changing the amount of charge stored in the floating gate and thus adjusting the threshold voltage V_TH of the transistor.

[0029] The programming operation addresses the target floating gate cell through external column and row decoders, employing a program-verify closed-loop control strategy to gradually approach the target weight value. After each programming pulse, the equivalent output conductance of the cell is read and compared with the target value. If the deviation is within the tolerance range, programming stops; otherwise, programming pulses continue to be applied until convergence. The controllable weight accuracy range is 4-6 bits, corresponding to 16-64 distinguishable weight levels.

[0030] There is a nonlinear mapping relationship between the programming pulse width, the threshold voltage offset, and the change in equivalent output conductance. Multiple programming response characteristic curves correspond to the programming response characteristics under different initial states. By calibrating these curves, the required programming pulse parameters, including pulse amplitude, pulse width, and pulse count, can be accurately calculated based on the target weight value.

[0031] In some possible embodiments, the size of the floating gate transistor multiply-accumulate cell array 102 is set to 256×256.

[0032] For example, the floating gate transistor multiply-accumulate unit array 102 is a two-dimensional cross array structure with M rows and N columns, where M and N are both positive integers. Preferably, M=N=256, forming an array of size 256×256. Each array unit is a floating gate transistor multiplication unit, used to store programmable analog weights and perform analog multiplication operations on the input signal.

[0033] Each floating-gate transistor multiplication unit includes: A floating-gate transistor, in which the floating gate is used to store the amount of charge representing a weight; The storage weight voltage terminal is connected to the control gate of the floating gate transistor to provide the bias voltage required to read the weight; The input signal terminal is connected to the drain of the floating gate transistor and is used to receive analog voltage input signals. The output current summation line is connected to the source of the floating gate transistor and is used to output the weighted product current of the input signal. The programmable charge storage region, located in the floating gate region of the floating gate transistor, injects or releases charge through the Fowler-Nordheim tunneling effect, enabling the programmable adjustment of the weight values.

[0034] The floating-gate transistor operates in the deep linear region. The relationship between its drain-source current I_DS and the effective gate voltage (V_GS - V_TH) and drain-source voltage V_DS satisfies: I_DS = β × (V_GS - V_TH) × V_DS, where β is the transistor gain factor and V_TH is the threshold voltage. When the storage weight voltage is fixed, a change in the threshold voltage V_TH is equivalent to a change in the weight value. The drain-source voltage V_DS serves as the input signal, and the output current I_DS is the result of the multiplication.

[0035] In some possible embodiments, the programmable interconnect routing network 103 includes: An input-side routing network, configured before each column of input signal terminals in the array, is used to route analog voltage signals output from an external digital-to-analog converter to the input signal terminals of a specified column. The output-side routing network, configured after each row of the array's output current summary line, is used to route the output current of each row to a specified output accumulation line or subsequent processing circuitry. Inter-layer routing networks, configured within or between arrays, are used to interconnect signals between different rows or columns of cells to support complex topologies such as sliding window connections and residual connections for convolution operations.

[0036] In some possible embodiments, the configurable switches in the programmable interconnect routing network are NMOS transistors. The gates of each NMOS transistor are connected to the output of the configuration controller. The NMOS transistors are turned on / off by a high / low level control signal, thereby changing the physical routing path of the analog signal between the floating gate transistor multiply-accumulate cell array. Specifically, the configuration controller 104 parses the digital configuration word → outputs a control signal to drive the NMOS switches; the NMOS switches turn on / off to determine whether the signal is connected, thereby changing the topology connection between the input signal terminal 203 and the output current summation line 204.

[0037] For example, the source and drain of the NMOS transistor are connected to different signal paths (e.g., connected to the output current summary line 204 of a certain unit, or connected to the input signal terminal 203 of the next unit, or connected to the overall input / output bus); the gate of the NMOS transistor is connected to the output terminal of the configuration controller 104. When the configuration controller outputs a high level, the NMOS is turned on, and the signal path is connected; when the output level is low, it is turned off, and the signal path is disconnected. The floating gate transistor multiply-accumulate units 102 are arranged in a 256×256 two-dimensional matrix. The output current summary line 204 of all units in each column is connected to the same column-directed output accumulator line; the input signal terminal 203 of all units in each row is connected to the same row-directed input signal line. The NMOS switch matrix of the programmable interconnect routing network 103 is distributed among the input bus, output bus, and row and column signal lines. By switching the on and off of the NMOS by the configuration controller, an input signal terminal 203 can be routed to any specified multiply-accumulate unit, or the output current summary line 204 of any unit can be routed to a specified output accumulator line, thereby physically changing the topological connection relationship between units. The configurable switches are implemented using NMOS transfer transistors or CMOS transfer gates. Each switch has an independent on / off control terminal, driven by a control signal output from the configuration controller 104. When using NMOS transfer transistors as switching elements, their on-resistance is related to the gate control voltage. Preferably, the on-resistance is reduced by increasing the gate control voltage swing, thereby minimizing the adverse effects on the accuracy of the analog signal.

[0038] like Figure 3 As shown, the programmable interconnected routing network 103 is configured with convolutional neural network topology connections, fully connected neural network topology connections, and residual neural network topology connections.

[0039] For example, the same physical array can load different digital configuration words through the configuration controller 104 to achieve equivalent connection relationships for various neural network topologies, including at least: Convolutional topology configuration: The input signal is routed to the floating gate unit column corresponding to the convolutional kernel through the programmable interconnection routing network 103. The input feature map regions covered by the same convolutional kernel are connected to the same output accumulation line, realizing weight-sharing convolutional computation. It supports two sub-modes: standard convolution and depthwise separable convolution.

[0040] Fully connected topology configuration: All input signal terminals are connected to all floating gate cell columns through the programmable interconnect routing network 103, while the output current of all rows is summarized to a single output accumulation line, realizing matrix-vector multiplication operation of the fully connected layer.

[0041] Residual connection topology configuration: Based on convolutional or fully connected topology, the output current of a specific layer is directly bypassed to the input of the subsequent layer through the programmable interconnection routing network 103, realizing cross-layer residual connection and skipping the intermediate nonlinear transformation stage.

[0042] In some possible embodiments, the configuration controller 104 is configured as an on-chip micro-sequencer.

[0043] In some possible embodiments, the configuration controller 104 is configured to parse a 32-bit configuration word received from an external SPI interface into the on / off state of each configurable switch in the programmable interconnect routing network 103.

[0044] For example, the configuration controller 104 is connected to the control terminal of each switch in the programmable interconnect routing network 103 to control the on / off state of each switch according to the externally input digital configuration word, thereby changing the interconnection relationship between the floating gate transistor multiply-accumulate units.

[0045] The configuration controller 104 includes: Configuration interface unit: Preferably, the SPI (Serial Peripheral Interface) protocol is used to receive 32-bit configuration words from an external host chip; Configuration parsing unit: Parses the received 32-bit configuration word and extracts the control bit information of each switch; Switch driving unit: Converts the parsed control bit information into on / off driving signals for each switch. The driving voltage swing is preferably from 0V to VDD (power supply voltage) to ensure that the NMOS switches are fully turned on. Configuration storage register: Used to cache the currently loaded configuration word, supporting online updates and hot switching of configuration words.

[0046] The configuration controller 104 is preferably an on-chip micro-sequencer or a dedicated finite state machine (FSM) to achieve low-latency response for configuration switching.

[0047] Based on the above technical solution, this embodiment of the invention provides a complete data processing flow for the reconfigurable analog-in-memory multiply-accumulate array, which may include: Step S1 (Configuration Phase): The external host sends a 32-bit digital configuration word to the configuration controller via the SPI interface to define the target neural network topology type (convolutional / fully connected / residual connection).

[0048] Step S2 (Reconstruction Execution): The configuration controller parses the configuration word, controls the NMOS switching network, and reconstructs the same physical array into the target topology path.

[0049] Step S3 (Weight Programming): Each floating gate transistor cell injects charge through the Fowler-Nordheim tunneling effect, programming the simulated weight to the target conductance value.

[0050] Step S4 (Inference Stage): The input data is converted into an analog voltage signal V by the input digital-to-analog converter. i It is applied to the unit input terminal.

[0051] Step S5 (Analog Multiplication): Each floating-gate transistor performs multiplication in the deep linear region, outputting current. (G) ij (For conductivity weights).

[0052] Step S6 (Current Summation): The output currents of all cells in the same column are summed naturally on the output accumulation line to obtain the multiplication and accumulation result. .

[0053] Step S7 (Direct Output): The current of the accumulated result is directly output to the next stage analog circuit without the need for analog-to-digital conversion.

[0054] Compared with the prior art, the present invention has the following beneficial effects: This invention introduces a programmable interconnect routing network 103, enabling the same physical array to be switched online to various topologies such as convolutional, fully connected, and residual connections via digital configuration words. This improves topology flexibility by more than five times compared to fixed arrays. A single chip can adapt to various AI model architecture changes, significantly expanding the chip's application scope and product lifecycle.

[0055] Topology switching is completed in the analog domain, without relying on external digital circuits for data rearrangement and format conversion. This avoids the power consumption and latency overhead caused by multiple analog-to-digital and digital-to-analog conversions, and fully preserves the energy efficiency advantages of analog computing.

[0056] By configuring the controller 104 to achieve online switching of the topology, the "software-defined hardware" design concept enables system designers to dynamically configure the computing topology according to the computing power requirements of specific AI models, thereby achieving optimal matching of computing resources.

[0057] The residual connection topology configuration enables the array of this invention to directly support the computation of deep residual networks such as ResNet, without the need to process cross-layer data paths off-chip or in the digital domain, further improving system integration and computational efficiency.

[0058] The weight reprogramming capability based on the Fowler-Nordheim tunneling effect enables the array to be updated and adapt to dynamically changing computational tasks.

[0059] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0060] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0061] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0062] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0063] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A reconfigurable analog-in-memory multiply-accumulate array, characterized in that, include: The floating gate transistor multiply-accumulate unit array includes multiple floating gate transistor multiply-accumulate units, and each of the floating gate transistor multiply-accumulate units stores programmable analog weights; A programmable interconnect routing network is located between the input bus and the floating gate transistor multiply-accumulate unit array, and is also located between the floating gate transistor multiply-accumulate unit array and the output bus, and includes configurable switches; A configuration controller is used to control the on / off state of each switch in the programmable interconnect routing network according to an external digital configuration word, thereby changing the interconnection relationship between the floating gate transistor multiply-accumulate units.

2. The reconfigurable analog-in-memory multiply-accumulate array according to claim 1, characterized in that, It also includes: an input digital-to-analog converter; The input digital-to-analog converter is used to convert the input data into digital data to obtain the input data corresponding to the floating gate transistor multiply-accumulate unit array.

3. The reconfigurable analog-in-memory multiply-accumulate array according to claim 1, characterized in that, The floating gate transistor multiply-accumulate unit includes a floating gate transistor (201), a storage weight voltage terminal (202), a drain-connected input signal terminal (203), a source-connected output current summation line (204), and a programmable charge storage region (205). The floating gate of the floating gate transistor (201) serves as the programmable charge storage region (205) for storing the amount of charge representing the analog weight; the stored weight voltage terminal (202) is connected to the control gate of the floating gate transistor (201) to provide the bias voltage required to read the weight; the drain-connected input signal terminal (203) is connected to the drain of the floating gate transistor (201) to receive the analog voltage input signal; the source-connected output current summation line (204) is connected to the source of the floating gate transistor (201) to output the product current of the weight and the input signal.

4. The reconfigurable analog-in-memory multiply-accumulate array according to claim 1, characterized in that, The analog weights stored in the floating gate transistor multiply-accumulate unit are programmed using the Fowler-Nordheim tunneling current, with a weight precision of 4-6 bits.

5. The reconfigurable analog-in-memory multiply-accumulate array according to claim 1, characterized in that, The size of the floating gate transistor multiply-accumulate cell array is set to 256×256.

6. The reconfigurable analog-in-memory multiply-accumulate array according to claim 1, characterized in that, The programmable interconnect routing network includes: An input-side routing network, configured before each column of input signal terminals in the array, is used to route analog voltage signals output from an external digital-to-analog converter to the input signal terminals of a specified column. The output-side routing network, configured after each row of the array's output current summary line, is used to route the output current of each row to a specified output accumulation line or subsequent processing circuitry. Inter-layer routing networks, configured within or between arrays, are used to interconnect signals between different rows or columns of cells to support complex topologies such as sliding window connections and residual connections for convolution operations.

7. The reconfigurable analog-in-memory multiply-accumulate array according to claim 1, characterized in that, The configurable switches in the programmable interconnect routing network are NMOS transistors. The gate of each NMOS transistor is connected to the output of the configuration controller. The conduction / cutoff of the NMOS transistors is controlled by the high / low level of the control signal, thereby changing the physical routing path of the analog signal between the floating gate transistor multiply-accumulate unit array.

8. The reconfigurable analog-in-memory multiply-accumulate array according to claim 1, characterized in that, The programmable interconnected routing network is configured with convolutional neural network topology connections, fully connected neural network topology connections, and residual neural network topology connections.

9. The reconfigurable analog-in-memory multiply-accumulate array according to claim 1, characterized in that, The configuration controller is configured as an on-chip micro-sequencer.

10. The reconfigurable analog-in-memory multiply-accumulate array according to claim 1, characterized in that, The configuration controller is configured to parse the 32-bit configuration word received from the external SPI interface into the on / off state of each configurable switch in the programmable interconnect routing network.

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