A mixed-precision exponential function approximation processing method and vector processor

Abstract

The application discloses a mixed-precision exponential function approximation processing method and a vector processor, and belongs to the technical field of processor hardware acceleration. The method is executed by a vector processor hardware, and includes the following steps: an FP32 input vector and function mode information are received, and a to-be-reduced value is generated according to the function mode; input boundary judgment is completed before range reduction, and abnormal input directly generates corresponding candidate results; a legal to-be-reduced value is decomposed into an integer order code and a predetermined interval remainder, an exponential approximation value of the remainder is solved by using the remainder, and an exponential function reconstruction result is obtained in combination with the integer order code; after the reconstruction result and various candidate results are selected element by element, RNE rounding from FP32 to BF16 is only executed once, and a BF16 exponential operation result is output. In the application, intermediate operation is kept at FP32 precision, multi-stage rounding errors are inhibited, hardware units are multiplexed, special values, overflow and subnormal processing are completely supported, and the application is suitable for AI inference scene EXP and EXP2 hardware acceleration requirements.

Description

Technical Field

[0001] This application relates to the fields of floating-point processors, vector computing, and artificial intelligence accelerators, and in particular to a mixed-precision exponential function approximation method and a vector processor. Background Technology

[0002] During the inference process of large language models, operators such as Softmax, Sigmoid, and SiLU all require extensive calls to the exponential function. If the exponential function is directly implemented using general basic operation sequences, it will generate long data dependency chains, resulting in frequent intermediate register write-backs and data movement overhead. If a complete dedicated exponential operation unit is configured specifically for correct rounding of FP32, it will lead to problems such as increased chip area, increased power consumption, and a large amount of verification workload.

[0003] Existing low-precision exponentiation hardware solutions mostly employ low-precision input, function lookup tables, or residual lookup tables to perform exponentiation operations. These solutions often lose the original FP32 data information at the input stage or require significant hardware storage resources. For the final output, which only requires a BF16 format inference data path, continuing to pursue complete FP32 low-bit precision will result in ineffective hardware overhead that cannot be utilized by subsequent links, leading to a mismatch between hardware resource scale and target output precision.

[0004] Inside a vector processor that has already been configured with FP32 fused multiply-accumulate units and FP32 to BF16 conversion resources, if the existing general-purpose exponential function implementation scheme is directly ported, it is still necessary to write the intermediate operation results back to the register or move the data to other operation units. The processor's existing arithmetic units and format conversion resources cannot directly form a closed exponential processing data path from FP32 input to BF16 output.

[0005] Therefore, there is an urgent need for a technical solution that can retain the original input information of FP32, adapt the exponential approximation algorithm to the internal data path of the vector processor, reuse the processor's existing FP32 fusion multiply-accumulate hardware resources to complete the exponential approximation operation, and directly output the BF16 operation result at the end of the link. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this application provides a hybrid precision exponential function approximation method and a vector processor. Without configuring a complete general-purpose FP32 exponential operation unit, it can perform operations on the natural exponential function and the base-2 exponential function of the FP32 input vector. At the same time, it fully utilizes the processor's built-in fused multiply-accumulate unit and BF16 conversion hardware resources, reducing chip area, power consumption, number of operations, and register bandwidth overhead.

[0007] To achieve the above objectives, this application provides a mixed-precision exponential function approximation method, executed by a vector processor hardware, comprising: Receives an input vector in FP32 format and function mode information for selecting a natural exponential function or a base-2 exponential function; For the valid elements in the input vector, a value to be reduced is formed based on the functional mode information; Before reducing the range, a finite input boundary judgment is performed on the value to be reduced. For inputs that are NaN, infinity, or exceed the target output range of BF16, special values, overflow, or underflow candidate results are directly output. The value to be reduced by boundary judgment is decomposed into an integer exponent and a remainder term located within a predetermined bounded interval; Calculate an approximate value of the remainder index based on the remainder term; Based on the integer exponent and the approximate value of the remainder exponent, the result of the exponential function reconstruction is obtained; Element-wise selection is performed on the reconstruction results of the exponential function, the candidate results of special values, the candidate results of overflow, and the candidate results of underflow. Perform FP32 to BF16 RNE rounding only once after selection is complete, and output the exponentiation result in BF16 format.

[0008] Furthermore, the step of forming a value to be reduced based on the functional mode information for the effective elements in the input vector further includes: when the functional mode is selected as a base-2 exponential function, the FP32 input element is directly used as the value to be reduced; when the functional mode is selected as a natural exponential function, the input element is operated with log2(e) to obtain the value to be reduced, so that the natural exponential function and the base-2 exponential function reuse the same set of residual term exponent approximation calculation path.

[0009] Furthermore, it also includes: splitting log2(e) into a high-order constant L_hi and a low-order constant L_lo, and obtaining the value to be reduced in the natural exponential function mode by fma (x, L_hi, x×L_lo) through the fusion multiplication and addition operation.

[0010] Furthermore, the step of decomposing the value to be reduced by boundary judgment into an integer exponent and a remainder term located within a predetermined bounded interval further includes: performing roundEven on the value to be reduced z to obtain an integer exponent n, a remainder term r=zn, and the remainder term interval constraint being r∈[-0.5,0.5]; and calculating the remainder term r using the fused multiply-add operation r=fma (-1.0f, (float) n, z).

[0011] Furthermore, the step of calculating the approximate value of the remainder exponent based on the remainder term also includes: the approximate value of the remainder exponent is calculated using a fifth-order Horner structure polynomial, and each level of operation of the polynomial is performed by calling the FP32 fused multiply-accumulate unit; the intermediate results of the polynomial operation are stored in the processor's internal intermediate registers and are not written to the software-visible general-purpose registers.

[0012] Furthermore, the fifth-order Horner structure polynomial is: P (r)=c0+r (c1+r (c2+r (c3+r (c4+r×c5)))); c0 to c5 are preset polynomial coefficients, which are stored in read-only memory, microsequence constant memory, or configuration register set.

[0013] Furthermore, the step of obtaining the exponential function reconstruction result based on the integer exponent and the remainder exponent approximation further includes: extracting the unbiased exponent of the remainder exponent approximation and adding the unbiased exponent to the integer exponent; If the exponent result falls within the range of BF16 normal numbers, the lower bits of the mantissa are retained for subsequent BF16 rounding. If the exponent result exceeds the maximum exponent of BF16, an overflow candidate result is generated; If the exponent result is lower than the minimum normal exponent of BF16, the significant number carrying the hidden bit is shifted to the right, and the protection bit, round bit, and sticky bit GRS information are generated and transmitted to the BF16 rounding path.

[0014] Furthermore, it also includes: Receive the first FP32 source vector and the second FP32 source vector, and perform exponential approximation on the two source vectors respectively; Write the BF16 result corresponding to the first FP32 source vector into the first part of the full-width BF16 destination vector, and write the BF16 result corresponding to the second FP32 source vector into the second part of the full-width BF16 destination vector. The full-width BF16 destination vector bit width is equal to the vector processor physical vector bit width VLEN.

[0015] Furthermore, it also includes a dedicated Softmax bypass mode; when the dedicated Softmax bypass mode is enabled, if the input is zero, the candidate result of BF16 value 1 will be directly output; if the input is less than the configurable underflow threshold, the candidate result of BF16 value zero will be directly output; and other inputs will enter the range reduction and polynomial calculation process.

[0016] Furthermore, it also includes: acquiring mode control parameters, which are derived from at least one of configuration registers, instruction mode fields, and microarchitecture control signals; selecting underflow processing as asymptotic subnormal output or zero-level underflow through the mode control parameters, and selecting to output infinity or a maximum finite number of BF16 when overflowing.

[0017] To achieve the above objectives, this application also provides a hybrid precision exponential function vector processor, comprising: The input classification and function selection module is configured to receive input vectors in FP32 format and select the function mode information of natural exponential function or exponential function with base 2, and to complete the judgment of NaN, infinite and finite input boundaries, and output special values, overflow and underflow candidate results; The mode conversion module is configured to directly pass through the input as the value to be reduced in the base-2 exponential function mode, and to generate the value to be reduced in the natural exponential function mode by combining the input with the constant log2(e). The range reduction module is configured to decompose the value to be reduced through boundary judgment into the remainder of the integer exponent and the predetermined bounded interval; The coefficient storage module is configured to store the polynomial coefficients required for approximating the remainder term exponent. The approximation control module is connected to the coefficient storage module and the processor's built-in FP32 fusion multiply-accumulate unit. It is configured to schedule the FP32 fusion multiply-accumulate unit to calculate the approximate value of the remainder term exponent based on the remainder term. The exponent reconstruction module is configured to combine the integer exponent to complete the exponent reconstruction, process normal numbers, overflows, subnormal numbers and generate GRS rounding auxiliary bits; The special value selection module is configured to perform element-wise multi-way selection on the exponential reconstruction result, special value candidate result, overflow candidate result, and underflow candidate result. The BF16 rounding output module is configured to perform RNE rounding from FP32 to BF16 only once after multiplexing is completed and output the BF16 calculation result.

[0018] Furthermore, the range reduction module includes an FP32 splitting circuit, an integer generation circuit, a nearest even number determination circuit, an integer to FP32 conversion circuit, and a remainder calculation path; the range reduction module outputs the integer exponent n obtained by rounding up, and the remainder r in the interval [-0.5, 0.5].

[0019] Furthermore, it also includes a mode control module; the mode control module receives mode control information from at least one of the following sources: configuration register, instruction mode field, and microarchitecture control signal, for enabling or disabling Softmax bypass mode, and for configuring overflow output strategy and underflow output strategy; when Softmax bypass mode is enabled, it directly outputs BF16 value 1 candidate for zero input, and directly outputs BF16 zero candidate for input below the threshold.

[0020] Furthermore, the vector physical bit width VLEN = 128 bits; the processor receives two FP32 source vectors, each containing 4 FP32 elements; the 4 BF16 results obtained from the operation of the first source vector are written into the destination vector [63:0], and the 4 BF16 results obtained from the operation of the second source vector are written into the destination vector [127:64], and concatenated to obtain a 128-bit full-width BF16 destination vector.

[0021] To achieve the above objectives, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor employs a mixed-precision exponential function vector processor as described above, for executing the computer program stored in the memory to implement the mixed-precision exponential function approximation processing method as described above.

[0022] To achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program, which is loaded and executed by a processor to implement the mixed-precision exponential function approximation method as described above.

[0023] Compared with the prior art, this application has the following beneficial effects: This application's hybrid precision exponential function approximation method and vector processor achieve EXP / EXP2 hardware acceleration and bypass abnormal inputs with pre-boundary judgment; constrains the remainder term to a narrow interval for polynomial approximation, reuses FP3 fusion multiply-accumulate units to reduce hardware cost; maintains FP32 precision throughout the entire link and performs FP32 to BF16 rounding only once at the end, suppressing multi-level rounding errors, fully supporting BF16 normal, subnormal, and overflow special value outputs, and also supporting dual-source vector concatenation, balancing computational accuracy, hardware area, and vector operation throughput, and adapting to AI inference hardware scenarios.

[0024] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of the hybrid precision exponential function approximation method according to an embodiment of this application; Figure 2 This is a schematic diagram of the hybrid precision exponential function processor architecture according to an embodiment of this application; Figure 3 This is a schematic diagram of the data path structure for range reduction, coefficient storage, and FP32 fusion multiply-add multiplexing in an embodiment of this application; Figure 4 This is a schematic diagram of the exponent reconstruction, subnormal processing, and BF16 RNE data path in an embodiment of this application. Figure 5 This is a schematic diagram illustrating the generation of a BF16 target vector by concatenating the results of 128-bit dual-source FP32 vector operations in an embodiment of this application. Figure 6 This is a schematic diagram of the electronic device structure according to an embodiment of this application.

[0026] The above figures are only used to illustrate the technical solution of this application and are not intended to limit the scope of protection of this application. Detailed Implementation

[0027] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application.

[0028] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0029] The term "comprising" and its variations as used in this application are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0030] It should be noted that the terms "first" and "second" may be used in this application only to distinguish different devices, components or parts, and are not used to define the order of functions performed by these devices, components or parts or their interdependence.

[0031] It should be noted that the terms "one" and "more" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "More" should be understood as two or more.

[0032] It should be noted that the vector processor described in this application is a processor capable of performing element-wise fused multiplication and addition operations on multiple FP32 floating-point elements within a vector, and configured with FP32 to BF16 rounding output resources. The fused multiplication and addition operation follows the mathematical logic a×b+c, and performs a floating-point rounding after merging the product and addend; according to different embodiments, the rounding output resources can convert the two sets of FP32 operation results and pack them into different bit segments of the same BF16 destination vector.

[0033] It should be noted that, in this specification, the exponential function processing request refers to the control event that triggers the vector processor to perform the natural exponential function EXP or the base-2 exponential function EXP2 on the FP32 input vector. This request can originate from program instructions, internal micro-operations, coprocessor commands, or internal processor control signals. This application protects the hardware execution flow and the connection relationships between modules, and does not limit the instruction name, mnemonic, opcode, or field position of the triggering request.

[0034] Example 1 This application provides a mixed-precision exponential function approximation method. This method is executed by a vector processor hardware and can perform natural exponential function EXP or base-2 exponential function EXP2 operations on FP32 format input vectors, and finally output the exponential operation result in BF16 format.

[0035] Figure 1 This is a flowchart of the mixed-precision exponential function approximation method according to an embodiment of this application. The following will refer to... Figure 1 The present application provides a detailed description of the hybrid precision exponential function approximation method according to its embodiments.

[0036] First, in step S1, an input vector in FP32 format and function mode information are received. The vector processor obtains the input vector in FP32 format, which contains several FP32 floating-point elements; simultaneously, it receives function mode information, which is used to select whether to execute the natural exponential function EXP operation or the base-2 exponential function EXP2 operation.

[0037] In one exemplary embodiment, the vector processor has a physical vector width (VLEN) of 128 bits, and a single input vector can carry four FP32 floating-point elements.

[0038] In step S2, for the valid elements in the input vector, a value to be reduced is formed based on the function mode information. Each valid element of the input vector is traversed, and a value to be reduced, z, is generated according to the function mode. When the function mode is selected as the base-2 exponential function EXP2, the FP32 input element is directly used as the value to be reduced, z=x; when the function mode is selected as the natural exponential function EXP, the value is reduced according to the conversion relationship. The input element x is operated with the constant log2(e) to obtain the value to be reduced z, thereby enabling EXP mode and EXP2 mode to reuse all subsequent calculation paths.

[0039] In a preferred embodiment, log2(e) is split into a high-order constant L_hi and a low-order constant L_lo. The value to be reduced in EXP mode is calculated by fma(x, L_hi, x×L_lo) through a fused multiplication-addition operation, thereby alleviating the calculation error introduced by single constant multiplication in scenarios with large input values.

[0040] In step S3, a finite input boundary check is performed on the values ​​to be reduced before range reduction is executed. Before entering the range reduction operation, each value to be reduced is classified and checked element by element to identify special inputs such as NaN and positive or negative infinity. At the same time, it is determined whether the output result of the finite input after exponential operation exceeds the numerical range that can be expressed in the BF16 format. For NaN, infinity, and inputs whose operation results exceed the BF16 output range, corresponding special value candidate results, overflow candidate results, or underflow candidate results are directly generated. These inputs will not enter the subsequent range reduction calculation process. Only the legal finite values ​​to be reduced that pass the boundary check are transferred to step S4 for further processing.

[0041] In step S4, the value to be reduced, determined by boundary conditions, is decomposed into an integer exponent and a remainder term within a predetermined bounded interval. The range reduction module inside the vector processor performs the decomposition operation on the value to be reduced, z, by rounding down to the nearest even number to obtain the integer exponent n. Then, the FP32 fusion multiply-accumulate unit is called to perform fma(-1.0f,(float)n,z) to calculate the remainder term r, which is constrained to the predetermined bounded interval [-0.5,0.5]. The integer exponent n is output to the exponent reconstruction stage, and the remainder term r is sent to the polynomial approximation calculation link.

[0042] In step S5, the approximate value of the remainder exponent is calculated based on the remainder term. The FP32 fusion multiply-accumulate unit configured in the vector processor is invoked, and a fifth-order Horner polynomial is used to complete the calculation based on the remainder term r. r Approximation calculations yield approximate values ​​for the remainder exponent. The polynomial expression is: P(r) = c0 + r(c1 + r(c2 + r(c3 + r(c4 + r × c5)))) In the formula, c0-c5 are preset polynomial coefficients, which are stored in read-only memory, micro-sequence constant memory, or configuration register set. Each stage of polynomial operation is performed using the FP32 fused multiply-accumulate unit. All intermediate results generated by polynomial operations are stored only in the processor's internal intermediate registers and are not written to software-visible general-purpose registers, thus reducing processor register bandwidth overhead.

[0043] In step S6, the exponential function reconstruction result is obtained based on the integer exponent and the approximate value of the remainder exponent. The exponential reconstruction module completes the equivalent of P(r)×2. n Reconstruction operation: Extracting the approximate value of the remainder exponent The unbiased exponent is added to the integer exponent n, and branch processing is performed based on the resulting exponent. If the exponent falls within the range of BF16 normal numbers, the lower bits of the mantissa are retained for subsequent rounding. If the exponent is greater than the maximum exponent of BF16, overflow is detected and overflow candidate results are generated. If the exponent is less than the minimum normal exponent of BF16, a right shift operation is performed on the significant number carrying the hidden bits, and the guard bit, round bit, and sticky bit GRS information are generated simultaneously. The significant number and GRS information are passed together to the subsequent BF16 rounding path to complete the rounding preparation of the subnormal number, and finally the exponential function reconstruction result is obtained.

[0044] In step S7, the exponential function reconstruction result, special value candidate result, overflow candidate result, and underflow candidate result are selected element-by-element. The multi-way selection module takes each element in the vector as a unit, using the special value candidate result, overflow candidate result, and underflow candidate result output in step S3, and the exponential function reconstruction result output in step S6 as multiple inputs; based on the pre-labeled input classification information of each element, the corresponding element to be rounded is selected element by element. In this step, the selection operations for special values, overflow, and underflow are all completed before the format conversion and rounding, and precision conversion is not performed in the middle of the operation chain.

[0045] In step S8, RNE rounding from FP32 to BF16 is performed only once after selection is complete, outputting the exponentiation result in BF16 format. After element-wise multi-way selection is completed, the entire computation chain performs only one nearest even-number RNE rounding, completing the conversion from internal FP32 precision to the BF16 target format, and outputting the exponentiation result in BF16 format. This embodiment does not perform FP32 to BF16 format conversion in the middle of the computation chain from steps S4 to S6, avoiding the accumulation of errors caused by multi-level rounding.

[0046] For example, the method of this application also supports dual-source vector concatenation output: receiving a first FP32 source vector and a second FP32 source vector, and performing the above-described complete processing flow of steps S1-S8 on the two source vectors respectively; writing the BF16 result obtained by the operation of the first FP32 source vector into the first part of the full-width BF16 destination vector, and writing the BF16 result corresponding to the second FP32 source vector into the second part of the full-width BF16 destination vector, wherein the bit width of the full-width BF16 destination vector is equal to the physical vector bit width VLEN of the vector processor.

[0047] For example, the method of this application also configures a dedicated Softmax bypass mode; when the dedicated Softmax bypass mode is enabled, if the input is zero, the candidate result of BF16 value 1 is directly output; if the input is less than the configurable underflow threshold, the candidate result of BF16 value zero is directly output; and other inputs enter the complete exponent calculation process of steps S1-S8.

[0048] For example, configurable mode control parameters can be used to select whether underflow processing is asymptotic subnormal output or zero-scale underflow, and to select whether the output is infinity or a maximum finite number of BF16 when overflowing.

[0049] In this embodiment, the output behavior of overflow and underflow is configurable through mode control, rather than being fixed in hardware. The source of mode control information can be at least one of the following: configuration registers, mode fields carried in instructions, and internal control signals of the microarchitecture. This invention does not limit the specific source of its implementation. In the actual RTL design phase, one or more sources can be selected according to the overall chip architecture. Using this mode control information, underflow can be configured as an asymptotic subnormal output mode or a nullified underflow mode, and overflow can be configured as an output infinity mode or an output BF16 maximum finite number mode.

[0050] Example 2 This embodiment provides a mixed-precision exponential function vector processor for executing the mixed-precision exponential function approximation processing method of the aforementioned embodiment 1. It can receive FP32 format input vectors, perform EXP and EXP2 exponential operations, and output BF16 format operation results.

[0051] Figure 2 This is a schematic diagram of the hybrid precision exponential function vector processor architecture according to an embodiment of this application, as shown below. Figure 2 As shown, the hybrid precision exponential function vector processor of this application embodiment includes: an input classification and function selection module 201, a mode transformation module 202, a range reduction module 203, a coefficient storage module 204, an approximation control module 205, an FP32 fusion multiply-accumulate unit 206, an exponent reconstruction module 207, a special value selection module 208, a BF16 rounding output module 209, and a mode control module 210, wherein... The mode control module 210 is electrically connected to the input classification and function selection module 201, the exponent reconstruction module 207, and the BF16 rounding output module 209, respectively. The mode control module 210 outputs multiple control signals to configure the function mode, enable or disable the Softmax bypass mode, and configure the overflow output strategy and underflow output strategy. When the Softmax bypass mode is enabled, the mode control module 210 sends a bypass control signal to the input classification and function selection module 201, directly outputting a candidate result of BF16 equal to 1 for elements with zero input, and directly outputting a candidate result of BF16 equal to 0 for elements with input less than the configurable underflow threshold. The overflow strategy can be configured to output infinity or a maximum finite number of BF16. The underflow strategy can be configured to output an asymptotically normal number or directly set to zero.

[0052] The input classification and function selection module 201 receives source vectors in FP32 format and EXP / EXP2 function mode information, and also receives control signals output by the mode control module 210. The input classification and function selection module 201 performs input boundary judgment element by element, identifies special inputs such as NaN and positive and negative infinity, and judges whether the result of the finite input after exponential operation exceeds the range that BF16 can express. It generates special value candidate results, overflow candidate results, and underflow candidate results, and outputs the above candidate results to the special value selection module 208. At the same time, it outputs the legal finite elements to be processed that have passed the boundary judgment to the mode transformation module 202.

[0053] The mode conversion module 202 has its input connected to the output of the input classification and function selection module 201. The mode conversion module 202 generates the value to be reduced based on the function mode information: when operating in EXP2 mode, it directly uses the input element as the value to be reduced; when operating in EXP mode, it uses the input element as the value to be reduced. The conversion relationship is used to calculate the value to be reduced by operating the input element with a pre-stored constant; the mode conversion module 202 outputs the generated value to be reduced to the range reduction module 203.

[0054] The range reduction module 203 receives the value to be reduced from the mode conversion module 202, performs decomposition operations on the valid value to be reduced, rounds to the nearest even number to obtain the integer exponent, and then obtains the remainder term through fusion multiplication and addition operations; the remainder term is constrained to a predetermined bounded interval [-0.5, 0.5]. The range reduction module 203 outputs two data paths: one is the integer exponent, which is sent to the exponent reconstruction module 207; the other is the remainder term, which is sent to the approximation control module 205.

[0055] The coefficient storage module 204 is connected to the approximation control module 205. The coefficient storage module 204 is used to store multiple sets of preset polynomial coefficients for approximation of the remainder exponential polynomial.

[0056] The approximation control module 205 reads the polynomial coefficients from the coefficient storage module 204, receives the remainder term output by the range reduction module 203, and schedules the FP32 fusion multiply-accumulate unit 206 to perform Horner structure polynomial operations to calculate the approximate value of the remainder term exponent. The FP32 fusion multiply-accumulate unit 206 outputs the approximate value of the remainder term exponent and sends it to the exponent reconstruction module 207.

[0057] In this embodiment, the EXP mode and the EXP2 mode share the same set of coefficient storage module 204 and FP32 fusion multiply-accumulate unit 206 calculation path.

[0058] The exponent reconstruction module 207 receives two input data streams: an integer exponent from the range reduction module 203 and a remainder exponent approximation from the FP32 fusion multiply-accumulate unit 206. The exponent reconstruction module 207 adds the unbiased exponent of the remainder exponent approximation to the integer exponent to complete the exponent reconstruction operation. The operation result is processed for normal number, overflow, underflow / subnormal branch, and the subnormal path generates a protection bit G, a rounding bit R, and a sticky bit S GRS auxiliary rounding information. The exponent reconstruction result is then output to the special value selection module 208.

[0059] The special value selection module 208 has two sets of data inputs: the first set of inputs comes from the special value candidate results, overflow candidate results, and underflow candidate results output by the input classification and function selection module 201; the second set of inputs comes from the exponent reconstruction results output by the exponent reconstruction module 207. The special value selection module 208 performs multi-way selection at an element-by-element granularity, selects the rounding result corresponding to each element, and outputs it to the BF16 rounding output module 209.

[0060] The BF16 rounding output module 209 receives the rounding result output by the special value selection module 208 and the mode configuration signal from the mode control module 210. After the multiplexing is completed, the BF16 rounding output module 209 performs only one nearest even number RNE rounding operation from FP32 to BF16 and outputs the exponent calculation result in BF16 format.

[0061] In an optional embodiment of this application, the vector processor supports dual-source vector operation and concatenation output, with a vector physical bit width VLEN of 128 bits; the input classification and function selection module 201 simultaneously receives a first FP32 source vector and a second FP32 source vector; the two source vectors respectively pass through a complete operation link to obtain two sets of BF16 operation results; the BF16 rounding output module 209 writes the BF16 result corresponding to the first FP32 source vector into the lower 64 bits of the destination vector, writes the BF16 result corresponding to the second FP32 source vector into the upper 64 bits of the destination vector, and concatenates to output a full-width BF16 destination vector with a bit width of 128 bits.

[0062] Figure 3 This is a schematic diagram of the data path structure for range reduction, coefficient storage, and FP32 fusion multiply-add multiplexing in an embodiment of this application, as shown below. Figure 3 As shown, the data path performs the range reduction operation in step S4 and the remainder polynomial approximation operation in step S5. The overall data flow sequentially passes through: FP32 splitting → generation of the nearest even integer → n and remainder term feedback → coefficient storage and input selection → FP32 fusion multiply-accumulate unit → intermediate result feedback.

[0063] FP32 splitting: Receive the floating-point number z (FP32 format) to be reduced after boundary judgment, and parse and split the floating-point number to separate the sign bit, exponent, mantissa and hidden bit, complete the parsing of the internal bit field of the floating-point number, and prepare for integer generation.

[0064] Recent Even Integer Generation: Based on the FP32's split output of sign, exponent, mantissa, and hidden bits, the roundEven (rounding to the nearest even number) hardware logic is implemented to generate the integer exponent n. This circuit includes alignment shift logic and rounding determination logic; based on the fractional part bits, it determines whether to perform a +1 carry, thus rounding to the nearest even number and outputting the integer exponent n.

[0065] Feedback on n and remainder terms: On one hand, the integer exponent n is output and sent to the subsequent exponent reconstruction module; on the other hand, the integer n is converted back to FP32 floating-point format, and the FP32 fused multiply-accumulate unit is called to perform the operation. The remainder r is calculated and constrained to the interval [-0.5, 0.5]. The remainder r is then output to the polynomial calculation path.

[0066] Coefficient storage and input selection: This module reads the pre-stored polynomial coefficients c0-c5, and simultaneously receives the remainder r and the intermediate results of the previous operation; the internal multiplexer selects the input operand according to the Horner polynomial operation timing, providing the operation input source to the FP32 fused multiply-accumulate unit. The polynomial coefficients can be stored in ROM, microsequence constant memory, or configuration register set.

[0067] The FP32 fused multiply-accumulate unit is a built-in hardware arithmetic unit of the vector processor, performing fused multiply-accumulate operations of a×b+c. This hardware unit is reused for each Horner iteration of the polynomial, eliminating the need for additional dedicated polynomial computation hardware.

[0068] Intermediate result feedback: The intermediate polynomial results output by the FP32 fused multiply-accumulate unit are latched in the processor's internal intermediate registers and not written to the software-visible general-purpose registers; the intermediate results are fed back to the "coefficient storage and input selection" module to participate in the next stage of Horner polynomial iterative calculation. After all iterations are completed, the approximate value of the remainder exponent (P(r)) is output and sent to the exponent reconstruction module.

[0069] This application's FP32 fusion multiply-add multiplexed data path allows the EXP / EXP2 operation paths to share the same complete hardware path. Since the multiplexed processor already has FP32-FMA hardware, there is no need to design a dedicated polynomial operation unit. Intermediate results are only fed back internally, reducing register read / write bandwidth.

[0070] Figure 4 This is a schematic diagram of the exponent reconstruction, subnormal processing, and BF16 RNE data path in an embodiment of this application, as shown below. Figure 4 As shown, the processor receives the exponent and integer exponent n of the approximate exponent value P(r) from the previous stage output, performs exponent reconstruction, overflow / overflow, and subnormalization processing, and finally completes multiplexing and BF16 rounding to the nearest even number output. The data stream is as follows: P(r) exponent and integer n → exponent adder → normalization / overflow judgment → subnormal shift and GRS generation → special value selection → BF16 RNE output.

[0071] The input consists of two parts: the unbiased exponent (integer) of the remainder exponent approximation P(r), where P(r) is 2... r The first is the polynomial approximation result; the second is the integer exponent n output by the range reduction module, which is the integer correction obtained by roundEven(z), logically equivalent to completing the operation P(r)×2. n .

[0072] It should be noted that the n fed into the exponent adder here is in integer form, no longer in FP32 floating-point format.

[0073] Normal / Overflow Detection: Compare the total exponent obtained from the addition with the upper and lower thresholds of the exponent in BF16 format to complete the three-branch determination: The total exponent is in the BF16 normal number exponent range: it belongs to the normal number path, the low-order bits of the mantissa are retained and directly sent to the next stage; If the total exponent is greater than the maximum exponent of BF16: an overflow is determined, the overflow state is marked, and overflow candidate results are generated; If the total exponent is less than the minimum normal exponent of BF16, it is determined that the subnormal processing path needs to be entered, and the difference between the effective number and the exponent is sent to the subnormal shift hardware.

[0074] Subnormal shift and GRS generation When the determination result is a subnormal scenario, a right shift operation is performed on the significant number carrying the hidden bit. The number of shift bits is determined by the difference between the exponent and the minimum exponent of BF16. During the shift, the guard bit G, round bit R, and sticky bit S (GRS) are extracted. The GRS bit is used for the decision of BF16 rounding to the nearest even number RNE. The significant digits are output together with the GRS information to ensure the rounding accuracy of subnormal numbers. For normal number paths, no shift is performed, and the lower bits of the mantissa are directly output as the source of GRS.

[0075] Special value selection: Receive three types of inputs: (1) the operation results and GRS of the normal / subnormal path output; (2) the special value candidate results obtained in step S3; (3) the overflow and underflow candidate results.

[0076] Based on the previously entered element-by-element classification tags, element-by-element multi-way selection is completed before rounding. No floating-point format conversion is performed in the intermediate stage; all precision conversions are postponed to the next stage.

[0077] BF16 RNE Output: Receives the selected data to be rounded and GRS bits, performs BF16 nearest even number (RNE) rounding, completes the conversion of FP32 internal precision to BF16 format, and outputs the final BF16 exponentiation result.

[0078] In this embodiment, the BF16 RNE data path performs FP32 to BF16 rounding only once in the entire operation link, without performing format conversion in the middle of the reconstruction link, thus avoiding the accumulation of errors caused by multi-level rounding.

[0079] Figure 5 This is a schematic diagram illustrating the generation of a BF16 destination vector by concatenating the results of 128-bit dual-source FP32 vector operations according to an embodiment of this application. Figure 5As shown, the vector processor's physical vector width VLEN is 128 bits. In this mode, it simultaneously reads two FP32 source vectors, src0 and src1, executes the aforementioned exponential operation pipeline on each, and then concatenates the results of the two operations to generate a complete 128-bit BF16 destination vector. The data flow is as follows: src0: 4 FP32 elements → 4 BF16 results → destination vector [63:0] → src1: 4 FP32 elements → 4 BF16 results → destination vector [127:64] → 128-bit BF16 destination vector.

[0080] src0: 4 FP32 elements. src0 is the first source vector, and the 128-bit vector register carries 4 FP32 floating-point elements. Perform EXP or EXP2 operation and output 4 BF16 format operation results.

[0081] 4 BF16 results → destination vector [63:0]: The 4 BF16 results corresponding to src0, each BF16 occupies 16 bits, totaling 64 bits, are written to the lower half bit segment [63:0] of the 128-bit destination vector register.

[0082] src1: 4 FP32 elements. src1 is the second source vector, which also contains 4 FP32 floating-point elements. It reuses the same set of exponentiation hardware pipeline, independently completes the EXP / EXP2 exponentiation operation, and outputs another 4 BF16 operation results.

[0083] In this embodiment, the vector register width of the vector processor remains unchanged. By concatenating dual-source input and result, a single instruction can simultaneously perform exponentiation operations on 8 elements, thereby improving the throughput of vector SIMD operations. By time-sharing the exponentiation pipeline, it is not necessary to instantiate two sets of exponentiation hardware, thus balancing computational throughput and hardware overhead.

[0084] It should be noted that the dual-source splicing mode in this embodiment is an optional working mode; in the single-source working mode, only one FP32 input vector is processed and four BF16 results are output. The high half of the target vector can be set to zero or remain unchanged. This application does not limit this.

[0085] Example 3 In embodiments of the present invention, an electronic device is also provided. Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention, such as... Figure 6 As shown, the electronic device of the present invention includes a processor 601 and a memory 602, wherein, Processor 601 is the hybrid precision exponential function vector processor of the above embodiment.

[0086] The memory 602 stores a computer program, which, when read and executed by the processor 601, performs the steps described above in the embodiment of the mixed precision exponential function approximation processing method.

[0087] Example 4

[0088] In embodiments of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, wherein the computer program is configured to execute the steps in the embodiments of the mixed precision exponential function approximation processing method as described above when running.

[0089] In this embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0090] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for approximating a mixed-precision exponential function, characterized in that, Executed by vector processor hardware, including: Receives an input vector in FP32 format and function mode information for selecting a natural exponential function or a base-2 exponential function; For the valid elements in the input vector, a value to be reduced is formed based on the functional mode information; Before reducing the range, a finite input boundary judgment is performed on the value to be reduced. For inputs that are NaN, infinity, or exceed the target output range of BF16, special values, overflow, or underflow candidate results are directly output. The value to be reduced by boundary judgment is decomposed into an integer exponent and a remainder term located within a predetermined bounded interval; The processor's built-in FP32 fused multiply-accumulate operation resources are invoked to calculate an approximate value of the remainder term exponent based on the remainder term. Based on the integer exponent and the approximate value of the remainder exponent, the result of the exponential function reconstruction is obtained; Element-wise selection is performed on the reconstruction results of the exponential function, the candidate results of special values, the candidate results of overflow, and the candidate results of underflow. Perform FP32 to BF16 RNE rounding only once after selection is complete, and output the exponentiation result in BF16 format.

2. The method according to claim 1, characterized in that, The step of forming a value to be reduced based on the functional mode information for the effective elements in the input vector further includes: when the functional mode is selected as a base-2 exponential function, the FP32 input element is directly used as the value to be reduced; when the functional mode is selected as a natural exponential function, the input element is operated with log2(e) to obtain the value to be reduced, so that the natural exponential function and the base-2 exponential function reuse the same set of residual term exponent approximation calculation path.

3. The method according to claim 2, characterized in that, Also includes: The log2(e) is split into a high-order constant L_hi and a low-order constant L_lo. The value to be reduced in the natural exponential function mode is obtained by fma (x, L_hi, x×L_lo) through the fusion multiplication and addition operation.

4. The method according to claim 1, characterized in that, The step of decomposing the value to be reduced by boundary judgment into an integer exponent and a remainder term located within a predetermined bounded interval further includes: performing roundEven rounding on the value to be reduced z to obtain an integer exponent n, a remainder term r = zn, and the remainder term interval constraint being r ∈ [-0.5, 0.5]; and calculating the remainder term r using the fused multiply-add operation r = fma (-1.0f, (float) n, z).

5. The method according to claim 1, characterized in that, The step of calculating the approximate value of the remainder exponent based on the remainder term further includes: the approximate value of the remainder exponent is calculated using a fifth-order Horner structure polynomial, and each level of operation of the polynomial is performed by calling the FP32 fused multiply-accumulate unit; the intermediate results of the polynomial operation are stored in the processor's internal intermediate registers and are not written to the software-visible general-purpose registers.

6. The method according to claim 5, characterized in that, The fifth-order Horner structure polynomial is: P (r)=c0+r (c1+r (c2+r (c3+r (c4+r×c5)))); c0 to c5 are preset polynomial coefficients, which are stored in read-only memory, microsequence constant memory, or configuration register set.

7. The method according to claim 1, characterized in that, The step of obtaining the reconstructed result of the exponential function based on the integer exponent and the approximate value of the remainder exponent further includes: extracting the unbiased exponent of the approximate value of the remainder exponent and adding the unbiased exponent to the integer exponent; If the exponent result falls within the range of BF16 normal numbers, the lower bits of the mantissa are retained for subsequent BF16 rounding. If the exponent result exceeds the maximum exponent of BF16, an overflow candidate result is generated; If the exponent result is lower than the minimum normal exponent of BF16, the significant number carrying the hidden bit is shifted to the right, and the protection bit, round bit, and sticky bit GRS information are generated and transmitted to the BF16 rounding path.

8. The method according to claim 1, characterized in that, Also includes: Receive the first FP32 source vector and the second FP32 source vector, and perform exponential approximation on the two source vectors respectively; Write the BF16 result corresponding to the first FP32 source vector into the first part of the full-width BF16 destination vector, and write the BF16 result corresponding to the second FP32 source vector into the second part of the full-width BF16 destination vector. The full-width BF16 destination vector bit width is equal to the vector processor physical vector bit width VLEN.

9. The method according to claim 1, characterized in that, It also includes a dedicated Softmax bypass mode; when the dedicated Softmax bypass mode is enabled, if the input is zero, the candidate result of BF16 value 1 will be directly output; if the input is less than the configurable underflow threshold, the candidate result of BF16 value zero will be directly output; and other inputs will enter the range reduction and polynomial calculation process.

10. The method according to claim 1, characterized in that, Also includes: Obtain mode control parameters, which are derived from at least one of the configuration register, instruction mode field, and microarchitecture control signals; select underflow processing as asymptotic subnormal output or zero-level underflow through the mode control parameters, and select output infinity or a maximum finite number of BF16 when overflowing.

11. A hybrid precision exponential function vector processor, characterized in that, include: The input classification and function selection module is configured to receive input vectors in FP32 format and select the function mode information of natural exponential function or exponential function with base 2, and to complete the judgment of NaN, infinite and finite input boundaries, and output special values, overflow and underflow candidate results; The mode conversion module is configured to directly pass through the input as the value to be reduced in the base-2 exponential function mode, and to generate the value to be reduced in the natural exponential function mode by combining the input with the constant log2(e). The range reduction module is configured to decompose the value to be reduced through boundary judgment into the remainder of the integer exponent and the predetermined bounded interval; The coefficient storage module is configured to store the polynomial coefficients required for approximating the remainder term exponent. The approximation control module is connected to the coefficient storage module and the processor's built-in FP32 fusion multiply-accumulate unit. It is configured to schedule the FP32 fusion multiply-accumulate unit to calculate the approximate value of the remainder term exponent based on the remainder term. The exponent reconstruction module is configured to combine the integer exponent to complete the exponent reconstruction, process normal numbers, overflows, subnormal numbers and generate GRS rounding auxiliary bits; The special value selection module is configured to perform element-wise multi-way selection on the exponential reconstruction result, special value candidate result, overflow candidate result, and underflow candidate result. The BF16 rounding output module is configured to perform RNE rounding from FP32 to BF16 only once after multiplexing is completed and output the BF16 calculation result.

12. The vector processor according to claim 11, characterized in that, The range reduction module includes an FP32 splitting circuit, an integer generation circuit, a nearest even number determination circuit, an integer to FP32 conversion circuit, and a remainder calculation path; the range reduction module outputs the integer exponent n obtained by rounding up, and the remainder r in the interval [-0.5, 0.5].

13. The vector processor according to claim 11, characterized in that, It also includes a mode control module; the mode control module receives mode control information from at least one of the following sources: configuration register, instruction mode field, and microarchitecture control signal, and is used to enable or disable Softmax bypass mode, and also to configure overflow output strategy and underflow output strategy; when Softmax bypass mode is enabled, it directly outputs BF16 value 1 candidate for zero input, and directly outputs BF16 zero candidate for input below the threshold.

14. The vector processor according to claim 11, characterized in that, The physical width of the vector is VLEN = 128 bits; the processor receives two FP32 source vectors, each containing 4 FP32 elements; the 4 BF16 results obtained from the operation of the first source vector are written into the destination vector [63:0], and the 4 BF16 results obtained from the operation of the second source vector are written into the destination vector [127:64], and concatenated to obtain a 128-bit full-width BF16 destination vector.

15. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor employs the mixed-precision exponential function vector processor according to any one of claims 11 to 14, for executing the computer program stored in the memory to implement the mixed-precision exponential function approximation processing method according to any one of claims 1 to 10.

16. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which is loaded and executed by a processor to implement the mixed-precision exponential function approximation method as described in any one of claims 1 to 9.

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